driver.h revision 347861
1/*- 2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/mlx5/driver.h 347861 2019-05-16 18:12:14Z hselasky $ 26 */ 27 28#ifndef MLX5_DRIVER_H 29#define MLX5_DRIVER_H 30 31#include <linux/kernel.h> 32#include <linux/completion.h> 33#include <linux/pci.h> 34#include <linux/cache.h> 35#include <linux/rbtree.h> 36#include <linux/if_ether.h> 37#include <linux/semaphore.h> 38#include <linux/slab.h> 39#include <linux/vmalloc.h> 40#include <linux/radix-tree.h> 41#include <linux/idr.h> 42 43#include <dev/mlx5/device.h> 44#include <dev/mlx5/doorbell.h> 45#include <dev/mlx5/srq.h> 46 47#define MLX5_QCOUNTER_SETS_NETDEV 64 48#define MLX5_MAX_NUMBER_OF_VFS 128 49 50enum { 51 MLX5_BOARD_ID_LEN = 64, 52 MLX5_MAX_NAME_LEN = 16, 53}; 54 55enum { 56 MLX5_CMD_TIMEOUT_MSEC = 8 * 60 * 1000, 57 MLX5_CMD_WQ_MAX_NAME = 32, 58}; 59 60enum { 61 CMD_OWNER_SW = 0x0, 62 CMD_OWNER_HW = 0x1, 63 CMD_STATUS_SUCCESS = 0, 64}; 65 66enum mlx5_sqp_t { 67 MLX5_SQP_SMI = 0, 68 MLX5_SQP_GSI = 1, 69 MLX5_SQP_IEEE_1588 = 2, 70 MLX5_SQP_SNIFFER = 3, 71 MLX5_SQP_SYNC_UMR = 4, 72}; 73 74enum { 75 MLX5_MAX_PORTS = 2, 76}; 77 78enum { 79 MLX5_EQ_VEC_PAGES = 0, 80 MLX5_EQ_VEC_CMD = 1, 81 MLX5_EQ_VEC_ASYNC = 2, 82 MLX5_EQ_VEC_COMP_BASE, 83}; 84 85enum { 86 MLX5_MAX_IRQ_NAME = 32 87}; 88 89enum { 90 MLX5_ATOMIC_MODE_OFF = 16, 91 MLX5_ATOMIC_MODE_NONE = 0 << MLX5_ATOMIC_MODE_OFF, 92 MLX5_ATOMIC_MODE_IB_COMP = 1 << MLX5_ATOMIC_MODE_OFF, 93 MLX5_ATOMIC_MODE_CX = 2 << MLX5_ATOMIC_MODE_OFF, 94 MLX5_ATOMIC_MODE_8B = 3 << MLX5_ATOMIC_MODE_OFF, 95 MLX5_ATOMIC_MODE_16B = 4 << MLX5_ATOMIC_MODE_OFF, 96 MLX5_ATOMIC_MODE_32B = 5 << MLX5_ATOMIC_MODE_OFF, 97 MLX5_ATOMIC_MODE_64B = 6 << MLX5_ATOMIC_MODE_OFF, 98 MLX5_ATOMIC_MODE_128B = 7 << MLX5_ATOMIC_MODE_OFF, 99 MLX5_ATOMIC_MODE_256B = 8 << MLX5_ATOMIC_MODE_OFF, 100}; 101 102enum { 103 MLX5_ATOMIC_MODE_DCT_OFF = 20, 104 MLX5_ATOMIC_MODE_DCT_NONE = 0 << MLX5_ATOMIC_MODE_DCT_OFF, 105 MLX5_ATOMIC_MODE_DCT_IB_COMP = 1 << MLX5_ATOMIC_MODE_DCT_OFF, 106 MLX5_ATOMIC_MODE_DCT_CX = 2 << MLX5_ATOMIC_MODE_DCT_OFF, 107 MLX5_ATOMIC_MODE_DCT_8B = 3 << MLX5_ATOMIC_MODE_DCT_OFF, 108 MLX5_ATOMIC_MODE_DCT_16B = 4 << MLX5_ATOMIC_MODE_DCT_OFF, 109 MLX5_ATOMIC_MODE_DCT_32B = 5 << MLX5_ATOMIC_MODE_DCT_OFF, 110 MLX5_ATOMIC_MODE_DCT_64B = 6 << MLX5_ATOMIC_MODE_DCT_OFF, 111 MLX5_ATOMIC_MODE_DCT_128B = 7 << MLX5_ATOMIC_MODE_DCT_OFF, 112 MLX5_ATOMIC_MODE_DCT_256B = 8 << MLX5_ATOMIC_MODE_DCT_OFF, 113}; 114 115enum { 116 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, 117 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, 118 MLX5_ATOMIC_OPS_MASKED_CMP_SWAP = 1 << 2, 119 MLX5_ATOMIC_OPS_MASKED_FETCH_ADD = 1 << 3, 120}; 121 122enum { 123 MLX5_REG_QPTS = 0x4002, 124 MLX5_REG_QETCR = 0x4005, 125 MLX5_REG_QPDP = 0x4007, 126 MLX5_REG_QTCT = 0x400A, 127 MLX5_REG_QPDPM = 0x4013, 128 MLX5_REG_QHLL = 0x4016, 129 MLX5_REG_QCAM = 0x4019, 130 MLX5_REG_DCBX_PARAM = 0x4020, 131 MLX5_REG_DCBX_APP = 0x4021, 132 MLX5_REG_PCAP = 0x5001, 133 MLX5_REG_FPGA_CAP = 0x4022, 134 MLX5_REG_FPGA_CTRL = 0x4023, 135 MLX5_REG_FPGA_ACCESS_REG = 0x4024, 136 MLX5_REG_FPGA_SHELL_CNTR = 0x4025, 137 MLX5_REG_PMTU = 0x5003, 138 MLX5_REG_PTYS = 0x5004, 139 MLX5_REG_PAOS = 0x5006, 140 MLX5_REG_PFCC = 0x5007, 141 MLX5_REG_PPCNT = 0x5008, 142 MLX5_REG_PMAOS = 0x5012, 143 MLX5_REG_PUDE = 0x5009, 144 MLX5_REG_PPTB = 0x500B, 145 MLX5_REG_PBMC = 0x500C, 146 MLX5_REG_PMPE = 0x5010, 147 MLX5_REG_PELC = 0x500e, 148 MLX5_REG_PVLC = 0x500f, 149 MLX5_REG_PMLP = 0x5002, 150 MLX5_REG_PCAM = 0x507f, 151 MLX5_REG_NODE_DESC = 0x6001, 152 MLX5_REG_HOST_ENDIANNESS = 0x7004, 153 MLX5_REG_MTMP = 0x900a, 154 MLX5_REG_MCIA = 0x9014, 155 MLX5_REG_MPCNT = 0x9051, 156 MLX5_REG_MCQI = 0x9061, 157 MLX5_REG_MCC = 0x9062, 158 MLX5_REG_MCDA = 0x9063, 159 MLX5_REG_MCAM = 0x907f, 160}; 161 162enum dbg_rsc_type { 163 MLX5_DBG_RSC_QP, 164 MLX5_DBG_RSC_EQ, 165 MLX5_DBG_RSC_CQ, 166}; 167 168enum { 169 MLX5_INTERFACE_PROTOCOL_IB = 0, 170 MLX5_INTERFACE_PROTOCOL_ETH = 1, 171 MLX5_INTERFACE_NUMBER = 2, 172}; 173 174struct mlx5_field_desc { 175 struct dentry *dent; 176 int i; 177}; 178 179struct mlx5_rsc_debug { 180 struct mlx5_core_dev *dev; 181 void *object; 182 enum dbg_rsc_type type; 183 struct dentry *root; 184 struct mlx5_field_desc fields[0]; 185}; 186 187enum mlx5_dev_event { 188 MLX5_DEV_EVENT_SYS_ERROR, 189 MLX5_DEV_EVENT_PORT_UP, 190 MLX5_DEV_EVENT_PORT_DOWN, 191 MLX5_DEV_EVENT_PORT_INITIALIZED, 192 MLX5_DEV_EVENT_LID_CHANGE, 193 MLX5_DEV_EVENT_PKEY_CHANGE, 194 MLX5_DEV_EVENT_GUID_CHANGE, 195 MLX5_DEV_EVENT_CLIENT_REREG, 196 MLX5_DEV_EVENT_VPORT_CHANGE, 197 MLX5_DEV_EVENT_ERROR_STATE_DCBX, 198 MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE, 199 MLX5_DEV_EVENT_LOCAL_OPER_CHANGE, 200 MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE, 201}; 202 203enum mlx5_port_status { 204 MLX5_PORT_UP = 1 << 0, 205 MLX5_PORT_DOWN = 1 << 1, 206}; 207 208enum { 209 MLX5_VSC_SPACE_SUPPORTED = 0x1, 210 MLX5_VSC_SPACE_OFFSET = 0x4, 211 MLX5_VSC_COUNTER_OFFSET = 0x8, 212 MLX5_VSC_SEMA_OFFSET = 0xC, 213 MLX5_VSC_ADDR_OFFSET = 0x10, 214 MLX5_VSC_DATA_OFFSET = 0x14, 215 MLX5_VSC_MAX_RETRIES = 0x1000, 216}; 217 218#define MLX5_PROT_MASK(link_mode) (1 << link_mode) 219 220struct mlx5_uuar_info { 221 struct mlx5_uar *uars; 222 int num_uars; 223 int num_low_latency_uuars; 224 unsigned long *bitmap; 225 unsigned int *count; 226 struct mlx5_bf *bfs; 227 228 /* 229 * protect uuar allocation data structs 230 */ 231 struct mutex lock; 232 u32 ver; 233}; 234 235struct mlx5_bf { 236 void __iomem *reg; 237 void __iomem *regreg; 238 int buf_size; 239 struct mlx5_uar *uar; 240 unsigned long offset; 241 int need_lock; 242 /* protect blue flame buffer selection when needed 243 */ 244 spinlock_t lock; 245 246 /* serialize 64 bit writes when done as two 32 bit accesses 247 */ 248 spinlock_t lock32; 249 int uuarn; 250}; 251 252struct mlx5_cmd_first { 253 __be32 data[4]; 254}; 255 256struct cache_ent; 257struct mlx5_fw_page { 258 union { 259 struct rb_node rb_node; 260 struct list_head list; 261 }; 262 struct mlx5_cmd_first first; 263 struct mlx5_core_dev *dev; 264 bus_dmamap_t dma_map; 265 bus_addr_t dma_addr; 266 void *virt_addr; 267 struct cache_ent *cache; 268 u32 numpages; 269 u16 load_done; 270#define MLX5_LOAD_ST_NONE 0 271#define MLX5_LOAD_ST_SUCCESS 1 272#define MLX5_LOAD_ST_FAILURE 2 273 u16 func_id; 274}; 275#define mlx5_cmd_msg mlx5_fw_page 276 277struct mlx5_cmd_debug { 278 struct dentry *dbg_root; 279 struct dentry *dbg_in; 280 struct dentry *dbg_out; 281 struct dentry *dbg_outlen; 282 struct dentry *dbg_status; 283 struct dentry *dbg_run; 284 void *in_msg; 285 void *out_msg; 286 u8 status; 287 u16 inlen; 288 u16 outlen; 289}; 290 291struct cache_ent { 292 /* protect block chain allocations 293 */ 294 spinlock_t lock; 295 struct list_head head; 296}; 297 298struct cmd_msg_cache { 299 struct cache_ent large; 300 struct cache_ent med; 301 302}; 303 304struct mlx5_traffic_counter { 305 u64 packets; 306 u64 octets; 307}; 308 309enum mlx5_cmd_mode { 310 MLX5_CMD_MODE_POLLING, 311 MLX5_CMD_MODE_EVENTS 312}; 313 314struct mlx5_cmd_stats { 315 u64 sum; 316 u64 n; 317 struct dentry *root; 318 struct dentry *avg; 319 struct dentry *count; 320 /* protect command average calculations */ 321 spinlock_t lock; 322}; 323 324struct mlx5_cmd { 325 struct mlx5_fw_page *cmd_page; 326 bus_dma_tag_t dma_tag; 327 struct sx dma_sx; 328 struct mtx dma_mtx; 329#define MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx) 330#define MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx) 331#define MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx) 332 struct cv dma_cv; 333#define MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv) 334#define MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx) 335 void *cmd_buf; 336 dma_addr_t dma; 337 u16 cmdif_rev; 338 u8 log_sz; 339 u8 log_stride; 340 int max_reg_cmds; 341 int events; 342 u32 __iomem *vector; 343 344 /* protect command queue allocations 345 */ 346 spinlock_t alloc_lock; 347 348 /* protect token allocations 349 */ 350 spinlock_t token_lock; 351 u8 token; 352 unsigned long bitmask; 353 char wq_name[MLX5_CMD_WQ_MAX_NAME]; 354 struct workqueue_struct *wq; 355 struct semaphore sem; 356 struct semaphore pages_sem; 357 enum mlx5_cmd_mode mode; 358 struct mlx5_cmd_work_ent * volatile ent_arr[MLX5_MAX_COMMANDS]; 359 volatile enum mlx5_cmd_mode ent_mode[MLX5_MAX_COMMANDS]; 360 struct mlx5_cmd_debug dbg; 361 struct cmd_msg_cache cache; 362 int checksum_disabled; 363 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 364}; 365 366struct mlx5_port_caps { 367 int gid_table_len; 368 int pkey_table_len; 369 u8 ext_port_cap; 370}; 371 372struct mlx5_buf { 373 bus_dma_tag_t dma_tag; 374 bus_dmamap_t dma_map; 375 struct mlx5_core_dev *dev; 376 struct { 377 void *buf; 378 } direct; 379 u64 *page_list; 380 int npages; 381 int size; 382 u8 page_shift; 383 u8 load_done; 384}; 385 386struct mlx5_frag_buf { 387 struct mlx5_buf_list *frags; 388 int npages; 389 int size; 390 u8 page_shift; 391}; 392 393struct mlx5_eq { 394 struct mlx5_core_dev *dev; 395 __be32 __iomem *doorbell; 396 u32 cons_index; 397 struct mlx5_buf buf; 398 int size; 399 u8 irqn; 400 u8 eqn; 401 int nent; 402 u64 mask; 403 struct list_head list; 404 int index; 405 struct mlx5_rsc_debug *dbg; 406}; 407 408struct mlx5_core_psv { 409 u32 psv_idx; 410 struct psv_layout { 411 u32 pd; 412 u16 syndrome; 413 u16 reserved; 414 u16 bg; 415 u16 app_tag; 416 u32 ref_tag; 417 } psv; 418}; 419 420struct mlx5_core_sig_ctx { 421 struct mlx5_core_psv psv_memory; 422 struct mlx5_core_psv psv_wire; 423#if (__FreeBSD_version >= 1100000) 424 struct ib_sig_err err_item; 425#endif 426 bool sig_status_checked; 427 bool sig_err_exists; 428 u32 sigerr_count; 429}; 430 431enum { 432 MLX5_MKEY_MR = 1, 433 MLX5_MKEY_MW, 434 MLX5_MKEY_MR_USER, 435}; 436 437struct mlx5_core_mkey { 438 u64 iova; 439 u64 size; 440 u32 key; 441 u32 pd; 442 u32 type; 443}; 444 445struct mlx5_core_mr { 446 u64 iova; 447 u64 size; 448 u32 key; 449 u32 pd; 450}; 451 452enum mlx5_res_type { 453 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, 454 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, 455 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, 456 MLX5_RES_SRQ = 3, 457 MLX5_RES_XSRQ = 4, 458 MLX5_RES_DCT = 5, 459}; 460 461struct mlx5_core_rsc_common { 462 enum mlx5_res_type res; 463 atomic_t refcount; 464 struct completion free; 465}; 466 467struct mlx5_core_srq { 468 struct mlx5_core_rsc_common common; /* must be first */ 469 u32 srqn; 470 int max; 471 size_t max_gs; 472 size_t max_avail_gather; 473 int wqe_shift; 474 void (*event)(struct mlx5_core_srq *, int); 475 atomic_t refcount; 476 struct completion free; 477}; 478 479struct mlx5_eq_table { 480 void __iomem *update_ci; 481 void __iomem *update_arm_ci; 482 struct list_head comp_eqs_list; 483 struct mlx5_eq pages_eq; 484 struct mlx5_eq async_eq; 485 struct mlx5_eq cmd_eq; 486 int num_comp_vectors; 487 /* protect EQs list 488 */ 489 spinlock_t lock; 490}; 491 492struct mlx5_uar { 493 u32 index; 494 void __iomem *bf_map; 495 void __iomem *map; 496}; 497 498 499struct mlx5_core_health { 500 struct mlx5_health_buffer __iomem *health; 501 __be32 __iomem *health_counter; 502 struct timer_list timer; 503 u32 prev; 504 int miss_counter; 505 u32 fatal_error; 506 struct workqueue_struct *wq_watchdog; 507 /* wq spinlock to synchronize draining */ 508 spinlock_t wq_lock; 509 struct workqueue_struct *wq; 510 unsigned long flags; 511 struct work_struct work; 512 struct delayed_work recover_work; 513 unsigned int last_reset_req; 514}; 515 516#define MLX5_CQ_LINEAR_ARRAY_SIZE 1024 517 518struct mlx5_cq_linear_array_entry { 519 spinlock_t lock; 520 struct mlx5_core_cq * volatile cq; 521}; 522 523struct mlx5_cq_table { 524 /* protect radix tree 525 */ 526 spinlock_t lock; 527 struct radix_tree_root tree; 528 struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE]; 529}; 530 531struct mlx5_qp_table { 532 /* protect radix tree 533 */ 534 spinlock_t lock; 535 struct radix_tree_root tree; 536}; 537 538struct mlx5_srq_table { 539 /* protect radix tree 540 */ 541 spinlock_t lock; 542 struct radix_tree_root tree; 543}; 544 545struct mlx5_mr_table { 546 /* protect radix tree 547 */ 548 spinlock_t lock; 549 struct radix_tree_root tree; 550}; 551 552struct mlx5_irq_info { 553 char name[MLX5_MAX_IRQ_NAME]; 554}; 555 556struct mlx5_priv { 557 char name[MLX5_MAX_NAME_LEN]; 558 struct mlx5_eq_table eq_table; 559 struct msix_entry *msix_arr; 560 struct mlx5_irq_info *irq_info; 561 struct mlx5_uuar_info uuari; 562 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock); 563 int disable_irqs; 564 565 struct io_mapping *bf_mapping; 566 567 /* pages stuff */ 568 struct workqueue_struct *pg_wq; 569 struct rb_root page_root; 570 s64 fw_pages; 571 atomic_t reg_pages; 572 s64 pages_per_func[MLX5_MAX_NUMBER_OF_VFS]; 573 struct mlx5_core_health health; 574 575 struct mlx5_srq_table srq_table; 576 577 /* start: qp staff */ 578 struct mlx5_qp_table qp_table; 579 struct dentry *qp_debugfs; 580 struct dentry *eq_debugfs; 581 struct dentry *cq_debugfs; 582 struct dentry *cmdif_debugfs; 583 /* end: qp staff */ 584 585 /* start: cq staff */ 586 struct mlx5_cq_table cq_table; 587 /* end: cq staff */ 588 589 /* start: mr staff */ 590 struct mlx5_mr_table mr_table; 591 /* end: mr staff */ 592 593 /* start: alloc staff */ 594 int numa_node; 595 596 struct mutex pgdir_mutex; 597 struct list_head pgdir_list; 598 /* end: alloc staff */ 599 struct dentry *dbg_root; 600 601 /* protect mkey key part */ 602 spinlock_t mkey_lock; 603 u8 mkey_key; 604 605 struct list_head dev_list; 606 struct list_head ctx_list; 607 spinlock_t ctx_lock; 608 unsigned long pci_dev_data; 609}; 610 611enum mlx5_device_state { 612 MLX5_DEVICE_STATE_UP, 613 MLX5_DEVICE_STATE_INTERNAL_ERROR, 614}; 615 616enum mlx5_interface_state { 617 MLX5_INTERFACE_STATE_UP, 618}; 619 620enum mlx5_pci_status { 621 MLX5_PCI_STATUS_DISABLED, 622 MLX5_PCI_STATUS_ENABLED, 623}; 624 625#define MLX5_MAX_RESERVED_GIDS 8 626 627struct mlx5_rsvd_gids { 628 unsigned int start; 629 unsigned int count; 630 struct ida ida; 631}; 632 633struct mlx5_special_contexts { 634 int resd_lkey; 635}; 636 637struct mlx5_flow_root_namespace; 638struct mlx5_dump_data; 639struct mlx5_core_dev { 640 struct pci_dev *pdev; 641 /* sync pci state */ 642 struct mutex pci_status_mutex; 643 enum mlx5_pci_status pci_status; 644 char board_id[MLX5_BOARD_ID_LEN]; 645 struct mlx5_cmd cmd; 646 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 647 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 648 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 649 struct { 650 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; 651 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; 652 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; 653 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; 654 } caps; 655 phys_addr_t iseg_base; 656 struct mlx5_init_seg __iomem *iseg; 657 enum mlx5_device_state state; 658 /* sync interface state */ 659 struct mutex intf_state_mutex; 660 unsigned long intf_state; 661 void (*event) (struct mlx5_core_dev *dev, 662 enum mlx5_dev_event event, 663 unsigned long param); 664 struct mlx5_priv priv; 665 struct mlx5_profile *profile; 666 atomic_t num_qps; 667 u32 vsc_addr; 668 u32 issi; 669 struct mlx5_special_contexts special_contexts; 670 unsigned int module_status[MLX5_MAX_PORTS]; 671 struct mlx5_flow_root_namespace *root_ns; 672 struct mlx5_flow_root_namespace *fdb_root_ns; 673 struct mlx5_flow_root_namespace *esw_egress_root_ns; 674 struct mlx5_flow_root_namespace *esw_ingress_root_ns; 675 struct mlx5_flow_root_namespace *sniffer_rx_root_ns; 676 struct mlx5_flow_root_namespace *sniffer_tx_root_ns; 677 u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER]; 678 struct mlx5_dump_data *dump_data; 679 680 struct sysctl_ctx_list sysctl_ctx; 681 int msix_eqvec; 682 683 struct { 684 struct mlx5_rsvd_gids reserved_gids; 685 atomic_t roce_en; 686 } roce; 687#ifdef CONFIG_MLX5_FPGA 688 struct mlx5_fpga_device *fpga; 689#endif 690}; 691 692enum { 693 MLX5_WOL_DISABLE = 0, 694 MLX5_WOL_SECURED_MAGIC = 1 << 1, 695 MLX5_WOL_MAGIC = 1 << 2, 696 MLX5_WOL_ARP = 1 << 3, 697 MLX5_WOL_BROADCAST = 1 << 4, 698 MLX5_WOL_MULTICAST = 1 << 5, 699 MLX5_WOL_UNICAST = 1 << 6, 700 MLX5_WOL_PHY_ACTIVITY = 1 << 7, 701}; 702 703struct mlx5_db { 704 __be32 *db; 705 union { 706 struct mlx5_db_pgdir *pgdir; 707 struct mlx5_ib_user_db_page *user_page; 708 } u; 709 dma_addr_t dma; 710 int index; 711}; 712 713struct mlx5_net_counters { 714 u64 packets; 715 u64 octets; 716}; 717 718struct mlx5_ptys_reg { 719 u8 an_dis_admin; 720 u8 an_dis_ap; 721 u8 local_port; 722 u8 proto_mask; 723 u32 eth_proto_cap; 724 u16 ib_link_width_cap; 725 u16 ib_proto_cap; 726 u32 eth_proto_admin; 727 u16 ib_link_width_admin; 728 u16 ib_proto_admin; 729 u32 eth_proto_oper; 730 u16 ib_link_width_oper; 731 u16 ib_proto_oper; 732 u32 eth_proto_lp_advertise; 733}; 734 735struct mlx5_pvlc_reg { 736 u8 local_port; 737 u8 vl_hw_cap; 738 u8 vl_admin; 739 u8 vl_operational; 740}; 741 742struct mlx5_pmtu_reg { 743 u8 local_port; 744 u16 max_mtu; 745 u16 admin_mtu; 746 u16 oper_mtu; 747}; 748 749struct mlx5_vport_counters { 750 struct mlx5_net_counters received_errors; 751 struct mlx5_net_counters transmit_errors; 752 struct mlx5_net_counters received_ib_unicast; 753 struct mlx5_net_counters transmitted_ib_unicast; 754 struct mlx5_net_counters received_ib_multicast; 755 struct mlx5_net_counters transmitted_ib_multicast; 756 struct mlx5_net_counters received_eth_broadcast; 757 struct mlx5_net_counters transmitted_eth_broadcast; 758 struct mlx5_net_counters received_eth_unicast; 759 struct mlx5_net_counters transmitted_eth_unicast; 760 struct mlx5_net_counters received_eth_multicast; 761 struct mlx5_net_counters transmitted_eth_multicast; 762}; 763 764enum { 765 MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES, 766}; 767 768struct mlx5_core_dct { 769 struct mlx5_core_rsc_common common; /* must be first */ 770 void (*event)(struct mlx5_core_dct *, int); 771 int dctn; 772 struct completion drained; 773 struct mlx5_rsc_debug *dbg; 774 int pid; 775}; 776 777enum { 778 MLX5_COMP_EQ_SIZE = 1024, 779}; 780 781enum { 782 MLX5_PTYS_IB = 1 << 0, 783 MLX5_PTYS_EN = 1 << 2, 784}; 785 786struct mlx5_db_pgdir { 787 struct list_head list; 788 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE); 789 struct mlx5_fw_page *fw_page; 790 __be32 *db_page; 791 dma_addr_t db_dma; 792}; 793 794typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 795 796struct mlx5_cmd_work_ent { 797 struct mlx5_cmd_msg *in; 798 struct mlx5_cmd_msg *out; 799 int uin_size; 800 void *uout; 801 int uout_size; 802 mlx5_cmd_cbk_t callback; 803 struct delayed_work cb_timeout_work; 804 void *context; 805 int idx; 806 struct completion done; 807 struct mlx5_cmd *cmd; 808 struct work_struct work; 809 struct mlx5_cmd_layout *lay; 810 int ret; 811 int page_queue; 812 u8 status; 813 u8 token; 814 u64 ts1; 815 u64 ts2; 816 u16 op; 817 u8 busy; 818 bool polling; 819}; 820 821struct mlx5_pas { 822 u64 pa; 823 u8 log_sz; 824}; 825 826enum port_state_policy { 827 MLX5_POLICY_DOWN = 0, 828 MLX5_POLICY_UP = 1, 829 MLX5_POLICY_FOLLOW = 2, 830 MLX5_POLICY_INVALID = 0xffffffff 831}; 832 833static inline void * 834mlx5_buf_offset(struct mlx5_buf *buf, int offset) 835{ 836 return ((char *)buf->direct.buf + offset); 837} 838 839 840extern struct workqueue_struct *mlx5_core_wq; 841 842#define STRUCT_FIELD(header, field) \ 843 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 844 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 845 846static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 847{ 848 return pci_get_drvdata(pdev); 849} 850 851extern struct dentry *mlx5_debugfs_root; 852 853static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 854{ 855 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 856} 857 858static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 859{ 860 return ioread32be(&dev->iseg->fw_rev) >> 16; 861} 862 863static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 864{ 865 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 866} 867 868static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev) 869{ 870 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 871} 872 873static inline int mlx5_get_gid_table_len(u16 param) 874{ 875 if (param > 4) { 876 printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n"); 877 return 0; 878 } 879 880 return 8 * (1 << param); 881} 882 883static inline void *mlx5_vzalloc(unsigned long size) 884{ 885 void *rtn; 886 887 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); 888 return rtn; 889} 890 891static inline void *mlx5_vmalloc(unsigned long size) 892{ 893 void *rtn; 894 895 rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN); 896 if (!rtn) 897 rtn = vmalloc(size); 898 return rtn; 899} 900 901static inline u32 mlx5_base_mkey(const u32 key) 902{ 903 return key & 0xffffff00u; 904} 905 906int mlx5_cmd_init(struct mlx5_core_dev *dev); 907void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 908void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 909void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 910void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); 911int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); 912int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 913 int out_size); 914int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, 915 void *out, int out_size, mlx5_cmd_cbk_t callback, 916 void *context); 917int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, 918 void *out, int out_size); 919int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 920int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 921int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 922int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 923int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 924void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 925void mlx5_health_cleanup(struct mlx5_core_dev *dev); 926int mlx5_health_init(struct mlx5_core_dev *dev); 927void mlx5_start_health_poll(struct mlx5_core_dev *dev); 928void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health); 929void mlx5_drain_health_wq(struct mlx5_core_dev *dev); 930void mlx5_drain_health_recovery(struct mlx5_core_dev *dev); 931void mlx5_trigger_health_work(struct mlx5_core_dev *dev); 932 933#define mlx5_buf_alloc_node(dev, size, direct, buf, node) \ 934 mlx5_buf_alloc(dev, size, direct, buf) 935int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct, 936 struct mlx5_buf *buf); 937void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); 938int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 939 struct mlx5_srq_attr *in); 940int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); 941int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 942 struct mlx5_srq_attr *out); 943int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 944int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 945 u16 lwm, int is_srq); 946void mlx5_init_mr_table(struct mlx5_core_dev *dev); 947void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev); 948int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, 949 struct mlx5_core_mr *mkey, 950 u32 *in, int inlen, 951 u32 *out, int outlen, 952 mlx5_cmd_cbk_t callback, void *context); 953int mlx5_core_create_mkey(struct mlx5_core_dev *dev, 954 struct mlx5_core_mr *mr, 955 u32 *in, int inlen); 956int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey); 957int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey, 958 u32 *out, int outlen); 959int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 960 u32 *mkey); 961int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 962int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 963int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, 964 u16 opmod, u8 port); 965void mlx5_fwp_flush(struct mlx5_fw_page *fwp); 966void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp); 967struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num); 968void mlx5_fwp_free(struct mlx5_fw_page *fwp); 969u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset); 970void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset); 971void mlx5_pagealloc_init(struct mlx5_core_dev *dev); 972void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 973int mlx5_pagealloc_start(struct mlx5_core_dev *dev); 974void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 975void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 976 s32 npages); 977int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 978int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 979s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev); 980void mlx5_register_debugfs(void); 981void mlx5_unregister_debugfs(void); 982int mlx5_eq_init(struct mlx5_core_dev *dev); 983void mlx5_eq_cleanup(struct mlx5_core_dev *dev); 984void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); 985void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); 986void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); 987void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); 988struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); 989void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vector, enum mlx5_cmd_mode mode); 990void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); 991int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 992 int nent, u64 mask, const char *name, struct mlx5_uar *uar); 993int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 994int mlx5_start_eqs(struct mlx5_core_dev *dev); 995int mlx5_stop_eqs(struct mlx5_core_dev *dev); 996int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn); 997int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 998int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 999int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable, 1000 u64 addr); 1001 1002int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 1003void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 1004int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 1005 int size_in, void *data_out, int size_out, 1006 u16 reg_num, int arg, int write); 1007 1008void mlx5_toggle_port_link(struct mlx5_core_dev *dev); 1009 1010int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1011void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1012int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 1013 u32 *out, int outlen); 1014int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); 1015void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); 1016int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); 1017void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); 1018int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 1019int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 1020 int node); 1021void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 1022 1023const char *mlx5_command_str(int command); 1024int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 1025void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 1026int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 1027 int npsvs, u32 *sig_index); 1028int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 1029void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 1030u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev); 1031int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode); 1032int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout); 1033int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout); 1034int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode); 1035int mlx5_core_access_pvlc(struct mlx5_core_dev *dev, 1036 struct mlx5_pvlc_reg *pvlc, int write); 1037int mlx5_core_access_ptys(struct mlx5_core_dev *dev, 1038 struct mlx5_ptys_reg *ptys, int write); 1039int mlx5_core_access_pmtu(struct mlx5_core_dev *dev, 1040 struct mlx5_pmtu_reg *pmtu, int write); 1041int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port); 1042int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port); 1043int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 1044 int priority, int *is_enable); 1045int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 1046 int priority, int enable); 1047int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol, 1048 void *out, int out_size); 1049int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev, 1050 void *in, int in_size); 1051int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear, 1052 void *out, int out_size); 1053int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in, 1054 int in_size); 1055int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev, 1056 u8 num_of_samples, u16 sample_index, 1057 void *out, int out_size); 1058int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev); 1059int mlx5_vsc_lock(struct mlx5_core_dev *mdev); 1060void mlx5_vsc_unlock(struct mlx5_core_dev *mdev); 1061int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space); 1062int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, const u32 *data); 1063int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data); 1064int mlx5_vsc_lock_addr_space(struct mlx5_core_dev *mdev, u32 addr); 1065int mlx5_vsc_unlock_addr_space(struct mlx5_core_dev *mdev, u32 addr); 1066 1067static inline u32 mlx5_mkey_to_idx(u32 mkey) 1068{ 1069 return mkey >> 8; 1070} 1071 1072static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 1073{ 1074 return mkey_idx << 8; 1075} 1076 1077static inline u8 mlx5_mkey_variant(u32 mkey) 1078{ 1079 return mkey & 0xff; 1080} 1081 1082enum { 1083 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 1084 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 1085}; 1086 1087enum { 1088 MAX_MR_CACHE_ENTRIES = 15, 1089}; 1090 1091struct mlx5_interface { 1092 void * (*add)(struct mlx5_core_dev *dev); 1093 void (*remove)(struct mlx5_core_dev *dev, void *context); 1094 void (*event)(struct mlx5_core_dev *dev, void *context, 1095 enum mlx5_dev_event event, unsigned long param); 1096 void * (*get_dev)(void *context); 1097 int protocol; 1098 struct list_head list; 1099}; 1100 1101void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); 1102int mlx5_register_interface(struct mlx5_interface *intf); 1103void mlx5_unregister_interface(struct mlx5_interface *intf); 1104 1105unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); 1106int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, 1107 u8 roce_version, u8 roce_l3_type, const u8 *gid, 1108 const u8 *mac, bool vlan, u16 vlan_id); 1109 1110struct mlx5_profile { 1111 u64 mask; 1112 u8 log_max_qp; 1113 struct { 1114 int size; 1115 int limit; 1116 } mr_cache[MAX_MR_CACHE_ENTRIES]; 1117}; 1118 1119enum { 1120 MLX5_PCI_DEV_IS_VF = 1 << 0, 1121}; 1122 1123enum { 1124 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, 1125}; 1126 1127static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) 1128{ 1129 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); 1130} 1131 1132#endif /* MLX5_DRIVER_H */ 1133