driver.h revision 331586
1/*- 2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/mlx5/driver.h 331586 2018-03-26 20:59:26Z hselasky $ 26 */ 27 28#ifndef MLX5_DRIVER_H 29#define MLX5_DRIVER_H 30 31#include <linux/kernel.h> 32#include <linux/completion.h> 33#include <linux/pci.h> 34#include <linux/cache.h> 35#include <linux/rbtree.h> 36#include <linux/if_ether.h> 37#include <linux/semaphore.h> 38#include <linux/slab.h> 39#include <linux/vmalloc.h> 40#include <linux/radix-tree.h> 41 42#include <dev/mlx5/device.h> 43#include <dev/mlx5/doorbell.h> 44 45#define MLX5_QCOUNTER_SETS_NETDEV 64 46#define MLX5_MAX_NUMBER_OF_VFS 128 47 48enum { 49 MLX5_BOARD_ID_LEN = 64, 50 MLX5_MAX_NAME_LEN = 16, 51}; 52 53enum { 54 MLX5_CMD_TIMEOUT_MSEC = 8 * 60 * 1000, 55 MLX5_CMD_WQ_MAX_NAME = 32, 56}; 57 58enum { 59 CMD_OWNER_SW = 0x0, 60 CMD_OWNER_HW = 0x1, 61 CMD_STATUS_SUCCESS = 0, 62}; 63 64enum mlx5_sqp_t { 65 MLX5_SQP_SMI = 0, 66 MLX5_SQP_GSI = 1, 67 MLX5_SQP_IEEE_1588 = 2, 68 MLX5_SQP_SNIFFER = 3, 69 MLX5_SQP_SYNC_UMR = 4, 70}; 71 72enum { 73 MLX5_MAX_PORTS = 2, 74}; 75 76enum { 77 MLX5_EQ_VEC_PAGES = 0, 78 MLX5_EQ_VEC_CMD = 1, 79 MLX5_EQ_VEC_ASYNC = 2, 80 MLX5_EQ_VEC_COMP_BASE, 81}; 82 83enum { 84 MLX5_MAX_IRQ_NAME = 32 85}; 86 87enum { 88 MLX5_ATOMIC_MODE_OFF = 16, 89 MLX5_ATOMIC_MODE_NONE = 0 << MLX5_ATOMIC_MODE_OFF, 90 MLX5_ATOMIC_MODE_IB_COMP = 1 << MLX5_ATOMIC_MODE_OFF, 91 MLX5_ATOMIC_MODE_CX = 2 << MLX5_ATOMIC_MODE_OFF, 92 MLX5_ATOMIC_MODE_8B = 3 << MLX5_ATOMIC_MODE_OFF, 93 MLX5_ATOMIC_MODE_16B = 4 << MLX5_ATOMIC_MODE_OFF, 94 MLX5_ATOMIC_MODE_32B = 5 << MLX5_ATOMIC_MODE_OFF, 95 MLX5_ATOMIC_MODE_64B = 6 << MLX5_ATOMIC_MODE_OFF, 96 MLX5_ATOMIC_MODE_128B = 7 << MLX5_ATOMIC_MODE_OFF, 97 MLX5_ATOMIC_MODE_256B = 8 << MLX5_ATOMIC_MODE_OFF, 98}; 99 100enum { 101 MLX5_ATOMIC_MODE_DCT_OFF = 20, 102 MLX5_ATOMIC_MODE_DCT_NONE = 0 << MLX5_ATOMIC_MODE_DCT_OFF, 103 MLX5_ATOMIC_MODE_DCT_IB_COMP = 1 << MLX5_ATOMIC_MODE_DCT_OFF, 104 MLX5_ATOMIC_MODE_DCT_CX = 2 << MLX5_ATOMIC_MODE_DCT_OFF, 105 MLX5_ATOMIC_MODE_DCT_8B = 3 << MLX5_ATOMIC_MODE_DCT_OFF, 106 MLX5_ATOMIC_MODE_DCT_16B = 4 << MLX5_ATOMIC_MODE_DCT_OFF, 107 MLX5_ATOMIC_MODE_DCT_32B = 5 << MLX5_ATOMIC_MODE_DCT_OFF, 108 MLX5_ATOMIC_MODE_DCT_64B = 6 << MLX5_ATOMIC_MODE_DCT_OFF, 109 MLX5_ATOMIC_MODE_DCT_128B = 7 << MLX5_ATOMIC_MODE_DCT_OFF, 110 MLX5_ATOMIC_MODE_DCT_256B = 8 << MLX5_ATOMIC_MODE_DCT_OFF, 111}; 112 113enum { 114 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, 115 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, 116 MLX5_ATOMIC_OPS_MASKED_CMP_SWAP = 1 << 2, 117 MLX5_ATOMIC_OPS_MASKED_FETCH_ADD = 1 << 3, 118}; 119 120enum { 121 MLX5_REG_QETCR = 0x4005, 122 MLX5_REG_QPDP = 0x4007, 123 MLX5_REG_QTCT = 0x400A, 124 MLX5_REG_QHLL = 0x4016, 125 MLX5_REG_DCBX_PARAM = 0x4020, 126 MLX5_REG_DCBX_APP = 0x4021, 127 MLX5_REG_PCAP = 0x5001, 128 MLX5_REG_PMTU = 0x5003, 129 MLX5_REG_PTYS = 0x5004, 130 MLX5_REG_PAOS = 0x5006, 131 MLX5_REG_PFCC = 0x5007, 132 MLX5_REG_PPCNT = 0x5008, 133 MLX5_REG_PMAOS = 0x5012, 134 MLX5_REG_PUDE = 0x5009, 135 MLX5_REG_PPTB = 0x500B, 136 MLX5_REG_PBMC = 0x500C, 137 MLX5_REG_PMPE = 0x5010, 138 MLX5_REG_PELC = 0x500e, 139 MLX5_REG_PVLC = 0x500f, 140 MLX5_REG_PMLP = 0x5002, 141 MLX5_REG_NODE_DESC = 0x6001, 142 MLX5_REG_HOST_ENDIANNESS = 0x7004, 143 MLX5_REG_MCIA = 0x9014, 144 MLX5_REG_MPCNT = 0x9051, 145}; 146 147enum dbg_rsc_type { 148 MLX5_DBG_RSC_QP, 149 MLX5_DBG_RSC_EQ, 150 MLX5_DBG_RSC_CQ, 151}; 152 153enum { 154 MLX5_INTERFACE_PROTOCOL_IB = 0, 155 MLX5_INTERFACE_PROTOCOL_ETH = 1, 156 MLX5_INTERFACE_NUMBER = 2, 157}; 158 159struct mlx5_field_desc { 160 struct dentry *dent; 161 int i; 162}; 163 164struct mlx5_rsc_debug { 165 struct mlx5_core_dev *dev; 166 void *object; 167 enum dbg_rsc_type type; 168 struct dentry *root; 169 struct mlx5_field_desc fields[0]; 170}; 171 172enum mlx5_dev_event { 173 MLX5_DEV_EVENT_SYS_ERROR, 174 MLX5_DEV_EVENT_PORT_UP, 175 MLX5_DEV_EVENT_PORT_DOWN, 176 MLX5_DEV_EVENT_PORT_INITIALIZED, 177 MLX5_DEV_EVENT_LID_CHANGE, 178 MLX5_DEV_EVENT_PKEY_CHANGE, 179 MLX5_DEV_EVENT_GUID_CHANGE, 180 MLX5_DEV_EVENT_CLIENT_REREG, 181 MLX5_DEV_EVENT_VPORT_CHANGE, 182 MLX5_DEV_EVENT_ERROR_STATE_DCBX, 183 MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE, 184 MLX5_DEV_EVENT_LOCAL_OPER_CHANGE, 185 MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE, 186}; 187 188enum mlx5_port_status { 189 MLX5_PORT_UP = 1 << 0, 190 MLX5_PORT_DOWN = 1 << 1, 191}; 192 193enum mlx5_link_mode { 194 MLX5_1000BASE_CX_SGMII = 0, 195 MLX5_1000BASE_KX = 1, 196 MLX5_10GBASE_CX4 = 2, 197 MLX5_10GBASE_KX4 = 3, 198 MLX5_10GBASE_KR = 4, 199 MLX5_20GBASE_KR2 = 5, 200 MLX5_40GBASE_CR4 = 6, 201 MLX5_40GBASE_KR4 = 7, 202 MLX5_56GBASE_R4 = 8, 203 MLX5_10GBASE_CR = 12, 204 MLX5_10GBASE_SR = 13, 205 MLX5_10GBASE_ER = 14, 206 MLX5_40GBASE_SR4 = 15, 207 MLX5_40GBASE_LR4 = 16, 208 MLX5_100GBASE_CR4 = 20, 209 MLX5_100GBASE_SR4 = 21, 210 MLX5_100GBASE_KR4 = 22, 211 MLX5_100GBASE_LR4 = 23, 212 MLX5_100BASE_TX = 24, 213 MLX5_1000BASE_T = 25, 214 MLX5_10GBASE_T = 26, 215 MLX5_25GBASE_CR = 27, 216 MLX5_25GBASE_KR = 28, 217 MLX5_25GBASE_SR = 29, 218 MLX5_50GBASE_CR2 = 30, 219 MLX5_50GBASE_KR2 = 31, 220 MLX5_LINK_MODES_NUMBER, 221}; 222 223enum { 224 MLX5_VSC_SPACE_SUPPORTED = 0x1, 225 MLX5_VSC_SPACE_OFFSET = 0x4, 226 MLX5_VSC_COUNTER_OFFSET = 0x8, 227 MLX5_VSC_SEMA_OFFSET = 0xC, 228 MLX5_VSC_ADDR_OFFSET = 0x10, 229 MLX5_VSC_DATA_OFFSET = 0x14, 230 MLX5_VSC_MAX_RETRIES = 0x1000, 231}; 232 233#define MLX5_PROT_MASK(link_mode) (1 << link_mode) 234 235struct mlx5_uuar_info { 236 struct mlx5_uar *uars; 237 int num_uars; 238 int num_low_latency_uuars; 239 unsigned long *bitmap; 240 unsigned int *count; 241 struct mlx5_bf *bfs; 242 243 /* 244 * protect uuar allocation data structs 245 */ 246 struct mutex lock; 247 u32 ver; 248}; 249 250struct mlx5_bf { 251 void __iomem *reg; 252 void __iomem *regreg; 253 int buf_size; 254 struct mlx5_uar *uar; 255 unsigned long offset; 256 int need_lock; 257 /* protect blue flame buffer selection when needed 258 */ 259 spinlock_t lock; 260 261 /* serialize 64 bit writes when done as two 32 bit accesses 262 */ 263 spinlock_t lock32; 264 int uuarn; 265}; 266 267struct mlx5_cmd_first { 268 __be32 data[4]; 269}; 270 271struct cache_ent; 272struct mlx5_fw_page { 273 union { 274 struct rb_node rb_node; 275 struct list_head list; 276 }; 277 struct mlx5_cmd_first first; 278 struct mlx5_core_dev *dev; 279 bus_dmamap_t dma_map; 280 bus_addr_t dma_addr; 281 void *virt_addr; 282 struct cache_ent *cache; 283 u32 numpages; 284 u16 load_done; 285#define MLX5_LOAD_ST_NONE 0 286#define MLX5_LOAD_ST_SUCCESS 1 287#define MLX5_LOAD_ST_FAILURE 2 288 u16 func_id; 289}; 290#define mlx5_cmd_msg mlx5_fw_page 291 292struct mlx5_cmd_debug { 293 struct dentry *dbg_root; 294 struct dentry *dbg_in; 295 struct dentry *dbg_out; 296 struct dentry *dbg_outlen; 297 struct dentry *dbg_status; 298 struct dentry *dbg_run; 299 void *in_msg; 300 void *out_msg; 301 u8 status; 302 u16 inlen; 303 u16 outlen; 304}; 305 306struct cache_ent { 307 /* protect block chain allocations 308 */ 309 spinlock_t lock; 310 struct list_head head; 311}; 312 313struct cmd_msg_cache { 314 struct cache_ent large; 315 struct cache_ent med; 316 317}; 318 319struct mlx5_traffic_counter { 320 u64 packets; 321 u64 octets; 322}; 323 324struct mlx5_cmd_stats { 325 u64 sum; 326 u64 n; 327 struct dentry *root; 328 struct dentry *avg; 329 struct dentry *count; 330 /* protect command average calculations */ 331 spinlock_t lock; 332}; 333 334struct mlx5_cmd { 335 struct mlx5_fw_page *cmd_page; 336 bus_dma_tag_t dma_tag; 337 struct sx dma_sx; 338 struct mtx dma_mtx; 339#define MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx) 340#define MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx) 341#define MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx) 342 struct cv dma_cv; 343#define MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv) 344#define MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx) 345 void *cmd_buf; 346 dma_addr_t dma; 347 u16 cmdif_rev; 348 u8 log_sz; 349 u8 log_stride; 350 int max_reg_cmds; 351 int events; 352 u32 __iomem *vector; 353 354 /* protect command queue allocations 355 */ 356 spinlock_t alloc_lock; 357 358 /* protect token allocations 359 */ 360 spinlock_t token_lock; 361 u8 token; 362 unsigned long bitmask; 363 char wq_name[MLX5_CMD_WQ_MAX_NAME]; 364 struct workqueue_struct *wq; 365 struct semaphore sem; 366 struct semaphore pages_sem; 367 int mode; 368 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; 369 struct mlx5_cmd_debug dbg; 370 struct cmd_msg_cache cache; 371 int checksum_disabled; 372 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 373 int moving_to_polling; 374}; 375 376struct mlx5_port_caps { 377 int gid_table_len; 378 int pkey_table_len; 379 u8 ext_port_cap; 380}; 381 382struct mlx5_buf { 383 bus_dma_tag_t dma_tag; 384 bus_dmamap_t dma_map; 385 struct mlx5_core_dev *dev; 386 struct { 387 void *buf; 388 } direct; 389 u64 *page_list; 390 int npages; 391 int size; 392 u8 page_shift; 393 u8 load_done; 394}; 395 396struct mlx5_eq { 397 struct mlx5_core_dev *dev; 398 __be32 __iomem *doorbell; 399 u32 cons_index; 400 struct mlx5_buf buf; 401 int size; 402 u8 irqn; 403 u8 eqn; 404 int nent; 405 u64 mask; 406 struct list_head list; 407 int index; 408 struct mlx5_rsc_debug *dbg; 409}; 410 411struct mlx5_core_psv { 412 u32 psv_idx; 413 struct psv_layout { 414 u32 pd; 415 u16 syndrome; 416 u16 reserved; 417 u16 bg; 418 u16 app_tag; 419 u32 ref_tag; 420 } psv; 421}; 422 423struct mlx5_core_sig_ctx { 424 struct mlx5_core_psv psv_memory; 425 struct mlx5_core_psv psv_wire; 426#if (__FreeBSD_version >= 1100000) 427 struct ib_sig_err err_item; 428#endif 429 bool sig_status_checked; 430 bool sig_err_exists; 431 u32 sigerr_count; 432}; 433 434struct mlx5_core_mr { 435 u64 iova; 436 u64 size; 437 u32 key; 438 u32 pd; 439}; 440 441enum mlx5_res_type { 442 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, 443 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, 444 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, 445 MLX5_RES_SRQ = 3, 446 MLX5_RES_XSRQ = 4, 447 MLX5_RES_DCT = 5, 448}; 449 450struct mlx5_core_rsc_common { 451 enum mlx5_res_type res; 452 atomic_t refcount; 453 struct completion free; 454}; 455 456struct mlx5_core_srq { 457 struct mlx5_core_rsc_common common; /* must be first */ 458 u32 srqn; 459 int max; 460 int max_gs; 461 int max_avail_gather; 462 int wqe_shift; 463 void (*event)(struct mlx5_core_srq *, int); 464 atomic_t refcount; 465 struct completion free; 466}; 467 468struct mlx5_eq_table { 469 void __iomem *update_ci; 470 void __iomem *update_arm_ci; 471 struct list_head comp_eqs_list; 472 struct mlx5_eq pages_eq; 473 struct mlx5_eq async_eq; 474 struct mlx5_eq cmd_eq; 475 int num_comp_vectors; 476 /* protect EQs list 477 */ 478 spinlock_t lock; 479}; 480 481struct mlx5_uar { 482 u32 index; 483 void __iomem *bf_map; 484 void __iomem *map; 485}; 486 487 488struct mlx5_core_health { 489 struct mlx5_health_buffer __iomem *health; 490 __be32 __iomem *health_counter; 491 struct timer_list timer; 492 u32 prev; 493 int miss_counter; 494 bool sick; 495 /* wq spinlock to synchronize draining */ 496 spinlock_t wq_lock; 497 struct workqueue_struct *wq; 498 unsigned long flags; 499 struct work_struct work; 500}; 501 502#define MLX5_CQ_LINEAR_ARRAY_SIZE 1024 503 504struct mlx5_cq_linear_array_entry { 505 spinlock_t lock; 506 struct mlx5_core_cq * volatile cq; 507}; 508 509struct mlx5_cq_table { 510 /* protect radix tree 511 */ 512 spinlock_t lock; 513 struct radix_tree_root tree; 514 struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE]; 515}; 516 517struct mlx5_qp_table { 518 /* protect radix tree 519 */ 520 spinlock_t lock; 521 struct radix_tree_root tree; 522}; 523 524struct mlx5_srq_table { 525 /* protect radix tree 526 */ 527 spinlock_t lock; 528 struct radix_tree_root tree; 529}; 530 531struct mlx5_mr_table { 532 /* protect radix tree 533 */ 534 spinlock_t lock; 535 struct radix_tree_root tree; 536}; 537 538struct mlx5_irq_info { 539 char name[MLX5_MAX_IRQ_NAME]; 540}; 541 542struct mlx5_priv { 543 char name[MLX5_MAX_NAME_LEN]; 544 struct mlx5_eq_table eq_table; 545 struct msix_entry *msix_arr; 546 struct mlx5_irq_info *irq_info; 547 struct mlx5_uuar_info uuari; 548 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock); 549 550 struct io_mapping *bf_mapping; 551 552 /* pages stuff */ 553 struct workqueue_struct *pg_wq; 554 struct rb_root page_root; 555 s64 fw_pages; 556 atomic_t reg_pages; 557 s64 pages_per_func[MLX5_MAX_NUMBER_OF_VFS]; 558 struct mlx5_core_health health; 559 560 struct mlx5_srq_table srq_table; 561 562 /* start: qp staff */ 563 struct mlx5_qp_table qp_table; 564 struct dentry *qp_debugfs; 565 struct dentry *eq_debugfs; 566 struct dentry *cq_debugfs; 567 struct dentry *cmdif_debugfs; 568 /* end: qp staff */ 569 570 /* start: cq staff */ 571 struct mlx5_cq_table cq_table; 572 /* end: cq staff */ 573 574 /* start: mr staff */ 575 struct mlx5_mr_table mr_table; 576 /* end: mr staff */ 577 578 /* start: alloc staff */ 579 int numa_node; 580 581 struct mutex pgdir_mutex; 582 struct list_head pgdir_list; 583 /* end: alloc staff */ 584 struct dentry *dbg_root; 585 586 /* protect mkey key part */ 587 spinlock_t mkey_lock; 588 u8 mkey_key; 589 590 struct list_head dev_list; 591 struct list_head ctx_list; 592 spinlock_t ctx_lock; 593 unsigned long pci_dev_data; 594}; 595 596enum mlx5_device_state { 597 MLX5_DEVICE_STATE_UP, 598 MLX5_DEVICE_STATE_INTERNAL_ERROR, 599}; 600 601enum mlx5_interface_state { 602 MLX5_INTERFACE_STATE_DOWN = BIT(0), 603 MLX5_INTERFACE_STATE_UP = BIT(1), 604 MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2), 605}; 606 607enum mlx5_pci_status { 608 MLX5_PCI_STATUS_DISABLED, 609 MLX5_PCI_STATUS_ENABLED, 610}; 611 612struct mlx5_special_contexts { 613 int resd_lkey; 614}; 615 616struct mlx5_flow_root_namespace; 617struct mlx5_dump_data; 618struct mlx5_core_dev { 619 struct pci_dev *pdev; 620 /* sync pci state */ 621 struct mutex pci_status_mutex; 622 enum mlx5_pci_status pci_status; 623 char board_id[MLX5_BOARD_ID_LEN]; 624 struct mlx5_cmd cmd; 625 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 626 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 627 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 628 phys_addr_t iseg_base; 629 struct mlx5_init_seg __iomem *iseg; 630 enum mlx5_device_state state; 631 /* sync interface state */ 632 struct mutex intf_state_mutex; 633 unsigned long intf_state; 634 void (*event) (struct mlx5_core_dev *dev, 635 enum mlx5_dev_event event, 636 unsigned long param); 637 struct mlx5_priv priv; 638 struct mlx5_profile *profile; 639 atomic_t num_qps; 640 u32 vsc_addr; 641 u32 issi; 642 struct mlx5_special_contexts special_contexts; 643 unsigned int module_status[MLX5_MAX_PORTS]; 644 struct mlx5_flow_root_namespace *root_ns; 645 struct mlx5_flow_root_namespace *fdb_root_ns; 646 struct mlx5_flow_root_namespace *esw_egress_root_ns; 647 struct mlx5_flow_root_namespace *esw_ingress_root_ns; 648 struct mlx5_flow_root_namespace *sniffer_rx_root_ns; 649 struct mlx5_flow_root_namespace *sniffer_tx_root_ns; 650 u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER]; 651 struct mlx5_dump_data *dump_data; 652}; 653 654enum { 655 MLX5_WOL_DISABLE = 0, 656 MLX5_WOL_SECURED_MAGIC = 1 << 1, 657 MLX5_WOL_MAGIC = 1 << 2, 658 MLX5_WOL_ARP = 1 << 3, 659 MLX5_WOL_BROADCAST = 1 << 4, 660 MLX5_WOL_MULTICAST = 1 << 5, 661 MLX5_WOL_UNICAST = 1 << 6, 662 MLX5_WOL_PHY_ACTIVITY = 1 << 7, 663}; 664 665struct mlx5_db { 666 __be32 *db; 667 union { 668 struct mlx5_db_pgdir *pgdir; 669 struct mlx5_ib_user_db_page *user_page; 670 } u; 671 dma_addr_t dma; 672 int index; 673}; 674 675struct mlx5_net_counters { 676 u64 packets; 677 u64 octets; 678}; 679 680struct mlx5_ptys_reg { 681 u8 an_dis_admin; 682 u8 an_dis_ap; 683 u8 local_port; 684 u8 proto_mask; 685 u32 eth_proto_cap; 686 u16 ib_link_width_cap; 687 u16 ib_proto_cap; 688 u32 eth_proto_admin; 689 u16 ib_link_width_admin; 690 u16 ib_proto_admin; 691 u32 eth_proto_oper; 692 u16 ib_link_width_oper; 693 u16 ib_proto_oper; 694 u32 eth_proto_lp_advertise; 695}; 696 697struct mlx5_pvlc_reg { 698 u8 local_port; 699 u8 vl_hw_cap; 700 u8 vl_admin; 701 u8 vl_operational; 702}; 703 704struct mlx5_pmtu_reg { 705 u8 local_port; 706 u16 max_mtu; 707 u16 admin_mtu; 708 u16 oper_mtu; 709}; 710 711struct mlx5_vport_counters { 712 struct mlx5_net_counters received_errors; 713 struct mlx5_net_counters transmit_errors; 714 struct mlx5_net_counters received_ib_unicast; 715 struct mlx5_net_counters transmitted_ib_unicast; 716 struct mlx5_net_counters received_ib_multicast; 717 struct mlx5_net_counters transmitted_ib_multicast; 718 struct mlx5_net_counters received_eth_broadcast; 719 struct mlx5_net_counters transmitted_eth_broadcast; 720 struct mlx5_net_counters received_eth_unicast; 721 struct mlx5_net_counters transmitted_eth_unicast; 722 struct mlx5_net_counters received_eth_multicast; 723 struct mlx5_net_counters transmitted_eth_multicast; 724}; 725 726enum { 727 MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES, 728}; 729 730struct mlx5_core_dct { 731 struct mlx5_core_rsc_common common; /* must be first */ 732 void (*event)(struct mlx5_core_dct *, int); 733 int dctn; 734 struct completion drained; 735 struct mlx5_rsc_debug *dbg; 736 int pid; 737}; 738 739enum { 740 MLX5_COMP_EQ_SIZE = 1024, 741}; 742 743enum { 744 MLX5_PTYS_IB = 1 << 0, 745 MLX5_PTYS_EN = 1 << 2, 746}; 747 748struct mlx5_db_pgdir { 749 struct list_head list; 750 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE); 751 struct mlx5_fw_page *fw_page; 752 __be32 *db_page; 753 dma_addr_t db_dma; 754}; 755 756typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 757 758struct mlx5_cmd_work_ent { 759 struct mlx5_cmd_msg *in; 760 struct mlx5_cmd_msg *out; 761 int uin_size; 762 void *uout; 763 int uout_size; 764 mlx5_cmd_cbk_t callback; 765 struct delayed_work cb_timeout_work; 766 void *context; 767 int idx; 768 struct completion done; 769 struct mlx5_cmd *cmd; 770 struct work_struct work; 771 struct mlx5_cmd_layout *lay; 772 int ret; 773 int page_queue; 774 u8 status; 775 u8 token; 776 u64 ts1; 777 u64 ts2; 778 u16 op; 779 u8 busy; 780}; 781 782struct mlx5_pas { 783 u64 pa; 784 u8 log_sz; 785}; 786 787enum port_state_policy { 788 MLX5_POLICY_DOWN = 0, 789 MLX5_POLICY_UP = 1, 790 MLX5_POLICY_FOLLOW = 2, 791 MLX5_POLICY_INVALID = 0xffffffff 792}; 793 794static inline void * 795mlx5_buf_offset(struct mlx5_buf *buf, int offset) 796{ 797 return ((char *)buf->direct.buf + offset); 798} 799 800 801extern struct workqueue_struct *mlx5_core_wq; 802 803#define STRUCT_FIELD(header, field) \ 804 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 805 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 806 807static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 808{ 809 return pci_get_drvdata(pdev); 810} 811 812extern struct dentry *mlx5_debugfs_root; 813 814static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 815{ 816 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 817} 818 819static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 820{ 821 return ioread32be(&dev->iseg->fw_rev) >> 16; 822} 823 824static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 825{ 826 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 827} 828 829static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev) 830{ 831 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 832} 833 834static inline int mlx5_get_gid_table_len(u16 param) 835{ 836 if (param > 4) { 837 printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n"); 838 return 0; 839 } 840 841 return 8 * (1 << param); 842} 843 844static inline void *mlx5_vzalloc(unsigned long size) 845{ 846 void *rtn; 847 848 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); 849 return rtn; 850} 851 852static inline void *mlx5_vmalloc(unsigned long size) 853{ 854 void *rtn; 855 856 rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN); 857 if (!rtn) 858 rtn = vmalloc(size); 859 return rtn; 860} 861 862static inline u32 mlx5_base_mkey(const u32 key) 863{ 864 return key & 0xffffff00u; 865} 866 867int mlx5_cmd_init(struct mlx5_core_dev *dev); 868void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 869void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 870void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 871int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr); 872int mlx5_cmd_status_to_err_v2(void *ptr); 873int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type, 874 enum mlx5_cap_mode cap_mode); 875int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 876 int out_size); 877int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, 878 void *out, int out_size, mlx5_cmd_cbk_t callback, 879 void *context); 880int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 881int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 882int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 883int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 884int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 885void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); 886void mlx5_health_cleanup(struct mlx5_core_dev *dev); 887int mlx5_health_init(struct mlx5_core_dev *dev); 888void mlx5_start_health_poll(struct mlx5_core_dev *dev); 889void mlx5_stop_health_poll(struct mlx5_core_dev *dev); 890void mlx5_drain_health_wq(struct mlx5_core_dev *dev); 891 892#define mlx5_buf_alloc_node(dev, size, direct, buf, node) \ 893 mlx5_buf_alloc(dev, size, direct, buf) 894int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct, 895 struct mlx5_buf *buf); 896void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); 897int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 898 struct mlx5_create_srq_mbox_in *in, int inlen, 899 int is_xrc); 900int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); 901int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 902 struct mlx5_query_srq_mbox_out *out); 903int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 904int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 905 u16 lwm, int is_srq); 906void mlx5_init_mr_table(struct mlx5_core_dev *dev); 907void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev); 908int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 909 struct mlx5_create_mkey_mbox_in *in, int inlen, 910 mlx5_cmd_cbk_t callback, void *context, 911 struct mlx5_create_mkey_mbox_out *out); 912int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr); 913int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 914 struct mlx5_query_mkey_mbox_out *out, int outlen); 915int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, 916 u32 *mkey); 917int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 918int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); 919int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, 920 u16 opmod, u8 port); 921void mlx5_fwp_flush(struct mlx5_fw_page *fwp); 922void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp); 923struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num); 924void mlx5_fwp_free(struct mlx5_fw_page *fwp); 925u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset); 926void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset); 927void mlx5_pagealloc_init(struct mlx5_core_dev *dev); 928void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 929int mlx5_pagealloc_start(struct mlx5_core_dev *dev); 930void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 931void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 932 s32 npages); 933int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 934int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 935s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev); 936void mlx5_register_debugfs(void); 937void mlx5_unregister_debugfs(void); 938int mlx5_eq_init(struct mlx5_core_dev *dev); 939void mlx5_eq_cleanup(struct mlx5_core_dev *dev); 940void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); 941void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); 942void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); 943void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); 944struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); 945void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u32 vector); 946void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); 947int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 948 int nent, u64 mask, const char *name, struct mlx5_uar *uar); 949int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 950int mlx5_start_eqs(struct mlx5_core_dev *dev); 951int mlx5_stop_eqs(struct mlx5_core_dev *dev); 952int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn); 953int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 954int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 955int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable, 956 u64 addr); 957 958int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 959void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 960int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 961 int size_in, void *data_out, int size_out, 962 u16 reg_num, int arg, int write); 963 964void mlx5_toggle_port_link(struct mlx5_core_dev *dev); 965 966int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 967void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 968int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 969 struct mlx5_query_eq_mbox_out *out, int outlen); 970int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); 971void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); 972int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); 973void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); 974int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 975int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, 976 int node); 977void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 978 979const char *mlx5_command_str(int command); 980int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 981void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 982int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 983 int npsvs, u32 *sig_index); 984int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 985void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 986u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev); 987int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode); 988int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout); 989int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout); 990int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode); 991int mlx5_core_access_pvlc(struct mlx5_core_dev *dev, 992 struct mlx5_pvlc_reg *pvlc, int write); 993int mlx5_core_access_ptys(struct mlx5_core_dev *dev, 994 struct mlx5_ptys_reg *ptys, int write); 995int mlx5_core_access_pmtu(struct mlx5_core_dev *dev, 996 struct mlx5_pmtu_reg *pmtu, int write); 997int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port); 998int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port); 999int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 1000 int priority, int *is_enable); 1001int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 1002 int priority, int enable); 1003int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol, 1004 void *out, int out_size); 1005int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev, 1006 void *in, int in_size); 1007int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear, 1008 void *out, int out_size); 1009int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in, 1010 int in_size); 1011int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev, 1012 u8 num_of_samples, u16 sample_index, 1013 void *out, int out_size); 1014int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev); 1015int mlx5_vsc_lock(struct mlx5_core_dev *mdev); 1016void mlx5_vsc_unlock(struct mlx5_core_dev *mdev); 1017int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space); 1018int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, u32 *data); 1019int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data); 1020static inline u32 mlx5_mkey_to_idx(u32 mkey) 1021{ 1022 return mkey >> 8; 1023} 1024 1025static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 1026{ 1027 return mkey_idx << 8; 1028} 1029 1030static inline u8 mlx5_mkey_variant(u32 mkey) 1031{ 1032 return mkey & 0xff; 1033} 1034 1035enum { 1036 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 1037 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 1038}; 1039 1040enum { 1041 MAX_MR_CACHE_ENTRIES = 15, 1042}; 1043 1044struct mlx5_interface { 1045 void * (*add)(struct mlx5_core_dev *dev); 1046 void (*remove)(struct mlx5_core_dev *dev, void *context); 1047 void (*event)(struct mlx5_core_dev *dev, void *context, 1048 enum mlx5_dev_event event, unsigned long param); 1049 void * (*get_dev)(void *context); 1050 int protocol; 1051 struct list_head list; 1052}; 1053 1054void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); 1055int mlx5_register_interface(struct mlx5_interface *intf); 1056void mlx5_unregister_interface(struct mlx5_interface *intf); 1057 1058struct mlx5_profile { 1059 u64 mask; 1060 u8 log_max_qp; 1061 struct { 1062 int size; 1063 int limit; 1064 } mr_cache[MAX_MR_CACHE_ENTRIES]; 1065}; 1066 1067enum { 1068 MLX5_PCI_DEV_IS_VF = 1 << 0, 1069}; 1070 1071enum { 1072 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, 1073}; 1074 1075static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) 1076{ 1077 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); 1078} 1079 1080#endif /* MLX5_DRIVER_H */ 1081