device.h revision 347862
1/*- 2 * Copyright (c) 2013-2018, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/11/sys/dev/mlx5/device.h 347862 2019-05-16 18:13:02Z hselasky $ 26 */ 27 28#ifndef MLX5_DEVICE_H 29#define MLX5_DEVICE_H 30 31#include <linux/types.h> 32#include <rdma/ib_verbs.h> 33#include <dev/mlx5/mlx5_ifc.h> 34 35#define FW_INIT_TIMEOUT_MILI 2000 36#define FW_INIT_WAIT_MS 2 37 38#if defined(__LITTLE_ENDIAN) 39#define MLX5_SET_HOST_ENDIANNESS 0 40#elif defined(__BIG_ENDIAN) 41#define MLX5_SET_HOST_ENDIANNESS 0x80 42#else 43#error Host endianness not defined 44#endif 45 46/* helper macros */ 47#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 48#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 49#define __mlx5_bit_off(typ, fld) __offsetof(struct mlx5_ifc_##typ##_bits, fld) 50#define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16) 51#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 52#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 53#define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf)) 54#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) 55#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 56#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) 57#define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 58#define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld)) 59#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) 60 61#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 62#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 63#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 64#define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64) 65#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 66#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) 67#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 68#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 69 70/* insert a value to a struct */ 71#define MLX5_SET(typ, p, fld, v) do { \ 72 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 73 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 74 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 75 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 76 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ 77 << __mlx5_dw_bit_off(typ, fld))); \ 78} while (0) 79 80#define MLX5_SET_TO_ONES(typ, p, fld) do { \ 81 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 82 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 83 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 84 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 85 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ 86 << __mlx5_dw_bit_off(typ, fld))); \ 87} while (0) 88 89#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ 90__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 91__mlx5_mask(typ, fld)) 92 93#define MLX5_GET_PR(typ, p, fld) ({ \ 94 u32 ___t = MLX5_GET(typ, p, fld); \ 95 pr_debug(#fld " = 0x%x\n", ___t); \ 96 ___t; \ 97}) 98 99#define __MLX5_SET64(typ, p, fld, v) do { \ 100 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ 101 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ 102} while (0) 103 104#define MLX5_SET64(typ, p, fld, v) do { \ 105 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 106 __MLX5_SET64(typ, p, fld, v); \ 107} while (0) 108 109#define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \ 110 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 111 __MLX5_SET64(typ, p, fld[idx], v); \ 112} while (0) 113 114#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) 115 116#define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\ 117__mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \ 118__mlx5_mask16(typ, fld)) 119 120#define MLX5_SET16(typ, p, fld, v) do { \ 121 u16 _v = v; \ 122 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \ 123 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \ 124 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \ 125 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \ 126 << __mlx5_16_bit_off(typ, fld))); \ 127} while (0) 128 129#define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\ 130 __mlx5_64_off(typ, fld))) 131 132#define MLX5_GET_BE(type_t, typ, p, fld) ({ \ 133 type_t tmp; \ 134 switch (sizeof(tmp)) { \ 135 case sizeof(u8): \ 136 tmp = (__force type_t)MLX5_GET(typ, p, fld); \ 137 break; \ 138 case sizeof(u16): \ 139 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \ 140 break; \ 141 case sizeof(u32): \ 142 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \ 143 break; \ 144 case sizeof(u64): \ 145 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \ 146 break; \ 147 } \ 148 tmp; \ 149 }) 150 151#define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8 152#define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8 153#define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1 154#define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\ 155 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\ 156 MLX5_BY_PASS_NUM_MULTICAST_PRIOS) 157 158/* insert a value to a struct */ 159#define MLX5_VSC_SET(typ, p, fld, v) do { \ 160 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 161 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 162 *((__le32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 163 cpu_to_le32((le32_to_cpu(*((__le32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 164 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ 165 << __mlx5_dw_bit_off(typ, fld))); \ 166} while (0) 167 168#define MLX5_VSC_GET(typ, p, fld) ((le32_to_cpu(*((__le32 *)(p) +\ 169__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 170__mlx5_mask(typ, fld)) 171 172#define MLX5_VSC_GET_PR(typ, p, fld) ({ \ 173 u32 ___t = MLX5_VSC_GET(typ, p, fld); \ 174 pr_debug(#fld " = 0x%x\n", ___t); \ 175 ___t; \ 176}) 177 178enum { 179 MLX5_MAX_COMMANDS = 32, 180 MLX5_CMD_DATA_BLOCK_SIZE = 512, 181 MLX5_CMD_MBOX_SIZE = 1024, 182 MLX5_PCI_CMD_XPORT = 7, 183 MLX5_MKEY_BSF_OCTO_SIZE = 4, 184 MLX5_MAX_PSVS = 4, 185}; 186 187enum { 188 MLX5_EXTENDED_UD_AV = 0x80000000, 189}; 190 191enum { 192 MLX5_CQ_FLAGS_OI = 2, 193}; 194 195enum { 196 MLX5_STAT_RATE_OFFSET = 5, 197}; 198 199enum { 200 MLX5_INLINE_SEG = 0x80000000, 201}; 202 203enum { 204 MLX5_HW_START_PADDING = MLX5_INLINE_SEG, 205}; 206 207enum { 208 MLX5_MIN_PKEY_TABLE_SIZE = 128, 209 MLX5_MAX_LOG_PKEY_TABLE = 5, 210}; 211 212enum { 213 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31 214}; 215 216enum { 217 MLX5_PERM_LOCAL_READ = 1 << 2, 218 MLX5_PERM_LOCAL_WRITE = 1 << 3, 219 MLX5_PERM_REMOTE_READ = 1 << 4, 220 MLX5_PERM_REMOTE_WRITE = 1 << 5, 221 MLX5_PERM_ATOMIC = 1 << 6, 222 MLX5_PERM_UMR_EN = 1 << 7, 223}; 224 225enum { 226 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 227 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 228 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 229 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 230 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 231}; 232 233enum { 234 MLX5_MKEY_REMOTE_INVAL = 1 << 24, 235 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 236 MLX5_MKEY_BSF_EN = 1 << 30, 237 MLX5_MKEY_LEN64 = 1 << 31, 238}; 239 240enum { 241 MLX5_EN_RD = (u64)1, 242 MLX5_EN_WR = (u64)2 243}; 244 245enum { 246 MLX5_BF_REGS_PER_PAGE = 4, 247 MLX5_MAX_UAR_PAGES = 1 << 8, 248 MLX5_NON_FP_BF_REGS_PER_PAGE = 2, 249 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE, 250}; 251 252enum { 253 MLX5_MKEY_MASK_LEN = 1ull << 0, 254 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 255 MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 256 MLX5_MKEY_MASK_PD = 1ull << 7, 257 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 258 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, 259 MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 260 MLX5_MKEY_MASK_KEY = 1ull << 13, 261 MLX5_MKEY_MASK_QPN = 1ull << 14, 262 MLX5_MKEY_MASK_LR = 1ull << 17, 263 MLX5_MKEY_MASK_LW = 1ull << 18, 264 MLX5_MKEY_MASK_RR = 1ull << 19, 265 MLX5_MKEY_MASK_RW = 1ull << 20, 266 MLX5_MKEY_MASK_A = 1ull << 21, 267 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 268 MLX5_MKEY_MASK_FREE = 1ull << 29, 269}; 270 271enum { 272 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), 273 274 MLX5_UMR_CHECK_NOT_FREE = (1 << 5), 275 MLX5_UMR_CHECK_FREE = (2 << 5), 276 277 MLX5_UMR_INLINE = (1 << 7), 278}; 279 280#define MLX5_UMR_MTT_ALIGNMENT 0x40 281#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) 282#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT 283 284enum { 285 MLX5_EVENT_QUEUE_TYPE_QP = 0, 286 MLX5_EVENT_QUEUE_TYPE_RQ = 1, 287 MLX5_EVENT_QUEUE_TYPE_SQ = 2, 288}; 289 290enum { 291 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 292 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 293 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 294 MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 295 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 296 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 297 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 298}; 299 300enum { 301 MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX = 1, 302 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE, 303 MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE, 304 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE, 305 MLX5_MAX_INLINE_RECEIVE_SIZE = 64 306}; 307 308enum { 309 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, 310 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 311 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 312 MLX5_DEV_CAP_FLAG_APM = 1LL << 17, 313 MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD = 1LL << 21, 314 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, 315 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, 316 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, 317 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 33, 318 MLX5_DEV_CAP_FLAG_ROCE = 1LL << 34, 319 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37, 320 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, 321 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, 322 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR = 1LL << 48, 323}; 324 325enum { 326 MLX5_ROCE_VERSION_1 = 0, 327 MLX5_ROCE_VERSION_1_5 = 1, 328 MLX5_ROCE_VERSION_2 = 2, 329}; 330 331enum { 332 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1, 333 MLX5_ROCE_VERSION_1_5_CAP = 1 << MLX5_ROCE_VERSION_1_5, 334 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2, 335}; 336 337enum { 338 MLX5_ROCE_L3_TYPE_IPV4 = 0, 339 MLX5_ROCE_L3_TYPE_IPV6 = 1, 340}; 341 342enum { 343 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1, 344 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2, 345}; 346 347enum { 348 MLX5_OPCODE_NOP = 0x00, 349 MLX5_OPCODE_SEND_INVAL = 0x01, 350 MLX5_OPCODE_RDMA_WRITE = 0x08, 351 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 352 MLX5_OPCODE_SEND = 0x0a, 353 MLX5_OPCODE_SEND_IMM = 0x0b, 354 MLX5_OPCODE_LSO = 0x0e, 355 MLX5_OPCODE_RDMA_READ = 0x10, 356 MLX5_OPCODE_ATOMIC_CS = 0x11, 357 MLX5_OPCODE_ATOMIC_FA = 0x12, 358 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 359 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 360 MLX5_OPCODE_BIND_MW = 0x18, 361 MLX5_OPCODE_CONFIG_CMD = 0x1f, 362 363 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 364 MLX5_RECV_OPCODE_SEND = 0x01, 365 MLX5_RECV_OPCODE_SEND_IMM = 0x02, 366 MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 367 368 MLX5_CQE_OPCODE_ERROR = 0x1e, 369 MLX5_CQE_OPCODE_RESIZE = 0x16, 370 371 MLX5_OPCODE_SET_PSV = 0x20, 372 MLX5_OPCODE_GET_PSV = 0x21, 373 MLX5_OPCODE_CHECK_PSV = 0x22, 374 MLX5_OPCODE_RGET_PSV = 0x26, 375 MLX5_OPCODE_RCHECK_PSV = 0x27, 376 377 MLX5_OPCODE_UMR = 0x25, 378 379 MLX5_OPCODE_SIGNATURE_CANCELED = (1 << 15), 380}; 381 382enum { 383 MLX5_SET_PORT_RESET_QKEY = 0, 384 MLX5_SET_PORT_GUID0 = 16, 385 MLX5_SET_PORT_NODE_GUID = 17, 386 MLX5_SET_PORT_SYS_GUID = 18, 387 MLX5_SET_PORT_GID_TABLE = 19, 388 MLX5_SET_PORT_PKEY_TABLE = 20, 389}; 390 391enum { 392 MLX5_MAX_PAGE_SHIFT = 31 393}; 394 395enum { 396 MLX5_ADAPTER_PAGE_SHIFT = 12, 397 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 398}; 399 400enum { 401 MLX5_CAP_OFF_CMDIF_CSUM = 46, 402}; 403 404enum { 405 /* 406 * Max wqe size for rdma read is 512 bytes, so this 407 * limits our max_sge_rd as the wqe needs to fit: 408 * - ctrl segment (16 bytes) 409 * - rdma segment (16 bytes) 410 * - scatter elements (16 bytes each) 411 */ 412 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16 413}; 414 415struct mlx5_cmd_layout { 416 u8 type; 417 u8 rsvd0[3]; 418 __be32 inlen; 419 __be64 in_ptr; 420 __be32 in[4]; 421 __be32 out[4]; 422 __be64 out_ptr; 423 __be32 outlen; 424 u8 token; 425 u8 sig; 426 u8 rsvd1; 427 u8 status_own; 428}; 429 430enum mlx5_fatal_assert_bit_offsets { 431 MLX5_RFR_OFFSET = 31, 432}; 433 434struct mlx5_health_buffer { 435 __be32 assert_var[5]; 436 __be32 rsvd0[3]; 437 __be32 assert_exit_ptr; 438 __be32 assert_callra; 439 __be32 rsvd1[2]; 440 __be32 fw_ver; 441 __be32 hw_id; 442 __be32 rfr; 443 u8 irisc_index; 444 u8 synd; 445 __be16 ext_synd; 446}; 447 448enum mlx5_initializing_bit_offsets { 449 MLX5_FW_RESET_SUPPORTED_OFFSET = 30, 450}; 451 452enum mlx5_cmd_addr_l_sz_offset { 453 MLX5_NIC_IFC_OFFSET = 8, 454}; 455 456struct mlx5_init_seg { 457 __be32 fw_rev; 458 __be32 cmdif_rev_fw_sub; 459 __be32 rsvd0[2]; 460 __be32 cmdq_addr_h; 461 __be32 cmdq_addr_l_sz; 462 __be32 cmd_dbell; 463 __be32 rsvd1[120]; 464 __be32 initializing; 465 struct mlx5_health_buffer health; 466 __be32 rsvd2[880]; 467 __be32 internal_timer_h; 468 __be32 internal_timer_l; 469 __be32 rsvd3[2]; 470 __be32 health_counter; 471 __be32 rsvd4[1019]; 472 __be64 ieee1588_clk; 473 __be32 ieee1588_clk_type; 474 __be32 clr_intx; 475}; 476 477struct mlx5_eqe_comp { 478 __be32 reserved[6]; 479 __be32 cqn; 480}; 481 482struct mlx5_eqe_qp_srq { 483 __be32 reserved[6]; 484 __be32 qp_srq_n; 485}; 486 487struct mlx5_eqe_cq_err { 488 __be32 cqn; 489 u8 reserved1[7]; 490 u8 syndrome; 491}; 492 493struct mlx5_eqe_port_state { 494 u8 reserved0[8]; 495 u8 port; 496}; 497 498struct mlx5_eqe_gpio { 499 __be32 reserved0[2]; 500 __be64 gpio_event; 501}; 502 503struct mlx5_eqe_congestion { 504 u8 type; 505 u8 rsvd0; 506 u8 congestion_level; 507}; 508 509struct mlx5_eqe_stall_vl { 510 u8 rsvd0[3]; 511 u8 port_vl; 512}; 513 514struct mlx5_eqe_cmd { 515 __be32 vector; 516 __be32 rsvd[6]; 517}; 518 519struct mlx5_eqe_page_req { 520 u8 rsvd0[2]; 521 __be16 func_id; 522 __be32 num_pages; 523 __be32 rsvd1[5]; 524}; 525 526struct mlx5_eqe_vport_change { 527 u8 rsvd0[2]; 528 __be16 vport_num; 529 __be32 rsvd1[6]; 530}; 531 532 533#define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF 534#define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF 535 536enum { 537 MLX5_MODULE_STATUS_PLUGGED_ENABLED = 0x1, 538 MLX5_MODULE_STATUS_UNPLUGGED = 0x2, 539 MLX5_MODULE_STATUS_ERROR = 0x3, 540 MLX5_MODULE_STATUS_PLUGGED_DISABLED = 0x4, 541}; 542 543enum { 544 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED = 0x0, 545 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE = 0x1, 546 MLX5_MODULE_EVENT_ERROR_BUS_STUCK = 0x2, 547 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT = 0x3, 548 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST = 0x4, 549 MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE = 0x5, 550 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE = 0x6, 551 MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED = 0x7, 552 MLX5_MODULE_EVENT_ERROR_PCIE_SYSTEM_POWER_SLOT_EXCEEDED = 0xc, 553}; 554 555struct mlx5_eqe_port_module_event { 556 u8 rsvd0; 557 u8 module; 558 u8 rsvd1; 559 u8 module_status; 560 u8 rsvd2[2]; 561 u8 error_type; 562}; 563 564struct mlx5_eqe_general_notification_event { 565 u32 rq_user_index_delay_drop; 566 u32 rsvd0[6]; 567}; 568 569struct mlx5_eqe_temp_warning { 570 __be64 sensor_warning_msb; 571 __be64 sensor_warning_lsb; 572} __packed; 573 574union ev_data { 575 __be32 raw[7]; 576 struct mlx5_eqe_cmd cmd; 577 struct mlx5_eqe_comp comp; 578 struct mlx5_eqe_qp_srq qp_srq; 579 struct mlx5_eqe_cq_err cq_err; 580 struct mlx5_eqe_port_state port; 581 struct mlx5_eqe_gpio gpio; 582 struct mlx5_eqe_congestion cong; 583 struct mlx5_eqe_stall_vl stall_vl; 584 struct mlx5_eqe_page_req req_pages; 585 struct mlx5_eqe_port_module_event port_module_event; 586 struct mlx5_eqe_vport_change vport_change; 587 struct mlx5_eqe_general_notification_event general_notifications; 588 struct mlx5_eqe_temp_warning temp_warning; 589} __packed; 590 591struct mlx5_eqe { 592 u8 rsvd0; 593 u8 type; 594 u8 rsvd1; 595 u8 sub_type; 596 __be32 rsvd2[7]; 597 union ev_data data; 598 __be16 rsvd3; 599 u8 signature; 600 u8 owner; 601} __packed; 602 603struct mlx5_cmd_prot_block { 604 u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 605 u8 rsvd0[48]; 606 __be64 next; 607 __be32 block_num; 608 u8 rsvd1; 609 u8 token; 610 u8 ctrl_sig; 611 u8 sig; 612}; 613 614#define MLX5_NUM_CMDS_IN_ADAPTER_PAGE \ 615 (MLX5_ADAPTER_PAGE_SIZE / MLX5_CMD_MBOX_SIZE) 616CTASSERT(MLX5_CMD_MBOX_SIZE >= sizeof(struct mlx5_cmd_prot_block)); 617CTASSERT(MLX5_CMD_MBOX_SIZE <= MLX5_ADAPTER_PAGE_SIZE); 618 619enum { 620 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, 621}; 622 623struct mlx5_err_cqe { 624 u8 rsvd0[32]; 625 __be32 srqn; 626 u8 rsvd1[18]; 627 u8 vendor_err_synd; 628 u8 syndrome; 629 __be32 s_wqe_opcode_qpn; 630 __be16 wqe_counter; 631 u8 signature; 632 u8 op_own; 633}; 634 635struct mlx5_cqe64 { 636 u8 tunneled_etc; 637 u8 rsvd0[3]; 638 u8 lro_tcppsh_abort_dupack; 639 u8 lro_min_ttl; 640 __be16 lro_tcp_win; 641 __be32 lro_ack_seq_num; 642 __be32 rss_hash_result; 643 u8 rss_hash_type; 644 u8 ml_path; 645 u8 rsvd20[2]; 646 __be16 check_sum; 647 __be16 slid; 648 __be32 flags_rqpn; 649 u8 hds_ip_ext; 650 u8 l4_hdr_type_etc; 651 __be16 vlan_info; 652 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ 653 __be32 imm_inval_pkey; 654 u8 rsvd40[4]; 655 __be32 byte_cnt; 656 __be64 timestamp; 657 __be32 sop_drop_qpn; 658 __be16 wqe_counter; 659 u8 signature; 660 u8 op_own; 661}; 662 663static inline bool get_cqe_lro_timestamp_valid(struct mlx5_cqe64 *cqe) 664{ 665 return (cqe->lro_tcppsh_abort_dupack >> 7) & 1; 666} 667 668static inline bool get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) 669{ 670 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1; 671} 672 673static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) 674{ 675 return (cqe->l4_hdr_type_etc >> 4) & 0x7; 676} 677 678static inline u16 get_cqe_vlan(struct mlx5_cqe64 *cqe) 679{ 680 return be16_to_cpu(cqe->vlan_info) & 0xfff; 681} 682 683static inline void get_cqe_smac(struct mlx5_cqe64 *cqe, u8 *smac) 684{ 685 memcpy(smac, &cqe->rss_hash_type , 4); 686 memcpy(smac + 4, &cqe->slid , 2); 687} 688 689static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe) 690{ 691 return cqe->l4_hdr_type_etc & 0x1; 692} 693 694static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe) 695{ 696 return cqe->tunneled_etc & 0x1; 697} 698 699enum { 700 CQE_L4_HDR_TYPE_NONE = 0x0, 701 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, 702 CQE_L4_HDR_TYPE_UDP = 0x2, 703 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, 704 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, 705}; 706 707enum { 708 /* source L3 hash types */ 709 CQE_RSS_SRC_HTYPE_IP = 0x3 << 0, 710 CQE_RSS_SRC_HTYPE_IPV4 = 0x1 << 0, 711 CQE_RSS_SRC_HTYPE_IPV6 = 0x2 << 0, 712 713 /* destination L3 hash types */ 714 CQE_RSS_DST_HTYPE_IP = 0x3 << 2, 715 CQE_RSS_DST_HTYPE_IPV4 = 0x1 << 2, 716 CQE_RSS_DST_HTYPE_IPV6 = 0x2 << 2, 717 718 /* source L4 hash types */ 719 CQE_RSS_SRC_HTYPE_L4 = 0x3 << 4, 720 CQE_RSS_SRC_HTYPE_TCP = 0x1 << 4, 721 CQE_RSS_SRC_HTYPE_UDP = 0x2 << 4, 722 CQE_RSS_SRC_HTYPE_IPSEC = 0x3 << 4, 723 724 /* destination L4 hash types */ 725 CQE_RSS_DST_HTYPE_L4 = 0x3 << 6, 726 CQE_RSS_DST_HTYPE_TCP = 0x1 << 6, 727 CQE_RSS_DST_HTYPE_UDP = 0x2 << 6, 728 CQE_RSS_DST_HTYPE_IPSEC = 0x3 << 6, 729}; 730 731enum { 732 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0, 733 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1, 734 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2, 735}; 736 737enum { 738 CQE_L2_OK = 1 << 0, 739 CQE_L3_OK = 1 << 1, 740 CQE_L4_OK = 1 << 2, 741}; 742 743struct mlx5_sig_err_cqe { 744 u8 rsvd0[16]; 745 __be32 expected_trans_sig; 746 __be32 actual_trans_sig; 747 __be32 expected_reftag; 748 __be32 actual_reftag; 749 __be16 syndrome; 750 u8 rsvd22[2]; 751 __be32 mkey; 752 __be64 err_offset; 753 u8 rsvd30[8]; 754 __be32 qpn; 755 u8 rsvd38[2]; 756 u8 signature; 757 u8 op_own; 758}; 759 760struct mlx5_wqe_srq_next_seg { 761 u8 rsvd0[2]; 762 __be16 next_wqe_index; 763 u8 signature; 764 u8 rsvd1[11]; 765}; 766 767union mlx5_ext_cqe { 768 struct ib_grh grh; 769 u8 inl[64]; 770}; 771 772struct mlx5_cqe128 { 773 union mlx5_ext_cqe inl_grh; 774 struct mlx5_cqe64 cqe64; 775}; 776 777enum { 778 MLX5_MKEY_STATUS_FREE = 1 << 6, 779}; 780 781struct mlx5_mkey_seg { 782 /* This is a two bit field occupying bits 31-30. 783 * bit 31 is always 0, 784 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation 785 */ 786 u8 status; 787 u8 pcie_control; 788 u8 flags; 789 u8 version; 790 __be32 qpn_mkey7_0; 791 u8 rsvd1[4]; 792 __be32 flags_pd; 793 __be64 start_addr; 794 __be64 len; 795 __be32 bsfs_octo_size; 796 u8 rsvd2[16]; 797 __be32 xlt_oct_size; 798 u8 rsvd3[3]; 799 u8 log2_page_size; 800 u8 rsvd4[4]; 801}; 802 803#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 804 805enum { 806 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 807}; 808 809static inline int mlx5_host_is_le(void) 810{ 811#if defined(__LITTLE_ENDIAN) 812 return 1; 813#elif defined(__BIG_ENDIAN) 814 return 0; 815#else 816#error Host endianness not defined 817#endif 818} 819 820#define MLX5_CMD_OP_MAX 0x939 821 822enum { 823 VPORT_STATE_DOWN = 0x0, 824 VPORT_STATE_UP = 0x1, 825}; 826 827enum { 828 MLX5_L3_PROT_TYPE_IPV4 = 0, 829 MLX5_L3_PROT_TYPE_IPV6 = 1, 830}; 831 832enum { 833 MLX5_L4_PROT_TYPE_TCP = 0, 834 MLX5_L4_PROT_TYPE_UDP = 1, 835}; 836 837enum { 838 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, 839 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, 840 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, 841 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, 842 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, 843}; 844 845enum { 846 MLX5_MATCH_OUTER_HEADERS = 1 << 0, 847 MLX5_MATCH_MISC_PARAMETERS = 1 << 1, 848 MLX5_MATCH_INNER_HEADERS = 1 << 2, 849 850}; 851 852enum { 853 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, 854 MLX5_FLOW_TABLE_TYPE_EGRESS_ACL = 2, 855 MLX5_FLOW_TABLE_TYPE_INGRESS_ACL = 3, 856 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, 857 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 5, 858 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 6, 859 MLX5_FLOW_TABLE_TYPE_NIC_RX_RDMA = 7, 860}; 861 862enum { 863 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_NONE = 0, 864 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_IF_NO_VLAN = 1, 865 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_OVERWRITE = 2 866}; 867 868enum { 869 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_STRIP = 1 << 0, 870 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_STRIP = 1 << 1, 871 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_INSERT = 1 << 2, 872 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_INSERT = 1 << 3 873}; 874 875enum { 876 MLX5_UC_ADDR_CHANGE = (1 << 0), 877 MLX5_MC_ADDR_CHANGE = (1 << 1), 878 MLX5_VLAN_CHANGE = (1 << 2), 879 MLX5_PROMISC_CHANGE = (1 << 3), 880 MLX5_MTU_CHANGE = (1 << 4), 881}; 882 883enum mlx5_list_type { 884 MLX5_NIC_VPORT_LIST_TYPE_UC = 0x0, 885 MLX5_NIC_VPORT_LIST_TYPE_MC = 0x1, 886 MLX5_NIC_VPORT_LIST_TYPE_VLAN = 0x2, 887}; 888 889enum { 890 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0, 891 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1, 892 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2, 893}; 894 895/* MLX5 DEV CAPs */ 896 897/* TODO: EAT.ME */ 898enum mlx5_cap_mode { 899 HCA_CAP_OPMOD_GET_MAX = 0, 900 HCA_CAP_OPMOD_GET_CUR = 1, 901}; 902 903enum mlx5_cap_type { 904 MLX5_CAP_GENERAL = 0, 905 MLX5_CAP_ETHERNET_OFFLOADS, 906 MLX5_CAP_ODP, 907 MLX5_CAP_ATOMIC, 908 MLX5_CAP_ROCE, 909 MLX5_CAP_IPOIB_OFFLOADS, 910 MLX5_CAP_EOIB_OFFLOADS, 911 MLX5_CAP_FLOW_TABLE, 912 MLX5_CAP_ESWITCH_FLOW_TABLE, 913 MLX5_CAP_ESWITCH, 914 MLX5_CAP_SNAPSHOT, 915 MLX5_CAP_VECTOR_CALC, 916 MLX5_CAP_QOS, 917 MLX5_CAP_DEBUG, 918 /* NUM OF CAP Types */ 919 MLX5_CAP_NUM 920}; 921 922enum mlx5_qcam_reg_groups { 923 MLX5_QCAM_REGS_FIRST_128 = 0x0, 924}; 925 926enum mlx5_qcam_feature_groups { 927 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0, 928}; 929 930enum mlx5_pcam_reg_groups { 931 MLX5_PCAM_REGS_5000_TO_507F = 0x0, 932}; 933 934enum mlx5_pcam_feature_groups { 935 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0, 936}; 937 938enum mlx5_mcam_reg_groups { 939 MLX5_MCAM_REGS_FIRST_128 = 0x0, 940}; 941 942enum mlx5_mcam_feature_groups { 943 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0, 944}; 945 946/* GET Dev Caps macros */ 947#define MLX5_CAP_GEN(mdev, cap) \ 948 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap) 949 950#define MLX5_CAP_GEN_MAX(mdev, cap) \ 951 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap) 952 953#define MLX5_CAP_ETH(mdev, cap) \ 954 MLX5_GET(per_protocol_networking_offload_caps,\ 955 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap) 956 957#define MLX5_CAP_ETH_MAX(mdev, cap) \ 958 MLX5_GET(per_protocol_networking_offload_caps,\ 959 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap) 960 961#define MLX5_CAP_ROCE(mdev, cap) \ 962 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap) 963 964#define MLX5_CAP_ROCE_MAX(mdev, cap) \ 965 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap) 966 967#define MLX5_CAP_ATOMIC(mdev, cap) \ 968 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap) 969 970#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ 971 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap) 972 973#define MLX5_CAP_FLOWTABLE(mdev, cap) \ 974 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap) 975 976#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \ 977 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap) 978 979#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ 980 MLX5_GET(flow_table_eswitch_cap, \ 981 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 982 983#define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \ 984 MLX5_GET(flow_table_eswitch_cap, \ 985 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 986 987#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ 988 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap) 989 990#define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \ 991 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap) 992 993#define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \ 994 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap) 995 996#define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \ 997 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap) 998 999#define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \ 1000 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap) 1001 1002#define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \ 1003 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap) 1004 1005#define MLX5_CAP_ESW(mdev, cap) \ 1006 MLX5_GET(e_switch_cap, \ 1007 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap) 1008 1009#define MLX5_CAP_ESW_MAX(mdev, cap) \ 1010 MLX5_GET(e_switch_cap, \ 1011 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap) 1012 1013#define MLX5_CAP_ODP(mdev, cap)\ 1014 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap) 1015 1016#define MLX5_CAP_ODP_MAX(mdev, cap)\ 1017 MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap) 1018 1019#define MLX5_CAP_SNAPSHOT(mdev, cap) \ 1020 MLX5_GET(snapshot_cap, \ 1021 mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap) 1022 1023#define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \ 1024 MLX5_GET(snapshot_cap, \ 1025 mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap) 1026 1027#define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \ 1028 MLX5_GET(per_protocol_networking_offload_caps,\ 1029 mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap) 1030 1031#define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \ 1032 MLX5_GET(per_protocol_networking_offload_caps,\ 1033 mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap) 1034 1035#define MLX5_CAP_DEBUG(mdev, cap) \ 1036 MLX5_GET(debug_cap, \ 1037 mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap) 1038 1039#define MLX5_CAP_DEBUG_MAX(mdev, cap) \ 1040 MLX5_GET(debug_cap, \ 1041 mdev->hca_caps_max[MLX5_CAP_DEBUG], cap) 1042 1043#define MLX5_CAP_QOS(mdev, cap) \ 1044 MLX5_GET(qos_cap,\ 1045 mdev->hca_caps_cur[MLX5_CAP_QOS], cap) 1046 1047#define MLX5_CAP_QOS_MAX(mdev, cap) \ 1048 MLX5_GET(qos_cap,\ 1049 mdev->hca_caps_max[MLX5_CAP_QOS], cap) 1050 1051#define MLX5_CAP_PCAM_FEATURE(mdev, fld) \ 1052 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld) 1053 1054#define MLX5_CAP_MCAM_FEATURE(mdev, fld) \ 1055 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld) 1056 1057#define MLX5_CAP_MCAM_REG(mdev, reg) \ 1058 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg) 1059 1060#define MLX5_CAP_QCAM_REG(mdev, fld) \ 1061 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld) 1062 1063#define MLX5_CAP_QCAM_FEATURE(mdev, fld) \ 1064 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld) 1065 1066#define MLX5_CAP_FPGA(mdev, cap) \ 1067 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap) 1068 1069#define MLX5_CAP64_FPGA(mdev, cap) \ 1070 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap) 1071 1072enum { 1073 MLX5_CMD_STAT_OK = 0x0, 1074 MLX5_CMD_STAT_INT_ERR = 0x1, 1075 MLX5_CMD_STAT_BAD_OP_ERR = 0x2, 1076 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, 1077 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, 1078 MLX5_CMD_STAT_BAD_RES_ERR = 0x5, 1079 MLX5_CMD_STAT_RES_BUSY = 0x6, 1080 MLX5_CMD_STAT_LIM_ERR = 0x8, 1081 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, 1082 MLX5_CMD_STAT_IX_ERR = 0xa, 1083 MLX5_CMD_STAT_NO_RES_ERR = 0xf, 1084 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, 1085 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, 1086 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, 1087 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, 1088 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, 1089}; 1090 1091enum { 1092 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0, 1093 MLX5_RFC_2863_COUNTERS_GROUP = 0x1, 1094 MLX5_RFC_2819_COUNTERS_GROUP = 0x2, 1095 MLX5_RFC_3635_COUNTERS_GROUP = 0x3, 1096 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5, 1097 MLX5_ETHERNET_DISCARD_COUNTERS_GROUP = 0x6, 1098 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10, 1099 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11, 1100 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12, 1101 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16, 1102 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20, 1103}; 1104 1105enum { 1106 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0, 1107 MLX5_PCIE_LANE_COUNTERS_GROUP = 0x1, 1108 MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP = 0x2, 1109}; 1110 1111enum { 1112 MLX5_NUM_UUARS_PER_PAGE = MLX5_NON_FP_BF_REGS_PER_PAGE, 1113 MLX5_DEF_TOT_UUARS = 8 * MLX5_NUM_UUARS_PER_PAGE, 1114}; 1115 1116enum { 1117 NUM_DRIVER_UARS = 4, 1118 NUM_LOW_LAT_UUARS = 4, 1119}; 1120 1121enum { 1122 MLX5_CAP_PORT_TYPE_IB = 0x0, 1123 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1124}; 1125 1126enum { 1127 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_L2 = 0x0, 1128 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_VPORT_CONFIG = 0x1, 1129 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_NOT_REQUIRED = 0x2 1130}; 1131 1132enum mlx5_inline_modes { 1133 MLX5_INLINE_MODE_NONE, 1134 MLX5_INLINE_MODE_L2, 1135 MLX5_INLINE_MODE_IP, 1136 MLX5_INLINE_MODE_TCP_UDP, 1137}; 1138 1139enum { 1140 MLX5_QUERY_VPORT_STATE_OUT_STATE_FOLLOW = 0x2, 1141}; 1142 1143static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) 1144{ 1145 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) 1146 return 0; 1147 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; 1148} 1149 1150struct mlx5_ifc_mcia_reg_bits { 1151 u8 l[0x1]; 1152 u8 reserved_0[0x7]; 1153 u8 module[0x8]; 1154 u8 reserved_1[0x8]; 1155 u8 status[0x8]; 1156 1157 u8 i2c_device_address[0x8]; 1158 u8 page_number[0x8]; 1159 u8 device_address[0x10]; 1160 1161 u8 reserved_2[0x10]; 1162 u8 size[0x10]; 1163 1164 u8 reserved_3[0x20]; 1165 1166 u8 dword_0[0x20]; 1167 u8 dword_1[0x20]; 1168 u8 dword_2[0x20]; 1169 u8 dword_3[0x20]; 1170 u8 dword_4[0x20]; 1171 u8 dword_5[0x20]; 1172 u8 dword_6[0x20]; 1173 u8 dword_7[0x20]; 1174 u8 dword_8[0x20]; 1175 u8 dword_9[0x20]; 1176 u8 dword_10[0x20]; 1177 u8 dword_11[0x20]; 1178}; 1179 1180#define MLX5_CMD_OP_QUERY_EEPROM 0x93c 1181 1182struct mlx5_mini_cqe8 { 1183 union { 1184 __be32 rx_hash_result; 1185 __be16 checksum; 1186 __be16 rsvd; 1187 struct { 1188 __be16 wqe_counter; 1189 u8 s_wqe_opcode; 1190 u8 reserved; 1191 } s_wqe_info; 1192 }; 1193 __be32 byte_cnt; 1194}; 1195 1196enum { 1197 MLX5_NO_INLINE_DATA, 1198 MLX5_INLINE_DATA32_SEG, 1199 MLX5_INLINE_DATA64_SEG, 1200 MLX5_COMPRESSED, 1201}; 1202 1203enum mlx5_exp_cqe_zip_recv_type { 1204 MLX5_CQE_FORMAT_HASH, 1205 MLX5_CQE_FORMAT_CSUM, 1206}; 1207 1208#define MLX5E_CQE_FORMAT_MASK 0xc 1209static inline int mlx5_get_cqe_format(const struct mlx5_cqe64 *cqe) 1210{ 1211 return (cqe->op_own & MLX5E_CQE_FORMAT_MASK) >> 2; 1212} 1213 1214enum { 1215 MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1, 1216 MLX5_GEN_EVENT_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5, 1217}; 1218 1219/* 8 regular priorities + 1 for multicast */ 1220#define MLX5_NUM_BYPASS_FTS 9 1221 1222#endif /* MLX5_DEVICE_H */ 1223