device.h revision 337114
1290650Shselasky/*- 2337098Shselasky * Copyright (c) 2013-2018, Mellanox Technologies, Ltd. All rights reserved. 3290650Shselasky * 4290650Shselasky * Redistribution and use in source and binary forms, with or without 5290650Shselasky * modification, are permitted provided that the following conditions 6290650Shselasky * are met: 7290650Shselasky * 1. Redistributions of source code must retain the above copyright 8290650Shselasky * notice, this list of conditions and the following disclaimer. 9290650Shselasky * 2. Redistributions in binary form must reproduce the above copyright 10290650Shselasky * notice, this list of conditions and the following disclaimer in the 11290650Shselasky * documentation and/or other materials provided with the distribution. 12290650Shselasky * 13290650Shselasky * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14290650Shselasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15290650Shselasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16290650Shselasky * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17290650Shselasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18290650Shselasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19290650Shselasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20290650Shselasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21290650Shselasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22290650Shselasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23290650Shselasky * SUCH DAMAGE. 24290650Shselasky * 25290650Shselasky * $FreeBSD: stable/11/sys/dev/mlx5/device.h 337114 2018-08-02 08:55:19Z hselasky $ 26290650Shselasky */ 27290650Shselasky 28290650Shselasky#ifndef MLX5_DEVICE_H 29290650Shselasky#define MLX5_DEVICE_H 30290650Shselasky 31290650Shselasky#include <linux/types.h> 32290650Shselasky#include <rdma/ib_verbs.h> 33290650Shselasky#include <dev/mlx5/mlx5_ifc.h> 34290650Shselasky 35290650Shselasky#define FW_INIT_TIMEOUT_MILI 2000 36290650Shselasky#define FW_INIT_WAIT_MS 2 37290650Shselasky 38290650Shselasky#if defined(__LITTLE_ENDIAN) 39290650Shselasky#define MLX5_SET_HOST_ENDIANNESS 0 40290650Shselasky#elif defined(__BIG_ENDIAN) 41290650Shselasky#define MLX5_SET_HOST_ENDIANNESS 0x80 42290650Shselasky#else 43290650Shselasky#error Host endianness not defined 44290650Shselasky#endif 45290650Shselasky 46290650Shselasky/* helper macros */ 47290650Shselasky#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 48290650Shselasky#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 49290650Shselasky#define __mlx5_bit_off(typ, fld) __offsetof(struct mlx5_ifc_##typ##_bits, fld) 50337098Shselasky#define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16) 51290650Shselasky#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 52290650Shselasky#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 53337098Shselasky#define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf)) 54290650Shselasky#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) 55290650Shselasky#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 56290650Shselasky#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) 57337098Shselasky#define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 58337098Shselasky#define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld)) 59290650Shselasky#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) 60290650Shselasky 61290650Shselasky#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 62290650Shselasky#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 63290650Shselasky#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 64306233Shselasky#define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64) 65290650Shselasky#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 66290650Shselasky#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) 67290650Shselasky#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 68290650Shselasky#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 69290650Shselasky 70290650Shselasky/* insert a value to a struct */ 71290650Shselasky#define MLX5_SET(typ, p, fld, v) do { \ 72290650Shselasky BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 73290650Shselasky BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 74290650Shselasky *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 75290650Shselasky cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 76290650Shselasky (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ 77290650Shselasky << __mlx5_dw_bit_off(typ, fld))); \ 78290650Shselasky} while (0) 79290650Shselasky 80290650Shselasky#define MLX5_SET_TO_ONES(typ, p, fld) do { \ 81290650Shselasky BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 82290650Shselasky BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 83290650Shselasky *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 84290650Shselasky cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 85290650Shselasky (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ 86290650Shselasky << __mlx5_dw_bit_off(typ, fld))); \ 87290650Shselasky} while (0) 88290650Shselasky 89290650Shselasky#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ 90290650Shselasky__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 91290650Shselasky__mlx5_mask(typ, fld)) 92290650Shselasky 93290650Shselasky#define MLX5_GET_PR(typ, p, fld) ({ \ 94290650Shselasky u32 ___t = MLX5_GET(typ, p, fld); \ 95290650Shselasky pr_debug(#fld " = 0x%x\n", ___t); \ 96290650Shselasky ___t; \ 97290650Shselasky}) 98290650Shselasky 99331807Shselasky#define __MLX5_SET64(typ, p, fld, v) do { \ 100290650Shselasky BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ 101290650Shselasky *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ 102290650Shselasky} while (0) 103290650Shselasky 104331807Shselasky#define MLX5_SET64(typ, p, fld, v) do { \ 105331807Shselasky BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 106331807Shselasky __MLX5_SET64(typ, p, fld, v); \ 107331807Shselasky} while (0) 108331807Shselasky 109331807Shselasky#define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \ 110331807Shselasky BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 111331807Shselasky __MLX5_SET64(typ, p, fld[idx], v); \ 112331807Shselasky} while (0) 113331807Shselasky 114290650Shselasky#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) 115290650Shselasky 116337098Shselasky#define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\ 117337098Shselasky__mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \ 118337098Shselasky__mlx5_mask16(typ, fld)) 119337098Shselasky 120337098Shselasky#define MLX5_SET16(typ, p, fld, v) do { \ 121337098Shselasky u16 _v = v; \ 122337098Shselasky BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \ 123337098Shselasky *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \ 124337098Shselasky cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \ 125337098Shselasky (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \ 126337098Shselasky << __mlx5_16_bit_off(typ, fld))); \ 127337098Shselasky} while (0) 128337098Shselasky 129329204Shselasky#define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\ 130329204Shselasky __mlx5_64_off(typ, fld))) 131329204Shselasky 132329204Shselasky#define MLX5_GET_BE(type_t, typ, p, fld) ({ \ 133329204Shselasky type_t tmp; \ 134329204Shselasky switch (sizeof(tmp)) { \ 135329204Shselasky case sizeof(u8): \ 136329204Shselasky tmp = (__force type_t)MLX5_GET(typ, p, fld); \ 137329204Shselasky break; \ 138329204Shselasky case sizeof(u16): \ 139329204Shselasky tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \ 140329204Shselasky break; \ 141329204Shselasky case sizeof(u32): \ 142329204Shselasky tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \ 143329204Shselasky break; \ 144329204Shselasky case sizeof(u64): \ 145329204Shselasky tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \ 146329204Shselasky break; \ 147329204Shselasky } \ 148329204Shselasky tmp; \ 149329204Shselasky }) 150329204Shselasky 151329204Shselasky#define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8 152329204Shselasky#define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8 153329204Shselasky#define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1 154329204Shselasky#define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\ 155329204Shselasky MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\ 156329204Shselasky MLX5_BY_PASS_NUM_MULTICAST_PRIOS) 157329204Shselasky 158331585Shselasky/* insert a value to a struct */ 159331585Shselasky#define MLX5_VSC_SET(typ, p, fld, v) do { \ 160331585Shselasky BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 161331585Shselasky BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 162331585Shselasky *((__le32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 163331585Shselasky cpu_to_le32((le32_to_cpu(*((__le32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 164331585Shselasky (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ 165331585Shselasky << __mlx5_dw_bit_off(typ, fld))); \ 166331585Shselasky} while (0) 167331585Shselasky 168331585Shselasky#define MLX5_VSC_GET(typ, p, fld) ((le32_to_cpu(*((__le32 *)(p) +\ 169331585Shselasky__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 170331585Shselasky__mlx5_mask(typ, fld)) 171331585Shselasky 172331585Shselasky#define MLX5_VSC_GET_PR(typ, p, fld) ({ \ 173331585Shselasky u32 ___t = MLX5_VSC_GET(typ, p, fld); \ 174331585Shselasky pr_debug(#fld " = 0x%x\n", ___t); \ 175331585Shselasky ___t; \ 176331585Shselasky}) 177331585Shselasky 178290650Shselaskyenum { 179290650Shselasky MLX5_MAX_COMMANDS = 32, 180290650Shselasky MLX5_CMD_DATA_BLOCK_SIZE = 512, 181322150Shselasky MLX5_CMD_MBOX_SIZE = 1024, 182290650Shselasky MLX5_PCI_CMD_XPORT = 7, 183290650Shselasky MLX5_MKEY_BSF_OCTO_SIZE = 4, 184290650Shselasky MLX5_MAX_PSVS = 4, 185290650Shselasky}; 186290650Shselasky 187290650Shselaskyenum { 188290650Shselasky MLX5_EXTENDED_UD_AV = 0x80000000, 189290650Shselasky}; 190290650Shselasky 191290650Shselaskyenum { 192306233Shselasky MLX5_CQ_FLAGS_OI = 2, 193306233Shselasky}; 194306233Shselasky 195306233Shselaskyenum { 196290650Shselasky MLX5_STAT_RATE_OFFSET = 5, 197290650Shselasky}; 198290650Shselasky 199290650Shselaskyenum { 200290650Shselasky MLX5_INLINE_SEG = 0x80000000, 201290650Shselasky}; 202290650Shselasky 203290650Shselaskyenum { 204290650Shselasky MLX5_HW_START_PADDING = MLX5_INLINE_SEG, 205290650Shselasky}; 206290650Shselasky 207290650Shselaskyenum { 208290650Shselasky MLX5_MIN_PKEY_TABLE_SIZE = 128, 209290650Shselasky MLX5_MAX_LOG_PKEY_TABLE = 5, 210290650Shselasky}; 211290650Shselasky 212290650Shselaskyenum { 213306233Shselasky MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31 214306233Shselasky}; 215306233Shselasky 216306233Shselaskyenum { 217290650Shselasky MLX5_PERM_LOCAL_READ = 1 << 2, 218290650Shselasky MLX5_PERM_LOCAL_WRITE = 1 << 3, 219290650Shselasky MLX5_PERM_REMOTE_READ = 1 << 4, 220290650Shselasky MLX5_PERM_REMOTE_WRITE = 1 << 5, 221290650Shselasky MLX5_PERM_ATOMIC = 1 << 6, 222290650Shselasky MLX5_PERM_UMR_EN = 1 << 7, 223290650Shselasky}; 224290650Shselasky 225290650Shselaskyenum { 226290650Shselasky MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 227290650Shselasky MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 228290650Shselasky MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 229290650Shselasky MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 230290650Shselasky MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 231290650Shselasky}; 232290650Shselasky 233290650Shselaskyenum { 234290650Shselasky MLX5_MKEY_REMOTE_INVAL = 1 << 24, 235290650Shselasky MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 236290650Shselasky MLX5_MKEY_BSF_EN = 1 << 30, 237290650Shselasky MLX5_MKEY_LEN64 = 1 << 31, 238290650Shselasky}; 239290650Shselasky 240290650Shselaskyenum { 241290650Shselasky MLX5_EN_RD = (u64)1, 242290650Shselasky MLX5_EN_WR = (u64)2 243290650Shselasky}; 244290650Shselasky 245290650Shselaskyenum { 246290650Shselasky MLX5_BF_REGS_PER_PAGE = 4, 247290650Shselasky MLX5_MAX_UAR_PAGES = 1 << 8, 248290650Shselasky MLX5_NON_FP_BF_REGS_PER_PAGE = 2, 249290650Shselasky MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE, 250290650Shselasky}; 251290650Shselasky 252290650Shselaskyenum { 253290650Shselasky MLX5_MKEY_MASK_LEN = 1ull << 0, 254290650Shselasky MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 255290650Shselasky MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 256290650Shselasky MLX5_MKEY_MASK_PD = 1ull << 7, 257290650Shselasky MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 258290650Shselasky MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, 259290650Shselasky MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 260290650Shselasky MLX5_MKEY_MASK_KEY = 1ull << 13, 261290650Shselasky MLX5_MKEY_MASK_QPN = 1ull << 14, 262290650Shselasky MLX5_MKEY_MASK_LR = 1ull << 17, 263290650Shselasky MLX5_MKEY_MASK_LW = 1ull << 18, 264290650Shselasky MLX5_MKEY_MASK_RR = 1ull << 19, 265290650Shselasky MLX5_MKEY_MASK_RW = 1ull << 20, 266290650Shselasky MLX5_MKEY_MASK_A = 1ull << 21, 267290650Shselasky MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 268290650Shselasky MLX5_MKEY_MASK_FREE = 1ull << 29, 269290650Shselasky}; 270290650Shselasky 271290650Shselaskyenum { 272306233Shselasky MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), 273306233Shselasky 274306233Shselasky MLX5_UMR_CHECK_NOT_FREE = (1 << 5), 275306233Shselasky MLX5_UMR_CHECK_FREE = (2 << 5), 276306233Shselasky 277306233Shselasky MLX5_UMR_INLINE = (1 << 7), 278306233Shselasky}; 279306233Shselasky 280306233Shselasky#define MLX5_UMR_MTT_ALIGNMENT 0x40 281306233Shselasky#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) 282306233Shselasky#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT 283306233Shselasky 284306233Shselaskyenum { 285306233Shselasky MLX5_EVENT_QUEUE_TYPE_QP = 0, 286306233Shselasky MLX5_EVENT_QUEUE_TYPE_RQ = 1, 287306233Shselasky MLX5_EVENT_QUEUE_TYPE_SQ = 2, 288306233Shselasky}; 289306233Shselasky 290306233Shselaskyenum { 291290650Shselasky MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 292290650Shselasky MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 293290650Shselasky MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 294290650Shselasky MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 295290650Shselasky MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 296290650Shselasky MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 297290650Shselasky MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 298290650Shselasky}; 299290650Shselasky 300290650Shselaskyenum { 301306233Shselasky MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX = 1, 302306233Shselasky MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE, 303306233Shselasky MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE, 304306233Shselasky MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE, 305306233Shselasky MLX5_MAX_INLINE_RECEIVE_SIZE = 64 306306233Shselasky}; 307306233Shselasky 308306233Shselaskyenum { 309290650Shselasky MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, 310290650Shselasky MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 311290650Shselasky MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 312290650Shselasky MLX5_DEV_CAP_FLAG_APM = 1LL << 17, 313290650Shselasky MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD = 1LL << 21, 314290650Shselasky MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, 315290650Shselasky MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, 316290650Shselasky MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, 317306233Shselasky MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 33, 318290650Shselasky MLX5_DEV_CAP_FLAG_ROCE = 1LL << 34, 319290650Shselasky MLX5_DEV_CAP_FLAG_DCT = 1LL << 37, 320290650Shselasky MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, 321290650Shselasky MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, 322306233Shselasky MLX5_DEV_CAP_FLAG_DRAIN_SIGERR = 1LL << 48, 323290650Shselasky}; 324290650Shselasky 325290650Shselaskyenum { 326290650Shselasky MLX5_ROCE_VERSION_1 = 0, 327290650Shselasky MLX5_ROCE_VERSION_1_5 = 1, 328290650Shselasky MLX5_ROCE_VERSION_2 = 2, 329290650Shselasky}; 330290650Shselasky 331290650Shselaskyenum { 332290650Shselasky MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1, 333290650Shselasky MLX5_ROCE_VERSION_1_5_CAP = 1 << MLX5_ROCE_VERSION_1_5, 334290650Shselasky MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2, 335290650Shselasky}; 336290650Shselasky 337290650Shselaskyenum { 338290650Shselasky MLX5_ROCE_L3_TYPE_IPV4 = 0, 339290650Shselasky MLX5_ROCE_L3_TYPE_IPV6 = 1, 340290650Shselasky}; 341290650Shselasky 342290650Shselaskyenum { 343290650Shselasky MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1, 344290650Shselasky MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2, 345290650Shselasky}; 346290650Shselasky 347290650Shselaskyenum { 348290650Shselasky MLX5_OPCODE_NOP = 0x00, 349290650Shselasky MLX5_OPCODE_SEND_INVAL = 0x01, 350290650Shselasky MLX5_OPCODE_RDMA_WRITE = 0x08, 351290650Shselasky MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 352290650Shselasky MLX5_OPCODE_SEND = 0x0a, 353290650Shselasky MLX5_OPCODE_SEND_IMM = 0x0b, 354290650Shselasky MLX5_OPCODE_LSO = 0x0e, 355290650Shselasky MLX5_OPCODE_RDMA_READ = 0x10, 356290650Shselasky MLX5_OPCODE_ATOMIC_CS = 0x11, 357290650Shselasky MLX5_OPCODE_ATOMIC_FA = 0x12, 358290650Shselasky MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 359290650Shselasky MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 360290650Shselasky MLX5_OPCODE_BIND_MW = 0x18, 361290650Shselasky MLX5_OPCODE_CONFIG_CMD = 0x1f, 362290650Shselasky 363290650Shselasky MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 364290650Shselasky MLX5_RECV_OPCODE_SEND = 0x01, 365290650Shselasky MLX5_RECV_OPCODE_SEND_IMM = 0x02, 366290650Shselasky MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 367290650Shselasky 368290650Shselasky MLX5_CQE_OPCODE_ERROR = 0x1e, 369290650Shselasky MLX5_CQE_OPCODE_RESIZE = 0x16, 370290650Shselasky 371290650Shselasky MLX5_OPCODE_SET_PSV = 0x20, 372290650Shselasky MLX5_OPCODE_GET_PSV = 0x21, 373290650Shselasky MLX5_OPCODE_CHECK_PSV = 0x22, 374290650Shselasky MLX5_OPCODE_RGET_PSV = 0x26, 375290650Shselasky MLX5_OPCODE_RCHECK_PSV = 0x27, 376290650Shselasky 377290650Shselasky MLX5_OPCODE_UMR = 0x25, 378290650Shselasky 379306233Shselasky MLX5_OPCODE_SIGNATURE_CANCELED = (1 << 15), 380290650Shselasky}; 381290650Shselasky 382290650Shselaskyenum { 383290650Shselasky MLX5_SET_PORT_RESET_QKEY = 0, 384290650Shselasky MLX5_SET_PORT_GUID0 = 16, 385290650Shselasky MLX5_SET_PORT_NODE_GUID = 17, 386290650Shselasky MLX5_SET_PORT_SYS_GUID = 18, 387290650Shselasky MLX5_SET_PORT_GID_TABLE = 19, 388290650Shselasky MLX5_SET_PORT_PKEY_TABLE = 20, 389290650Shselasky}; 390290650Shselasky 391290650Shselaskyenum { 392290650Shselasky MLX5_MAX_PAGE_SHIFT = 31 393290650Shselasky}; 394290650Shselasky 395290650Shselaskyenum { 396290650Shselasky MLX5_ADAPTER_PAGE_SHIFT = 12, 397290650Shselasky MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 398290650Shselasky}; 399290650Shselasky 400290650Shselaskyenum { 401290650Shselasky MLX5_CAP_OFF_CMDIF_CSUM = 46, 402290650Shselasky}; 403290650Shselasky 404329204Shselaskyenum { 405329204Shselasky /* 406329204Shselasky * Max wqe size for rdma read is 512 bytes, so this 407329204Shselasky * limits our max_sge_rd as the wqe needs to fit: 408329204Shselasky * - ctrl segment (16 bytes) 409329204Shselasky * - rdma segment (16 bytes) 410329204Shselasky * - scatter elements (16 bytes each) 411329204Shselasky */ 412329204Shselasky MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16 413329204Shselasky}; 414329204Shselasky 415290650Shselaskystruct mlx5_cmd_layout { 416290650Shselasky u8 type; 417290650Shselasky u8 rsvd0[3]; 418290650Shselasky __be32 inlen; 419290650Shselasky __be64 in_ptr; 420290650Shselasky __be32 in[4]; 421290650Shselasky __be32 out[4]; 422290650Shselasky __be64 out_ptr; 423290650Shselasky __be32 outlen; 424290650Shselasky u8 token; 425290650Shselasky u8 sig; 426290650Shselasky u8 rsvd1; 427290650Shselasky u8 status_own; 428290650Shselasky}; 429290650Shselasky 430331814Shselaskyenum mlx5_fatal_assert_bit_offsets { 431331814Shselasky MLX5_RFR_OFFSET = 31, 432331814Shselasky}; 433331814Shselasky 434290650Shselaskystruct mlx5_health_buffer { 435290650Shselasky __be32 assert_var[5]; 436290650Shselasky __be32 rsvd0[3]; 437290650Shselasky __be32 assert_exit_ptr; 438290650Shselasky __be32 assert_callra; 439290650Shselasky __be32 rsvd1[2]; 440290650Shselasky __be32 fw_ver; 441290650Shselasky __be32 hw_id; 442331814Shselasky __be32 rfr; 443290650Shselasky u8 irisc_index; 444290650Shselasky u8 synd; 445331580Shselasky __be16 ext_synd; 446290650Shselasky}; 447290650Shselasky 448331814Shselaskyenum mlx5_initializing_bit_offsets { 449331814Shselasky MLX5_FW_RESET_SUPPORTED_OFFSET = 30, 450331814Shselasky}; 451331814Shselasky 452331814Shselaskyenum mlx5_cmd_addr_l_sz_offset { 453331814Shselasky MLX5_NIC_IFC_OFFSET = 8, 454331814Shselasky}; 455331814Shselasky 456290650Shselaskystruct mlx5_init_seg { 457290650Shselasky __be32 fw_rev; 458290650Shselasky __be32 cmdif_rev_fw_sub; 459290650Shselasky __be32 rsvd0[2]; 460290650Shselasky __be32 cmdq_addr_h; 461290650Shselasky __be32 cmdq_addr_l_sz; 462290650Shselasky __be32 cmd_dbell; 463290650Shselasky __be32 rsvd1[120]; 464290650Shselasky __be32 initializing; 465290650Shselasky struct mlx5_health_buffer health; 466306233Shselasky __be32 rsvd2[880]; 467306233Shselasky __be32 internal_timer_h; 468306233Shselasky __be32 internal_timer_l; 469306233Shselasky __be32 rsvd3[2]; 470290650Shselasky __be32 health_counter; 471306233Shselasky __be32 rsvd4[1019]; 472290650Shselasky __be64 ieee1588_clk; 473290650Shselasky __be32 ieee1588_clk_type; 474290650Shselasky __be32 clr_intx; 475290650Shselasky}; 476290650Shselasky 477290650Shselaskystruct mlx5_eqe_comp { 478290650Shselasky __be32 reserved[6]; 479290650Shselasky __be32 cqn; 480290650Shselasky}; 481290650Shselasky 482290650Shselaskystruct mlx5_eqe_qp_srq { 483290650Shselasky __be32 reserved[6]; 484290650Shselasky __be32 qp_srq_n; 485290650Shselasky}; 486290650Shselasky 487290650Shselaskystruct mlx5_eqe_cq_err { 488290650Shselasky __be32 cqn; 489290650Shselasky u8 reserved1[7]; 490290650Shselasky u8 syndrome; 491290650Shselasky}; 492290650Shselasky 493290650Shselaskystruct mlx5_eqe_port_state { 494290650Shselasky u8 reserved0[8]; 495290650Shselasky u8 port; 496290650Shselasky}; 497290650Shselasky 498290650Shselaskystruct mlx5_eqe_gpio { 499290650Shselasky __be32 reserved0[2]; 500290650Shselasky __be64 gpio_event; 501290650Shselasky}; 502290650Shselasky 503290650Shselaskystruct mlx5_eqe_congestion { 504290650Shselasky u8 type; 505290650Shselasky u8 rsvd0; 506290650Shselasky u8 congestion_level; 507290650Shselasky}; 508290650Shselasky 509290650Shselaskystruct mlx5_eqe_stall_vl { 510290650Shselasky u8 rsvd0[3]; 511290650Shselasky u8 port_vl; 512290650Shselasky}; 513290650Shselasky 514290650Shselaskystruct mlx5_eqe_cmd { 515290650Shselasky __be32 vector; 516290650Shselasky __be32 rsvd[6]; 517290650Shselasky}; 518290650Shselasky 519290650Shselaskystruct mlx5_eqe_page_req { 520290650Shselasky u8 rsvd0[2]; 521290650Shselasky __be16 func_id; 522290650Shselasky __be32 num_pages; 523290650Shselasky __be32 rsvd1[5]; 524290650Shselasky}; 525290650Shselasky 526290650Shselaskystruct mlx5_eqe_vport_change { 527290650Shselasky u8 rsvd0[2]; 528290650Shselasky __be16 vport_num; 529290650Shselasky __be32 rsvd1[6]; 530290650Shselasky}; 531290650Shselasky 532290650Shselasky 533290650Shselasky#define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF 534290650Shselasky#define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF 535290650Shselasky 536290650Shselaskyenum { 537331575Shselasky MLX5_MODULE_STATUS_PLUGGED_ENABLED = 0x1, 538331575Shselasky MLX5_MODULE_STATUS_UNPLUGGED = 0x2, 539331575Shselasky MLX5_MODULE_STATUS_ERROR = 0x3, 540331575Shselasky MLX5_MODULE_STATUS_PLUGGED_DISABLED = 0x4, 541290650Shselasky}; 542290650Shselasky 543290650Shselaskyenum { 544290650Shselasky MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED = 0x0, 545290650Shselasky MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE = 0x1, 546290650Shselasky MLX5_MODULE_EVENT_ERROR_BUS_STUCK = 0x2, 547290650Shselasky MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT = 0x3, 548290650Shselasky MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST = 0x4, 549331575Shselasky MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE = 0x5, 550290650Shselasky MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE = 0x6, 551306233Shselasky MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED = 0x7, 552290650Shselasky}; 553290650Shselasky 554290650Shselaskystruct mlx5_eqe_port_module_event { 555290650Shselasky u8 rsvd0; 556290650Shselasky u8 module; 557290650Shselasky u8 rsvd1; 558290650Shselasky u8 module_status; 559290650Shselasky u8 rsvd2[2]; 560290650Shselasky u8 error_type; 561290650Shselasky}; 562290650Shselasky 563329205Shselaskystruct mlx5_eqe_general_notification_event { 564329205Shselasky u32 rq_user_index_delay_drop; 565329205Shselasky u32 rsvd0[6]; 566329205Shselasky}; 567329205Shselasky 568290650Shselaskyunion ev_data { 569290650Shselasky __be32 raw[7]; 570290650Shselasky struct mlx5_eqe_cmd cmd; 571290650Shselasky struct mlx5_eqe_comp comp; 572290650Shselasky struct mlx5_eqe_qp_srq qp_srq; 573290650Shselasky struct mlx5_eqe_cq_err cq_err; 574290650Shselasky struct mlx5_eqe_port_state port; 575290650Shselasky struct mlx5_eqe_gpio gpio; 576290650Shselasky struct mlx5_eqe_congestion cong; 577290650Shselasky struct mlx5_eqe_stall_vl stall_vl; 578290650Shselasky struct mlx5_eqe_page_req req_pages; 579290650Shselasky struct mlx5_eqe_port_module_event port_module_event; 580290650Shselasky struct mlx5_eqe_vport_change vport_change; 581329205Shselasky struct mlx5_eqe_general_notification_event general_notifications; 582290650Shselasky} __packed; 583290650Shselasky 584290650Shselaskystruct mlx5_eqe { 585290650Shselasky u8 rsvd0; 586290650Shselasky u8 type; 587290650Shselasky u8 rsvd1; 588290650Shselasky u8 sub_type; 589290650Shselasky __be32 rsvd2[7]; 590290650Shselasky union ev_data data; 591290650Shselasky __be16 rsvd3; 592290650Shselasky u8 signature; 593290650Shselasky u8 owner; 594290650Shselasky} __packed; 595290650Shselasky 596290650Shselaskystruct mlx5_cmd_prot_block { 597290650Shselasky u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 598290650Shselasky u8 rsvd0[48]; 599290650Shselasky __be64 next; 600290650Shselasky __be32 block_num; 601290650Shselasky u8 rsvd1; 602290650Shselasky u8 token; 603290650Shselasky u8 ctrl_sig; 604290650Shselasky u8 sig; 605290650Shselasky}; 606290650Shselasky 607322150Shselasky#define MLX5_NUM_CMDS_IN_ADAPTER_PAGE \ 608322150Shselasky (MLX5_ADAPTER_PAGE_SIZE / MLX5_CMD_MBOX_SIZE) 609322150ShselaskyCTASSERT(MLX5_CMD_MBOX_SIZE >= sizeof(struct mlx5_cmd_prot_block)); 610322150ShselaskyCTASSERT(MLX5_CMD_MBOX_SIZE <= MLX5_ADAPTER_PAGE_SIZE); 611322150Shselasky 612290650Shselaskyenum { 613290650Shselasky MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, 614290650Shselasky}; 615290650Shselasky 616290650Shselaskystruct mlx5_err_cqe { 617290650Shselasky u8 rsvd0[32]; 618290650Shselasky __be32 srqn; 619290650Shselasky u8 rsvd1[18]; 620290650Shselasky u8 vendor_err_synd; 621290650Shselasky u8 syndrome; 622290650Shselasky __be32 s_wqe_opcode_qpn; 623290650Shselasky __be16 wqe_counter; 624290650Shselasky u8 signature; 625290650Shselasky u8 op_own; 626290650Shselasky}; 627290650Shselasky 628290650Shselaskystruct mlx5_cqe64 { 629290650Shselasky u8 tunneled_etc; 630290650Shselasky u8 rsvd0[3]; 631290650Shselasky u8 lro_tcppsh_abort_dupack; 632290650Shselasky u8 lro_min_ttl; 633290650Shselasky __be16 lro_tcp_win; 634290650Shselasky __be32 lro_ack_seq_num; 635290650Shselasky __be32 rss_hash_result; 636290650Shselasky u8 rss_hash_type; 637290650Shselasky u8 ml_path; 638290650Shselasky u8 rsvd20[2]; 639290650Shselasky __be16 check_sum; 640290650Shselasky __be16 slid; 641290650Shselasky __be32 flags_rqpn; 642290650Shselasky u8 hds_ip_ext; 643290650Shselasky u8 l4_hdr_type_etc; 644290650Shselasky __be16 vlan_info; 645290650Shselasky __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ 646290650Shselasky __be32 imm_inval_pkey; 647290650Shselasky u8 rsvd40[4]; 648290650Shselasky __be32 byte_cnt; 649290650Shselasky __be64 timestamp; 650290650Shselasky __be32 sop_drop_qpn; 651290650Shselasky __be16 wqe_counter; 652290650Shselasky u8 signature; 653290650Shselasky u8 op_own; 654290650Shselasky}; 655290650Shselasky 656290650Shselaskystatic inline bool get_cqe_lro_timestamp_valid(struct mlx5_cqe64 *cqe) 657290650Shselasky{ 658290650Shselasky return (cqe->lro_tcppsh_abort_dupack >> 7) & 1; 659290650Shselasky} 660290650Shselasky 661290650Shselaskystatic inline bool get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) 662290650Shselasky{ 663290650Shselasky return (cqe->lro_tcppsh_abort_dupack >> 6) & 1; 664290650Shselasky} 665290650Shselasky 666290650Shselaskystatic inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) 667290650Shselasky{ 668290650Shselasky return (cqe->l4_hdr_type_etc >> 4) & 0x7; 669290650Shselasky} 670290650Shselasky 671290650Shselaskystatic inline u16 get_cqe_vlan(struct mlx5_cqe64 *cqe) 672290650Shselasky{ 673290650Shselasky return be16_to_cpu(cqe->vlan_info) & 0xfff; 674290650Shselasky} 675290650Shselasky 676290650Shselaskystatic inline void get_cqe_smac(struct mlx5_cqe64 *cqe, u8 *smac) 677290650Shselasky{ 678290650Shselasky memcpy(smac, &cqe->rss_hash_type , 4); 679290650Shselasky memcpy(smac + 4, &cqe->slid , 2); 680290650Shselasky} 681290650Shselasky 682290650Shselaskystatic inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe) 683290650Shselasky{ 684290650Shselasky return cqe->l4_hdr_type_etc & 0x1; 685290650Shselasky} 686290650Shselasky 687290650Shselaskystatic inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe) 688290650Shselasky{ 689290650Shselasky return cqe->tunneled_etc & 0x1; 690290650Shselasky} 691290650Shselasky 692290650Shselaskyenum { 693290650Shselasky CQE_L4_HDR_TYPE_NONE = 0x0, 694290650Shselasky CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, 695290650Shselasky CQE_L4_HDR_TYPE_UDP = 0x2, 696290650Shselasky CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, 697290650Shselasky CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, 698290650Shselasky}; 699290650Shselasky 700290650Shselaskyenum { 701290650Shselasky /* source L3 hash types */ 702290650Shselasky CQE_RSS_SRC_HTYPE_IP = 0x3 << 0, 703290650Shselasky CQE_RSS_SRC_HTYPE_IPV4 = 0x1 << 0, 704290650Shselasky CQE_RSS_SRC_HTYPE_IPV6 = 0x2 << 0, 705290650Shselasky 706290650Shselasky /* destination L3 hash types */ 707290650Shselasky CQE_RSS_DST_HTYPE_IP = 0x3 << 2, 708290650Shselasky CQE_RSS_DST_HTYPE_IPV4 = 0x1 << 2, 709290650Shselasky CQE_RSS_DST_HTYPE_IPV6 = 0x2 << 2, 710290650Shselasky 711290650Shselasky /* source L4 hash types */ 712290650Shselasky CQE_RSS_SRC_HTYPE_L4 = 0x3 << 4, 713290650Shselasky CQE_RSS_SRC_HTYPE_TCP = 0x1 << 4, 714290650Shselasky CQE_RSS_SRC_HTYPE_UDP = 0x2 << 4, 715290650Shselasky CQE_RSS_SRC_HTYPE_IPSEC = 0x3 << 4, 716290650Shselasky 717290650Shselasky /* destination L4 hash types */ 718290650Shselasky CQE_RSS_DST_HTYPE_L4 = 0x3 << 6, 719290650Shselasky CQE_RSS_DST_HTYPE_TCP = 0x1 << 6, 720290650Shselasky CQE_RSS_DST_HTYPE_UDP = 0x2 << 6, 721290650Shselasky CQE_RSS_DST_HTYPE_IPSEC = 0x3 << 6, 722290650Shselasky}; 723290650Shselasky 724290650Shselaskyenum { 725329204Shselasky MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0, 726329204Shselasky MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1, 727329204Shselasky MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2, 728290650Shselasky}; 729290650Shselasky 730290650Shselaskyenum { 731290650Shselasky CQE_L2_OK = 1 << 0, 732290650Shselasky CQE_L3_OK = 1 << 1, 733290650Shselasky CQE_L4_OK = 1 << 2, 734290650Shselasky}; 735290650Shselasky 736290650Shselaskystruct mlx5_sig_err_cqe { 737290650Shselasky u8 rsvd0[16]; 738290650Shselasky __be32 expected_trans_sig; 739290650Shselasky __be32 actual_trans_sig; 740290650Shselasky __be32 expected_reftag; 741290650Shselasky __be32 actual_reftag; 742290650Shselasky __be16 syndrome; 743290650Shselasky u8 rsvd22[2]; 744290650Shselasky __be32 mkey; 745290650Shselasky __be64 err_offset; 746290650Shselasky u8 rsvd30[8]; 747290650Shselasky __be32 qpn; 748290650Shselasky u8 rsvd38[2]; 749290650Shselasky u8 signature; 750290650Shselasky u8 op_own; 751290650Shselasky}; 752290650Shselasky 753290650Shselaskystruct mlx5_wqe_srq_next_seg { 754290650Shselasky u8 rsvd0[2]; 755290650Shselasky __be16 next_wqe_index; 756290650Shselasky u8 signature; 757290650Shselasky u8 rsvd1[11]; 758290650Shselasky}; 759290650Shselasky 760290650Shselaskyunion mlx5_ext_cqe { 761290650Shselasky struct ib_grh grh; 762290650Shselasky u8 inl[64]; 763290650Shselasky}; 764290650Shselasky 765290650Shselaskystruct mlx5_cqe128 { 766290650Shselasky union mlx5_ext_cqe inl_grh; 767290650Shselasky struct mlx5_cqe64 cqe64; 768290650Shselasky}; 769290650Shselasky 770306233Shselaskyenum { 771306233Shselasky MLX5_MKEY_STATUS_FREE = 1 << 6, 772306233Shselasky}; 773306233Shselasky 774290650Shselaskystruct mlx5_mkey_seg { 775290650Shselasky /* This is a two bit field occupying bits 31-30. 776290650Shselasky * bit 31 is always 0, 777290650Shselasky * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation 778290650Shselasky */ 779290650Shselasky u8 status; 780290650Shselasky u8 pcie_control; 781290650Shselasky u8 flags; 782290650Shselasky u8 version; 783290650Shselasky __be32 qpn_mkey7_0; 784290650Shselasky u8 rsvd1[4]; 785290650Shselasky __be32 flags_pd; 786290650Shselasky __be64 start_addr; 787290650Shselasky __be64 len; 788290650Shselasky __be32 bsfs_octo_size; 789290650Shselasky u8 rsvd2[16]; 790290650Shselasky __be32 xlt_oct_size; 791290650Shselasky u8 rsvd3[3]; 792290650Shselasky u8 log2_page_size; 793290650Shselasky u8 rsvd4[4]; 794290650Shselasky}; 795290650Shselasky 796290650Shselasky#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 797290650Shselasky 798290650Shselaskyenum { 799290650Shselasky MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 800290650Shselasky}; 801290650Shselasky 802306233Shselaskystatic inline int mlx5_host_is_le(void) 803306233Shselasky{ 804306233Shselasky#if defined(__LITTLE_ENDIAN) 805306233Shselasky return 1; 806306233Shselasky#elif defined(__BIG_ENDIAN) 807306233Shselasky return 0; 808306233Shselasky#else 809306233Shselasky#error Host endianness not defined 810306233Shselasky#endif 811306233Shselasky} 812306233Shselasky 813290650Shselasky#define MLX5_CMD_OP_MAX 0x939 814290650Shselasky 815290650Shselaskyenum { 816290650Shselasky VPORT_STATE_DOWN = 0x0, 817290650Shselasky VPORT_STATE_UP = 0x1, 818290650Shselasky}; 819290650Shselasky 820290650Shselaskyenum { 821290650Shselasky MLX5_L3_PROT_TYPE_IPV4 = 0, 822290650Shselasky MLX5_L3_PROT_TYPE_IPV6 = 1, 823290650Shselasky}; 824290650Shselasky 825290650Shselaskyenum { 826290650Shselasky MLX5_L4_PROT_TYPE_TCP = 0, 827290650Shselasky MLX5_L4_PROT_TYPE_UDP = 1, 828290650Shselasky}; 829290650Shselasky 830290650Shselaskyenum { 831290650Shselasky MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, 832290650Shselasky MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, 833290650Shselasky MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, 834290650Shselasky MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, 835290650Shselasky MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, 836290650Shselasky}; 837290650Shselasky 838290650Shselaskyenum { 839290650Shselasky MLX5_MATCH_OUTER_HEADERS = 1 << 0, 840290650Shselasky MLX5_MATCH_MISC_PARAMETERS = 1 << 1, 841290650Shselasky MLX5_MATCH_INNER_HEADERS = 1 << 2, 842290650Shselasky 843290650Shselasky}; 844290650Shselasky 845290650Shselaskyenum { 846290650Shselasky MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, 847290650Shselasky MLX5_FLOW_TABLE_TYPE_EGRESS_ACL = 2, 848290650Shselasky MLX5_FLOW_TABLE_TYPE_INGRESS_ACL = 3, 849290650Shselasky MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, 850306233Shselasky MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 5, 851306233Shselasky MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 6, 852329200Shselasky MLX5_FLOW_TABLE_TYPE_NIC_RX_RDMA = 7, 853290650Shselasky}; 854290650Shselasky 855290650Shselaskyenum { 856290650Shselasky MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_NONE = 0, 857290650Shselasky MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_IF_NO_VLAN = 1, 858290650Shselasky MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_OVERWRITE = 2 859290650Shselasky}; 860290650Shselasky 861290650Shselaskyenum { 862290650Shselasky MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_STRIP = 1 << 0, 863290650Shselasky MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_STRIP = 1 << 1, 864290650Shselasky MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_INSERT = 1 << 2, 865290650Shselasky MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_INSERT = 1 << 3 866290650Shselasky}; 867290650Shselasky 868291939Shselaskyenum { 869291939Shselasky MLX5_UC_ADDR_CHANGE = (1 << 0), 870291939Shselasky MLX5_MC_ADDR_CHANGE = (1 << 1), 871291939Shselasky MLX5_VLAN_CHANGE = (1 << 2), 872291939Shselasky MLX5_PROMISC_CHANGE = (1 << 3), 873291939Shselasky MLX5_MTU_CHANGE = (1 << 4), 874291939Shselasky}; 875291939Shselasky 876291939Shselaskyenum mlx5_list_type { 877291939Shselasky MLX5_NIC_VPORT_LIST_TYPE_UC = 0x0, 878291939Shselasky MLX5_NIC_VPORT_LIST_TYPE_MC = 0x1, 879291939Shselasky MLX5_NIC_VPORT_LIST_TYPE_VLAN = 0x2, 880291939Shselasky}; 881291939Shselasky 882291939Shselaskyenum { 883291939Shselasky MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0, 884291939Shselasky MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1, 885291939Shselasky MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2, 886291939Shselasky}; 887292838Shselasky 888290650Shselasky/* MLX5 DEV CAPs */ 889290650Shselasky 890290650Shselasky/* TODO: EAT.ME */ 891290650Shselaskyenum mlx5_cap_mode { 892290650Shselasky HCA_CAP_OPMOD_GET_MAX = 0, 893290650Shselasky HCA_CAP_OPMOD_GET_CUR = 1, 894290650Shselasky}; 895290650Shselasky 896290650Shselaskyenum mlx5_cap_type { 897290650Shselasky MLX5_CAP_GENERAL = 0, 898290650Shselasky MLX5_CAP_ETHERNET_OFFLOADS, 899290650Shselasky MLX5_CAP_ODP, 900290650Shselasky MLX5_CAP_ATOMIC, 901290650Shselasky MLX5_CAP_ROCE, 902290650Shselasky MLX5_CAP_IPOIB_OFFLOADS, 903290650Shselasky MLX5_CAP_EOIB_OFFLOADS, 904290650Shselasky MLX5_CAP_FLOW_TABLE, 905290650Shselasky MLX5_CAP_ESWITCH_FLOW_TABLE, 906290650Shselasky MLX5_CAP_ESWITCH, 907306233Shselasky MLX5_CAP_SNAPSHOT, 908306233Shselasky MLX5_CAP_VECTOR_CALC, 909306233Shselasky MLX5_CAP_QOS, 910306233Shselasky MLX5_CAP_DEBUG, 911290650Shselasky /* NUM OF CAP Types */ 912290650Shselasky MLX5_CAP_NUM 913290650Shselasky}; 914290650Shselasky 915337098Shselaskyenum mlx5_qcam_reg_groups { 916337098Shselasky MLX5_QCAM_REGS_FIRST_128 = 0x0, 917337098Shselasky}; 918337098Shselasky 919337098Shselaskyenum mlx5_qcam_feature_groups { 920337098Shselasky MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0, 921337098Shselasky}; 922337098Shselasky 923290650Shselasky/* GET Dev Caps macros */ 924290650Shselasky#define MLX5_CAP_GEN(mdev, cap) \ 925290650Shselasky MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap) 926290650Shselasky 927290650Shselasky#define MLX5_CAP_GEN_MAX(mdev, cap) \ 928290650Shselasky MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap) 929290650Shselasky 930290650Shselasky#define MLX5_CAP_ETH(mdev, cap) \ 931290650Shselasky MLX5_GET(per_protocol_networking_offload_caps,\ 932290650Shselasky mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap) 933290650Shselasky 934290650Shselasky#define MLX5_CAP_ETH_MAX(mdev, cap) \ 935290650Shselasky MLX5_GET(per_protocol_networking_offload_caps,\ 936290650Shselasky mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap) 937290650Shselasky 938290650Shselasky#define MLX5_CAP_ROCE(mdev, cap) \ 939290650Shselasky MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap) 940290650Shselasky 941290650Shselasky#define MLX5_CAP_ROCE_MAX(mdev, cap) \ 942290650Shselasky MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap) 943290650Shselasky 944290650Shselasky#define MLX5_CAP_ATOMIC(mdev, cap) \ 945290650Shselasky MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap) 946290650Shselasky 947290650Shselasky#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ 948290650Shselasky MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap) 949290650Shselasky 950290650Shselasky#define MLX5_CAP_FLOWTABLE(mdev, cap) \ 951290650Shselasky MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap) 952290650Shselasky 953290650Shselasky#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \ 954290650Shselasky MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap) 955290650Shselasky 956290650Shselasky#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ 957290650Shselasky MLX5_GET(flow_table_eswitch_cap, \ 958290650Shselasky mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 959290650Shselasky 960290650Shselasky#define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \ 961290650Shselasky MLX5_GET(flow_table_eswitch_cap, \ 962290650Shselasky mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 963290650Shselasky 964306233Shselasky#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ 965306233Shselasky MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap) 966291939Shselasky 967306233Shselasky#define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \ 968306233Shselasky MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap) 969291939Shselasky 970306233Shselasky#define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \ 971306233Shselasky MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap) 972291939Shselasky 973306233Shselasky#define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \ 974306233Shselasky MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap) 975291939Shselasky 976306233Shselasky#define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \ 977306233Shselasky MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap) 978306233Shselasky 979306233Shselasky#define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \ 980306233Shselasky MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap) 981306233Shselasky 982290650Shselasky#define MLX5_CAP_ESW(mdev, cap) \ 983290650Shselasky MLX5_GET(e_switch_cap, \ 984290650Shselasky mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap) 985290650Shselasky 986290650Shselasky#define MLX5_CAP_ESW_MAX(mdev, cap) \ 987290650Shselasky MLX5_GET(e_switch_cap, \ 988290650Shselasky mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap) 989290650Shselasky 990290650Shselasky#define MLX5_CAP_ODP(mdev, cap)\ 991290650Shselasky MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap) 992290650Shselasky 993290650Shselasky#define MLX5_CAP_ODP_MAX(mdev, cap)\ 994290650Shselasky MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap) 995290650Shselasky 996306233Shselasky#define MLX5_CAP_SNAPSHOT(mdev, cap) \ 997306233Shselasky MLX5_GET(snapshot_cap, \ 998306233Shselasky mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap) 999306233Shselasky 1000306233Shselasky#define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \ 1001306233Shselasky MLX5_GET(snapshot_cap, \ 1002306233Shselasky mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap) 1003306233Shselasky 1004306233Shselasky#define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \ 1005306233Shselasky MLX5_GET(per_protocol_networking_offload_caps,\ 1006306233Shselasky mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap) 1007306233Shselasky 1008306233Shselasky#define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \ 1009306233Shselasky MLX5_GET(per_protocol_networking_offload_caps,\ 1010306233Shselasky mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap) 1011306233Shselasky 1012306233Shselasky#define MLX5_CAP_DEBUG(mdev, cap) \ 1013306233Shselasky MLX5_GET(debug_cap, \ 1014306233Shselasky mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap) 1015306233Shselasky 1016306233Shselasky#define MLX5_CAP_DEBUG_MAX(mdev, cap) \ 1017306233Shselasky MLX5_GET(debug_cap, \ 1018306233Shselasky mdev->hca_caps_max[MLX5_CAP_DEBUG], cap) 1019306233Shselasky 1020306233Shselasky#define MLX5_CAP_QOS(mdev, cap) \ 1021306233Shselasky MLX5_GET(qos_cap,\ 1022306233Shselasky mdev->hca_caps_cur[MLX5_CAP_QOS], cap) 1023306233Shselasky 1024306233Shselasky#define MLX5_CAP_QOS_MAX(mdev, cap) \ 1025306233Shselasky MLX5_GET(qos_cap,\ 1026306233Shselasky mdev->hca_caps_max[MLX5_CAP_QOS], cap) 1027306233Shselasky 1028337098Shselasky#define MLX5_CAP_QCAM_REG(mdev, fld) \ 1029337098Shselasky MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld) 1030337098Shselasky 1031337098Shselasky#define MLX5_CAP_QCAM_FEATURE(mdev, fld) \ 1032337098Shselasky MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld) 1033337098Shselasky 1034290650Shselaskyenum { 1035290650Shselasky MLX5_CMD_STAT_OK = 0x0, 1036290650Shselasky MLX5_CMD_STAT_INT_ERR = 0x1, 1037290650Shselasky MLX5_CMD_STAT_BAD_OP_ERR = 0x2, 1038290650Shselasky MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, 1039290650Shselasky MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, 1040290650Shselasky MLX5_CMD_STAT_BAD_RES_ERR = 0x5, 1041290650Shselasky MLX5_CMD_STAT_RES_BUSY = 0x6, 1042290650Shselasky MLX5_CMD_STAT_LIM_ERR = 0x8, 1043290650Shselasky MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, 1044290650Shselasky MLX5_CMD_STAT_IX_ERR = 0xa, 1045290650Shselasky MLX5_CMD_STAT_NO_RES_ERR = 0xf, 1046290650Shselasky MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, 1047290650Shselasky MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, 1048290650Shselasky MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, 1049290650Shselasky MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, 1050290650Shselasky MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, 1051290650Shselasky}; 1052290650Shselasky 1053290650Shselaskyenum { 1054290650Shselasky MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0, 1055290650Shselasky MLX5_RFC_2863_COUNTERS_GROUP = 0x1, 1056290650Shselasky MLX5_RFC_2819_COUNTERS_GROUP = 0x2, 1057290650Shselasky MLX5_RFC_3635_COUNTERS_GROUP = 0x3, 1058290650Shselasky MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5, 1059308678Shselasky MLX5_ETHERNET_DISCARD_COUNTERS_GROUP = 0x6, 1060290650Shselasky MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10, 1061290650Shselasky MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11, 1062290650Shselasky MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12, 1063329204Shselasky MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16, 1064308678Shselasky MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20, 1065290650Shselasky}; 1066290650Shselasky 1067290650Shselaskyenum { 1068306233Shselasky MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0, 1069306233Shselasky MLX5_PCIE_LANE_COUNTERS_GROUP = 0x1, 1070306233Shselasky MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP = 0x2, 1071306233Shselasky}; 1072306233Shselasky 1073306233Shselaskyenum { 1074306233Shselasky MLX5_NUM_UUARS_PER_PAGE = MLX5_NON_FP_BF_REGS_PER_PAGE, 1075306233Shselasky MLX5_DEF_TOT_UUARS = 8 * MLX5_NUM_UUARS_PER_PAGE, 1076306233Shselasky}; 1077306233Shselasky 1078306233Shselaskyenum { 1079306233Shselasky NUM_DRIVER_UARS = 4, 1080306233Shselasky NUM_LOW_LAT_UUARS = 4, 1081306233Shselasky}; 1082306233Shselasky 1083306233Shselaskyenum { 1084290650Shselasky MLX5_CAP_PORT_TYPE_IB = 0x0, 1085290650Shselasky MLX5_CAP_PORT_TYPE_ETH = 0x1, 1086290650Shselasky}; 1087290650Shselasky 1088290650Shselaskyenum { 1089290650Shselasky MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_L2 = 0x0, 1090290650Shselasky MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_VPORT_CONFIG = 0x1, 1091290650Shselasky MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_NOT_REQUIRED = 0x2 1092290650Shselasky}; 1093290650Shselasky 1094337114Shselaskyenum mlx5_inline_modes { 1095337114Shselasky MLX5_INLINE_MODE_NONE, 1096337114Shselasky MLX5_INLINE_MODE_L2, 1097337114Shselasky MLX5_INLINE_MODE_IP, 1098337114Shselasky MLX5_INLINE_MODE_TCP_UDP, 1099337114Shselasky}; 1100337114Shselasky 1101290650Shselaskyenum { 1102290650Shselasky MLX5_QUERY_VPORT_STATE_OUT_STATE_FOLLOW = 0x2, 1103290650Shselasky}; 1104290650Shselasky 1105290650Shselaskystatic inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) 1106290650Shselasky{ 1107290650Shselasky if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) 1108290650Shselasky return 0; 1109290650Shselasky return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; 1110290650Shselasky} 1111290650Shselasky 1112290650Shselaskystruct mlx5_ifc_mcia_reg_bits { 1113290650Shselasky u8 l[0x1]; 1114290650Shselasky u8 reserved_0[0x7]; 1115290650Shselasky u8 module[0x8]; 1116290650Shselasky u8 reserved_1[0x8]; 1117290650Shselasky u8 status[0x8]; 1118290650Shselasky 1119290650Shselasky u8 i2c_device_address[0x8]; 1120290650Shselasky u8 page_number[0x8]; 1121290650Shselasky u8 device_address[0x10]; 1122290650Shselasky 1123290650Shselasky u8 reserved_2[0x10]; 1124290650Shselasky u8 size[0x10]; 1125290650Shselasky 1126290650Shselasky u8 reserved_3[0x20]; 1127290650Shselasky 1128290650Shselasky u8 dword_0[0x20]; 1129290650Shselasky u8 dword_1[0x20]; 1130290650Shselasky u8 dword_2[0x20]; 1131290650Shselasky u8 dword_3[0x20]; 1132290650Shselasky u8 dword_4[0x20]; 1133290650Shselasky u8 dword_5[0x20]; 1134290650Shselasky u8 dword_6[0x20]; 1135290650Shselasky u8 dword_7[0x20]; 1136290650Shselasky u8 dword_8[0x20]; 1137290650Shselasky u8 dword_9[0x20]; 1138290650Shselasky u8 dword_10[0x20]; 1139290650Shselasky u8 dword_11[0x20]; 1140290650Shselasky}; 1141290650Shselasky 1142290650Shselasky#define MLX5_CMD_OP_QUERY_EEPROM 0x93c 1143292838Shselasky 1144292838Shselaskystruct mlx5_mini_cqe8 { 1145292838Shselasky union { 1146308676Shselasky __be32 rx_hash_result; 1147308676Shselasky __be16 checksum; 1148308676Shselasky __be16 rsvd; 1149292838Shselasky struct { 1150308676Shselasky __be16 wqe_counter; 1151292838Shselasky u8 s_wqe_opcode; 1152292838Shselasky u8 reserved; 1153292838Shselasky } s_wqe_info; 1154292838Shselasky }; 1155308676Shselasky __be32 byte_cnt; 1156292838Shselasky}; 1157292838Shselasky 1158292838Shselaskyenum { 1159292838Shselasky MLX5_NO_INLINE_DATA, 1160292838Shselasky MLX5_INLINE_DATA32_SEG, 1161292838Shselasky MLX5_INLINE_DATA64_SEG, 1162292838Shselasky MLX5_COMPRESSED, 1163292838Shselasky}; 1164292838Shselasky 1165292838Shselaskyenum mlx5_exp_cqe_zip_recv_type { 1166292838Shselasky MLX5_CQE_FORMAT_HASH, 1167292838Shselasky MLX5_CQE_FORMAT_CSUM, 1168292838Shselasky}; 1169292838Shselasky 1170292838Shselasky#define MLX5E_CQE_FORMAT_MASK 0xc 1171292838Shselaskystatic inline int mlx5_get_cqe_format(const struct mlx5_cqe64 *cqe) 1172292838Shselasky{ 1173292838Shselasky return (cqe->op_own & MLX5E_CQE_FORMAT_MASK) >> 2; 1174292838Shselasky} 1175292838Shselasky 1176329205Shselaskyenum { 1177329205Shselasky MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1, 1178329205Shselasky}; 1179329205Shselasky 1180306233Shselasky/* 8 regular priorities + 1 for multicast */ 1181306233Shselasky#define MLX5_NUM_BYPASS_FTS 9 1182306233Shselasky 1183290650Shselasky#endif /* MLX5_DEVICE_H */ 1184