1290650Shselasky/*- 2337098Shselasky * Copyright (c) 2013-2018, Mellanox Technologies, Ltd. All rights reserved. 3290650Shselasky * 4290650Shselasky * Redistribution and use in source and binary forms, with or without 5290650Shselasky * modification, are permitted provided that the following conditions 6290650Shselasky * are met: 7290650Shselasky * 1. Redistributions of source code must retain the above copyright 8290650Shselasky * notice, this list of conditions and the following disclaimer. 9290650Shselasky * 2. Redistributions in binary form must reproduce the above copyright 10290650Shselasky * notice, this list of conditions and the following disclaimer in the 11290650Shselasky * documentation and/or other materials provided with the distribution. 12290650Shselasky * 13290650Shselasky * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14290650Shselasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15290650Shselasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16290650Shselasky * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17290650Shselasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18290650Shselasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19290650Shselasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20290650Shselasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21290650Shselasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22290650Shselasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23290650Shselasky * SUCH DAMAGE. 24290650Shselasky * 25290650Shselasky * $FreeBSD: stable/11/sys/dev/mlx5/device.h 361414 2020-05-23 12:00:46Z kib $ 26290650Shselasky */ 27290650Shselasky 28290650Shselasky#ifndef MLX5_DEVICE_H 29290650Shselasky#define MLX5_DEVICE_H 30290650Shselasky 31290650Shselasky#include <linux/types.h> 32290650Shselasky#include <rdma/ib_verbs.h> 33290650Shselasky#include <dev/mlx5/mlx5_ifc.h> 34290650Shselasky 35353254Shselasky#define FW_INIT_TIMEOUT_MILI 2000 36353254Shselasky#define FW_INIT_WAIT_MS 2 37353254Shselasky#define FW_PRE_INIT_TIMEOUT_MILI 120000 38353254Shselasky#define FW_INIT_WARN_MESSAGE_INTERVAL 20000 39290650Shselasky 40290650Shselasky#if defined(__LITTLE_ENDIAN) 41290650Shselasky#define MLX5_SET_HOST_ENDIANNESS 0 42290650Shselasky#elif defined(__BIG_ENDIAN) 43290650Shselasky#define MLX5_SET_HOST_ENDIANNESS 0x80 44290650Shselasky#else 45290650Shselasky#error Host endianness not defined 46290650Shselasky#endif 47290650Shselasky 48290650Shselasky/* helper macros */ 49290650Shselasky#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 50290650Shselasky#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 51290650Shselasky#define __mlx5_bit_off(typ, fld) __offsetof(struct mlx5_ifc_##typ##_bits, fld) 52337098Shselasky#define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16) 53290650Shselasky#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 54290650Shselasky#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 55337098Shselasky#define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf)) 56290650Shselasky#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) 57290650Shselasky#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 58290650Shselasky#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) 59337098Shselasky#define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 60337098Shselasky#define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld)) 61290650Shselasky#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) 62290650Shselasky 63290650Shselasky#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 64290650Shselasky#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 65290650Shselasky#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 66306233Shselasky#define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64) 67290650Shselasky#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 68290650Shselasky#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) 69290650Shselasky#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 70290650Shselasky#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 71290650Shselasky 72290650Shselasky/* insert a value to a struct */ 73290650Shselasky#define MLX5_SET(typ, p, fld, v) do { \ 74290650Shselasky BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 75290650Shselasky BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 76290650Shselasky *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 77290650Shselasky cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 78290650Shselasky (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ 79290650Shselasky << __mlx5_dw_bit_off(typ, fld))); \ 80290650Shselasky} while (0) 81290650Shselasky 82290650Shselasky#define MLX5_SET_TO_ONES(typ, p, fld) do { \ 83290650Shselasky BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 84290650Shselasky BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 85290650Shselasky *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 86290650Shselasky cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 87290650Shselasky (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ 88290650Shselasky << __mlx5_dw_bit_off(typ, fld))); \ 89290650Shselasky} while (0) 90290650Shselasky 91290650Shselasky#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ 92290650Shselasky__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 93290650Shselasky__mlx5_mask(typ, fld)) 94290650Shselasky 95290650Shselasky#define MLX5_GET_PR(typ, p, fld) ({ \ 96290650Shselasky u32 ___t = MLX5_GET(typ, p, fld); \ 97290650Shselasky pr_debug(#fld " = 0x%x\n", ___t); \ 98290650Shselasky ___t; \ 99290650Shselasky}) 100290650Shselasky 101331807Shselasky#define __MLX5_SET64(typ, p, fld, v) do { \ 102290650Shselasky BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ 103290650Shselasky *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ 104290650Shselasky} while (0) 105290650Shselasky 106331807Shselasky#define MLX5_SET64(typ, p, fld, v) do { \ 107331807Shselasky BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 108331807Shselasky __MLX5_SET64(typ, p, fld, v); \ 109331807Shselasky} while (0) 110331807Shselasky 111331807Shselasky#define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \ 112331807Shselasky BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 113331807Shselasky __MLX5_SET64(typ, p, fld[idx], v); \ 114331807Shselasky} while (0) 115331807Shselasky 116290650Shselasky#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) 117290650Shselasky 118337098Shselasky#define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\ 119337098Shselasky__mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \ 120337098Shselasky__mlx5_mask16(typ, fld)) 121337098Shselasky 122337098Shselasky#define MLX5_SET16(typ, p, fld, v) do { \ 123337098Shselasky u16 _v = v; \ 124337098Shselasky BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \ 125337098Shselasky *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \ 126337098Shselasky cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \ 127337098Shselasky (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \ 128337098Shselasky << __mlx5_16_bit_off(typ, fld))); \ 129337098Shselasky} while (0) 130337098Shselasky 131329204Shselasky#define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\ 132329204Shselasky __mlx5_64_off(typ, fld))) 133329204Shselasky 134329204Shselasky#define MLX5_GET_BE(type_t, typ, p, fld) ({ \ 135329204Shselasky type_t tmp; \ 136329204Shselasky switch (sizeof(tmp)) { \ 137329204Shselasky case sizeof(u8): \ 138329204Shselasky tmp = (__force type_t)MLX5_GET(typ, p, fld); \ 139329204Shselasky break; \ 140329204Shselasky case sizeof(u16): \ 141329204Shselasky tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \ 142329204Shselasky break; \ 143329204Shselasky case sizeof(u32): \ 144329204Shselasky tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \ 145329204Shselasky break; \ 146329204Shselasky case sizeof(u64): \ 147329204Shselasky tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \ 148329204Shselasky break; \ 149329204Shselasky } \ 150329204Shselasky tmp; \ 151329204Shselasky }) 152329204Shselasky 153329204Shselasky#define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8 154329204Shselasky#define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8 155329204Shselasky#define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1 156329204Shselasky#define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\ 157329204Shselasky MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\ 158329204Shselasky MLX5_BY_PASS_NUM_MULTICAST_PRIOS) 159329204Shselasky 160331585Shselasky/* insert a value to a struct */ 161331585Shselasky#define MLX5_VSC_SET(typ, p, fld, v) do { \ 162331585Shselasky BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 163331585Shselasky BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 164331585Shselasky *((__le32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 165331585Shselasky cpu_to_le32((le32_to_cpu(*((__le32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 166331585Shselasky (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ 167331585Shselasky << __mlx5_dw_bit_off(typ, fld))); \ 168331585Shselasky} while (0) 169331585Shselasky 170331585Shselasky#define MLX5_VSC_GET(typ, p, fld) ((le32_to_cpu(*((__le32 *)(p) +\ 171331585Shselasky__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 172331585Shselasky__mlx5_mask(typ, fld)) 173331585Shselasky 174331585Shselasky#define MLX5_VSC_GET_PR(typ, p, fld) ({ \ 175331585Shselasky u32 ___t = MLX5_VSC_GET(typ, p, fld); \ 176331585Shselasky pr_debug(#fld " = 0x%x\n", ___t); \ 177331585Shselasky ___t; \ 178331585Shselasky}) 179331585Shselasky 180290650Shselaskyenum { 181290650Shselasky MLX5_MAX_COMMANDS = 32, 182290650Shselasky MLX5_CMD_DATA_BLOCK_SIZE = 512, 183322150Shselasky MLX5_CMD_MBOX_SIZE = 1024, 184290650Shselasky MLX5_PCI_CMD_XPORT = 7, 185290650Shselasky MLX5_MKEY_BSF_OCTO_SIZE = 4, 186290650Shselasky MLX5_MAX_PSVS = 4, 187290650Shselasky}; 188290650Shselasky 189290650Shselaskyenum { 190290650Shselasky MLX5_EXTENDED_UD_AV = 0x80000000, 191290650Shselasky}; 192290650Shselasky 193290650Shselaskyenum { 194306233Shselasky MLX5_CQ_FLAGS_OI = 2, 195306233Shselasky}; 196306233Shselasky 197306233Shselaskyenum { 198290650Shselasky MLX5_STAT_RATE_OFFSET = 5, 199290650Shselasky}; 200290650Shselasky 201290650Shselaskyenum { 202290650Shselasky MLX5_INLINE_SEG = 0x80000000, 203290650Shselasky}; 204290650Shselasky 205290650Shselaskyenum { 206290650Shselasky MLX5_HW_START_PADDING = MLX5_INLINE_SEG, 207290650Shselasky}; 208290650Shselasky 209290650Shselaskyenum { 210290650Shselasky MLX5_MIN_PKEY_TABLE_SIZE = 128, 211290650Shselasky MLX5_MAX_LOG_PKEY_TABLE = 5, 212290650Shselasky}; 213290650Shselasky 214290650Shselaskyenum { 215306233Shselasky MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31 216306233Shselasky}; 217306233Shselasky 218306233Shselaskyenum { 219290650Shselasky MLX5_PERM_LOCAL_READ = 1 << 2, 220290650Shselasky MLX5_PERM_LOCAL_WRITE = 1 << 3, 221290650Shselasky MLX5_PERM_REMOTE_READ = 1 << 4, 222290650Shselasky MLX5_PERM_REMOTE_WRITE = 1 << 5, 223290650Shselasky MLX5_PERM_ATOMIC = 1 << 6, 224290650Shselasky MLX5_PERM_UMR_EN = 1 << 7, 225290650Shselasky}; 226290650Shselasky 227290650Shselaskyenum { 228290650Shselasky MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 229290650Shselasky MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 230290650Shselasky MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 231290650Shselasky MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 232290650Shselasky MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 233290650Shselasky}; 234290650Shselasky 235290650Shselaskyenum { 236290650Shselasky MLX5_MKEY_REMOTE_INVAL = 1 << 24, 237290650Shselasky MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 238290650Shselasky MLX5_MKEY_BSF_EN = 1 << 30, 239290650Shselasky MLX5_MKEY_LEN64 = 1 << 31, 240290650Shselasky}; 241290650Shselasky 242290650Shselaskyenum { 243290650Shselasky MLX5_EN_RD = (u64)1, 244290650Shselasky MLX5_EN_WR = (u64)2 245290650Shselasky}; 246290650Shselasky 247290650Shselaskyenum { 248290650Shselasky MLX5_BF_REGS_PER_PAGE = 4, 249290650Shselasky MLX5_MAX_UAR_PAGES = 1 << 8, 250290650Shselasky MLX5_NON_FP_BF_REGS_PER_PAGE = 2, 251290650Shselasky MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE, 252290650Shselasky}; 253290650Shselasky 254290650Shselaskyenum { 255290650Shselasky MLX5_MKEY_MASK_LEN = 1ull << 0, 256290650Shselasky MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 257290650Shselasky MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 258290650Shselasky MLX5_MKEY_MASK_PD = 1ull << 7, 259290650Shselasky MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 260290650Shselasky MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, 261290650Shselasky MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 262290650Shselasky MLX5_MKEY_MASK_KEY = 1ull << 13, 263290650Shselasky MLX5_MKEY_MASK_QPN = 1ull << 14, 264290650Shselasky MLX5_MKEY_MASK_LR = 1ull << 17, 265290650Shselasky MLX5_MKEY_MASK_LW = 1ull << 18, 266290650Shselasky MLX5_MKEY_MASK_RR = 1ull << 19, 267290650Shselasky MLX5_MKEY_MASK_RW = 1ull << 20, 268290650Shselasky MLX5_MKEY_MASK_A = 1ull << 21, 269290650Shselasky MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 270290650Shselasky MLX5_MKEY_MASK_FREE = 1ull << 29, 271290650Shselasky}; 272290650Shselasky 273290650Shselaskyenum { 274306233Shselasky MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), 275306233Shselasky 276306233Shselasky MLX5_UMR_CHECK_NOT_FREE = (1 << 5), 277306233Shselasky MLX5_UMR_CHECK_FREE = (2 << 5), 278306233Shselasky 279306233Shselasky MLX5_UMR_INLINE = (1 << 7), 280306233Shselasky}; 281306233Shselasky 282306233Shselasky#define MLX5_UMR_MTT_ALIGNMENT 0x40 283306233Shselasky#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) 284306233Shselasky#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT 285306233Shselasky 286306233Shselaskyenum { 287306233Shselasky MLX5_EVENT_QUEUE_TYPE_QP = 0, 288306233Shselasky MLX5_EVENT_QUEUE_TYPE_RQ = 1, 289306233Shselasky MLX5_EVENT_QUEUE_TYPE_SQ = 2, 290306233Shselasky}; 291306233Shselasky 292306233Shselaskyenum { 293290650Shselasky MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 294290650Shselasky MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 295290650Shselasky MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 296290650Shselasky MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 297290650Shselasky MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 298290650Shselasky MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 299290650Shselasky MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 300290650Shselasky}; 301290650Shselasky 302290650Shselaskyenum { 303306233Shselasky MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX = 1, 304306233Shselasky MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE, 305306233Shselasky MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE, 306306233Shselasky MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE, 307306233Shselasky MLX5_MAX_INLINE_RECEIVE_SIZE = 64 308306233Shselasky}; 309306233Shselasky 310306233Shselaskyenum { 311290650Shselasky MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, 312290650Shselasky MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 313290650Shselasky MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 314290650Shselasky MLX5_DEV_CAP_FLAG_APM = 1LL << 17, 315290650Shselasky MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD = 1LL << 21, 316290650Shselasky MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, 317290650Shselasky MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, 318290650Shselasky MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, 319306233Shselasky MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 33, 320290650Shselasky MLX5_DEV_CAP_FLAG_ROCE = 1LL << 34, 321290650Shselasky MLX5_DEV_CAP_FLAG_DCT = 1LL << 37, 322290650Shselasky MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, 323290650Shselasky MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, 324306233Shselasky MLX5_DEV_CAP_FLAG_DRAIN_SIGERR = 1LL << 48, 325290650Shselasky}; 326290650Shselasky 327290650Shselaskyenum { 328290650Shselasky MLX5_ROCE_VERSION_1 = 0, 329290650Shselasky MLX5_ROCE_VERSION_1_5 = 1, 330290650Shselasky MLX5_ROCE_VERSION_2 = 2, 331290650Shselasky}; 332290650Shselasky 333290650Shselaskyenum { 334290650Shselasky MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1, 335290650Shselasky MLX5_ROCE_VERSION_1_5_CAP = 1 << MLX5_ROCE_VERSION_1_5, 336290650Shselasky MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2, 337290650Shselasky}; 338290650Shselasky 339290650Shselaskyenum { 340290650Shselasky MLX5_ROCE_L3_TYPE_IPV4 = 0, 341290650Shselasky MLX5_ROCE_L3_TYPE_IPV6 = 1, 342290650Shselasky}; 343290650Shselasky 344290650Shselaskyenum { 345290650Shselasky MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1, 346290650Shselasky MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2, 347290650Shselasky}; 348290650Shselasky 349290650Shselaskyenum { 350290650Shselasky MLX5_OPCODE_NOP = 0x00, 351290650Shselasky MLX5_OPCODE_SEND_INVAL = 0x01, 352290650Shselasky MLX5_OPCODE_RDMA_WRITE = 0x08, 353290650Shselasky MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 354290650Shselasky MLX5_OPCODE_SEND = 0x0a, 355290650Shselasky MLX5_OPCODE_SEND_IMM = 0x0b, 356290650Shselasky MLX5_OPCODE_LSO = 0x0e, 357290650Shselasky MLX5_OPCODE_RDMA_READ = 0x10, 358290650Shselasky MLX5_OPCODE_ATOMIC_CS = 0x11, 359290650Shselasky MLX5_OPCODE_ATOMIC_FA = 0x12, 360290650Shselasky MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 361290650Shselasky MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 362290650Shselasky MLX5_OPCODE_BIND_MW = 0x18, 363290650Shselasky MLX5_OPCODE_CONFIG_CMD = 0x1f, 364290650Shselasky 365290650Shselasky MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 366290650Shselasky MLX5_RECV_OPCODE_SEND = 0x01, 367290650Shselasky MLX5_RECV_OPCODE_SEND_IMM = 0x02, 368290650Shselasky MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 369290650Shselasky 370290650Shselasky MLX5_CQE_OPCODE_ERROR = 0x1e, 371290650Shselasky MLX5_CQE_OPCODE_RESIZE = 0x16, 372290650Shselasky 373290650Shselasky MLX5_OPCODE_SET_PSV = 0x20, 374290650Shselasky MLX5_OPCODE_GET_PSV = 0x21, 375290650Shselasky MLX5_OPCODE_CHECK_PSV = 0x22, 376290650Shselasky MLX5_OPCODE_RGET_PSV = 0x26, 377290650Shselasky MLX5_OPCODE_RCHECK_PSV = 0x27, 378290650Shselasky 379290650Shselasky MLX5_OPCODE_UMR = 0x25, 380290650Shselasky 381306233Shselasky MLX5_OPCODE_SIGNATURE_CANCELED = (1 << 15), 382290650Shselasky}; 383290650Shselasky 384290650Shselaskyenum { 385290650Shselasky MLX5_SET_PORT_RESET_QKEY = 0, 386290650Shselasky MLX5_SET_PORT_GUID0 = 16, 387290650Shselasky MLX5_SET_PORT_NODE_GUID = 17, 388290650Shselasky MLX5_SET_PORT_SYS_GUID = 18, 389290650Shselasky MLX5_SET_PORT_GID_TABLE = 19, 390290650Shselasky MLX5_SET_PORT_PKEY_TABLE = 20, 391290650Shselasky}; 392290650Shselasky 393290650Shselaskyenum { 394290650Shselasky MLX5_MAX_PAGE_SHIFT = 31 395290650Shselasky}; 396290650Shselasky 397290650Shselaskyenum { 398290650Shselasky MLX5_ADAPTER_PAGE_SHIFT = 12, 399290650Shselasky MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 400290650Shselasky}; 401290650Shselasky 402290650Shselaskyenum { 403290650Shselasky MLX5_CAP_OFF_CMDIF_CSUM = 46, 404290650Shselasky}; 405290650Shselasky 406329204Shselaskyenum { 407329204Shselasky /* 408329204Shselasky * Max wqe size for rdma read is 512 bytes, so this 409329204Shselasky * limits our max_sge_rd as the wqe needs to fit: 410329204Shselasky * - ctrl segment (16 bytes) 411329204Shselasky * - rdma segment (16 bytes) 412329204Shselasky * - scatter elements (16 bytes each) 413329204Shselasky */ 414329204Shselasky MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16 415329204Shselasky}; 416329204Shselasky 417290650Shselaskystruct mlx5_cmd_layout { 418290650Shselasky u8 type; 419290650Shselasky u8 rsvd0[3]; 420290650Shselasky __be32 inlen; 421290650Shselasky __be64 in_ptr; 422290650Shselasky __be32 in[4]; 423290650Shselasky __be32 out[4]; 424290650Shselasky __be64 out_ptr; 425290650Shselasky __be32 outlen; 426290650Shselasky u8 token; 427290650Shselasky u8 sig; 428290650Shselasky u8 rsvd1; 429290650Shselasky u8 status_own; 430290650Shselasky}; 431290650Shselasky 432331814Shselaskyenum mlx5_fatal_assert_bit_offsets { 433331814Shselasky MLX5_RFR_OFFSET = 31, 434331814Shselasky}; 435331814Shselasky 436290650Shselaskystruct mlx5_health_buffer { 437290650Shselasky __be32 assert_var[5]; 438290650Shselasky __be32 rsvd0[3]; 439290650Shselasky __be32 assert_exit_ptr; 440290650Shselasky __be32 assert_callra; 441290650Shselasky __be32 rsvd1[2]; 442290650Shselasky __be32 fw_ver; 443290650Shselasky __be32 hw_id; 444331814Shselasky __be32 rfr; 445290650Shselasky u8 irisc_index; 446290650Shselasky u8 synd; 447331580Shselasky __be16 ext_synd; 448290650Shselasky}; 449290650Shselasky 450331814Shselaskyenum mlx5_initializing_bit_offsets { 451331814Shselasky MLX5_FW_RESET_SUPPORTED_OFFSET = 30, 452331814Shselasky}; 453331814Shselasky 454331814Shselaskyenum mlx5_cmd_addr_l_sz_offset { 455331814Shselasky MLX5_NIC_IFC_OFFSET = 8, 456331814Shselasky}; 457331814Shselasky 458290650Shselaskystruct mlx5_init_seg { 459290650Shselasky __be32 fw_rev; 460290650Shselasky __be32 cmdif_rev_fw_sub; 461290650Shselasky __be32 rsvd0[2]; 462290650Shselasky __be32 cmdq_addr_h; 463290650Shselasky __be32 cmdq_addr_l_sz; 464290650Shselasky __be32 cmd_dbell; 465290650Shselasky __be32 rsvd1[120]; 466290650Shselasky __be32 initializing; 467290650Shselasky struct mlx5_health_buffer health; 468306233Shselasky __be32 rsvd2[880]; 469306233Shselasky __be32 internal_timer_h; 470306233Shselasky __be32 internal_timer_l; 471306233Shselasky __be32 rsvd3[2]; 472290650Shselasky __be32 health_counter; 473306233Shselasky __be32 rsvd4[1019]; 474290650Shselasky __be64 ieee1588_clk; 475290650Shselasky __be32 ieee1588_clk_type; 476290650Shselasky __be32 clr_intx; 477290650Shselasky}; 478290650Shselasky 479290650Shselaskystruct mlx5_eqe_comp { 480290650Shselasky __be32 reserved[6]; 481290650Shselasky __be32 cqn; 482290650Shselasky}; 483290650Shselasky 484290650Shselaskystruct mlx5_eqe_qp_srq { 485290650Shselasky __be32 reserved[6]; 486290650Shselasky __be32 qp_srq_n; 487290650Shselasky}; 488290650Shselasky 489290650Shselaskystruct mlx5_eqe_cq_err { 490290650Shselasky __be32 cqn; 491290650Shselasky u8 reserved1[7]; 492290650Shselasky u8 syndrome; 493290650Shselasky}; 494290650Shselasky 495290650Shselaskystruct mlx5_eqe_port_state { 496290650Shselasky u8 reserved0[8]; 497290650Shselasky u8 port; 498290650Shselasky}; 499290650Shselasky 500290650Shselaskystruct mlx5_eqe_gpio { 501290650Shselasky __be32 reserved0[2]; 502290650Shselasky __be64 gpio_event; 503290650Shselasky}; 504290650Shselasky 505290650Shselaskystruct mlx5_eqe_congestion { 506290650Shselasky u8 type; 507290650Shselasky u8 rsvd0; 508290650Shselasky u8 congestion_level; 509290650Shselasky}; 510290650Shselasky 511290650Shselaskystruct mlx5_eqe_stall_vl { 512290650Shselasky u8 rsvd0[3]; 513290650Shselasky u8 port_vl; 514290650Shselasky}; 515290650Shselasky 516290650Shselaskystruct mlx5_eqe_cmd { 517290650Shselasky __be32 vector; 518290650Shselasky __be32 rsvd[6]; 519290650Shselasky}; 520290650Shselasky 521290650Shselaskystruct mlx5_eqe_page_req { 522290650Shselasky u8 rsvd0[2]; 523290650Shselasky __be16 func_id; 524290650Shselasky __be32 num_pages; 525290650Shselasky __be32 rsvd1[5]; 526290650Shselasky}; 527290650Shselasky 528290650Shselaskystruct mlx5_eqe_vport_change { 529290650Shselasky u8 rsvd0[2]; 530290650Shselasky __be16 vport_num; 531290650Shselasky __be32 rsvd1[6]; 532290650Shselasky}; 533290650Shselasky 534290650Shselasky 535290650Shselasky#define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF 536290650Shselasky#define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF 537290650Shselasky 538290650Shselaskyenum { 539331575Shselasky MLX5_MODULE_STATUS_PLUGGED_ENABLED = 0x1, 540331575Shselasky MLX5_MODULE_STATUS_UNPLUGGED = 0x2, 541331575Shselasky MLX5_MODULE_STATUS_ERROR = 0x3, 542353206Shselasky MLX5_MODULE_STATUS_NUM , 543290650Shselasky}; 544290650Shselasky 545290650Shselaskyenum { 546290650Shselasky MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED = 0x0, 547290650Shselasky MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE = 0x1, 548290650Shselasky MLX5_MODULE_EVENT_ERROR_BUS_STUCK = 0x2, 549290650Shselasky MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT = 0x3, 550290650Shselasky MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST = 0x4, 551331575Shselasky MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE = 0x5, 552290650Shselasky MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE = 0x6, 553306233Shselasky MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED = 0x7, 554361413Skib MLX5_MODULE_EVENT_ERROR_PMD_TYPE_NOT_ENABLED = 0x8, 555361414Skib MLX5_MODULE_EVENT_ERROR_LASTER_TEC_FAILURE = 0x9, 556361414Skib MLX5_MODULE_EVENT_ERROR_HIGH_CURRENT = 0xa, 557361414Skib MLX5_MODULE_EVENT_ERROR_HIGH_VOLTAGE = 0xb, 558361414Skib MLX5_MODULE_EVENT_ERROR_PCIE_SYS_POWER_SLOT_EXCEEDED = 0xc, 559361414Skib MLX5_MODULE_EVENT_ERROR_HIGH_POWER = 0xd, 560361414Skib MLX5_MODULE_EVENT_ERROR_MODULE_STATE_MACHINE_FAULT = 0xe, 561353206Shselasky MLX5_MODULE_EVENT_ERROR_NUM , 562290650Shselasky}; 563290650Shselasky 564290650Shselaskystruct mlx5_eqe_port_module_event { 565290650Shselasky u8 rsvd0; 566290650Shselasky u8 module; 567290650Shselasky u8 rsvd1; 568290650Shselasky u8 module_status; 569290650Shselasky u8 rsvd2[2]; 570290650Shselasky u8 error_type; 571290650Shselasky}; 572290650Shselasky 573329205Shselaskystruct mlx5_eqe_general_notification_event { 574329205Shselasky u32 rq_user_index_delay_drop; 575329205Shselasky u32 rsvd0[6]; 576329205Shselasky}; 577329205Shselasky 578347800Shselaskystruct mlx5_eqe_temp_warning { 579347800Shselasky __be64 sensor_warning_msb; 580347800Shselasky __be64 sensor_warning_lsb; 581347800Shselasky} __packed; 582347800Shselasky 583290650Shselaskyunion ev_data { 584290650Shselasky __be32 raw[7]; 585290650Shselasky struct mlx5_eqe_cmd cmd; 586290650Shselasky struct mlx5_eqe_comp comp; 587290650Shselasky struct mlx5_eqe_qp_srq qp_srq; 588290650Shselasky struct mlx5_eqe_cq_err cq_err; 589290650Shselasky struct mlx5_eqe_port_state port; 590290650Shselasky struct mlx5_eqe_gpio gpio; 591290650Shselasky struct mlx5_eqe_congestion cong; 592290650Shselasky struct mlx5_eqe_stall_vl stall_vl; 593290650Shselasky struct mlx5_eqe_page_req req_pages; 594290650Shselasky struct mlx5_eqe_port_module_event port_module_event; 595290650Shselasky struct mlx5_eqe_vport_change vport_change; 596329205Shselasky struct mlx5_eqe_general_notification_event general_notifications; 597347800Shselasky struct mlx5_eqe_temp_warning temp_warning; 598290650Shselasky} __packed; 599290650Shselasky 600290650Shselaskystruct mlx5_eqe { 601290650Shselasky u8 rsvd0; 602290650Shselasky u8 type; 603290650Shselasky u8 rsvd1; 604290650Shselasky u8 sub_type; 605290650Shselasky __be32 rsvd2[7]; 606290650Shselasky union ev_data data; 607290650Shselasky __be16 rsvd3; 608290650Shselasky u8 signature; 609290650Shselasky u8 owner; 610290650Shselasky} __packed; 611290650Shselasky 612290650Shselaskystruct mlx5_cmd_prot_block { 613290650Shselasky u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 614290650Shselasky u8 rsvd0[48]; 615290650Shselasky __be64 next; 616290650Shselasky __be32 block_num; 617290650Shselasky u8 rsvd1; 618290650Shselasky u8 token; 619290650Shselasky u8 ctrl_sig; 620290650Shselasky u8 sig; 621290650Shselasky}; 622290650Shselasky 623322150Shselasky#define MLX5_NUM_CMDS_IN_ADAPTER_PAGE \ 624322150Shselasky (MLX5_ADAPTER_PAGE_SIZE / MLX5_CMD_MBOX_SIZE) 625322150ShselaskyCTASSERT(MLX5_CMD_MBOX_SIZE >= sizeof(struct mlx5_cmd_prot_block)); 626322150ShselaskyCTASSERT(MLX5_CMD_MBOX_SIZE <= MLX5_ADAPTER_PAGE_SIZE); 627322150Shselasky 628290650Shselaskyenum { 629290650Shselasky MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, 630290650Shselasky}; 631290650Shselasky 632290650Shselaskystruct mlx5_err_cqe { 633290650Shselasky u8 rsvd0[32]; 634290650Shselasky __be32 srqn; 635290650Shselasky u8 rsvd1[18]; 636290650Shselasky u8 vendor_err_synd; 637290650Shselasky u8 syndrome; 638290650Shselasky __be32 s_wqe_opcode_qpn; 639290650Shselasky __be16 wqe_counter; 640290650Shselasky u8 signature; 641290650Shselasky u8 op_own; 642290650Shselasky}; 643290650Shselasky 644290650Shselaskystruct mlx5_cqe64 { 645290650Shselasky u8 tunneled_etc; 646290650Shselasky u8 rsvd0[3]; 647290650Shselasky u8 lro_tcppsh_abort_dupack; 648290650Shselasky u8 lro_min_ttl; 649290650Shselasky __be16 lro_tcp_win; 650290650Shselasky __be32 lro_ack_seq_num; 651290650Shselasky __be32 rss_hash_result; 652290650Shselasky u8 rss_hash_type; 653290650Shselasky u8 ml_path; 654290650Shselasky u8 rsvd20[2]; 655290650Shselasky __be16 check_sum; 656290650Shselasky __be16 slid; 657290650Shselasky __be32 flags_rqpn; 658290650Shselasky u8 hds_ip_ext; 659290650Shselasky u8 l4_hdr_type_etc; 660290650Shselasky __be16 vlan_info; 661290650Shselasky __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ 662290650Shselasky __be32 imm_inval_pkey; 663290650Shselasky u8 rsvd40[4]; 664290650Shselasky __be32 byte_cnt; 665290650Shselasky __be64 timestamp; 666290650Shselasky __be32 sop_drop_qpn; 667290650Shselasky __be16 wqe_counter; 668290650Shselasky u8 signature; 669290650Shselasky u8 op_own; 670290650Shselasky}; 671290650Shselasky 672290650Shselaskystatic inline bool get_cqe_lro_timestamp_valid(struct mlx5_cqe64 *cqe) 673290650Shselasky{ 674290650Shselasky return (cqe->lro_tcppsh_abort_dupack >> 7) & 1; 675290650Shselasky} 676290650Shselasky 677290650Shselaskystatic inline bool get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) 678290650Shselasky{ 679290650Shselasky return (cqe->lro_tcppsh_abort_dupack >> 6) & 1; 680290650Shselasky} 681290650Shselasky 682290650Shselaskystatic inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) 683290650Shselasky{ 684290650Shselasky return (cqe->l4_hdr_type_etc >> 4) & 0x7; 685290650Shselasky} 686290650Shselasky 687290650Shselaskystatic inline u16 get_cqe_vlan(struct mlx5_cqe64 *cqe) 688290650Shselasky{ 689290650Shselasky return be16_to_cpu(cqe->vlan_info) & 0xfff; 690290650Shselasky} 691290650Shselasky 692290650Shselaskystatic inline void get_cqe_smac(struct mlx5_cqe64 *cqe, u8 *smac) 693290650Shselasky{ 694290650Shselasky memcpy(smac, &cqe->rss_hash_type , 4); 695290650Shselasky memcpy(smac + 4, &cqe->slid , 2); 696290650Shselasky} 697290650Shselasky 698290650Shselaskystatic inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe) 699290650Shselasky{ 700290650Shselasky return cqe->l4_hdr_type_etc & 0x1; 701290650Shselasky} 702290650Shselasky 703290650Shselaskystatic inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe) 704290650Shselasky{ 705290650Shselasky return cqe->tunneled_etc & 0x1; 706290650Shselasky} 707290650Shselasky 708290650Shselaskyenum { 709290650Shselasky CQE_L4_HDR_TYPE_NONE = 0x0, 710290650Shselasky CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, 711290650Shselasky CQE_L4_HDR_TYPE_UDP = 0x2, 712290650Shselasky CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, 713290650Shselasky CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, 714290650Shselasky}; 715290650Shselasky 716290650Shselaskyenum { 717290650Shselasky /* source L3 hash types */ 718290650Shselasky CQE_RSS_SRC_HTYPE_IP = 0x3 << 0, 719290650Shselasky CQE_RSS_SRC_HTYPE_IPV4 = 0x1 << 0, 720290650Shselasky CQE_RSS_SRC_HTYPE_IPV6 = 0x2 << 0, 721290650Shselasky 722290650Shselasky /* destination L3 hash types */ 723290650Shselasky CQE_RSS_DST_HTYPE_IP = 0x3 << 2, 724290650Shselasky CQE_RSS_DST_HTYPE_IPV4 = 0x1 << 2, 725290650Shselasky CQE_RSS_DST_HTYPE_IPV6 = 0x2 << 2, 726290650Shselasky 727290650Shselasky /* source L4 hash types */ 728290650Shselasky CQE_RSS_SRC_HTYPE_L4 = 0x3 << 4, 729290650Shselasky CQE_RSS_SRC_HTYPE_TCP = 0x1 << 4, 730290650Shselasky CQE_RSS_SRC_HTYPE_UDP = 0x2 << 4, 731290650Shselasky CQE_RSS_SRC_HTYPE_IPSEC = 0x3 << 4, 732290650Shselasky 733290650Shselasky /* destination L4 hash types */ 734290650Shselasky CQE_RSS_DST_HTYPE_L4 = 0x3 << 6, 735290650Shselasky CQE_RSS_DST_HTYPE_TCP = 0x1 << 6, 736290650Shselasky CQE_RSS_DST_HTYPE_UDP = 0x2 << 6, 737290650Shselasky CQE_RSS_DST_HTYPE_IPSEC = 0x3 << 6, 738290650Shselasky}; 739290650Shselasky 740290650Shselaskyenum { 741329204Shselasky MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0, 742329204Shselasky MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1, 743329204Shselasky MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2, 744290650Shselasky}; 745290650Shselasky 746290650Shselaskyenum { 747290650Shselasky CQE_L2_OK = 1 << 0, 748290650Shselasky CQE_L3_OK = 1 << 1, 749290650Shselasky CQE_L4_OK = 1 << 2, 750290650Shselasky}; 751290650Shselasky 752290650Shselaskystruct mlx5_sig_err_cqe { 753290650Shselasky u8 rsvd0[16]; 754290650Shselasky __be32 expected_trans_sig; 755290650Shselasky __be32 actual_trans_sig; 756290650Shselasky __be32 expected_reftag; 757290650Shselasky __be32 actual_reftag; 758290650Shselasky __be16 syndrome; 759290650Shselasky u8 rsvd22[2]; 760290650Shselasky __be32 mkey; 761290650Shselasky __be64 err_offset; 762290650Shselasky u8 rsvd30[8]; 763290650Shselasky __be32 qpn; 764290650Shselasky u8 rsvd38[2]; 765290650Shselasky u8 signature; 766290650Shselasky u8 op_own; 767290650Shselasky}; 768290650Shselasky 769290650Shselaskystruct mlx5_wqe_srq_next_seg { 770290650Shselasky u8 rsvd0[2]; 771290650Shselasky __be16 next_wqe_index; 772290650Shselasky u8 signature; 773290650Shselasky u8 rsvd1[11]; 774290650Shselasky}; 775290650Shselasky 776290650Shselaskyunion mlx5_ext_cqe { 777290650Shselasky struct ib_grh grh; 778290650Shselasky u8 inl[64]; 779290650Shselasky}; 780290650Shselasky 781290650Shselaskystruct mlx5_cqe128 { 782290650Shselasky union mlx5_ext_cqe inl_grh; 783290650Shselasky struct mlx5_cqe64 cqe64; 784290650Shselasky}; 785290650Shselasky 786306233Shselaskyenum { 787306233Shselasky MLX5_MKEY_STATUS_FREE = 1 << 6, 788306233Shselasky}; 789306233Shselasky 790290650Shselaskystruct mlx5_mkey_seg { 791290650Shselasky /* This is a two bit field occupying bits 31-30. 792290650Shselasky * bit 31 is always 0, 793290650Shselasky * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation 794290650Shselasky */ 795290650Shselasky u8 status; 796290650Shselasky u8 pcie_control; 797290650Shselasky u8 flags; 798290650Shselasky u8 version; 799290650Shselasky __be32 qpn_mkey7_0; 800290650Shselasky u8 rsvd1[4]; 801290650Shselasky __be32 flags_pd; 802290650Shselasky __be64 start_addr; 803290650Shselasky __be64 len; 804290650Shselasky __be32 bsfs_octo_size; 805290650Shselasky u8 rsvd2[16]; 806290650Shselasky __be32 xlt_oct_size; 807290650Shselasky u8 rsvd3[3]; 808290650Shselasky u8 log2_page_size; 809290650Shselasky u8 rsvd4[4]; 810290650Shselasky}; 811290650Shselasky 812290650Shselasky#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 813290650Shselasky 814290650Shselaskyenum { 815290650Shselasky MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 816290650Shselasky}; 817290650Shselasky 818306233Shselaskystatic inline int mlx5_host_is_le(void) 819306233Shselasky{ 820306233Shselasky#if defined(__LITTLE_ENDIAN) 821306233Shselasky return 1; 822306233Shselasky#elif defined(__BIG_ENDIAN) 823306233Shselasky return 0; 824306233Shselasky#else 825306233Shselasky#error Host endianness not defined 826306233Shselasky#endif 827306233Shselasky} 828306233Shselasky 829290650Shselasky#define MLX5_CMD_OP_MAX 0x939 830290650Shselasky 831290650Shselaskyenum { 832290650Shselasky VPORT_STATE_DOWN = 0x0, 833290650Shselasky VPORT_STATE_UP = 0x1, 834359543Skib VPORT_STATE_FOLLOW = 0x2, 835290650Shselasky}; 836290650Shselasky 837290650Shselaskyenum { 838290650Shselasky MLX5_L3_PROT_TYPE_IPV4 = 0, 839290650Shselasky MLX5_L3_PROT_TYPE_IPV6 = 1, 840290650Shselasky}; 841290650Shselasky 842290650Shselaskyenum { 843290650Shselasky MLX5_L4_PROT_TYPE_TCP = 0, 844290650Shselasky MLX5_L4_PROT_TYPE_UDP = 1, 845290650Shselasky}; 846290650Shselasky 847290650Shselaskyenum { 848290650Shselasky MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, 849290650Shselasky MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, 850290650Shselasky MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, 851290650Shselasky MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, 852290650Shselasky MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, 853290650Shselasky}; 854290650Shselasky 855290650Shselaskyenum { 856290650Shselasky MLX5_MATCH_OUTER_HEADERS = 1 << 0, 857290650Shselasky MLX5_MATCH_MISC_PARAMETERS = 1 << 1, 858290650Shselasky MLX5_MATCH_INNER_HEADERS = 1 << 2, 859290650Shselasky 860290650Shselasky}; 861290650Shselasky 862290650Shselaskyenum { 863290650Shselasky MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, 864290650Shselasky MLX5_FLOW_TABLE_TYPE_EGRESS_ACL = 2, 865290650Shselasky MLX5_FLOW_TABLE_TYPE_INGRESS_ACL = 3, 866290650Shselasky MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, 867306233Shselasky MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 5, 868306233Shselasky MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 6, 869329200Shselasky MLX5_FLOW_TABLE_TYPE_NIC_RX_RDMA = 7, 870290650Shselasky}; 871290650Shselasky 872290650Shselaskyenum { 873290650Shselasky MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_NONE = 0, 874290650Shselasky MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_IF_NO_VLAN = 1, 875290650Shselasky MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_OVERWRITE = 2 876290650Shselasky}; 877290650Shselasky 878290650Shselaskyenum { 879290650Shselasky MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_STRIP = 1 << 0, 880290650Shselasky MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_STRIP = 1 << 1, 881290650Shselasky MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_INSERT = 1 << 2, 882290650Shselasky MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_INSERT = 1 << 3 883290650Shselasky}; 884290650Shselasky 885291939Shselaskyenum { 886291939Shselasky MLX5_UC_ADDR_CHANGE = (1 << 0), 887291939Shselasky MLX5_MC_ADDR_CHANGE = (1 << 1), 888291939Shselasky MLX5_VLAN_CHANGE = (1 << 2), 889291939Shselasky MLX5_PROMISC_CHANGE = (1 << 3), 890291939Shselasky MLX5_MTU_CHANGE = (1 << 4), 891291939Shselasky}; 892291939Shselasky 893291939Shselaskyenum mlx5_list_type { 894291939Shselasky MLX5_NIC_VPORT_LIST_TYPE_UC = 0x0, 895291939Shselasky MLX5_NIC_VPORT_LIST_TYPE_MC = 0x1, 896291939Shselasky MLX5_NIC_VPORT_LIST_TYPE_VLAN = 0x2, 897291939Shselasky}; 898291939Shselasky 899291939Shselaskyenum { 900291939Shselasky MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0, 901291939Shselasky MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1, 902291939Shselasky MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2, 903291939Shselasky}; 904292838Shselasky 905290650Shselasky/* MLX5 DEV CAPs */ 906290650Shselasky 907290650Shselasky/* TODO: EAT.ME */ 908290650Shselaskyenum mlx5_cap_mode { 909290650Shselasky HCA_CAP_OPMOD_GET_MAX = 0, 910290650Shselasky HCA_CAP_OPMOD_GET_CUR = 1, 911290650Shselasky}; 912290650Shselasky 913290650Shselaskyenum mlx5_cap_type { 914290650Shselasky MLX5_CAP_GENERAL = 0, 915290650Shselasky MLX5_CAP_ETHERNET_OFFLOADS, 916290650Shselasky MLX5_CAP_ODP, 917290650Shselasky MLX5_CAP_ATOMIC, 918290650Shselasky MLX5_CAP_ROCE, 919290650Shselasky MLX5_CAP_IPOIB_OFFLOADS, 920290650Shselasky MLX5_CAP_EOIB_OFFLOADS, 921290650Shselasky MLX5_CAP_FLOW_TABLE, 922290650Shselasky MLX5_CAP_ESWITCH_FLOW_TABLE, 923290650Shselasky MLX5_CAP_ESWITCH, 924306233Shselasky MLX5_CAP_SNAPSHOT, 925306233Shselasky MLX5_CAP_VECTOR_CALC, 926306233Shselasky MLX5_CAP_QOS, 927306233Shselasky MLX5_CAP_DEBUG, 928290650Shselasky /* NUM OF CAP Types */ 929290650Shselasky MLX5_CAP_NUM 930290650Shselasky}; 931290650Shselasky 932337098Shselaskyenum mlx5_qcam_reg_groups { 933337098Shselasky MLX5_QCAM_REGS_FIRST_128 = 0x0, 934337098Shselasky}; 935337098Shselasky 936337098Shselaskyenum mlx5_qcam_feature_groups { 937337098Shselasky MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0, 938337098Shselasky}; 939337098Shselasky 940347820Shselaskyenum mlx5_pcam_reg_groups { 941347820Shselasky MLX5_PCAM_REGS_5000_TO_507F = 0x0, 942347820Shselasky}; 943347820Shselasky 944347820Shselaskyenum mlx5_pcam_feature_groups { 945347820Shselasky MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0, 946347820Shselasky}; 947347820Shselasky 948347820Shselaskyenum mlx5_mcam_reg_groups { 949347820Shselasky MLX5_MCAM_REGS_FIRST_128 = 0x0, 950347820Shselasky}; 951347820Shselasky 952347820Shselaskyenum mlx5_mcam_feature_groups { 953347820Shselasky MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0, 954347820Shselasky}; 955347820Shselasky 956290650Shselasky/* GET Dev Caps macros */ 957290650Shselasky#define MLX5_CAP_GEN(mdev, cap) \ 958290650Shselasky MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap) 959290650Shselasky 960290650Shselasky#define MLX5_CAP_GEN_MAX(mdev, cap) \ 961290650Shselasky MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap) 962290650Shselasky 963290650Shselasky#define MLX5_CAP_ETH(mdev, cap) \ 964290650Shselasky MLX5_GET(per_protocol_networking_offload_caps,\ 965290650Shselasky mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap) 966290650Shselasky 967290650Shselasky#define MLX5_CAP_ETH_MAX(mdev, cap) \ 968290650Shselasky MLX5_GET(per_protocol_networking_offload_caps,\ 969290650Shselasky mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap) 970290650Shselasky 971290650Shselasky#define MLX5_CAP_ROCE(mdev, cap) \ 972290650Shselasky MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap) 973290650Shselasky 974290650Shselasky#define MLX5_CAP_ROCE_MAX(mdev, cap) \ 975290650Shselasky MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap) 976290650Shselasky 977290650Shselasky#define MLX5_CAP_ATOMIC(mdev, cap) \ 978290650Shselasky MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap) 979290650Shselasky 980290650Shselasky#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ 981290650Shselasky MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap) 982290650Shselasky 983290650Shselasky#define MLX5_CAP_FLOWTABLE(mdev, cap) \ 984290650Shselasky MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap) 985290650Shselasky 986290650Shselasky#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \ 987290650Shselasky MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap) 988290650Shselasky 989290650Shselasky#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ 990290650Shselasky MLX5_GET(flow_table_eswitch_cap, \ 991290650Shselasky mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 992290650Shselasky 993290650Shselasky#define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \ 994290650Shselasky MLX5_GET(flow_table_eswitch_cap, \ 995290650Shselasky mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 996290650Shselasky 997306233Shselasky#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ 998306233Shselasky MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap) 999291939Shselasky 1000306233Shselasky#define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \ 1001306233Shselasky MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap) 1002291939Shselasky 1003306233Shselasky#define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \ 1004306233Shselasky MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap) 1005291939Shselasky 1006306233Shselasky#define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \ 1007306233Shselasky MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap) 1008291939Shselasky 1009306233Shselasky#define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \ 1010306233Shselasky MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap) 1011306233Shselasky 1012306233Shselasky#define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \ 1013306233Shselasky MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap) 1014306233Shselasky 1015290650Shselasky#define MLX5_CAP_ESW(mdev, cap) \ 1016290650Shselasky MLX5_GET(e_switch_cap, \ 1017290650Shselasky mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap) 1018290650Shselasky 1019290650Shselasky#define MLX5_CAP_ESW_MAX(mdev, cap) \ 1020290650Shselasky MLX5_GET(e_switch_cap, \ 1021290650Shselasky mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap) 1022290650Shselasky 1023290650Shselasky#define MLX5_CAP_ODP(mdev, cap)\ 1024290650Shselasky MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap) 1025290650Shselasky 1026290650Shselasky#define MLX5_CAP_ODP_MAX(mdev, cap)\ 1027290650Shselasky MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap) 1028290650Shselasky 1029306233Shselasky#define MLX5_CAP_SNAPSHOT(mdev, cap) \ 1030306233Shselasky MLX5_GET(snapshot_cap, \ 1031306233Shselasky mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap) 1032306233Shselasky 1033306233Shselasky#define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \ 1034306233Shselasky MLX5_GET(snapshot_cap, \ 1035306233Shselasky mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap) 1036306233Shselasky 1037306233Shselasky#define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \ 1038306233Shselasky MLX5_GET(per_protocol_networking_offload_caps,\ 1039306233Shselasky mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap) 1040306233Shselasky 1041306233Shselasky#define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \ 1042306233Shselasky MLX5_GET(per_protocol_networking_offload_caps,\ 1043306233Shselasky mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap) 1044306233Shselasky 1045306233Shselasky#define MLX5_CAP_DEBUG(mdev, cap) \ 1046306233Shselasky MLX5_GET(debug_cap, \ 1047306233Shselasky mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap) 1048306233Shselasky 1049306233Shselasky#define MLX5_CAP_DEBUG_MAX(mdev, cap) \ 1050306233Shselasky MLX5_GET(debug_cap, \ 1051306233Shselasky mdev->hca_caps_max[MLX5_CAP_DEBUG], cap) 1052306233Shselasky 1053306233Shselasky#define MLX5_CAP_QOS(mdev, cap) \ 1054306233Shselasky MLX5_GET(qos_cap,\ 1055306233Shselasky mdev->hca_caps_cur[MLX5_CAP_QOS], cap) 1056306233Shselasky 1057306233Shselasky#define MLX5_CAP_QOS_MAX(mdev, cap) \ 1058306233Shselasky MLX5_GET(qos_cap,\ 1059306233Shselasky mdev->hca_caps_max[MLX5_CAP_QOS], cap) 1060306233Shselasky 1061347822Shselasky#define MLX5_CAP_PCAM_FEATURE(mdev, fld) \ 1062347822Shselasky MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld) 1063347822Shselasky 1064353244Shselasky#define MLX5_CAP_PCAM_REG(mdev, reg) \ 1065353244Shselasky MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg) 1066353244Shselasky 1067347822Shselasky#define MLX5_CAP_MCAM_FEATURE(mdev, fld) \ 1068347822Shselasky MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld) 1069347822Shselasky 1070347825Shselasky#define MLX5_CAP_MCAM_REG(mdev, reg) \ 1071347825Shselasky MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg) 1072347825Shselasky 1073337098Shselasky#define MLX5_CAP_QCAM_REG(mdev, fld) \ 1074337098Shselasky MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld) 1075337098Shselasky 1076337098Shselasky#define MLX5_CAP_QCAM_FEATURE(mdev, fld) \ 1077337098Shselasky MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld) 1078337098Shselasky 1079341958Shselasky#define MLX5_CAP_FPGA(mdev, cap) \ 1080341958Shselasky MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap) 1081341958Shselasky 1082341958Shselasky#define MLX5_CAP64_FPGA(mdev, cap) \ 1083341958Shselasky MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap) 1084341958Shselasky 1085290650Shselaskyenum { 1086290650Shselasky MLX5_CMD_STAT_OK = 0x0, 1087290650Shselasky MLX5_CMD_STAT_INT_ERR = 0x1, 1088290650Shselasky MLX5_CMD_STAT_BAD_OP_ERR = 0x2, 1089290650Shselasky MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, 1090290650Shselasky MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, 1091290650Shselasky MLX5_CMD_STAT_BAD_RES_ERR = 0x5, 1092290650Shselasky MLX5_CMD_STAT_RES_BUSY = 0x6, 1093290650Shselasky MLX5_CMD_STAT_LIM_ERR = 0x8, 1094290650Shselasky MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, 1095290650Shselasky MLX5_CMD_STAT_IX_ERR = 0xa, 1096290650Shselasky MLX5_CMD_STAT_NO_RES_ERR = 0xf, 1097290650Shselasky MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, 1098290650Shselasky MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, 1099290650Shselasky MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, 1100290650Shselasky MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, 1101290650Shselasky MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, 1102290650Shselasky}; 1103290650Shselasky 1104290650Shselaskyenum { 1105290650Shselasky MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0, 1106290650Shselasky MLX5_RFC_2863_COUNTERS_GROUP = 0x1, 1107290650Shselasky MLX5_RFC_2819_COUNTERS_GROUP = 0x2, 1108290650Shselasky MLX5_RFC_3635_COUNTERS_GROUP = 0x3, 1109290650Shselasky MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5, 1110308678Shselasky MLX5_ETHERNET_DISCARD_COUNTERS_GROUP = 0x6, 1111290650Shselasky MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10, 1112290650Shselasky MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11, 1113290650Shselasky MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12, 1114329204Shselasky MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16, 1115308678Shselasky MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20, 1116290650Shselasky}; 1117290650Shselasky 1118290650Shselaskyenum { 1119306233Shselasky MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0, 1120306233Shselasky MLX5_PCIE_LANE_COUNTERS_GROUP = 0x1, 1121306233Shselasky MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP = 0x2, 1122306233Shselasky}; 1123306233Shselasky 1124306233Shselaskyenum { 1125306233Shselasky MLX5_NUM_UUARS_PER_PAGE = MLX5_NON_FP_BF_REGS_PER_PAGE, 1126306233Shselasky MLX5_DEF_TOT_UUARS = 8 * MLX5_NUM_UUARS_PER_PAGE, 1127306233Shselasky}; 1128306233Shselasky 1129306233Shselaskyenum { 1130306233Shselasky NUM_DRIVER_UARS = 4, 1131306233Shselasky NUM_LOW_LAT_UUARS = 4, 1132306233Shselasky}; 1133306233Shselasky 1134306233Shselaskyenum { 1135290650Shselasky MLX5_CAP_PORT_TYPE_IB = 0x0, 1136290650Shselasky MLX5_CAP_PORT_TYPE_ETH = 0x1, 1137290650Shselasky}; 1138290650Shselasky 1139290650Shselaskyenum { 1140290650Shselasky MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_L2 = 0x0, 1141290650Shselasky MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_VPORT_CONFIG = 0x1, 1142290650Shselasky MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_NOT_REQUIRED = 0x2 1143290650Shselasky}; 1144290650Shselasky 1145337114Shselaskyenum mlx5_inline_modes { 1146337114Shselasky MLX5_INLINE_MODE_NONE, 1147337114Shselasky MLX5_INLINE_MODE_L2, 1148337114Shselasky MLX5_INLINE_MODE_IP, 1149337114Shselasky MLX5_INLINE_MODE_TCP_UDP, 1150337114Shselasky}; 1151337114Shselasky 1152290650Shselaskyenum { 1153290650Shselasky MLX5_QUERY_VPORT_STATE_OUT_STATE_FOLLOW = 0x2, 1154290650Shselasky}; 1155290650Shselasky 1156290650Shselaskystatic inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) 1157290650Shselasky{ 1158290650Shselasky if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) 1159290650Shselasky return 0; 1160290650Shselasky return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; 1161290650Shselasky} 1162290650Shselasky 1163290650Shselaskystruct mlx5_ifc_mcia_reg_bits { 1164290650Shselasky u8 l[0x1]; 1165290650Shselasky u8 reserved_0[0x7]; 1166290650Shselasky u8 module[0x8]; 1167290650Shselasky u8 reserved_1[0x8]; 1168290650Shselasky u8 status[0x8]; 1169290650Shselasky 1170290650Shselasky u8 i2c_device_address[0x8]; 1171290650Shselasky u8 page_number[0x8]; 1172290650Shselasky u8 device_address[0x10]; 1173290650Shselasky 1174290650Shselasky u8 reserved_2[0x10]; 1175290650Shselasky u8 size[0x10]; 1176290650Shselasky 1177290650Shselasky u8 reserved_3[0x20]; 1178290650Shselasky 1179290650Shselasky u8 dword_0[0x20]; 1180290650Shselasky u8 dword_1[0x20]; 1181290650Shselasky u8 dword_2[0x20]; 1182290650Shselasky u8 dword_3[0x20]; 1183290650Shselasky u8 dword_4[0x20]; 1184290650Shselasky u8 dword_5[0x20]; 1185290650Shselasky u8 dword_6[0x20]; 1186290650Shselasky u8 dword_7[0x20]; 1187290650Shselasky u8 dword_8[0x20]; 1188290650Shselasky u8 dword_9[0x20]; 1189290650Shselasky u8 dword_10[0x20]; 1190290650Shselasky u8 dword_11[0x20]; 1191290650Shselasky}; 1192290650Shselasky 1193290650Shselasky#define MLX5_CMD_OP_QUERY_EEPROM 0x93c 1194292838Shselasky 1195292838Shselaskystruct mlx5_mini_cqe8 { 1196292838Shselasky union { 1197308676Shselasky __be32 rx_hash_result; 1198308676Shselasky __be16 checksum; 1199308676Shselasky __be16 rsvd; 1200292838Shselasky struct { 1201308676Shselasky __be16 wqe_counter; 1202292838Shselasky u8 s_wqe_opcode; 1203292838Shselasky u8 reserved; 1204292838Shselasky } s_wqe_info; 1205292838Shselasky }; 1206308676Shselasky __be32 byte_cnt; 1207292838Shselasky}; 1208292838Shselasky 1209292838Shselaskyenum { 1210292838Shselasky MLX5_NO_INLINE_DATA, 1211292838Shselasky MLX5_INLINE_DATA32_SEG, 1212292838Shselasky MLX5_INLINE_DATA64_SEG, 1213292838Shselasky MLX5_COMPRESSED, 1214292838Shselasky}; 1215292838Shselasky 1216292838Shselaskyenum mlx5_exp_cqe_zip_recv_type { 1217292838Shselasky MLX5_CQE_FORMAT_HASH, 1218292838Shselasky MLX5_CQE_FORMAT_CSUM, 1219292838Shselasky}; 1220292838Shselasky 1221292838Shselasky#define MLX5E_CQE_FORMAT_MASK 0xc 1222292838Shselaskystatic inline int mlx5_get_cqe_format(const struct mlx5_cqe64 *cqe) 1223292838Shselasky{ 1224292838Shselasky return (cqe->op_own & MLX5E_CQE_FORMAT_MASK) >> 2; 1225292838Shselasky} 1226292838Shselasky 1227329205Shselaskyenum { 1228329205Shselasky MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1, 1229347862Shselasky MLX5_GEN_EVENT_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5, 1230329205Shselasky}; 1231329205Shselasky 1232347868Shselaskyenum { 1233347868Shselasky MLX5_FRL_LEVEL3 = 0x8, 1234347868Shselasky MLX5_FRL_LEVEL6 = 0x40, 1235347868Shselasky}; 1236347868Shselasky 1237306233Shselasky/* 8 regular priorities + 1 for multicast */ 1238306233Shselasky#define MLX5_NUM_BYPASS_FTS 9 1239306233Shselasky 1240290650Shselasky#endif /* MLX5_DEVICE_H */ 1241