qp.h revision 291694
1219820Sjeff/* 2219820Sjeff * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3219820Sjeff * 4219820Sjeff * This software is available to you under a choice of one of two 5219820Sjeff * licenses. You may choose to be licensed under the terms of the GNU 6219820Sjeff * General Public License (GPL) Version 2, available from the file 7219820Sjeff * COPYING in the main directory of this source tree, or the 8219820Sjeff * OpenIB.org BSD license below: 9219820Sjeff * 10219820Sjeff * Redistribution and use in source and binary forms, with or 11219820Sjeff * without modification, are permitted provided that the following 12219820Sjeff * conditions are met: 13219820Sjeff * 14219820Sjeff * - Redistributions of source code must retain the above 15219820Sjeff * copyright notice, this list of conditions and the following 16219820Sjeff * disclaimer. 17219820Sjeff * 18219820Sjeff * - Redistributions in binary form must reproduce the above 19219820Sjeff * copyright notice, this list of conditions and the following 20219820Sjeff * disclaimer in the documentation and/or other materials 21219820Sjeff * provided with the distribution. 22219820Sjeff * 23219820Sjeff * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24219820Sjeff * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25219820Sjeff * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26219820Sjeff * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27219820Sjeff * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28219820Sjeff * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29219820Sjeff * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30219820Sjeff * SOFTWARE. 31219820Sjeff */ 32219820Sjeff 33219820Sjeff#ifndef MLX4_QP_H 34219820Sjeff#define MLX4_QP_H 35219820Sjeff 36219820Sjeff#include <linux/types.h> 37219820Sjeff 38219820Sjeff#include <linux/mlx4/device.h> 39219820Sjeff 40219820Sjeff#define MLX4_INVALID_LKEY 0x100 41219820Sjeff 42291694Shselasky#define DS_SIZE_ALIGNMENT 16 43291694Shselasky 44291694Shselasky#define SET_BYTE_COUNT(byte_count) cpu_to_be32(byte_count) 45291694Shselasky#define SET_LSO_MSS(mss_hdr_size) cpu_to_be32(mss_hdr_size) 46291694Shselasky#define DS_BYTE_COUNT_MASK cpu_to_be32(0x7fffffff) 47291694Shselasky 48255932Salfredenum ib_m_qp_attr_mask { 49255932Salfred IB_M_EXT_CLASS_1 = 1 << 28, 50255932Salfred IB_M_EXT_CLASS_2 = 1 << 29, 51255932Salfred IB_M_EXT_CLASS_3 = 1 << 30, 52255932Salfred 53255932Salfred IB_M_QP_MOD_VEND_MASK = (IB_M_EXT_CLASS_1 | IB_M_EXT_CLASS_2 | 54255932Salfred IB_M_EXT_CLASS_3) 55255932Salfred}; 56255932Salfred 57219820Sjeffenum mlx4_qp_optpar { 58219820Sjeff MLX4_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 59219820Sjeff MLX4_QP_OPTPAR_RRE = 1 << 1, 60219820Sjeff MLX4_QP_OPTPAR_RAE = 1 << 2, 61219820Sjeff MLX4_QP_OPTPAR_RWE = 1 << 3, 62219820Sjeff MLX4_QP_OPTPAR_PKEY_INDEX = 1 << 4, 63219820Sjeff MLX4_QP_OPTPAR_Q_KEY = 1 << 5, 64219820Sjeff MLX4_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 65219820Sjeff MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 66219820Sjeff MLX4_QP_OPTPAR_SRA_MAX = 1 << 8, 67219820Sjeff MLX4_QP_OPTPAR_RRA_MAX = 1 << 9, 68219820Sjeff MLX4_QP_OPTPAR_PM_STATE = 1 << 10, 69219820Sjeff MLX4_QP_OPTPAR_RETRY_COUNT = 1 << 12, 70219820Sjeff MLX4_QP_OPTPAR_RNR_RETRY = 1 << 13, 71219820Sjeff MLX4_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 72219820Sjeff MLX4_QP_OPTPAR_SCHED_QUEUE = 1 << 16, 73219820Sjeff MLX4_QP_OPTPAR_COUNTER_INDEX = 1 << 20 74219820Sjeff}; 75219820Sjeff 76219820Sjeffenum mlx4_qp_state { 77219820Sjeff MLX4_QP_STATE_RST = 0, 78219820Sjeff MLX4_QP_STATE_INIT = 1, 79219820Sjeff MLX4_QP_STATE_RTR = 2, 80219820Sjeff MLX4_QP_STATE_RTS = 3, 81219820Sjeff MLX4_QP_STATE_SQER = 4, 82219820Sjeff MLX4_QP_STATE_SQD = 5, 83219820Sjeff MLX4_QP_STATE_ERR = 6, 84219820Sjeff MLX4_QP_STATE_SQ_DRAINING = 7, 85219820Sjeff MLX4_QP_NUM_STATE 86219820Sjeff}; 87219820Sjeff 88219820Sjeffenum { 89219820Sjeff MLX4_QP_ST_RC = 0x0, 90219820Sjeff MLX4_QP_ST_UC = 0x1, 91219820Sjeff MLX4_QP_ST_RD = 0x2, 92219820Sjeff MLX4_QP_ST_UD = 0x3, 93219820Sjeff MLX4_QP_ST_XRC = 0x6, 94219820Sjeff MLX4_QP_ST_MLX = 0x7 95219820Sjeff}; 96219820Sjeff 97219820Sjeffenum { 98219820Sjeff MLX4_QP_PM_MIGRATED = 0x3, 99219820Sjeff MLX4_QP_PM_ARMED = 0x0, 100219820Sjeff MLX4_QP_PM_REARM = 0x1 101219820Sjeff}; 102219820Sjeff 103219820Sjeffenum { 104219820Sjeff /* params1 */ 105219820Sjeff MLX4_QP_BIT_SRE = 1 << 15, 106219820Sjeff MLX4_QP_BIT_SWE = 1 << 14, 107219820Sjeff MLX4_QP_BIT_SAE = 1 << 13, 108219820Sjeff /* params2 */ 109219820Sjeff MLX4_QP_BIT_RRE = 1 << 15, 110219820Sjeff MLX4_QP_BIT_RWE = 1 << 14, 111219820Sjeff MLX4_QP_BIT_RAE = 1 << 13, 112219820Sjeff MLX4_QP_BIT_RIC = 1 << 4, 113272027Shselasky MLX4_QP_BIT_COLL_SYNC_RQ = 1 << 2, 114272027Shselasky MLX4_QP_BIT_COLL_SYNC_SQ = 1 << 1, 115272027Shselasky MLX4_QP_BIT_COLL_MASTER = 1 << 0 116219820Sjeff}; 117219820Sjeff 118255932Salfredenum { 119255932Salfred MLX4_RSS_HASH_XOR = 0, 120255932Salfred MLX4_RSS_HASH_TOP = 1, 121255932Salfred 122255932Salfred MLX4_RSS_UDP_IPV6 = 1 << 0, 123255932Salfred MLX4_RSS_UDP_IPV4 = 1 << 1, 124255932Salfred MLX4_RSS_TCP_IPV6 = 1 << 2, 125255932Salfred MLX4_RSS_IPV6 = 1 << 3, 126255932Salfred MLX4_RSS_TCP_IPV4 = 1 << 4, 127255932Salfred MLX4_RSS_IPV4 = 1 << 5, 128255932Salfred 129255932Salfred /* offset of mlx4_rss_context within mlx4_qp_context.pri_path */ 130255932Salfred MLX4_RSS_OFFSET_IN_QPC_PRI_PATH = 0x24, 131255932Salfred /* offset of being RSS indirection QP within mlx4_qp_context.flags */ 132255932Salfred MLX4_RSS_QPC_FLAG_OFFSET = 13, 133255932Salfred}; 134255932Salfred 135255932Salfredstruct mlx4_rss_context { 136255932Salfred __be32 base_qpn; 137255932Salfred __be32 default_qpn; 138255932Salfred u16 reserved; 139255932Salfred u8 hash_fn; 140255932Salfred u8 flags; 141255932Salfred __be32 rss_key[10]; 142255932Salfred __be32 base_qpn_udp; 143255932Salfred}; 144255932Salfred 145219820Sjeffstruct mlx4_qp_path { 146219820Sjeff u8 fl; 147272027Shselasky u8 vlan_control; 148255932Salfred u8 disable_pkey_check; 149219820Sjeff u8 pkey_index; 150219820Sjeff u8 counter_index; 151219820Sjeff u8 grh_mylmc; 152219820Sjeff __be16 rlid; 153219820Sjeff u8 ackto; 154219820Sjeff u8 mgid_index; 155219820Sjeff u8 static_rate; 156219820Sjeff u8 hop_limit; 157219820Sjeff __be32 tclass_flowlabel; 158219820Sjeff u8 rgid[16]; 159219820Sjeff u8 sched_queue; 160219820Sjeff u8 vlan_index; 161255932Salfred u8 feup; 162272027Shselasky u8 fvl_rx; 163219820Sjeff u8 reserved4[2]; 164219820Sjeff u8 dmac[6]; 165219820Sjeff}; 166219820Sjeff 167272027Shselaskyenum { /* fl */ 168272027Shselasky MLX4_FL_CV = 1 << 6, 169272027Shselasky MLX4_FL_ETH_HIDE_CQE_VLAN = 1 << 2, 170272027Shselasky MLX4_FL_ETH_SRC_CHECK_MC_LB = 1 << 1, 171272027Shselasky MLX4_FL_ETH_SRC_CHECK_UC_LB = 1 << 0, 172272027Shselasky}; 173272027Shselaskyenum { /* vlan_control */ 174272027Shselasky MLX4_VLAN_CTRL_ETH_SRC_CHECK_IF_COUNTER = 1 << 7, 175272027Shselasky MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED = 1 << 6, 176272027Shselasky MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED = 1 << 2, 177272027Shselasky MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED = 1 << 1,/* 802.1p priorty tag*/ 178272027Shselasky MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED = 1 << 0 179272027Shselasky}; 180272027Shselasky 181272027Shselaskyenum { /* feup */ 182272027Shselasky MLX4_FEUP_FORCE_ETH_UP = 1 << 6, /* force Eth UP */ 183272027Shselasky MLX4_FSM_FORCE_ETH_SRC_MAC = 1 << 5, /* force Source MAC */ 184272027Shselasky MLX4_FVL_FORCE_ETH_VLAN = 1 << 3 /* force Eth vlan */ 185272027Shselasky}; 186272027Shselasky 187272027Shselaskyenum { /* fvl_rx */ 188272027Shselasky MLX4_FVL_RX_FORCE_ETH_VLAN = 1 << 0 /* enforce Eth rx vlan */ 189272027Shselasky}; 190272027Shselasky 191219820Sjeffstruct mlx4_qp_context { 192219820Sjeff __be32 flags; 193219820Sjeff __be32 pd; 194219820Sjeff u8 mtu_msgmax; 195219820Sjeff u8 rq_size_stride; 196219820Sjeff u8 sq_size_stride; 197219820Sjeff u8 rlkey; 198219820Sjeff __be32 usr_page; 199219820Sjeff __be32 local_qpn; 200219820Sjeff __be32 remote_qpn; 201219820Sjeff struct mlx4_qp_path pri_path; 202219820Sjeff struct mlx4_qp_path alt_path; 203219820Sjeff __be32 params1; 204219820Sjeff u32 reserved1; 205219820Sjeff __be32 next_send_psn; 206219820Sjeff __be32 cqn_send; 207219820Sjeff u32 reserved2[2]; 208219820Sjeff __be32 last_acked_psn; 209219820Sjeff __be32 ssn; 210219820Sjeff __be32 params2; 211219820Sjeff __be32 rnr_nextrecvpsn; 212219820Sjeff __be32 xrcd; 213219820Sjeff __be32 cqn_recv; 214219820Sjeff __be64 db_rec_addr; 215219820Sjeff __be32 qkey; 216219820Sjeff __be32 srqn; 217219820Sjeff __be32 msn; 218219820Sjeff __be16 rq_wqe_counter; 219219820Sjeff __be16 sq_wqe_counter; 220219820Sjeff u32 reserved3[2]; 221219820Sjeff __be32 param3; 222219820Sjeff __be32 nummmcpeers_basemkey; 223219820Sjeff u8 log_page_size; 224219820Sjeff u8 reserved4[2]; 225219820Sjeff u8 mtt_base_addr_h; 226219820Sjeff __be32 mtt_base_addr_l; 227255932Salfred u32 reserved5[10]; 228219820Sjeff}; 229219820Sjeff 230272027Shselaskystruct mlx4_update_qp_context { 231272027Shselasky __be64 qp_mask; 232272027Shselasky __be64 primary_addr_path_mask; 233272027Shselasky __be64 secondary_addr_path_mask; 234272027Shselasky u64 reserved1; 235272027Shselasky struct mlx4_qp_context qp_context; 236272027Shselasky u64 reserved2[58]; 237272027Shselasky}; 238272027Shselasky 239272027Shselaskyenum { 240272027Shselasky MLX4_UPD_QP_MASK_PM_STATE = 32, 241272027Shselasky MLX4_UPD_QP_MASK_VSD = 33, 242272027Shselasky}; 243272027Shselasky 244272027Shselaskyenum { 245272027Shselasky MLX4_UPD_QP_PATH_MASK_PKEY_INDEX = 0 + 32, 246272027Shselasky MLX4_UPD_QP_PATH_MASK_FSM = 1 + 32, 247272027Shselasky MLX4_UPD_QP_PATH_MASK_MAC_INDEX = 2 + 32, 248272027Shselasky MLX4_UPD_QP_PATH_MASK_FVL = 3 + 32, 249272027Shselasky MLX4_UPD_QP_PATH_MASK_CV = 4 + 32, 250272027Shselasky MLX4_UPD_QP_PATH_MASK_VLAN_INDEX = 5 + 32, 251272027Shselasky MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN = 6 + 32, 252272027Shselasky MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED = 7 + 32, 253272027Shselasky MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P = 8 + 32, 254272027Shselasky MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED = 9 + 32, 255272027Shselasky MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED = 10 + 32, 256272027Shselasky MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P = 11 + 32, 257272027Shselasky MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED = 12 + 32, 258272027Shselasky MLX4_UPD_QP_PATH_MASK_FEUP = 13 + 32, 259272027Shselasky MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE = 14 + 32, 260272027Shselasky MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX = 15 + 32, 261272027Shselasky MLX4_UPD_QP_PATH_MASK_FVL_RX = 16 + 32, 262279584Shselasky MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_UC_LB = 18 + 32, 263279584Shselasky MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB = 19 + 32, 264272027Shselasky}; 265272027Shselasky 266272027Shselaskyenum { /* param3 */ 267272027Shselasky MLX4_STRIP_VLAN = 1 << 30 268272027Shselasky}; 269272027Shselasky 270272027Shselasky 271219820Sjeff/* Which firmware version adds support for NEC (NoErrorCompletion) bit */ 272219820Sjeff#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232) 273219820Sjeff 274219820Sjeffenum { 275291694Shselasky MLX4_WQE_CTRL_OWN = 1 << 31, 276219820Sjeff MLX4_WQE_CTRL_NEC = 1 << 29, 277291694Shselasky MLX4_WQE_CTRL_RR = 1 << 6, 278219820Sjeff MLX4_WQE_CTRL_FENCE = 1 << 6, 279219820Sjeff MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2, 280219820Sjeff MLX4_WQE_CTRL_SOLICITED = 1 << 1, 281219820Sjeff MLX4_WQE_CTRL_IP_CSUM = 1 << 4, 282219820Sjeff MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5, 283219820Sjeff MLX4_WQE_CTRL_INS_VLAN = 1 << 6, 284219820Sjeff MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7, 285219820Sjeff MLX4_WQE_CTRL_FORCE_LOOPBACK = 1 << 0, 286219820Sjeff}; 287219820Sjeff 288219820Sjeffstruct mlx4_wqe_ctrl_seg { 289219820Sjeff __be32 owner_opcode; 290219820Sjeff __be16 vlan_tag; 291219820Sjeff u8 ins_vlan; 292219820Sjeff u8 fence_size; 293219820Sjeff /* 294219820Sjeff * High 24 bits are SRC remote buffer; low 8 bits are flags: 295219820Sjeff * [7] SO (strong ordering) 296219820Sjeff * [5] TCP/UDP checksum 297219820Sjeff * [4] IP checksum 298219820Sjeff * [3:2] C (generate completion queue entry) 299219820Sjeff * [1] SE (solicited event) 300255932Salfred * [0] FL (force loopback) 301219820Sjeff */ 302255932Salfred union { 303255932Salfred __be32 srcrb_flags; 304255932Salfred __be16 srcrb_flags16[2]; 305255932Salfred }; 306219820Sjeff /* 307219820Sjeff * imm is immediate data for send/RDMA write w/ immediate; 308219820Sjeff * also invalidation key for send with invalidate; input 309219820Sjeff * modifier for WQEs on CCQs. 310219820Sjeff */ 311219820Sjeff __be32 imm; 312219820Sjeff}; 313219820Sjeff 314219820Sjeffenum { 315219820Sjeff MLX4_WQE_MLX_VL15 = 1 << 17, 316255932Salfred MLX4_WQE_MLX_SLR = 1 << 16 317219820Sjeff}; 318219820Sjeff 319219820Sjeffstruct mlx4_wqe_mlx_seg { 320219820Sjeff u8 owner; 321219820Sjeff u8 reserved1[2]; 322219820Sjeff u8 opcode; 323255932Salfred __be16 sched_prio; 324255932Salfred u8 reserved2; 325219820Sjeff u8 size; 326219820Sjeff /* 327219820Sjeff * [17] VL15 328219820Sjeff * [16] SLR 329219820Sjeff * [15:12] static rate 330219820Sjeff * [11:8] SL 331219820Sjeff * [4] ICRC 332219820Sjeff * [3:2] C 333219820Sjeff * [0] FL (force loopback) 334219820Sjeff */ 335219820Sjeff __be32 flags; 336219820Sjeff __be16 rlid; 337219820Sjeff u16 reserved3; 338219820Sjeff}; 339219820Sjeff 340219820Sjeffstruct mlx4_wqe_datagram_seg { 341219820Sjeff __be32 av[8]; 342219820Sjeff __be32 dqpn; 343219820Sjeff __be32 qkey; 344219820Sjeff __be16 vlan; 345219820Sjeff u8 mac[6]; 346219820Sjeff}; 347219820Sjeff 348219820Sjeffstruct mlx4_wqe_lso_seg { 349219820Sjeff __be32 mss_hdr_size; 350219820Sjeff __be32 header[0]; 351219820Sjeff}; 352219820Sjeff 353272027Shselaskyenum mlx4_wqe_bind_seg_flags2 { 354272027Shselasky MLX4_WQE_BIND_TYPE_2 = (1<<31), 355272027Shselasky MLX4_WQE_BIND_ZERO_BASED = (1<<30), 356272027Shselasky}; 357272027Shselasky 358219820Sjeffstruct mlx4_wqe_bind_seg { 359219820Sjeff __be32 flags1; 360219820Sjeff __be32 flags2; 361219820Sjeff __be32 new_rkey; 362219820Sjeff __be32 lkey; 363219820Sjeff __be64 addr; 364219820Sjeff __be64 length; 365219820Sjeff}; 366219820Sjeff 367219820Sjeffenum { 368219820Sjeff MLX4_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 369219820Sjeff MLX4_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 370272027Shselasky MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ = 1 << 29, 371272027Shselasky MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE = 1 << 30, 372272027Shselasky MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC = 1 << 31 373219820Sjeff}; 374219820Sjeff 375219820Sjeffstruct mlx4_wqe_fmr_seg { 376219820Sjeff __be32 flags; 377219820Sjeff __be32 mem_key; 378219820Sjeff __be64 buf_list; 379219820Sjeff __be64 start_addr; 380219820Sjeff __be64 reg_len; 381219820Sjeff __be32 offset; 382219820Sjeff __be32 page_size; 383219820Sjeff u32 reserved[2]; 384219820Sjeff}; 385219820Sjeff 386219820Sjeffstruct mlx4_wqe_fmr_ext_seg { 387219820Sjeff u8 flags; 388219820Sjeff u8 reserved; 389219820Sjeff __be16 app_mask; 390219820Sjeff __be16 wire_app_tag; 391219820Sjeff __be16 mem_app_tag; 392219820Sjeff __be32 wire_ref_tag_base; 393219820Sjeff __be32 mem_ref_tag_base; 394219820Sjeff}; 395219820Sjeff 396219820Sjeffstruct mlx4_wqe_local_inval_seg { 397272027Shselasky u64 reserved1; 398219820Sjeff __be32 mem_key; 399272027Shselasky u32 reserved2; 400272027Shselasky u64 reserved3[2]; 401219820Sjeff}; 402219820Sjeff 403219820Sjeffstruct mlx4_wqe_raddr_seg { 404219820Sjeff __be64 raddr; 405219820Sjeff __be32 rkey; 406219820Sjeff u32 reserved; 407219820Sjeff}; 408219820Sjeff 409219820Sjeffstruct mlx4_wqe_atomic_seg { 410219820Sjeff __be64 swap_add; 411219820Sjeff __be64 compare; 412219820Sjeff}; 413219820Sjeff 414219820Sjeffstruct mlx4_wqe_masked_atomic_seg { 415219820Sjeff __be64 swap_add; 416219820Sjeff __be64 compare; 417219820Sjeff __be64 swap_add_mask; 418219820Sjeff __be64 compare_mask; 419219820Sjeff}; 420219820Sjeff 421219820Sjeffstruct mlx4_wqe_data_seg { 422219820Sjeff __be32 byte_count; 423219820Sjeff __be32 lkey; 424219820Sjeff __be64 addr; 425219820Sjeff}; 426219820Sjeff 427219820Sjeffenum { 428219820Sjeff MLX4_INLINE_ALIGN = 64, 429219820Sjeff MLX4_INLINE_SEG = 1 << 31, 430219820Sjeff}; 431219820Sjeff 432219820Sjeffstruct mlx4_wqe_inline_seg { 433219820Sjeff __be32 byte_count; 434219820Sjeff}; 435219820Sjeff 436219820Sjeffint mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 437219820Sjeff enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state, 438219820Sjeff struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar, 439219820Sjeff int sqd_event, struct mlx4_qp *qp); 440219820Sjeff 441219820Sjeffint mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp, 442219820Sjeff struct mlx4_qp_context *context); 443219820Sjeff 444219820Sjeffint mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 445219820Sjeff struct mlx4_qp_context *context, 446219820Sjeff struct mlx4_qp *qp, enum mlx4_qp_state *qp_state); 447219820Sjeff 448219820Sjeffstatic inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn) 449219820Sjeff{ 450219820Sjeff return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1)); 451219820Sjeff} 452219820Sjeff 453219820Sjeffvoid mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp); 454219820Sjeff 455219820Sjeff#endif /* MLX4_QP_H */ 456