qp.h revision 272027 
1/*
2 * Copyright (c) 2007 Cisco Systems, Inc.  All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses.  You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 *     Redistribution and use in source and binary forms, with or
11 *     without modification, are permitted provided that the following
12 *     conditions are met:
13 *
14 *	- Redistributions of source code must retain the above
15 *	  copyright notice, this list of conditions and the following
16 *	  disclaimer.
17 *
18 *	- Redistributions in binary form must reproduce the above
19 *	  copyright notice, this list of conditions and the following
20 *	  disclaimer in the documentation and/or other materials
21 *	  provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX4_QP_H
34#define MLX4_QP_H
35
36#include <linux/types.h>
37
38#include <linux/mlx4/device.h>
39
40#define MLX4_INVALID_LKEY	0x100
41
42enum ib_m_qp_attr_mask {
43	IB_M_EXT_CLASS_1 = 1 << 28,
44	IB_M_EXT_CLASS_2 = 1 << 29,
45	IB_M_EXT_CLASS_3 = 1 << 30,
46
47	IB_M_QP_MOD_VEND_MASK = (IB_M_EXT_CLASS_1 | IB_M_EXT_CLASS_2 |
48				 IB_M_EXT_CLASS_3)
49};
50
51enum mlx4_qp_optpar {
52	MLX4_QP_OPTPAR_ALT_ADDR_PATH		= 1 << 0,
53	MLX4_QP_OPTPAR_RRE			= 1 << 1,
54	MLX4_QP_OPTPAR_RAE			= 1 << 2,
55	MLX4_QP_OPTPAR_RWE			= 1 << 3,
56	MLX4_QP_OPTPAR_PKEY_INDEX		= 1 << 4,
57	MLX4_QP_OPTPAR_Q_KEY			= 1 << 5,
58	MLX4_QP_OPTPAR_RNR_TIMEOUT		= 1 << 6,
59	MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH	= 1 << 7,
60	MLX4_QP_OPTPAR_SRA_MAX			= 1 << 8,
61	MLX4_QP_OPTPAR_RRA_MAX			= 1 << 9,
62	MLX4_QP_OPTPAR_PM_STATE			= 1 << 10,
63	MLX4_QP_OPTPAR_RETRY_COUNT		= 1 << 12,
64	MLX4_QP_OPTPAR_RNR_RETRY		= 1 << 13,
65	MLX4_QP_OPTPAR_ACK_TIMEOUT		= 1 << 14,
66	MLX4_QP_OPTPAR_SCHED_QUEUE		= 1 << 16,
67	MLX4_QP_OPTPAR_COUNTER_INDEX		= 1 << 20
68};
69
70enum mlx4_qp_state {
71	MLX4_QP_STATE_RST			= 0,
72	MLX4_QP_STATE_INIT			= 1,
73	MLX4_QP_STATE_RTR			= 2,
74	MLX4_QP_STATE_RTS			= 3,
75	MLX4_QP_STATE_SQER			= 4,
76	MLX4_QP_STATE_SQD			= 5,
77	MLX4_QP_STATE_ERR			= 6,
78	MLX4_QP_STATE_SQ_DRAINING		= 7,
79	MLX4_QP_NUM_STATE
80};
81
82enum {
83	MLX4_QP_ST_RC				= 0x0,
84	MLX4_QP_ST_UC				= 0x1,
85	MLX4_QP_ST_RD				= 0x2,
86	MLX4_QP_ST_UD				= 0x3,
87	MLX4_QP_ST_XRC				= 0x6,
88	MLX4_QP_ST_MLX				= 0x7
89};
90
91enum {
92	MLX4_QP_PM_MIGRATED			= 0x3,
93	MLX4_QP_PM_ARMED			= 0x0,
94	MLX4_QP_PM_REARM			= 0x1
95};
96
97enum {
98	/* params1 */
99	MLX4_QP_BIT_SRE				= 1 << 15,
100	MLX4_QP_BIT_SWE				= 1 << 14,
101	MLX4_QP_BIT_SAE				= 1 << 13,
102	/* params2 */
103	MLX4_QP_BIT_RRE				= 1 << 15,
104	MLX4_QP_BIT_RWE				= 1 << 14,
105	MLX4_QP_BIT_RAE				= 1 << 13,
106	MLX4_QP_BIT_RIC				= 1 <<	4,
107	MLX4_QP_BIT_COLL_SYNC_RQ                = 1 << 2,
108	MLX4_QP_BIT_COLL_SYNC_SQ                = 1 << 1,
109	MLX4_QP_BIT_COLL_MASTER                 = 1 << 0
110};
111
112enum {
113	MLX4_RSS_HASH_XOR			= 0,
114	MLX4_RSS_HASH_TOP			= 1,
115
116	MLX4_RSS_UDP_IPV6			= 1 << 0,
117	MLX4_RSS_UDP_IPV4			= 1 << 1,
118	MLX4_RSS_TCP_IPV6			= 1 << 2,
119	MLX4_RSS_IPV6				= 1 << 3,
120	MLX4_RSS_TCP_IPV4			= 1 << 4,
121	MLX4_RSS_IPV4				= 1 << 5,
122
123	/* offset of mlx4_rss_context within mlx4_qp_context.pri_path */
124	MLX4_RSS_OFFSET_IN_QPC_PRI_PATH		= 0x24,
125	/* offset of being RSS indirection QP within mlx4_qp_context.flags */
126	MLX4_RSS_QPC_FLAG_OFFSET		= 13,
127};
128
129struct mlx4_rss_context {
130	__be32			base_qpn;
131	__be32			default_qpn;
132	u16			reserved;
133	u8			hash_fn;
134	u8			flags;
135	__be32			rss_key[10];
136	__be32			base_qpn_udp;
137};
138
139struct mlx4_qp_path {
140	u8			fl;
141	u8			vlan_control;
142	u8			disable_pkey_check;
143	u8			pkey_index;
144	u8			counter_index;
145	u8			grh_mylmc;
146	__be16			rlid;
147	u8			ackto;
148	u8			mgid_index;
149	u8			static_rate;
150	u8			hop_limit;
151	__be32			tclass_flowlabel;
152	u8			rgid[16];
153	u8			sched_queue;
154	u8			vlan_index;
155	u8			feup;
156	u8			fvl_rx;
157	u8			reserved4[2];
158	u8			dmac[6];
159};
160
161enum { /* fl */
162	MLX4_FL_CV	= 1 << 6,
163	MLX4_FL_ETH_HIDE_CQE_VLAN	= 1 << 2,
164	MLX4_FL_ETH_SRC_CHECK_MC_LB	= 1 << 1,
165	MLX4_FL_ETH_SRC_CHECK_UC_LB	= 1 << 0,
166};
167enum { /* vlan_control */
168	MLX4_VLAN_CTRL_ETH_SRC_CHECK_IF_COUNTER	= 1 << 7,
169	MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED	= 1 << 6,
170	MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED	= 1 << 2,
171	MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED	= 1 << 1,/* 802.1p priorty tag*/
172	MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED	= 1 << 0
173};
174
175enum { /* feup */
176	MLX4_FEUP_FORCE_ETH_UP		= 1 << 6, /* force Eth UP */
177	MLX4_FSM_FORCE_ETH_SRC_MAC	= 1 << 5, /* force Source MAC */
178	MLX4_FVL_FORCE_ETH_VLAN		= 1 << 3  /* force Eth vlan */
179};
180
181enum { /* fvl_rx */
182	MLX4_FVL_RX_FORCE_ETH_VLAN	= 1 << 0 /* enforce Eth rx vlan */
183};
184
185struct mlx4_qp_context {
186	__be32			flags;
187	__be32			pd;
188	u8			mtu_msgmax;
189	u8			rq_size_stride;
190	u8			sq_size_stride;
191	u8			rlkey;
192	__be32			usr_page;
193	__be32			local_qpn;
194	__be32			remote_qpn;
195	struct			mlx4_qp_path pri_path;
196	struct			mlx4_qp_path alt_path;
197	__be32			params1;
198	u32			reserved1;
199	__be32			next_send_psn;
200	__be32			cqn_send;
201	u32			reserved2[2];
202	__be32			last_acked_psn;
203	__be32			ssn;
204	__be32			params2;
205	__be32			rnr_nextrecvpsn;
206	__be32			xrcd;
207	__be32			cqn_recv;
208	__be64			db_rec_addr;
209	__be32			qkey;
210	__be32			srqn;
211	__be32			msn;
212	__be16			rq_wqe_counter;
213	__be16			sq_wqe_counter;
214	u32			reserved3[2];
215	__be32			param3;
216	__be32			nummmcpeers_basemkey;
217	u8			log_page_size;
218	u8			reserved4[2];
219	u8			mtt_base_addr_h;
220	__be32			mtt_base_addr_l;
221	u32			reserved5[10];
222};
223
224struct mlx4_update_qp_context {
225	__be64			qp_mask;
226	__be64			primary_addr_path_mask;
227	__be64			secondary_addr_path_mask;
228	u64			reserved1;
229	struct mlx4_qp_context	qp_context;
230	u64			reserved2[58];
231};
232
233enum {
234	MLX4_UPD_QP_MASK_PM_STATE	= 32,
235	MLX4_UPD_QP_MASK_VSD		= 33,
236};
237
238enum {
239	MLX4_UPD_QP_PATH_MASK_PKEY_INDEX		= 0 + 32,
240	MLX4_UPD_QP_PATH_MASK_FSM			= 1 + 32,
241	MLX4_UPD_QP_PATH_MASK_MAC_INDEX			= 2 + 32,
242	MLX4_UPD_QP_PATH_MASK_FVL			= 3 + 32,
243	MLX4_UPD_QP_PATH_MASK_CV			= 4 + 32,
244	MLX4_UPD_QP_PATH_MASK_VLAN_INDEX		= 5 + 32,
245	MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN		= 6 + 32,
246	MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED	= 7 + 32,
247	MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P		= 8 + 32,
248	MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED	= 9 + 32,
249	MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED	= 10 + 32,
250	MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P		= 11 + 32,
251	MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED	= 12 + 32,
252	MLX4_UPD_QP_PATH_MASK_FEUP			= 13 + 32,
253	MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE		= 14 + 32,
254	MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX		= 15 + 32,
255	MLX4_UPD_QP_PATH_MASK_FVL_RX			= 16 + 32,
256};
257
258enum { /* param3 */
259	MLX4_STRIP_VLAN	= 1 << 30
260};
261
262
263/* Which firmware version adds support for NEC (NoErrorCompletion) bit */
264#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
265
266enum {
267	MLX4_WQE_CTRL_NEC		= 1 << 29,
268	MLX4_WQE_CTRL_FENCE		= 1 << 6,
269	MLX4_WQE_CTRL_CQ_UPDATE		= 3 << 2,
270	MLX4_WQE_CTRL_SOLICITED		= 1 << 1,
271	MLX4_WQE_CTRL_IP_CSUM		= 1 << 4,
272	MLX4_WQE_CTRL_TCP_UDP_CSUM	= 1 << 5,
273	MLX4_WQE_CTRL_INS_VLAN		= 1 << 6,
274	MLX4_WQE_CTRL_STRONG_ORDER	= 1 << 7,
275	MLX4_WQE_CTRL_FORCE_LOOPBACK	= 1 << 0,
276};
277
278struct mlx4_wqe_ctrl_seg {
279	__be32			owner_opcode;
280	__be16			vlan_tag;
281	u8			ins_vlan;
282	u8			fence_size;
283	/*
284	 * High 24 bits are SRC remote buffer; low 8 bits are flags:
285	 * [7]   SO (strong ordering)
286	 * [5]   TCP/UDP checksum
287	 * [4]   IP checksum
288	 * [3:2] C (generate completion queue entry)
289	 * [1]   SE (solicited event)
290	 * [0]   FL (force loopback)
291	 */
292	union {
293		__be32			srcrb_flags;
294		__be16			srcrb_flags16[2];
295	};
296	/*
297	 * imm is immediate data for send/RDMA write w/ immediate;
298	 * also invalidation key for send with invalidate; input
299	 * modifier for WQEs on CCQs.
300	 */
301	__be32			imm;
302};
303
304enum {
305	MLX4_WQE_MLX_VL15	= 1 << 17,
306	MLX4_WQE_MLX_SLR	= 1 << 16
307};
308
309struct mlx4_wqe_mlx_seg {
310	u8			owner;
311	u8			reserved1[2];
312	u8			opcode;
313	__be16			sched_prio;
314	u8			reserved2;
315	u8			size;
316	/*
317	 * [17]    VL15
318	 * [16]    SLR
319	 * [15:12] static rate
320	 * [11:8]  SL
321	 * [4]     ICRC
322	 * [3:2]   C
323	 * [0]     FL (force loopback)
324	 */
325	__be32			flags;
326	__be16			rlid;
327	u16			reserved3;
328};
329
330struct mlx4_wqe_datagram_seg {
331	__be32			av[8];
332	__be32			dqpn;
333	__be32			qkey;
334	__be16			vlan;
335	u8			mac[6];
336};
337
338struct mlx4_wqe_lso_seg {
339	__be32			mss_hdr_size;
340	__be32			header[0];
341};
342
343enum mlx4_wqe_bind_seg_flags2 {
344	MLX4_WQE_BIND_TYPE_2     = (1<<31),
345	MLX4_WQE_BIND_ZERO_BASED = (1<<30),
346};
347
348struct mlx4_wqe_bind_seg {
349	__be32			flags1;
350	__be32			flags2;
351	__be32			new_rkey;
352	__be32			lkey;
353	__be64			addr;
354	__be64			length;
355};
356
357enum {
358	MLX4_WQE_FMR_PERM_LOCAL_READ	= 1 << 27,
359	MLX4_WQE_FMR_PERM_LOCAL_WRITE	= 1 << 28,
360	MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ	= 1 << 29,
361	MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE	= 1 << 30,
362	MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC	= 1 << 31
363};
364
365struct mlx4_wqe_fmr_seg {
366	__be32			flags;
367	__be32			mem_key;
368	__be64			buf_list;
369	__be64			start_addr;
370	__be64			reg_len;
371	__be32			offset;
372	__be32			page_size;
373	u32			reserved[2];
374};
375
376struct mlx4_wqe_fmr_ext_seg {
377	u8			flags;
378	u8			reserved;
379	__be16			app_mask;
380	__be16			wire_app_tag;
381	__be16			mem_app_tag;
382	__be32			wire_ref_tag_base;
383	__be32			mem_ref_tag_base;
384};
385
386struct mlx4_wqe_local_inval_seg {
387	u64			reserved1;
388	__be32			mem_key;
389	u32			reserved2;
390	u64			reserved3[2];
391};
392
393struct mlx4_wqe_raddr_seg {
394	__be64			raddr;
395	__be32			rkey;
396	u32			reserved;
397};
398
399struct mlx4_wqe_atomic_seg {
400	__be64			swap_add;
401	__be64			compare;
402};
403
404struct mlx4_wqe_masked_atomic_seg {
405	__be64			swap_add;
406	__be64			compare;
407	__be64			swap_add_mask;
408	__be64			compare_mask;
409};
410
411struct mlx4_wqe_data_seg {
412	__be32			byte_count;
413	__be32			lkey;
414	__be64			addr;
415};
416
417enum {
418	MLX4_INLINE_ALIGN	= 64,
419	MLX4_INLINE_SEG		= 1 << 31,
420};
421
422struct mlx4_wqe_inline_seg {
423	__be32			byte_count;
424};
425
426int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
427		   enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
428		   struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
429		   int sqd_event, struct mlx4_qp *qp);
430
431int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
432		  struct mlx4_qp_context *context);
433
434int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
435		     struct mlx4_qp_context *context,
436		     struct mlx4_qp *qp, enum mlx4_qp_state *qp_state);
437
438static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
439{
440	return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1));
441}
442
443void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp);
444
445#endif /* MLX4_QP_H */
446