qp.h revision 255932
1219820Sjeff/* 2219820Sjeff * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3219820Sjeff * 4219820Sjeff * This software is available to you under a choice of one of two 5219820Sjeff * licenses. You may choose to be licensed under the terms of the GNU 6219820Sjeff * General Public License (GPL) Version 2, available from the file 7219820Sjeff * COPYING in the main directory of this source tree, or the 8219820Sjeff * OpenIB.org BSD license below: 9219820Sjeff * 10219820Sjeff * Redistribution and use in source and binary forms, with or 11219820Sjeff * without modification, are permitted provided that the following 12219820Sjeff * conditions are met: 13219820Sjeff * 14219820Sjeff * - Redistributions of source code must retain the above 15219820Sjeff * copyright notice, this list of conditions and the following 16219820Sjeff * disclaimer. 17219820Sjeff * 18219820Sjeff * - Redistributions in binary form must reproduce the above 19219820Sjeff * copyright notice, this list of conditions and the following 20219820Sjeff * disclaimer in the documentation and/or other materials 21219820Sjeff * provided with the distribution. 22219820Sjeff * 23219820Sjeff * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24219820Sjeff * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25219820Sjeff * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26219820Sjeff * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27219820Sjeff * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28219820Sjeff * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29219820Sjeff * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30219820Sjeff * SOFTWARE. 31219820Sjeff */ 32219820Sjeff 33219820Sjeff#ifndef MLX4_QP_H 34219820Sjeff#define MLX4_QP_H 35219820Sjeff 36219820Sjeff#include <linux/types.h> 37219820Sjeff 38219820Sjeff#include <linux/mlx4/device.h> 39219820Sjeff 40219820Sjeff#define MLX4_INVALID_LKEY 0x100 41219820Sjeff 42255932Salfredenum ib_m_qp_attr_mask { 43255932Salfred IB_M_EXT_CLASS_1 = 1 << 28, 44255932Salfred IB_M_EXT_CLASS_2 = 1 << 29, 45255932Salfred IB_M_EXT_CLASS_3 = 1 << 30, 46255932Salfred 47255932Salfred IB_M_QP_MOD_VEND_MASK = (IB_M_EXT_CLASS_1 | IB_M_EXT_CLASS_2 | 48255932Salfred IB_M_EXT_CLASS_3) 49255932Salfred}; 50255932Salfred 51219820Sjeffenum mlx4_qp_optpar { 52219820Sjeff MLX4_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 53219820Sjeff MLX4_QP_OPTPAR_RRE = 1 << 1, 54219820Sjeff MLX4_QP_OPTPAR_RAE = 1 << 2, 55219820Sjeff MLX4_QP_OPTPAR_RWE = 1 << 3, 56219820Sjeff MLX4_QP_OPTPAR_PKEY_INDEX = 1 << 4, 57219820Sjeff MLX4_QP_OPTPAR_Q_KEY = 1 << 5, 58219820Sjeff MLX4_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 59219820Sjeff MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 60219820Sjeff MLX4_QP_OPTPAR_SRA_MAX = 1 << 8, 61219820Sjeff MLX4_QP_OPTPAR_RRA_MAX = 1 << 9, 62219820Sjeff MLX4_QP_OPTPAR_PM_STATE = 1 << 10, 63219820Sjeff MLX4_QP_OPTPAR_RETRY_COUNT = 1 << 12, 64219820Sjeff MLX4_QP_OPTPAR_RNR_RETRY = 1 << 13, 65219820Sjeff MLX4_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 66219820Sjeff MLX4_QP_OPTPAR_SCHED_QUEUE = 1 << 16, 67219820Sjeff MLX4_QP_OPTPAR_COUNTER_INDEX = 1 << 20 68219820Sjeff}; 69219820Sjeff 70219820Sjeffenum mlx4_qp_state { 71219820Sjeff MLX4_QP_STATE_RST = 0, 72219820Sjeff MLX4_QP_STATE_INIT = 1, 73219820Sjeff MLX4_QP_STATE_RTR = 2, 74219820Sjeff MLX4_QP_STATE_RTS = 3, 75219820Sjeff MLX4_QP_STATE_SQER = 4, 76219820Sjeff MLX4_QP_STATE_SQD = 5, 77219820Sjeff MLX4_QP_STATE_ERR = 6, 78219820Sjeff MLX4_QP_STATE_SQ_DRAINING = 7, 79219820Sjeff MLX4_QP_NUM_STATE 80219820Sjeff}; 81219820Sjeff 82219820Sjeffenum { 83219820Sjeff MLX4_QP_ST_RC = 0x0, 84219820Sjeff MLX4_QP_ST_UC = 0x1, 85219820Sjeff MLX4_QP_ST_RD = 0x2, 86219820Sjeff MLX4_QP_ST_UD = 0x3, 87219820Sjeff MLX4_QP_ST_XRC = 0x6, 88219820Sjeff MLX4_QP_ST_MLX = 0x7 89219820Sjeff}; 90219820Sjeff 91219820Sjeffenum { 92219820Sjeff MLX4_QP_PM_MIGRATED = 0x3, 93219820Sjeff MLX4_QP_PM_ARMED = 0x0, 94219820Sjeff MLX4_QP_PM_REARM = 0x1 95219820Sjeff}; 96219820Sjeff 97219820Sjeffenum { 98219820Sjeff /* params1 */ 99219820Sjeff MLX4_QP_BIT_SRE = 1 << 15, 100219820Sjeff MLX4_QP_BIT_SWE = 1 << 14, 101219820Sjeff MLX4_QP_BIT_SAE = 1 << 13, 102219820Sjeff /* params2 */ 103219820Sjeff MLX4_QP_BIT_RRE = 1 << 15, 104219820Sjeff MLX4_QP_BIT_RWE = 1 << 14, 105219820Sjeff MLX4_QP_BIT_RAE = 1 << 13, 106219820Sjeff MLX4_QP_BIT_RIC = 1 << 4, 107255932Salfred MLX4_QP_BIT_COLL_SYNC_RQ = 1 << 2, 108255932Salfred MLX4_QP_BIT_COLL_SYNC_SQ = 1 << 1, 109255932Salfred MLX4_QP_BIT_COLL_MASTER = 1 << 0 110219820Sjeff}; 111219820Sjeff 112255932Salfredenum { 113255932Salfred MLX4_RSS_HASH_XOR = 0, 114255932Salfred MLX4_RSS_HASH_TOP = 1, 115255932Salfred 116255932Salfred MLX4_RSS_UDP_IPV6 = 1 << 0, 117255932Salfred MLX4_RSS_UDP_IPV4 = 1 << 1, 118255932Salfred MLX4_RSS_TCP_IPV6 = 1 << 2, 119255932Salfred MLX4_RSS_IPV6 = 1 << 3, 120255932Salfred MLX4_RSS_TCP_IPV4 = 1 << 4, 121255932Salfred MLX4_RSS_IPV4 = 1 << 5, 122255932Salfred 123255932Salfred /* offset of mlx4_rss_context within mlx4_qp_context.pri_path */ 124255932Salfred MLX4_RSS_OFFSET_IN_QPC_PRI_PATH = 0x24, 125255932Salfred /* offset of being RSS indirection QP within mlx4_qp_context.flags */ 126255932Salfred MLX4_RSS_QPC_FLAG_OFFSET = 13, 127255932Salfred}; 128255932Salfred 129255932Salfredstruct mlx4_rss_context { 130255932Salfred __be32 base_qpn; 131255932Salfred __be32 default_qpn; 132255932Salfred u16 reserved; 133255932Salfred u8 hash_fn; 134255932Salfred u8 flags; 135255932Salfred __be32 rss_key[10]; 136255932Salfred __be32 base_qpn_udp; 137255932Salfred}; 138255932Salfred 139219820Sjeffstruct mlx4_qp_path { 140219820Sjeff u8 fl; 141255932Salfred u8 reserved1[1]; 142255932Salfred u8 disable_pkey_check; 143219820Sjeff u8 pkey_index; 144219820Sjeff u8 counter_index; 145219820Sjeff u8 grh_mylmc; 146219820Sjeff __be16 rlid; 147219820Sjeff u8 ackto; 148219820Sjeff u8 mgid_index; 149219820Sjeff u8 static_rate; 150219820Sjeff u8 hop_limit; 151219820Sjeff __be32 tclass_flowlabel; 152219820Sjeff u8 rgid[16]; 153219820Sjeff u8 sched_queue; 154219820Sjeff u8 vlan_index; 155255932Salfred u8 feup; 156255932Salfred u8 reserved3; 157219820Sjeff u8 reserved4[2]; 158219820Sjeff u8 dmac[6]; 159219820Sjeff}; 160219820Sjeff 161219820Sjeffstruct mlx4_qp_context { 162219820Sjeff __be32 flags; 163219820Sjeff __be32 pd; 164219820Sjeff u8 mtu_msgmax; 165219820Sjeff u8 rq_size_stride; 166219820Sjeff u8 sq_size_stride; 167219820Sjeff u8 rlkey; 168219820Sjeff __be32 usr_page; 169219820Sjeff __be32 local_qpn; 170219820Sjeff __be32 remote_qpn; 171219820Sjeff struct mlx4_qp_path pri_path; 172219820Sjeff struct mlx4_qp_path alt_path; 173219820Sjeff __be32 params1; 174219820Sjeff u32 reserved1; 175219820Sjeff __be32 next_send_psn; 176219820Sjeff __be32 cqn_send; 177219820Sjeff u32 reserved2[2]; 178219820Sjeff __be32 last_acked_psn; 179219820Sjeff __be32 ssn; 180219820Sjeff __be32 params2; 181219820Sjeff __be32 rnr_nextrecvpsn; 182219820Sjeff __be32 xrcd; 183219820Sjeff __be32 cqn_recv; 184219820Sjeff __be64 db_rec_addr; 185219820Sjeff __be32 qkey; 186219820Sjeff __be32 srqn; 187219820Sjeff __be32 msn; 188219820Sjeff __be16 rq_wqe_counter; 189219820Sjeff __be16 sq_wqe_counter; 190219820Sjeff u32 reserved3[2]; 191219820Sjeff __be32 param3; 192219820Sjeff __be32 nummmcpeers_basemkey; 193219820Sjeff u8 log_page_size; 194219820Sjeff u8 reserved4[2]; 195219820Sjeff u8 mtt_base_addr_h; 196219820Sjeff __be32 mtt_base_addr_l; 197255932Salfred u32 reserved5[10]; 198219820Sjeff}; 199219820Sjeff 200219820Sjeff/* Which firmware version adds support for NEC (NoErrorCompletion) bit */ 201219820Sjeff#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232) 202219820Sjeff 203219820Sjeffenum { 204219820Sjeff MLX4_WQE_CTRL_NEC = 1 << 29, 205219820Sjeff MLX4_WQE_CTRL_FENCE = 1 << 6, 206219820Sjeff MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2, 207219820Sjeff MLX4_WQE_CTRL_SOLICITED = 1 << 1, 208219820Sjeff MLX4_WQE_CTRL_IP_CSUM = 1 << 4, 209219820Sjeff MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5, 210219820Sjeff MLX4_WQE_CTRL_INS_VLAN = 1 << 6, 211219820Sjeff MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7, 212219820Sjeff MLX4_WQE_CTRL_FORCE_LOOPBACK = 1 << 0, 213219820Sjeff}; 214219820Sjeff 215219820Sjeffstruct mlx4_wqe_ctrl_seg { 216219820Sjeff __be32 owner_opcode; 217219820Sjeff __be16 vlan_tag; 218219820Sjeff u8 ins_vlan; 219219820Sjeff u8 fence_size; 220219820Sjeff /* 221219820Sjeff * High 24 bits are SRC remote buffer; low 8 bits are flags: 222219820Sjeff * [7] SO (strong ordering) 223219820Sjeff * [5] TCP/UDP checksum 224219820Sjeff * [4] IP checksum 225219820Sjeff * [3:2] C (generate completion queue entry) 226219820Sjeff * [1] SE (solicited event) 227255932Salfred * [0] FL (force loopback) 228219820Sjeff */ 229255932Salfred union { 230255932Salfred __be32 srcrb_flags; 231255932Salfred __be16 srcrb_flags16[2]; 232255932Salfred }; 233219820Sjeff /* 234219820Sjeff * imm is immediate data for send/RDMA write w/ immediate; 235219820Sjeff * also invalidation key for send with invalidate; input 236219820Sjeff * modifier for WQEs on CCQs. 237219820Sjeff */ 238219820Sjeff __be32 imm; 239219820Sjeff}; 240219820Sjeff 241219820Sjeffenum { 242219820Sjeff MLX4_WQE_MLX_VL15 = 1 << 17, 243255932Salfred MLX4_WQE_MLX_SLR = 1 << 16 244219820Sjeff}; 245219820Sjeff 246219820Sjeffstruct mlx4_wqe_mlx_seg { 247219820Sjeff u8 owner; 248219820Sjeff u8 reserved1[2]; 249219820Sjeff u8 opcode; 250255932Salfred __be16 sched_prio; 251255932Salfred u8 reserved2; 252219820Sjeff u8 size; 253219820Sjeff /* 254219820Sjeff * [17] VL15 255219820Sjeff * [16] SLR 256219820Sjeff * [15:12] static rate 257219820Sjeff * [11:8] SL 258219820Sjeff * [4] ICRC 259219820Sjeff * [3:2] C 260219820Sjeff * [0] FL (force loopback) 261219820Sjeff */ 262219820Sjeff __be32 flags; 263219820Sjeff __be16 rlid; 264219820Sjeff u16 reserved3; 265219820Sjeff}; 266219820Sjeff 267219820Sjeffstruct mlx4_wqe_datagram_seg { 268219820Sjeff __be32 av[8]; 269219820Sjeff __be32 dqpn; 270219820Sjeff __be32 qkey; 271219820Sjeff __be16 vlan; 272219820Sjeff u8 mac[6]; 273219820Sjeff}; 274219820Sjeff 275219820Sjeffstruct mlx4_wqe_lso_seg { 276219820Sjeff __be32 mss_hdr_size; 277219820Sjeff __be32 header[0]; 278219820Sjeff}; 279219820Sjeff 280219820Sjeffstruct mlx4_wqe_bind_seg { 281219820Sjeff __be32 flags1; 282219820Sjeff __be32 flags2; 283219820Sjeff __be32 new_rkey; 284219820Sjeff __be32 lkey; 285219820Sjeff __be64 addr; 286219820Sjeff __be64 length; 287219820Sjeff}; 288219820Sjeff 289219820Sjeffenum { 290219820Sjeff MLX4_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 291219820Sjeff MLX4_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 292219820Sjeff MLX4_WQE_FMR_PERM_REMOTE_READ = 1 << 29, 293219820Sjeff MLX4_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30, 294219820Sjeff MLX4_WQE_FMR_PERM_ATOMIC = 1 << 31 295219820Sjeff}; 296219820Sjeff 297219820Sjeffstruct mlx4_wqe_fmr_seg { 298219820Sjeff __be32 flags; 299219820Sjeff __be32 mem_key; 300219820Sjeff __be64 buf_list; 301219820Sjeff __be64 start_addr; 302219820Sjeff __be64 reg_len; 303219820Sjeff __be32 offset; 304219820Sjeff __be32 page_size; 305219820Sjeff u32 reserved[2]; 306219820Sjeff}; 307219820Sjeff 308219820Sjeffstruct mlx4_wqe_fmr_ext_seg { 309219820Sjeff u8 flags; 310219820Sjeff u8 reserved; 311219820Sjeff __be16 app_mask; 312219820Sjeff __be16 wire_app_tag; 313219820Sjeff __be16 mem_app_tag; 314219820Sjeff __be32 wire_ref_tag_base; 315219820Sjeff __be32 mem_ref_tag_base; 316219820Sjeff}; 317219820Sjeff 318219820Sjeffstruct mlx4_wqe_local_inval_seg { 319219820Sjeff __be32 flags; 320219820Sjeff u32 reserved1; 321219820Sjeff __be32 mem_key; 322219820Sjeff u32 reserved2[2]; 323219820Sjeff __be32 guest_id; 324219820Sjeff __be64 pa; 325219820Sjeff}; 326219820Sjeff 327219820Sjeffstruct mlx4_wqe_raddr_seg { 328219820Sjeff __be64 raddr; 329219820Sjeff __be32 rkey; 330219820Sjeff u32 reserved; 331219820Sjeff}; 332219820Sjeff 333219820Sjeffstruct mlx4_wqe_atomic_seg { 334219820Sjeff __be64 swap_add; 335219820Sjeff __be64 compare; 336219820Sjeff}; 337219820Sjeff 338219820Sjeffstruct mlx4_wqe_masked_atomic_seg { 339219820Sjeff __be64 swap_add; 340219820Sjeff __be64 compare; 341219820Sjeff __be64 swap_add_mask; 342219820Sjeff __be64 compare_mask; 343219820Sjeff}; 344219820Sjeff 345219820Sjeffstruct mlx4_wqe_data_seg { 346219820Sjeff __be32 byte_count; 347219820Sjeff __be32 lkey; 348219820Sjeff __be64 addr; 349219820Sjeff}; 350219820Sjeff 351219820Sjeffenum { 352219820Sjeff MLX4_INLINE_ALIGN = 64, 353219820Sjeff MLX4_INLINE_SEG = 1 << 31, 354219820Sjeff}; 355219820Sjeff 356219820Sjeffstruct mlx4_wqe_inline_seg { 357219820Sjeff __be32 byte_count; 358219820Sjeff}; 359219820Sjeff 360219820Sjeffint mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 361219820Sjeff enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state, 362219820Sjeff struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar, 363219820Sjeff int sqd_event, struct mlx4_qp *qp); 364219820Sjeff 365219820Sjeffint mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp, 366219820Sjeff struct mlx4_qp_context *context); 367219820Sjeff 368219820Sjeffint mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 369219820Sjeff struct mlx4_qp_context *context, 370219820Sjeff struct mlx4_qp *qp, enum mlx4_qp_state *qp_state); 371219820Sjeff 372219820Sjeffstatic inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn) 373219820Sjeff{ 374219820Sjeff return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1)); 375219820Sjeff} 376219820Sjeff 377219820Sjeffvoid mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp); 378219820Sjeff 379219820Sjeff#endif /* MLX4_QP_H */ 380