1219820Sjeff/* 2219820Sjeff * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3219820Sjeff * 4219820Sjeff * This software is available to you under a choice of one of two 5219820Sjeff * licenses. You may choose to be licensed under the terms of the GNU 6219820Sjeff * General Public License (GPL) Version 2, available from the file 7219820Sjeff * COPYING in the main directory of this source tree, or the 8219820Sjeff * OpenIB.org BSD license below: 9219820Sjeff * 10219820Sjeff * Redistribution and use in source and binary forms, with or 11219820Sjeff * without modification, are permitted provided that the following 12219820Sjeff * conditions are met: 13219820Sjeff * 14219820Sjeff * - Redistributions of source code must retain the above 15219820Sjeff * copyright notice, this list of conditions and the following 16219820Sjeff * disclaimer. 17219820Sjeff * 18219820Sjeff * - Redistributions in binary form must reproduce the above 19219820Sjeff * copyright notice, this list of conditions and the following 20219820Sjeff * disclaimer in the documentation and/or other materials 21219820Sjeff * provided with the distribution. 22219820Sjeff * 23219820Sjeff * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24219820Sjeff * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25219820Sjeff * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26219820Sjeff * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27219820Sjeff * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28219820Sjeff * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29219820Sjeff * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30219820Sjeff * SOFTWARE. 31219820Sjeff */ 32219820Sjeff 33219820Sjeff#ifndef MLX4_QP_H 34219820Sjeff#define MLX4_QP_H 35219820Sjeff 36219820Sjeff#include <linux/types.h> 37219820Sjeff 38306486Shselasky#include <dev/mlx4/device.h> 39219820Sjeff 40219820Sjeff#define MLX4_INVALID_LKEY 0x100 41291694Shselasky#define DS_SIZE_ALIGNMENT 16 42291694Shselasky 43291694Shselasky#define SET_BYTE_COUNT(byte_count) cpu_to_be32(byte_count) 44291694Shselasky#define SET_LSO_MSS(mss_hdr_size) cpu_to_be32(mss_hdr_size) 45291694Shselasky#define DS_BYTE_COUNT_MASK cpu_to_be32(0x7fffffff) 46291694Shselasky 47219820Sjeffenum mlx4_qp_optpar { 48219820Sjeff MLX4_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 49219820Sjeff MLX4_QP_OPTPAR_RRE = 1 << 1, 50219820Sjeff MLX4_QP_OPTPAR_RAE = 1 << 2, 51219820Sjeff MLX4_QP_OPTPAR_RWE = 1 << 3, 52219820Sjeff MLX4_QP_OPTPAR_PKEY_INDEX = 1 << 4, 53219820Sjeff MLX4_QP_OPTPAR_Q_KEY = 1 << 5, 54219820Sjeff MLX4_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 55219820Sjeff MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 56219820Sjeff MLX4_QP_OPTPAR_SRA_MAX = 1 << 8, 57219820Sjeff MLX4_QP_OPTPAR_RRA_MAX = 1 << 9, 58219820Sjeff MLX4_QP_OPTPAR_PM_STATE = 1 << 10, 59219820Sjeff MLX4_QP_OPTPAR_RETRY_COUNT = 1 << 12, 60219820Sjeff MLX4_QP_OPTPAR_RNR_RETRY = 1 << 13, 61219820Sjeff MLX4_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 62219820Sjeff MLX4_QP_OPTPAR_SCHED_QUEUE = 1 << 16, 63329159Shselasky MLX4_QP_OPTPAR_COUNTER_INDEX = 1 << 20, 64329159Shselasky MLX4_QP_OPTPAR_VLAN_STRIPPING = 1 << 21, 65219820Sjeff}; 66219820Sjeff 67219820Sjeffenum mlx4_qp_state { 68219820Sjeff MLX4_QP_STATE_RST = 0, 69219820Sjeff MLX4_QP_STATE_INIT = 1, 70219820Sjeff MLX4_QP_STATE_RTR = 2, 71219820Sjeff MLX4_QP_STATE_RTS = 3, 72219820Sjeff MLX4_QP_STATE_SQER = 4, 73219820Sjeff MLX4_QP_STATE_SQD = 5, 74219820Sjeff MLX4_QP_STATE_ERR = 6, 75219820Sjeff MLX4_QP_STATE_SQ_DRAINING = 7, 76219820Sjeff MLX4_QP_NUM_STATE 77219820Sjeff}; 78219820Sjeff 79219820Sjeffenum { 80219820Sjeff MLX4_QP_ST_RC = 0x0, 81219820Sjeff MLX4_QP_ST_UC = 0x1, 82219820Sjeff MLX4_QP_ST_RD = 0x2, 83219820Sjeff MLX4_QP_ST_UD = 0x3, 84219820Sjeff MLX4_QP_ST_XRC = 0x6, 85219820Sjeff MLX4_QP_ST_MLX = 0x7 86219820Sjeff}; 87219820Sjeff 88219820Sjeffenum { 89219820Sjeff MLX4_QP_PM_MIGRATED = 0x3, 90219820Sjeff MLX4_QP_PM_ARMED = 0x0, 91219820Sjeff MLX4_QP_PM_REARM = 0x1 92219820Sjeff}; 93219820Sjeff 94219820Sjeffenum { 95219820Sjeff /* params1 */ 96219820Sjeff MLX4_QP_BIT_SRE = 1 << 15, 97219820Sjeff MLX4_QP_BIT_SWE = 1 << 14, 98219820Sjeff MLX4_QP_BIT_SAE = 1 << 13, 99219820Sjeff /* params2 */ 100219820Sjeff MLX4_QP_BIT_RRE = 1 << 15, 101219820Sjeff MLX4_QP_BIT_RWE = 1 << 14, 102219820Sjeff MLX4_QP_BIT_RAE = 1 << 13, 103329159Shselasky MLX4_QP_BIT_FPP = 1 << 3, 104219820Sjeff MLX4_QP_BIT_RIC = 1 << 4, 105219820Sjeff}; 106219820Sjeff 107255932Salfredenum { 108255932Salfred MLX4_RSS_HASH_XOR = 0, 109255932Salfred MLX4_RSS_HASH_TOP = 1, 110255932Salfred 111255932Salfred MLX4_RSS_UDP_IPV6 = 1 << 0, 112255932Salfred MLX4_RSS_UDP_IPV4 = 1 << 1, 113255932Salfred MLX4_RSS_TCP_IPV6 = 1 << 2, 114255932Salfred MLX4_RSS_IPV6 = 1 << 3, 115255932Salfred MLX4_RSS_TCP_IPV4 = 1 << 4, 116255932Salfred MLX4_RSS_IPV4 = 1 << 5, 117255932Salfred 118329159Shselasky MLX4_RSS_BY_OUTER_HEADERS = 0 << 6, 119329159Shselasky MLX4_RSS_BY_INNER_HEADERS = 2 << 6, 120329159Shselasky MLX4_RSS_BY_INNER_HEADERS_IPONLY = 3 << 6, 121329159Shselasky 122255932Salfred /* offset of mlx4_rss_context within mlx4_qp_context.pri_path */ 123255932Salfred MLX4_RSS_OFFSET_IN_QPC_PRI_PATH = 0x24, 124255932Salfred /* offset of being RSS indirection QP within mlx4_qp_context.flags */ 125255932Salfred MLX4_RSS_QPC_FLAG_OFFSET = 13, 126255932Salfred}; 127255932Salfred 128329159Shselasky#define MLX4_EN_RSS_KEY_SIZE 40 129329159Shselasky 130255932Salfredstruct mlx4_rss_context { 131255932Salfred __be32 base_qpn; 132255932Salfred __be32 default_qpn; 133255932Salfred u16 reserved; 134255932Salfred u8 hash_fn; 135255932Salfred u8 flags; 136329159Shselasky __be32 rss_key[MLX4_EN_RSS_KEY_SIZE / sizeof(__be32)]; 137255932Salfred __be32 base_qpn_udp; 138255932Salfred}; 139255932Salfred 140219820Sjeffstruct mlx4_qp_path { 141219820Sjeff u8 fl; 142329159Shselasky union { 143329159Shselasky u8 vlan_control; 144329159Shselasky u8 control; 145329159Shselasky }; 146255932Salfred u8 disable_pkey_check; 147219820Sjeff u8 pkey_index; 148219820Sjeff u8 counter_index; 149219820Sjeff u8 grh_mylmc; 150219820Sjeff __be16 rlid; 151219820Sjeff u8 ackto; 152219820Sjeff u8 mgid_index; 153219820Sjeff u8 static_rate; 154219820Sjeff u8 hop_limit; 155219820Sjeff __be32 tclass_flowlabel; 156219820Sjeff u8 rgid[16]; 157219820Sjeff u8 sched_queue; 158219820Sjeff u8 vlan_index; 159255932Salfred u8 feup; 160272027Shselasky u8 fvl_rx; 161219820Sjeff u8 reserved4[2]; 162329159Shselasky u8 dmac[ETH_ALEN]; 163219820Sjeff}; 164219820Sjeff 165272027Shselaskyenum { /* fl */ 166272027Shselasky MLX4_FL_CV = 1 << 6, 167329159Shselasky MLX4_FL_SV = 1 << 5, 168272027Shselasky MLX4_FL_ETH_HIDE_CQE_VLAN = 1 << 2, 169272027Shselasky MLX4_FL_ETH_SRC_CHECK_MC_LB = 1 << 1, 170272027Shselasky MLX4_FL_ETH_SRC_CHECK_UC_LB = 1 << 0, 171272027Shselasky}; 172329159Shselasky 173329159Shselaskyenum { /* control */ 174329159Shselasky MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER = 1 << 7, 175329159Shselasky}; 176329159Shselasky 177272027Shselaskyenum { /* vlan_control */ 178272027Shselasky MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED = 1 << 6, 179329159Shselasky MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED = 1 << 5, /* 802.1p priority tag */ 180329159Shselasky MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED = 1 << 4, 181272027Shselasky MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED = 1 << 2, 182329159Shselasky MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED = 1 << 1, /* 802.1p priority tag */ 183272027Shselasky MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED = 1 << 0 184272027Shselasky}; 185272027Shselasky 186272027Shselaskyenum { /* feup */ 187329159Shselasky MLX4_FEUP_FORCE_ETH_UP = 1 << 6, /* force Eth UP */ 188329159Shselasky MLX4_FSM_FORCE_ETH_SRC_MAC = 1 << 5, /* force Source MAC */ 189329159Shselasky MLX4_FVL_FORCE_ETH_VLAN = 1 << 3 /* force Eth vlan */ 190272027Shselasky}; 191272027Shselasky 192272027Shselaskyenum { /* fvl_rx */ 193329159Shselasky MLX4_FVL_RX_FORCE_ETH_VLAN = 1 << 0 /* enforce Eth rx vlan */ 194272027Shselasky}; 195272027Shselasky 196219820Sjeffstruct mlx4_qp_context { 197219820Sjeff __be32 flags; 198219820Sjeff __be32 pd; 199219820Sjeff u8 mtu_msgmax; 200219820Sjeff u8 rq_size_stride; 201219820Sjeff u8 sq_size_stride; 202329159Shselasky u8 rlkey_roce_mode; 203219820Sjeff __be32 usr_page; 204219820Sjeff __be32 local_qpn; 205219820Sjeff __be32 remote_qpn; 206219820Sjeff struct mlx4_qp_path pri_path; 207219820Sjeff struct mlx4_qp_path alt_path; 208219820Sjeff __be32 params1; 209219820Sjeff u32 reserved1; 210219820Sjeff __be32 next_send_psn; 211219820Sjeff __be32 cqn_send; 212329159Shselasky __be16 roce_entropy; 213329159Shselasky __be16 reserved2[3]; 214219820Sjeff __be32 last_acked_psn; 215219820Sjeff __be32 ssn; 216219820Sjeff __be32 params2; 217219820Sjeff __be32 rnr_nextrecvpsn; 218219820Sjeff __be32 xrcd; 219219820Sjeff __be32 cqn_recv; 220219820Sjeff __be64 db_rec_addr; 221219820Sjeff __be32 qkey; 222219820Sjeff __be32 srqn; 223219820Sjeff __be32 msn; 224219820Sjeff __be16 rq_wqe_counter; 225219820Sjeff __be16 sq_wqe_counter; 226329159Shselasky u32 reserved3; 227329159Shselasky __be16 rate_limit_params; 228329159Shselasky u8 reserved4; 229329159Shselasky u8 qos_vport; 230219820Sjeff __be32 param3; 231219820Sjeff __be32 nummmcpeers_basemkey; 232219820Sjeff u8 log_page_size; 233329159Shselasky u8 reserved5[2]; 234219820Sjeff u8 mtt_base_addr_h; 235219820Sjeff __be32 mtt_base_addr_l; 236329159Shselasky u32 reserved6[10]; 237219820Sjeff}; 238219820Sjeff 239272027Shselaskystruct mlx4_update_qp_context { 240272027Shselasky __be64 qp_mask; 241272027Shselasky __be64 primary_addr_path_mask; 242272027Shselasky __be64 secondary_addr_path_mask; 243272027Shselasky u64 reserved1; 244272027Shselasky struct mlx4_qp_context qp_context; 245272027Shselasky u64 reserved2[58]; 246272027Shselasky}; 247272027Shselasky 248272027Shselaskyenum { 249272027Shselasky MLX4_UPD_QP_MASK_PM_STATE = 32, 250272027Shselasky MLX4_UPD_QP_MASK_VSD = 33, 251329159Shselasky MLX4_UPD_QP_MASK_QOS_VPP = 34, 252329159Shselasky MLX4_UPD_QP_MASK_RATE_LIMIT = 35, 253272027Shselasky}; 254272027Shselasky 255272027Shselaskyenum { 256272027Shselasky MLX4_UPD_QP_PATH_MASK_PKEY_INDEX = 0 + 32, 257272027Shselasky MLX4_UPD_QP_PATH_MASK_FSM = 1 + 32, 258272027Shselasky MLX4_UPD_QP_PATH_MASK_MAC_INDEX = 2 + 32, 259272027Shselasky MLX4_UPD_QP_PATH_MASK_FVL = 3 + 32, 260272027Shselasky MLX4_UPD_QP_PATH_MASK_CV = 4 + 32, 261272027Shselasky MLX4_UPD_QP_PATH_MASK_VLAN_INDEX = 5 + 32, 262272027Shselasky MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN = 6 + 32, 263272027Shselasky MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED = 7 + 32, 264272027Shselasky MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P = 8 + 32, 265272027Shselasky MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED = 9 + 32, 266272027Shselasky MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED = 10 + 32, 267272027Shselasky MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P = 11 + 32, 268272027Shselasky MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED = 12 + 32, 269272027Shselasky MLX4_UPD_QP_PATH_MASK_FEUP = 13 + 32, 270272027Shselasky MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE = 14 + 32, 271272027Shselasky MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX = 15 + 32, 272272027Shselasky MLX4_UPD_QP_PATH_MASK_FVL_RX = 16 + 32, 273279584Shselasky MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_UC_LB = 18 + 32, 274279584Shselasky MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB = 19 + 32, 275329159Shselasky MLX4_UPD_QP_PATH_MASK_SV = 22 + 32, 276272027Shselasky}; 277272027Shselasky 278272027Shselaskyenum { /* param3 */ 279329159Shselasky MLX4_STRIP_VLAN = 1 << 30 280272027Shselasky}; 281272027Shselasky 282219820Sjeff/* Which firmware version adds support for NEC (NoErrorCompletion) bit */ 283219820Sjeff#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232) 284219820Sjeff 285219820Sjeffenum { 286291694Shselasky MLX4_WQE_CTRL_OWN = 1 << 31, 287219820Sjeff MLX4_WQE_CTRL_NEC = 1 << 29, 288291694Shselasky MLX4_WQE_CTRL_RR = 1 << 6, 289329159Shselasky MLX4_WQE_CTRL_IIP = 1 << 28, 290329159Shselasky MLX4_WQE_CTRL_ILP = 1 << 27, 291219820Sjeff MLX4_WQE_CTRL_FENCE = 1 << 6, 292219820Sjeff MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2, 293219820Sjeff MLX4_WQE_CTRL_SOLICITED = 1 << 1, 294219820Sjeff MLX4_WQE_CTRL_IP_CSUM = 1 << 4, 295219820Sjeff MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5, 296329159Shselasky MLX4_WQE_CTRL_INS_CVLAN = 1 << 6, 297329159Shselasky MLX4_WQE_CTRL_INS_SVLAN = 1 << 7, 298219820Sjeff MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7, 299219820Sjeff MLX4_WQE_CTRL_FORCE_LOOPBACK = 1 << 0, 300219820Sjeff}; 301219820Sjeff 302219820Sjeffstruct mlx4_wqe_ctrl_seg { 303219820Sjeff __be32 owner_opcode; 304329159Shselasky union { 305329159Shselasky struct { 306329159Shselasky __be16 vlan_tag; 307329159Shselasky u8 ins_vlan; 308329159Shselasky u8 fence_size; 309329159Shselasky }; 310329159Shselasky __be32 bf_qpn; 311329159Shselasky }; 312219820Sjeff /* 313219820Sjeff * High 24 bits are SRC remote buffer; low 8 bits are flags: 314219820Sjeff * [7] SO (strong ordering) 315219820Sjeff * [5] TCP/UDP checksum 316219820Sjeff * [4] IP checksum 317219820Sjeff * [3:2] C (generate completion queue entry) 318219820Sjeff * [1] SE (solicited event) 319255932Salfred * [0] FL (force loopback) 320219820Sjeff */ 321255932Salfred union { 322255932Salfred __be32 srcrb_flags; 323255932Salfred __be16 srcrb_flags16[2]; 324255932Salfred }; 325219820Sjeff /* 326219820Sjeff * imm is immediate data for send/RDMA write w/ immediate; 327219820Sjeff * also invalidation key for send with invalidate; input 328219820Sjeff * modifier for WQEs on CCQs. 329219820Sjeff */ 330219820Sjeff __be32 imm; 331219820Sjeff}; 332219820Sjeff 333219820Sjeffenum { 334219820Sjeff MLX4_WQE_MLX_VL15 = 1 << 17, 335255932Salfred MLX4_WQE_MLX_SLR = 1 << 16 336219820Sjeff}; 337219820Sjeff 338219820Sjeffstruct mlx4_wqe_mlx_seg { 339219820Sjeff u8 owner; 340219820Sjeff u8 reserved1[2]; 341219820Sjeff u8 opcode; 342255932Salfred __be16 sched_prio; 343255932Salfred u8 reserved2; 344219820Sjeff u8 size; 345219820Sjeff /* 346219820Sjeff * [17] VL15 347219820Sjeff * [16] SLR 348219820Sjeff * [15:12] static rate 349219820Sjeff * [11:8] SL 350219820Sjeff * [4] ICRC 351219820Sjeff * [3:2] C 352219820Sjeff * [0] FL (force loopback) 353219820Sjeff */ 354219820Sjeff __be32 flags; 355219820Sjeff __be16 rlid; 356219820Sjeff u16 reserved3; 357219820Sjeff}; 358219820Sjeff 359219820Sjeffstruct mlx4_wqe_datagram_seg { 360219820Sjeff __be32 av[8]; 361219820Sjeff __be32 dqpn; 362219820Sjeff __be32 qkey; 363219820Sjeff __be16 vlan; 364329159Shselasky u8 mac[ETH_ALEN]; 365219820Sjeff}; 366219820Sjeff 367219820Sjeffstruct mlx4_wqe_lso_seg { 368219820Sjeff __be32 mss_hdr_size; 369219820Sjeff __be32 header[0]; 370219820Sjeff}; 371219820Sjeff 372272027Shselaskyenum mlx4_wqe_bind_seg_flags2 { 373329159Shselasky MLX4_WQE_BIND_ZERO_BASED = (1 << 30), 374329159Shselasky MLX4_WQE_BIND_TYPE_2 = (1 << 31), 375272027Shselasky}; 376272027Shselasky 377219820Sjeffstruct mlx4_wqe_bind_seg { 378219820Sjeff __be32 flags1; 379219820Sjeff __be32 flags2; 380219820Sjeff __be32 new_rkey; 381219820Sjeff __be32 lkey; 382219820Sjeff __be64 addr; 383219820Sjeff __be64 length; 384219820Sjeff}; 385219820Sjeff 386219820Sjeffenum { 387219820Sjeff MLX4_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 388219820Sjeff MLX4_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 389272027Shselasky MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ = 1 << 29, 390272027Shselasky MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE = 1 << 30, 391272027Shselasky MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC = 1 << 31 392219820Sjeff}; 393219820Sjeff 394219820Sjeffstruct mlx4_wqe_fmr_seg { 395219820Sjeff __be32 flags; 396219820Sjeff __be32 mem_key; 397219820Sjeff __be64 buf_list; 398219820Sjeff __be64 start_addr; 399219820Sjeff __be64 reg_len; 400219820Sjeff __be32 offset; 401219820Sjeff __be32 page_size; 402219820Sjeff u32 reserved[2]; 403219820Sjeff}; 404219820Sjeff 405219820Sjeffstruct mlx4_wqe_fmr_ext_seg { 406219820Sjeff u8 flags; 407219820Sjeff u8 reserved; 408219820Sjeff __be16 app_mask; 409219820Sjeff __be16 wire_app_tag; 410219820Sjeff __be16 mem_app_tag; 411219820Sjeff __be32 wire_ref_tag_base; 412219820Sjeff __be32 mem_ref_tag_base; 413219820Sjeff}; 414219820Sjeff 415219820Sjeffstruct mlx4_wqe_local_inval_seg { 416272027Shselasky u64 reserved1; 417219820Sjeff __be32 mem_key; 418272027Shselasky u32 reserved2; 419272027Shselasky u64 reserved3[2]; 420219820Sjeff}; 421219820Sjeff 422219820Sjeffstruct mlx4_wqe_raddr_seg { 423219820Sjeff __be64 raddr; 424219820Sjeff __be32 rkey; 425219820Sjeff u32 reserved; 426219820Sjeff}; 427219820Sjeff 428219820Sjeffstruct mlx4_wqe_atomic_seg { 429219820Sjeff __be64 swap_add; 430219820Sjeff __be64 compare; 431219820Sjeff}; 432219820Sjeff 433219820Sjeffstruct mlx4_wqe_masked_atomic_seg { 434219820Sjeff __be64 swap_add; 435219820Sjeff __be64 compare; 436219820Sjeff __be64 swap_add_mask; 437219820Sjeff __be64 compare_mask; 438219820Sjeff}; 439219820Sjeff 440219820Sjeffstruct mlx4_wqe_data_seg { 441219820Sjeff __be32 byte_count; 442219820Sjeff __be32 lkey; 443219820Sjeff __be64 addr; 444219820Sjeff}; 445219820Sjeff 446219820Sjeffenum { 447219820Sjeff MLX4_INLINE_ALIGN = 64, 448219820Sjeff MLX4_INLINE_SEG = 1 << 31, 449219820Sjeff}; 450219820Sjeff 451219820Sjeffstruct mlx4_wqe_inline_seg { 452219820Sjeff __be32 byte_count; 453219820Sjeff}; 454219820Sjeff 455329159Shselaskyenum mlx4_update_qp_attr { 456329159Shselasky MLX4_UPDATE_QP_SMAC = 1 << 0, 457329159Shselasky MLX4_UPDATE_QP_VSD = 1 << 1, 458329159Shselasky MLX4_UPDATE_QP_RATE_LIMIT = 1 << 2, 459329159Shselasky MLX4_UPDATE_QP_QOS_VPORT = 1 << 3, 460329159Shselasky MLX4_UPDATE_QP_ETH_SRC_CHECK_MC_LB = 1 << 4, 461329159Shselasky MLX4_UPDATE_QP_SUPPORTED_ATTRS = (1 << 5) - 1 462329159Shselasky}; 463329159Shselasky 464329159Shselaskyenum mlx4_update_qp_params_flags { 465329159Shselasky MLX4_UPDATE_QP_PARAMS_FLAGS_ETH_CHECK_MC_LB = 1 << 0, 466329159Shselasky MLX4_UPDATE_QP_PARAMS_FLAGS_VSD_ENABLE = 1 << 1, 467329159Shselasky}; 468329159Shselasky 469329159Shselaskystruct mlx4_update_qp_params { 470329159Shselasky u8 smac_index; 471329159Shselasky u8 qos_vport; 472329159Shselasky u32 flags; 473329159Shselasky u16 rate_unit; 474329159Shselasky u16 rate_val; 475329159Shselasky}; 476329159Shselasky 477329159Shselaskyint mlx4_update_qp(struct mlx4_dev *dev, u32 qpn, 478329159Shselasky enum mlx4_update_qp_attr attr, 479329159Shselasky struct mlx4_update_qp_params *params); 480219820Sjeffint mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 481219820Sjeff enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state, 482219820Sjeff struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar, 483219820Sjeff int sqd_event, struct mlx4_qp *qp); 484219820Sjeff 485219820Sjeffint mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp, 486219820Sjeff struct mlx4_qp_context *context); 487219820Sjeff 488219820Sjeffint mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 489219820Sjeff struct mlx4_qp_context *context, 490219820Sjeff struct mlx4_qp *qp, enum mlx4_qp_state *qp_state); 491219820Sjeff 492219820Sjeffstatic inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn) 493219820Sjeff{ 494219820Sjeff return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1)); 495219820Sjeff} 496219820Sjeff 497219820Sjeffvoid mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp); 498219820Sjeff 499329159Shselaskystatic inline u16 folded_qp(u32 q) 500329159Shselasky{ 501329159Shselasky u16 res; 502329159Shselasky 503329159Shselasky res = ((q & 0xff) ^ ((q & 0xff0000) >> 16)) | (q & 0xff00); 504329159Shselasky return res; 505329159Shselasky} 506329159Shselasky 507329159Shselaskyu16 mlx4_qp_roce_entropy(struct mlx4_dev *dev, u32 qpn); 508329159Shselasky 509219820Sjeff#endif /* MLX4_QP_H */ 510