mlx4_ib_cq.c revision 331769
1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses.  You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 *     Redistribution and use in source and binary forms, with or
12 *     without modification, are permitted provided that the following
13 *     conditions are met:
14 *
15 *      - Redistributions of source code must retain the above
16 *        copyright notice, this list of conditions and the following
17 *        disclaimer.
18 *
19 *      - Redistributions in binary form must reproduce the above
20 *        copyright notice, this list of conditions and the following
21 *        disclaimer in the documentation and/or other materials
22 *        provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34#include <dev/mlx4/cq.h>
35#include <dev/mlx4/qp.h>
36#include <dev/mlx4/srq.h>
37#include <dev/mlx4/driver.h>
38#include <linux/slab.h>
39
40#include "mlx4_ib.h"
41#include <rdma/mlx4-abi.h>
42
43static void mlx4_ib_cq_comp(struct mlx4_cq *cq)
44{
45	struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
46	ibcq->comp_handler(ibcq, ibcq->cq_context);
47}
48
49static void mlx4_ib_cq_event(struct mlx4_cq *cq, enum mlx4_event type)
50{
51	struct ib_event event;
52	struct ib_cq *ibcq;
53
54	if (type != MLX4_EVENT_TYPE_CQ_ERROR) {
55		pr_warn("Unexpected event type %d "
56		       "on CQ %06x\n", type, cq->cqn);
57		return;
58	}
59
60	ibcq = &to_mibcq(cq)->ibcq;
61	if (ibcq->event_handler) {
62		event.device     = ibcq->device;
63		event.event      = IB_EVENT_CQ_ERR;
64		event.element.cq = ibcq;
65		ibcq->event_handler(&event, ibcq->cq_context);
66	}
67}
68
69static void *get_cqe_from_buf(struct mlx4_ib_cq_buf *buf, int n)
70{
71	return mlx4_buf_offset(&buf->buf, n * buf->entry_size);
72}
73
74static void *get_cqe(struct mlx4_ib_cq *cq, int n)
75{
76	return get_cqe_from_buf(&cq->buf, n);
77}
78
79static void *get_sw_cqe(struct mlx4_ib_cq *cq, int n)
80{
81	struct mlx4_cqe *cqe = get_cqe(cq, n & cq->ibcq.cqe);
82	struct mlx4_cqe *tcqe = ((cq->buf.entry_size == 64) ? (cqe + 1) : cqe);
83
84	return (!!(tcqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
85		!!(n & (cq->ibcq.cqe + 1))) ? NULL : cqe;
86}
87
88static struct mlx4_cqe *next_cqe_sw(struct mlx4_ib_cq *cq)
89{
90	return get_sw_cqe(cq, cq->mcq.cons_index);
91}
92
93int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
94{
95	struct mlx4_ib_cq *mcq = to_mcq(cq);
96	struct mlx4_ib_dev *dev = to_mdev(cq->device);
97
98	return mlx4_cq_modify(dev->dev, &mcq->mcq, cq_count, cq_period);
99}
100
101static int mlx4_ib_alloc_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int nent)
102{
103	int err;
104
105	err = mlx4_buf_alloc(dev->dev, nent * dev->dev->caps.cqe_size,
106			     PAGE_SIZE * 2, &buf->buf, GFP_KERNEL);
107
108	if (err)
109		goto out;
110
111	buf->entry_size = dev->dev->caps.cqe_size;
112	err = mlx4_mtt_init(dev->dev, buf->buf.npages, buf->buf.page_shift,
113				    &buf->mtt);
114	if (err)
115		goto err_buf;
116
117	err = mlx4_buf_write_mtt(dev->dev, &buf->mtt, &buf->buf, GFP_KERNEL);
118	if (err)
119		goto err_mtt;
120
121	return 0;
122
123err_mtt:
124	mlx4_mtt_cleanup(dev->dev, &buf->mtt);
125
126err_buf:
127	mlx4_buf_free(dev->dev, nent * buf->entry_size, &buf->buf);
128
129out:
130	return err;
131}
132
133static void mlx4_ib_free_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int cqe)
134{
135	mlx4_buf_free(dev->dev, (cqe + 1) * buf->entry_size, &buf->buf);
136}
137
138static int mlx4_ib_get_cq_umem(struct mlx4_ib_dev *dev, struct ib_ucontext *context,
139			       struct mlx4_ib_cq_buf *buf, struct ib_umem **umem,
140			       u64 buf_addr, int cqe)
141{
142	int err;
143	int cqe_size = dev->dev->caps.cqe_size;
144
145	*umem = ib_umem_get(context, buf_addr, cqe * cqe_size,
146			    IB_ACCESS_LOCAL_WRITE, 1);
147	if (IS_ERR(*umem))
148		return PTR_ERR(*umem);
149
150	err = mlx4_mtt_init(dev->dev, ib_umem_page_count(*umem),
151			    ilog2((*umem)->page_size), &buf->mtt);
152	if (err)
153		goto err_buf;
154
155	err = mlx4_ib_umem_write_mtt(dev, &buf->mtt, *umem);
156	if (err)
157		goto err_mtt;
158
159	return 0;
160
161err_mtt:
162	mlx4_mtt_cleanup(dev->dev, &buf->mtt);
163
164err_buf:
165	ib_umem_release(*umem);
166
167	return err;
168}
169
170#define CQ_CREATE_FLAGS_SUPPORTED IB_CQ_FLAGS_TIMESTAMP_COMPLETION
171struct ib_cq *mlx4_ib_create_cq(struct ib_device *ibdev,
172				const struct ib_cq_init_attr *attr,
173				struct ib_ucontext *context,
174				struct ib_udata *udata)
175{
176	int entries = attr->cqe;
177	int vector = attr->comp_vector;
178	struct mlx4_ib_dev *dev = to_mdev(ibdev);
179	struct mlx4_ib_cq *cq;
180	struct mlx4_uar *uar;
181	int err;
182
183	if (entries < 1 || entries > dev->dev->caps.max_cqes)
184		return ERR_PTR(-EINVAL);
185
186	if (attr->flags & ~CQ_CREATE_FLAGS_SUPPORTED)
187		return ERR_PTR(-EINVAL);
188
189	cq = kmalloc(sizeof *cq, GFP_KERNEL);
190	if (!cq)
191		return ERR_PTR(-ENOMEM);
192
193	entries      = roundup_pow_of_two(entries + 1);
194	cq->ibcq.cqe = entries - 1;
195	mutex_init(&cq->resize_mutex);
196	spin_lock_init(&cq->lock);
197	cq->resize_buf = NULL;
198	cq->resize_umem = NULL;
199	cq->create_flags = attr->flags;
200	INIT_LIST_HEAD(&cq->send_qp_list);
201	INIT_LIST_HEAD(&cq->recv_qp_list);
202
203	if (context) {
204		struct mlx4_ib_create_cq ucmd;
205
206		if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
207			err = -EFAULT;
208			goto err_cq;
209		}
210
211		err = mlx4_ib_get_cq_umem(dev, context, &cq->buf, &cq->umem,
212					  ucmd.buf_addr, entries);
213		if (err)
214			goto err_cq;
215
216		err = mlx4_ib_db_map_user(to_mucontext(context), ucmd.db_addr,
217					  &cq->db);
218		if (err)
219			goto err_mtt;
220
221		uar = &to_mucontext(context)->uar;
222	} else {
223		err = mlx4_db_alloc(dev->dev, &cq->db, 1, GFP_KERNEL);
224		if (err)
225			goto err_cq;
226
227		cq->mcq.set_ci_db  = cq->db.db;
228		cq->mcq.arm_db     = cq->db.db + 1;
229		*cq->mcq.set_ci_db = 0;
230		*cq->mcq.arm_db    = 0;
231
232		err = mlx4_ib_alloc_cq_buf(dev, &cq->buf, entries);
233		if (err)
234			goto err_db;
235
236		uar = &dev->priv_uar;
237	}
238
239	if (dev->eq_table)
240		vector = dev->eq_table[vector % ibdev->num_comp_vectors];
241
242	err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, uar,
243			    cq->db.dma, &cq->mcq, vector, 0,
244			    !!(cq->create_flags & IB_CQ_FLAGS_TIMESTAMP_COMPLETION));
245	if (err)
246		goto err_dbmap;
247
248	cq->mcq.comp = mlx4_ib_cq_comp;
249	cq->mcq.event = mlx4_ib_cq_event;
250
251	if (context)
252		if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof (__u32))) {
253			err = -EFAULT;
254			goto err_cq_free;
255		}
256
257	return &cq->ibcq;
258
259err_cq_free:
260	mlx4_cq_free(dev->dev, &cq->mcq);
261
262err_dbmap:
263	if (context)
264		mlx4_ib_db_unmap_user(to_mucontext(context), &cq->db);
265
266err_mtt:
267	mlx4_mtt_cleanup(dev->dev, &cq->buf.mtt);
268
269	if (context)
270		ib_umem_release(cq->umem);
271	else
272		mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
273
274err_db:
275	if (!context)
276		mlx4_db_free(dev->dev, &cq->db);
277
278err_cq:
279	kfree(cq);
280
281	return ERR_PTR(err);
282}
283
284static int mlx4_alloc_resize_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
285				  int entries)
286{
287	int err;
288
289	if (cq->resize_buf)
290		return -EBUSY;
291
292	cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_KERNEL);
293	if (!cq->resize_buf)
294		return -ENOMEM;
295
296	err = mlx4_ib_alloc_cq_buf(dev, &cq->resize_buf->buf, entries);
297	if (err) {
298		kfree(cq->resize_buf);
299		cq->resize_buf = NULL;
300		return err;
301	}
302
303	cq->resize_buf->cqe = entries - 1;
304
305	return 0;
306}
307
308static int mlx4_alloc_resize_umem(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
309				   int entries, struct ib_udata *udata)
310{
311	struct mlx4_ib_resize_cq ucmd;
312	int err;
313
314	if (cq->resize_umem)
315		return -EBUSY;
316
317	if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd))
318		return -EFAULT;
319
320	cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_KERNEL);
321	if (!cq->resize_buf)
322		return -ENOMEM;
323
324	err = mlx4_ib_get_cq_umem(dev, cq->umem->context, &cq->resize_buf->buf,
325				  &cq->resize_umem, ucmd.buf_addr, entries);
326	if (err) {
327		kfree(cq->resize_buf);
328		cq->resize_buf = NULL;
329		return err;
330	}
331
332	cq->resize_buf->cqe = entries - 1;
333
334	return 0;
335}
336
337static int mlx4_ib_get_outstanding_cqes(struct mlx4_ib_cq *cq)
338{
339	u32 i;
340
341	i = cq->mcq.cons_index;
342	while (get_sw_cqe(cq, i))
343		++i;
344
345	return i - cq->mcq.cons_index;
346}
347
348static void mlx4_ib_cq_resize_copy_cqes(struct mlx4_ib_cq *cq)
349{
350	struct mlx4_cqe *cqe, *new_cqe;
351	int i;
352	int cqe_size = cq->buf.entry_size;
353	int cqe_inc = cqe_size == 64 ? 1 : 0;
354
355	i = cq->mcq.cons_index;
356	cqe = get_cqe(cq, i & cq->ibcq.cqe);
357	cqe += cqe_inc;
358
359	while ((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) != MLX4_CQE_OPCODE_RESIZE) {
360		new_cqe = get_cqe_from_buf(&cq->resize_buf->buf,
361					   (i + 1) & cq->resize_buf->cqe);
362		memcpy(new_cqe, get_cqe(cq, i & cq->ibcq.cqe), cqe_size);
363		new_cqe += cqe_inc;
364
365		new_cqe->owner_sr_opcode = (cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK) |
366			(((i + 1) & (cq->resize_buf->cqe + 1)) ? MLX4_CQE_OWNER_MASK : 0);
367		cqe = get_cqe(cq, ++i & cq->ibcq.cqe);
368		cqe += cqe_inc;
369	}
370	++cq->mcq.cons_index;
371}
372
373int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
374{
375	struct mlx4_ib_dev *dev = to_mdev(ibcq->device);
376	struct mlx4_ib_cq *cq = to_mcq(ibcq);
377	struct mlx4_mtt mtt;
378	int outst_cqe;
379	int err;
380
381	mutex_lock(&cq->resize_mutex);
382	if (entries < 1 || entries > dev->dev->caps.max_cqes) {
383		err = -EINVAL;
384		goto out;
385	}
386
387	entries = roundup_pow_of_two(entries + 1);
388	if (entries == ibcq->cqe + 1) {
389		err = 0;
390		goto out;
391	}
392
393	if (entries > dev->dev->caps.max_cqes + 1) {
394		err = -EINVAL;
395		goto out;
396	}
397
398	if (ibcq->uobject) {
399		err = mlx4_alloc_resize_umem(dev, cq, entries, udata);
400		if (err)
401			goto out;
402	} else {
403		/* Can't be smaller than the number of outstanding CQEs */
404		outst_cqe = mlx4_ib_get_outstanding_cqes(cq);
405		if (entries < outst_cqe + 1) {
406			err = -EINVAL;
407			goto out;
408		}
409
410		err = mlx4_alloc_resize_buf(dev, cq, entries);
411		if (err)
412			goto out;
413	}
414
415	mtt = cq->buf.mtt;
416
417	err = mlx4_cq_resize(dev->dev, &cq->mcq, entries, &cq->resize_buf->buf.mtt);
418	if (err)
419		goto err_buf;
420
421	mlx4_mtt_cleanup(dev->dev, &mtt);
422	if (ibcq->uobject) {
423		cq->buf      = cq->resize_buf->buf;
424		cq->ibcq.cqe = cq->resize_buf->cqe;
425		ib_umem_release(cq->umem);
426		cq->umem     = cq->resize_umem;
427
428		kfree(cq->resize_buf);
429		cq->resize_buf = NULL;
430		cq->resize_umem = NULL;
431	} else {
432		struct mlx4_ib_cq_buf tmp_buf;
433		int tmp_cqe = 0;
434
435		spin_lock_irq(&cq->lock);
436		if (cq->resize_buf) {
437			mlx4_ib_cq_resize_copy_cqes(cq);
438			tmp_buf = cq->buf;
439			tmp_cqe = cq->ibcq.cqe;
440			cq->buf      = cq->resize_buf->buf;
441			cq->ibcq.cqe = cq->resize_buf->cqe;
442
443			kfree(cq->resize_buf);
444			cq->resize_buf = NULL;
445		}
446		spin_unlock_irq(&cq->lock);
447
448		if (tmp_cqe)
449			mlx4_ib_free_cq_buf(dev, &tmp_buf, tmp_cqe);
450	}
451
452	goto out;
453
454err_buf:
455	mlx4_mtt_cleanup(dev->dev, &cq->resize_buf->buf.mtt);
456	if (!ibcq->uobject)
457		mlx4_ib_free_cq_buf(dev, &cq->resize_buf->buf,
458				    cq->resize_buf->cqe);
459
460	kfree(cq->resize_buf);
461	cq->resize_buf = NULL;
462
463	if (cq->resize_umem) {
464		ib_umem_release(cq->resize_umem);
465		cq->resize_umem = NULL;
466	}
467
468out:
469	mutex_unlock(&cq->resize_mutex);
470
471	return err;
472}
473
474int mlx4_ib_destroy_cq(struct ib_cq *cq)
475{
476	struct mlx4_ib_dev *dev = to_mdev(cq->device);
477	struct mlx4_ib_cq *mcq = to_mcq(cq);
478
479	mlx4_cq_free(dev->dev, &mcq->mcq);
480	mlx4_mtt_cleanup(dev->dev, &mcq->buf.mtt);
481
482	if (cq->uobject) {
483		mlx4_ib_db_unmap_user(to_mucontext(cq->uobject->context), &mcq->db);
484		ib_umem_release(mcq->umem);
485	} else {
486		mlx4_ib_free_cq_buf(dev, &mcq->buf, cq->cqe);
487		mlx4_db_free(dev->dev, &mcq->db);
488	}
489
490	kfree(mcq);
491
492	return 0;
493}
494
495static void dump_cqe(void *cqe)
496{
497	__be32 *buf = cqe;
498
499	pr_debug("CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
500	       be32_to_cpu(buf[0]), be32_to_cpu(buf[1]), be32_to_cpu(buf[2]),
501	       be32_to_cpu(buf[3]), be32_to_cpu(buf[4]), be32_to_cpu(buf[5]),
502	       be32_to_cpu(buf[6]), be32_to_cpu(buf[7]));
503}
504
505static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe,
506				     struct ib_wc *wc)
507{
508	if (cqe->syndrome == MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR) {
509		pr_debug("local QP operation err "
510		       "(QPN %06x, WQE index %x, vendor syndrome %02x, "
511		       "opcode = %02x)\n",
512		       be32_to_cpu(cqe->my_qpn), be16_to_cpu(cqe->wqe_index),
513		       cqe->vendor_err_syndrome,
514		       cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
515		dump_cqe(cqe);
516	}
517
518	switch (cqe->syndrome) {
519	case MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR:
520		wc->status = IB_WC_LOC_LEN_ERR;
521		break;
522	case MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR:
523		wc->status = IB_WC_LOC_QP_OP_ERR;
524		break;
525	case MLX4_CQE_SYNDROME_LOCAL_PROT_ERR:
526		wc->status = IB_WC_LOC_PROT_ERR;
527		break;
528	case MLX4_CQE_SYNDROME_WR_FLUSH_ERR:
529		wc->status = IB_WC_WR_FLUSH_ERR;
530		break;
531	case MLX4_CQE_SYNDROME_MW_BIND_ERR:
532		wc->status = IB_WC_MW_BIND_ERR;
533		break;
534	case MLX4_CQE_SYNDROME_BAD_RESP_ERR:
535		wc->status = IB_WC_BAD_RESP_ERR;
536		break;
537	case MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR:
538		wc->status = IB_WC_LOC_ACCESS_ERR;
539		break;
540	case MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
541		wc->status = IB_WC_REM_INV_REQ_ERR;
542		break;
543	case MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR:
544		wc->status = IB_WC_REM_ACCESS_ERR;
545		break;
546	case MLX4_CQE_SYNDROME_REMOTE_OP_ERR:
547		wc->status = IB_WC_REM_OP_ERR;
548		break;
549	case MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
550		wc->status = IB_WC_RETRY_EXC_ERR;
551		break;
552	case MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
553		wc->status = IB_WC_RNR_RETRY_EXC_ERR;
554		break;
555	case MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR:
556		wc->status = IB_WC_REM_ABORT_ERR;
557		break;
558	default:
559		wc->status = IB_WC_GENERAL_ERR;
560		break;
561	}
562
563	wc->vendor_err = cqe->vendor_err_syndrome;
564}
565
566static int mlx4_ib_ipoib_csum_ok(__be16 status, __be16 checksum)
567{
568	return ((status & cpu_to_be16(MLX4_CQE_STATUS_IPV4      |
569				      MLX4_CQE_STATUS_IPV4F     |
570				      MLX4_CQE_STATUS_IPV4OPT   |
571				      MLX4_CQE_STATUS_IPV6      |
572				      MLX4_CQE_STATUS_IPOK)) ==
573		cpu_to_be16(MLX4_CQE_STATUS_IPV4        |
574			    MLX4_CQE_STATUS_IPOK))              &&
575		(status & cpu_to_be16(MLX4_CQE_STATUS_UDP       |
576				      MLX4_CQE_STATUS_TCP))     &&
577		checksum == cpu_to_be16(0xffff);
578}
579
580static void use_tunnel_data(struct mlx4_ib_qp *qp, struct mlx4_ib_cq *cq, struct ib_wc *wc,
581			    unsigned tail, struct mlx4_cqe *cqe, int is_eth)
582{
583	struct mlx4_ib_proxy_sqp_hdr *hdr;
584
585	ib_dma_sync_single_for_cpu(qp->ibqp.device,
586				   qp->sqp_proxy_rcv[tail].map,
587				   sizeof (struct mlx4_ib_proxy_sqp_hdr),
588				   DMA_FROM_DEVICE);
589	hdr = (struct mlx4_ib_proxy_sqp_hdr *) (qp->sqp_proxy_rcv[tail].addr);
590	wc->pkey_index	= be16_to_cpu(hdr->tun.pkey_index);
591	wc->src_qp	= be32_to_cpu(hdr->tun.flags_src_qp) & 0xFFFFFF;
592	wc->wc_flags   |= (hdr->tun.g_ml_path & 0x80) ? (IB_WC_GRH) : 0;
593	wc->dlid_path_bits = 0;
594
595	if (is_eth) {
596		wc->vlan_id = be16_to_cpu(hdr->tun.sl_vid);
597		memcpy(&(wc->smac[0]), (char *)&hdr->tun.mac_31_0, 4);
598		memcpy(&(wc->smac[4]), (char *)&hdr->tun.slid_mac_47_32, 2);
599		wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC);
600	} else {
601		wc->slid        = be16_to_cpu(hdr->tun.slid_mac_47_32);
602		wc->sl          = (u8) (be16_to_cpu(hdr->tun.sl_vid) >> 12);
603	}
604}
605
606static void mlx4_ib_qp_sw_comp(struct mlx4_ib_qp *qp, int num_entries,
607			       struct ib_wc *wc, int *npolled, int is_send)
608{
609	struct mlx4_ib_wq *wq;
610	unsigned cur;
611	int i;
612
613	wq = is_send ? &qp->sq : &qp->rq;
614	cur = wq->head - wq->tail;
615
616	if (cur == 0)
617		return;
618
619	for (i = 0;  i < cur && *npolled < num_entries; i++) {
620		wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
621		wc->status = IB_WC_WR_FLUSH_ERR;
622		wc->vendor_err = MLX4_CQE_SYNDROME_WR_FLUSH_ERR;
623		wq->tail++;
624		(*npolled)++;
625		wc->qp = &qp->ibqp;
626		wc++;
627	}
628}
629
630static void mlx4_ib_poll_sw_comp(struct mlx4_ib_cq *cq, int num_entries,
631				 struct ib_wc *wc, int *npolled)
632{
633	struct mlx4_ib_qp *qp;
634
635	*npolled = 0;
636	/* Find uncompleted WQEs belonging to that cq and retrun
637	 * simulated FLUSH_ERR completions
638	 */
639	list_for_each_entry(qp, &cq->send_qp_list, cq_send_list) {
640		mlx4_ib_qp_sw_comp(qp, num_entries, wc + *npolled, npolled, 1);
641		if (*npolled >= num_entries)
642			goto out;
643	}
644
645	list_for_each_entry(qp, &cq->recv_qp_list, cq_recv_list) {
646		mlx4_ib_qp_sw_comp(qp, num_entries, wc + *npolled, npolled, 0);
647		if (*npolled >= num_entries)
648			goto out;
649	}
650
651out:
652	return;
653}
654
655static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq,
656			    struct mlx4_ib_qp **cur_qp,
657			    struct ib_wc *wc)
658{
659	struct mlx4_cqe *cqe;
660	struct mlx4_qp *mqp;
661	struct mlx4_ib_wq *wq;
662	struct mlx4_ib_srq *srq;
663	struct mlx4_srq *msrq = NULL;
664	int is_send;
665	int is_error;
666	int is_eth;
667	u32 g_mlpath_rqpn;
668	u16 wqe_ctr;
669	unsigned tail = 0;
670
671repoll:
672	cqe = next_cqe_sw(cq);
673	if (!cqe)
674		return -EAGAIN;
675
676	if (cq->buf.entry_size == 64)
677		cqe++;
678
679	++cq->mcq.cons_index;
680
681	/*
682	 * Make sure we read CQ entry contents after we've checked the
683	 * ownership bit.
684	 */
685	rmb();
686
687	is_send  = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK;
688	is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
689		MLX4_CQE_OPCODE_ERROR;
690
691	/* Resize CQ in progress */
692	if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_CQE_OPCODE_RESIZE)) {
693		if (cq->resize_buf) {
694			struct mlx4_ib_dev *dev = to_mdev(cq->ibcq.device);
695
696			mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
697			cq->buf      = cq->resize_buf->buf;
698			cq->ibcq.cqe = cq->resize_buf->cqe;
699
700			kfree(cq->resize_buf);
701			cq->resize_buf = NULL;
702		}
703
704		goto repoll;
705	}
706
707	if (!*cur_qp ||
708	    (be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) {
709		/*
710		 * We do not have to take the QP table lock here,
711		 * because CQs will be locked while QPs are removed
712		 * from the table.
713		 */
714		mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev,
715				       be32_to_cpu(cqe->vlan_my_qpn));
716		*cur_qp = to_mibqp(mqp);
717	}
718
719	wc->qp = &(*cur_qp)->ibqp;
720
721	if (wc->qp->qp_type == IB_QPT_XRC_TGT) {
722		u32 srq_num;
723		g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn);
724		srq_num       = g_mlpath_rqpn & 0xffffff;
725		/* SRQ is also in the radix tree */
726		msrq = mlx4_srq_lookup(to_mdev(cq->ibcq.device)->dev,
727				       srq_num);
728	}
729
730	if (is_send) {
731		wq = &(*cur_qp)->sq;
732		if (!(*cur_qp)->sq_signal_bits) {
733			wqe_ctr = be16_to_cpu(cqe->wqe_index);
734			wq->tail += (u16) (wqe_ctr - (u16) wq->tail);
735		}
736		wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
737		++wq->tail;
738	} else if ((*cur_qp)->ibqp.srq) {
739		srq = to_msrq((*cur_qp)->ibqp.srq);
740		wqe_ctr = be16_to_cpu(cqe->wqe_index);
741		wc->wr_id = srq->wrid[wqe_ctr];
742		mlx4_ib_free_srq_wqe(srq, wqe_ctr);
743	} else if (msrq) {
744		srq = to_mibsrq(msrq);
745		wqe_ctr = be16_to_cpu(cqe->wqe_index);
746		wc->wr_id = srq->wrid[wqe_ctr];
747		mlx4_ib_free_srq_wqe(srq, wqe_ctr);
748	} else {
749		wq	  = &(*cur_qp)->rq;
750		tail	  = wq->tail & (wq->wqe_cnt - 1);
751		wc->wr_id = wq->wrid[tail];
752		++wq->tail;
753	}
754
755	if (unlikely(is_error)) {
756		mlx4_ib_handle_error_cqe((struct mlx4_err_cqe *) cqe, wc);
757		return 0;
758	}
759
760	wc->status = IB_WC_SUCCESS;
761
762	if (is_send) {
763		wc->wc_flags = 0;
764		switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
765		case MLX4_OPCODE_RDMA_WRITE_IMM:
766			wc->wc_flags |= IB_WC_WITH_IMM;
767		case MLX4_OPCODE_RDMA_WRITE:
768			wc->opcode    = IB_WC_RDMA_WRITE;
769			break;
770		case MLX4_OPCODE_SEND_IMM:
771			wc->wc_flags |= IB_WC_WITH_IMM;
772		case MLX4_OPCODE_SEND:
773		case MLX4_OPCODE_SEND_INVAL:
774			wc->opcode    = IB_WC_SEND;
775			break;
776		case MLX4_OPCODE_RDMA_READ:
777			wc->opcode    = IB_WC_RDMA_READ;
778			wc->byte_len  = be32_to_cpu(cqe->byte_cnt);
779			break;
780		case MLX4_OPCODE_ATOMIC_CS:
781			wc->opcode    = IB_WC_COMP_SWAP;
782			wc->byte_len  = 8;
783			break;
784		case MLX4_OPCODE_ATOMIC_FA:
785			wc->opcode    = IB_WC_FETCH_ADD;
786			wc->byte_len  = 8;
787			break;
788		case MLX4_OPCODE_MASKED_ATOMIC_CS:
789			wc->opcode    = IB_WC_MASKED_COMP_SWAP;
790			wc->byte_len  = 8;
791			break;
792		case MLX4_OPCODE_MASKED_ATOMIC_FA:
793			wc->opcode    = IB_WC_MASKED_FETCH_ADD;
794			wc->byte_len  = 8;
795			break;
796		case MLX4_OPCODE_LSO:
797			wc->opcode    = IB_WC_LSO;
798			break;
799		case MLX4_OPCODE_FMR:
800			wc->opcode    = IB_WC_REG_MR;
801			break;
802		case MLX4_OPCODE_LOCAL_INVAL:
803			wc->opcode    = IB_WC_LOCAL_INV;
804			break;
805		}
806	} else {
807		wc->byte_len = be32_to_cpu(cqe->byte_cnt);
808
809		switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
810		case MLX4_RECV_OPCODE_RDMA_WRITE_IMM:
811			wc->opcode	= IB_WC_RECV_RDMA_WITH_IMM;
812			wc->wc_flags	= IB_WC_WITH_IMM;
813			wc->ex.imm_data = cqe->immed_rss_invalid;
814			break;
815		case MLX4_RECV_OPCODE_SEND_INVAL:
816			wc->opcode	= IB_WC_RECV;
817			wc->wc_flags	= IB_WC_WITH_INVALIDATE;
818			wc->ex.invalidate_rkey = be32_to_cpu(cqe->immed_rss_invalid);
819			break;
820		case MLX4_RECV_OPCODE_SEND:
821			wc->opcode   = IB_WC_RECV;
822			wc->wc_flags = 0;
823			break;
824		case MLX4_RECV_OPCODE_SEND_IMM:
825			wc->opcode	= IB_WC_RECV;
826			wc->wc_flags	= IB_WC_WITH_IMM;
827			wc->ex.imm_data = cqe->immed_rss_invalid;
828			break;
829		}
830
831		is_eth = (rdma_port_get_link_layer(wc->qp->device,
832						  (*cur_qp)->port) ==
833			  IB_LINK_LAYER_ETHERNET);
834		if (mlx4_is_mfunc(to_mdev(cq->ibcq.device)->dev)) {
835			if ((*cur_qp)->mlx4_ib_qp_type &
836			    (MLX4_IB_QPT_PROXY_SMI_OWNER |
837			     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
838				use_tunnel_data(*cur_qp, cq, wc, tail, cqe,
839						is_eth);
840				return 0;
841			}
842		}
843
844		wc->slid	   = be16_to_cpu(cqe->rlid);
845		g_mlpath_rqpn	   = be32_to_cpu(cqe->g_mlpath_rqpn);
846		wc->src_qp	   = g_mlpath_rqpn & 0xffffff;
847		wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f;
848		wc->wc_flags	  |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0;
849		wc->pkey_index     = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f;
850		wc->wc_flags	  |= mlx4_ib_ipoib_csum_ok(cqe->status,
851					cqe->checksum) ? IB_WC_IP_CSUM_OK : 0;
852		if (is_eth) {
853			wc->sl  = be16_to_cpu(cqe->sl_vid) >> 13;
854			if (be32_to_cpu(cqe->vlan_my_qpn) &
855					MLX4_CQE_CVLAN_PRESENT_MASK) {
856				wc->vlan_id = be16_to_cpu(cqe->sl_vid) &
857					MLX4_CQE_VID_MASK;
858			} else {
859				wc->vlan_id = 0xffff;
860			}
861			memcpy(wc->smac, cqe->smac, ETH_ALEN);
862			wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC);
863		} else {
864			wc->sl  = be16_to_cpu(cqe->sl_vid) >> 12;
865			wc->vlan_id = 0xffff;
866		}
867	}
868
869	return 0;
870}
871
872int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
873{
874	struct mlx4_ib_cq *cq = to_mcq(ibcq);
875	struct mlx4_ib_qp *cur_qp = NULL;
876	unsigned long flags;
877	int npolled;
878	struct mlx4_ib_dev *mdev = to_mdev(cq->ibcq.device);
879
880	spin_lock_irqsave(&cq->lock, flags);
881	if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
882		mlx4_ib_poll_sw_comp(cq, num_entries, wc, &npolled);
883		goto out;
884	}
885
886	for (npolled = 0; npolled < num_entries; ++npolled) {
887		if (mlx4_ib_poll_one(cq, &cur_qp, wc + npolled))
888			break;
889	}
890
891	mlx4_cq_set_ci(&cq->mcq);
892
893out:
894	spin_unlock_irqrestore(&cq->lock, flags);
895
896	return npolled;
897}
898
899int mlx4_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
900{
901	mlx4_cq_arm(&to_mcq(ibcq)->mcq,
902		    (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
903		    MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT,
904		    to_mdev(ibcq->device)->uar_map,
905		    MLX4_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->uar_lock));
906
907	return 0;
908}
909
910void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
911{
912	u32 prod_index;
913	int nfreed = 0;
914	struct mlx4_cqe *cqe, *dest;
915	u8 owner_bit;
916	int cqe_inc = cq->buf.entry_size == 64 ? 1 : 0;
917
918	/*
919	 * First we need to find the current producer index, so we
920	 * know where to start cleaning from.  It doesn't matter if HW
921	 * adds new entries after this loop -- the QP we're worried
922	 * about is already in RESET, so the new entries won't come
923	 * from our QP and therefore don't need to be checked.
924	 */
925	for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); ++prod_index)
926		if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
927			break;
928
929	/*
930	 * Now sweep backwards through the CQ, removing CQ entries
931	 * that match our QP by copying older entries on top of them.
932	 */
933	while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
934		cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
935		cqe += cqe_inc;
936
937		if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) {
938			if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK))
939				mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index));
940			++nfreed;
941		} else if (nfreed) {
942			dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
943			dest += cqe_inc;
944
945			owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK;
946			memcpy(dest, cqe, sizeof *cqe);
947			dest->owner_sr_opcode = owner_bit |
948				(dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
949		}
950	}
951
952	if (nfreed) {
953		cq->mcq.cons_index += nfreed;
954		/*
955		 * Make sure update of buffer contents is done before
956		 * updating consumer index.
957		 */
958		wmb();
959		mlx4_cq_set_ci(&cq->mcq);
960	}
961}
962
963void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
964{
965	spin_lock_irq(&cq->lock);
966	__mlx4_ib_cq_clean(cq, qpn, srq);
967	spin_unlock_irq(&cq->lock);
968}
969