en.h revision 341909 
1/*
2 * Copyright (c) 2007, 2014 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses.  You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 *     Redistribution and use in source and binary forms, with or
11 *     without modification, are permitted provided that the following
12 *     conditions are met:
13 *
14 *      - Redistributions of source code must retain the above
15 *        copyright notice, this list of conditions and the following
16 *        disclaimer.
17 *
18 *      - Redistributions in binary form must reproduce the above
19 *        copyright notice, this list of conditions and the following
20 *        disclaimer in the documentation and/or other materials
21 *        provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#ifndef _MLX4_EN_H_
35#define _MLX4_EN_H_
36
37#include <linux/bitops.h>
38#include <linux/compiler.h>
39#include <linux/list.h>
40#include <linux/mutex.h>
41#include <linux/kobject.h>
42#include <linux/netdevice.h>
43#include <linux/if_vlan.h>
44#include <linux/if_ether.h>
45#ifdef CONFIG_MLX4_EN_DCB
46#include <linux/dcbnl.h>
47#endif
48
49#include <dev/mlx4/device.h>
50#include <dev/mlx4/qp.h>
51#include <dev/mlx4/cq.h>
52#include <dev/mlx4/srq.h>
53#include <dev/mlx4/doorbell.h>
54#include <dev/mlx4/cmd.h>
55
56#include <netinet/tcp_lro.h>
57
58#include "en_port.h"
59#include <dev/mlx4/stats.h>
60
61#define DRV_NAME	"mlx4_en"
62
63#define MLX4_EN_MSG_LEVEL	(NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
64
65/*
66 * Device constants
67 */
68
69
70#define MLX4_EN_PAGE_SHIFT	12
71#define MLX4_EN_PAGE_SIZE	(1 << MLX4_EN_PAGE_SHIFT)
72#define	MLX4_NET_IP_ALIGN	2	/* bytes */
73#define DEF_RX_RINGS		16
74#define MAX_RX_RINGS		128
75#define MIN_RX_RINGS		4
76#define TXBB_SIZE		64
77#define HEADROOM		(2048 / TXBB_SIZE + 1)
78#define INIT_OWNER_BIT		0xffffffff
79#define STAMP_STRIDE		64
80#define STAMP_DWORDS		(STAMP_STRIDE / 4)
81#define STAMP_SHIFT		31
82#define STAMP_VAL		0x7fffffff
83#define STATS_DELAY		(HZ / 4)
84#define SERVICE_TASK_DELAY	(HZ / 4)
85#define MAX_NUM_OF_FS_RULES	256
86
87#define MLX4_EN_FILTER_HASH_SHIFT 4
88#define MLX4_EN_FILTER_EXPIRY_QUOTA 60
89
90#ifdef CONFIG_NET_RX_BUSY_POLL
91#define LL_EXTENDED_STATS
92#endif
93
94/* vlan valid range */
95#define VLAN_MIN_VALUE		1
96#define VLAN_MAX_VALUE		4094
97
98/*
99 * OS related constants and tunables
100 */
101
102#define MLX4_EN_WATCHDOG_TIMEOUT	(15 * HZ)
103
104#define MLX4_EN_ALLOC_SIZE     PAGE_ALIGN(PAGE_SIZE)
105#define MLX4_EN_ALLOC_ORDER    get_order(MLX4_EN_ALLOC_SIZE)
106
107enum mlx4_en_alloc_type {
108	MLX4_EN_ALLOC_NEW = 0,
109	MLX4_EN_ALLOC_REPLACEMENT = 1,
110};
111
112/* Maximum ring sizes */
113#define MLX4_EN_DEF_TX_QUEUE_SIZE       4096
114
115/* Minimum packet number till arming the CQ */
116#define MLX4_EN_MIN_RX_ARM	2048
117#define MLX4_EN_MIN_TX_ARM	2048
118
119/* Maximum ring sizes */
120#define MLX4_EN_MAX_TX_SIZE	8192
121#define MLX4_EN_MAX_RX_SIZE	8192
122
123/* Minimum ring sizes */
124#define MLX4_EN_MIN_RX_SIZE	(4096 / TXBB_SIZE)
125#define MLX4_EN_MIN_TX_SIZE	(4096 / TXBB_SIZE)
126
127#define MLX4_EN_SMALL_PKT_SIZE		64
128
129#define MLX4_EN_MAX_TX_RING_P_UP	32
130#define MLX4_EN_NUM_UP			1
131
132#define MAX_TX_RINGS			(MLX4_EN_MAX_TX_RING_P_UP * \
133					MLX4_EN_NUM_UP)
134
135#define MLX4_EN_NO_VLAN			0xffff
136
137#define MLX4_EN_DEF_TX_RING_SIZE	1024
138#define MLX4_EN_DEF_RX_RING_SIZE  	1024
139
140/* Target number of bytes to coalesce with interrupt moderation */
141#define MLX4_EN_RX_COAL_TARGET	44
142#define MLX4_EN_RX_COAL_TIME	0x10
143
144#define MLX4_EN_TX_COAL_PKTS	64
145#define MLX4_EN_TX_COAL_TIME	64
146
147#define MLX4_EN_RX_RATE_LOW		400000
148#define MLX4_EN_RX_COAL_TIME_LOW	0
149#define MLX4_EN_RX_RATE_HIGH		450000
150#define MLX4_EN_RX_COAL_TIME_HIGH	128
151#define MLX4_EN_RX_SIZE_THRESH		1024
152#define MLX4_EN_RX_RATE_THRESH		(1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
153#define MLX4_EN_SAMPLE_INTERVAL		0
154#define MLX4_EN_AVG_PKT_SMALL		256
155
156#define MLX4_EN_AUTO_CONF	0xffff
157
158#define MLX4_EN_DEF_RX_PAUSE	1
159#define MLX4_EN_DEF_TX_PAUSE	1
160
161/* Interval between successive polls in the Tx routine when polling is used
162   instead of interrupts (in per-core Tx rings) - should be power of 2 */
163#define MLX4_EN_TX_POLL_MODER	16
164#define MLX4_EN_TX_POLL_TIMEOUT	(HZ / 4)
165
166#define MLX4_EN_64_ALIGN	(64 - NET_SKB_PAD)
167#define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
168#define HEADER_COPY_SIZE       (128)
169#define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETHER_HDR_LEN)
170
171#define MLX4_EN_MIN_MTU		46
172#define ETH_BCAST		0xffffffffffffULL
173
174#define MLX4_EN_LOOPBACK_RETRIES	5
175#define MLX4_EN_LOOPBACK_TIMEOUT	100
176
177#ifdef MLX4_EN_PERF_STAT
178/* Number of samples to 'average' */
179#define AVG_SIZE			128
180#define AVG_FACTOR			1024
181
182#define INC_PERF_COUNTER(cnt)		(++(cnt))
183#define ADD_PERF_COUNTER(cnt, add)	((cnt) += (add))
184#define AVG_PERF_COUNTER(cnt, sample) \
185	((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
186#define GET_PERF_COUNTER(cnt)		(cnt)
187#define GET_AVG_PERF_COUNTER(cnt)	((cnt) / AVG_FACTOR)
188
189#else
190
191#define INC_PERF_COUNTER(cnt)		do {} while (0)
192#define ADD_PERF_COUNTER(cnt, add)	do {} while (0)
193#define AVG_PERF_COUNTER(cnt, sample)	do {} while (0)
194#define GET_PERF_COUNTER(cnt)		(0)
195#define GET_AVG_PERF_COUNTER(cnt)	(0)
196#endif /* MLX4_EN_PERF_STAT */
197
198/* Constants for TX flow */
199enum {
200	MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
201	MAX_BF = 256,
202	MIN_PKT_LEN = 17,
203};
204
205/*
206 * Configurables
207 */
208
209enum cq_type {
210	RX = 0,
211	TX = 1,
212};
213
214
215/*
216 * Useful macros
217 */
218#define ROUNDUP_LOG2(x)		ilog2(roundup_pow_of_two(x))
219#define XNOR(x, y)		(!(x) == !(y))
220#define ILLEGAL_MAC(addr)	(addr == 0xffffffffffffULL || addr == 0x0)
221
222struct mlx4_en_tx_info {
223	bus_dmamap_t dma_map;
224        struct mbuf *mb;
225        u32 nr_txbb;
226	u32 nr_bytes;
227};
228
229
230#define MLX4_EN_BIT_DESC_OWN	0x80000000
231#define CTRL_SIZE	sizeof(struct mlx4_wqe_ctrl_seg)
232#define MLX4_EN_MEMTYPE_PAD	0x100
233#define DS_SIZE		sizeof(struct mlx4_wqe_data_seg)
234
235
236struct mlx4_en_tx_desc {
237	struct mlx4_wqe_ctrl_seg ctrl;
238	union {
239		struct mlx4_wqe_data_seg data; /* at least one data segment */
240		struct mlx4_wqe_lso_seg lso;
241		struct mlx4_wqe_inline_seg inl;
242	};
243};
244
245#define MLX4_EN_USE_SRQ		0x01000000
246
247#define MLX4_EN_RX_BUDGET 64
248
249#define	MLX4_EN_TX_MAX_DESC_SIZE 512	/* bytes */
250#define	MLX4_EN_TX_MAX_MBUF_SIZE 65536	/* bytes */
251#define	MLX4_EN_TX_MAX_PAYLOAD_SIZE 65536	/* bytes */
252#define	MLX4_EN_TX_MAX_MBUF_FRAGS \
253    ((MLX4_EN_TX_MAX_DESC_SIZE - 128) / DS_SIZE_ALIGNMENT) /* units */
254#define	MLX4_EN_TX_WQE_MAX_WQEBBS			\
255    (MLX4_EN_TX_MAX_DESC_SIZE / TXBB_SIZE) /* units */
256
257#define MLX4_EN_CX3_LOW_ID	0x1000
258#define MLX4_EN_CX3_HIGH_ID	0x1005
259
260struct mlx4_en_tx_ring {
261        spinlock_t tx_lock;
262	bus_dma_tag_t dma_tag;
263	struct mlx4_hwq_resources wqres;
264	u32 size ; /* number of TXBBs */
265	u32 size_mask;
266	u16 stride;
267	u16 cqn;	/* index of port CQ associated with this ring */
268	u32 prod;
269	u32 cons;
270	u32 buf_size;
271	u32 doorbell_qpn;
272	u8 *buf;
273	u16 poll_cnt;
274	struct mlx4_en_tx_info *tx_info;
275	u8 queue_index;
276	u32 last_nr_txbb;
277	struct mlx4_qp qp;
278	struct mlx4_qp_context context;
279	int qpn;
280	enum mlx4_qp_state qp_state;
281	struct mlx4_srq dummy;
282	u64 bytes;
283	u64 packets;
284	u64 tx_csum;
285	u64 queue_stopped;
286	u64 oversized_packets;
287	u64 wake_queue;
288	u64 tso_packets;
289	u64 defrag_attempts;
290	struct mlx4_bf bf;
291	bool bf_enabled;
292	int hwtstamp_tx_type;
293	spinlock_t comp_lock;
294	int inline_thold;
295	u64 watchdog_time;
296};
297
298struct mlx4_en_rx_desc {
299	/* actual number of entries depends on rx ring stride */
300	struct mlx4_wqe_data_seg data[0];
301};
302
303struct mlx4_en_rx_mbuf {
304	bus_dmamap_t dma_map;
305	struct mbuf *mbuf;
306};
307
308struct mlx4_en_rx_spare {
309	bus_dmamap_t dma_map;
310	struct mbuf *mbuf;
311	u64 paddr_be;
312};
313
314struct mlx4_en_rx_ring {
315	struct mlx4_hwq_resources wqres;
316	bus_dma_tag_t dma_tag;
317	struct mlx4_en_rx_spare spare;
318	u32 size ;	/* number of Rx descs*/
319	u32 actual_size;
320	u32 size_mask;
321	u16 stride;
322	u16 log_stride;
323	u16 cqn;	/* index of port CQ associated with this ring */
324	u32 prod;
325	u32 cons;
326	u32 buf_size;
327	u8  fcs_del;
328	u32 rx_mb_size;
329	int qpn;
330	u8 *buf;
331	struct mlx4_en_rx_mbuf *mbuf;
332	u64 errors;
333	u64 bytes;
334	u64 packets;
335#ifdef LL_EXTENDED_STATS
336	u64 yields;
337	u64 misses;
338	u64 cleaned;
339#endif
340	u64 csum_ok;
341	u64 csum_none;
342	int hwtstamp_rx_filter;
343	int numa_node;
344	struct lro_ctrl lro;
345};
346
347static inline int mlx4_en_can_lro(__be16 status)
348{
349	const __be16 status_all = cpu_to_be16(
350			MLX4_CQE_STATUS_IPV4    |
351			MLX4_CQE_STATUS_IPV4F   |
352			MLX4_CQE_STATUS_IPV6    |
353			MLX4_CQE_STATUS_IPV4OPT |
354			MLX4_CQE_STATUS_TCP     |
355			MLX4_CQE_STATUS_UDP     |
356			MLX4_CQE_STATUS_IPOK);
357	const __be16 status_ipv4_ipok_tcp = cpu_to_be16(
358			MLX4_CQE_STATUS_IPV4    |
359			MLX4_CQE_STATUS_IPOK    |
360			MLX4_CQE_STATUS_TCP);
361	const __be16 status_ipv6_ipok_tcp = cpu_to_be16(
362			MLX4_CQE_STATUS_IPV6    |
363			MLX4_CQE_STATUS_IPOK    |
364			MLX4_CQE_STATUS_TCP);
365
366	status &= status_all;
367	return (status == status_ipv4_ipok_tcp ||
368			status == status_ipv6_ipok_tcp);
369}
370
371struct mlx4_en_cq {
372	struct mlx4_cq          mcq;
373	struct mlx4_hwq_resources wqres;
374	int                     ring;
375	spinlock_t              lock;
376	struct net_device      *dev;
377        /* Per-core Tx cq processing support */
378        struct timer_list timer;
379	int size;
380	int buf_size;
381	unsigned vector;
382	enum cq_type is_tx;
383	u16 moder_time;
384	u16 moder_cnt;
385	struct mlx4_cqe *buf;
386	struct task cq_task;
387	struct taskqueue *tq;
388#define MLX4_EN_OPCODE_ERROR	0x1e
389	u32 tot_rx;
390	u32 tot_tx;
391	u32 curr_poll_rx_cpu_id;
392
393#ifdef CONFIG_NET_RX_BUSY_POLL
394	unsigned int state;
395#define MLX4_EN_CQ_STATE_IDLE        0
396#define MLX4_EN_CQ_STATE_NAPI     1    /* NAPI owns this CQ */
397#define MLX4_EN_CQ_STATE_POLL     2    /* poll owns this CQ */
398#define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATE_NAPI | MLX4_EN_CQ_STATE_POLL)
399#define MLX4_EN_CQ_STATE_NAPI_YIELD  4    /* NAPI yielded this CQ */
400#define MLX4_EN_CQ_STATE_POLL_YIELD  8    /* poll yielded this CQ */
401#define CQ_YIELD (MLX4_EN_CQ_STATE_NAPI_YIELD | MLX4_EN_CQ_STATE_POLL_YIELD)
402#define CQ_USER_PEND (MLX4_EN_CQ_STATE_POLL | MLX4_EN_CQ_STATE_POLL_YIELD)
403	spinlock_t poll_lock; /* protects from LLS/napi conflicts */
404#endif  /* CONFIG_NET_RX_BUSY_POLL */
405};
406
407struct mlx4_en_port_profile {
408	u32 flags;
409	u32 tx_ring_num;
410	u32 rx_ring_num;
411	u32 tx_ring_size;
412	u32 rx_ring_size;
413	u8 rx_pause;
414	u8 rx_ppp;
415	u8 tx_pause;
416	u8 tx_ppp;
417	int rss_rings;
418	int inline_thold;
419};
420
421struct mlx4_en_profile {
422	int rss_xor;
423	int udp_rss;
424	u8 rss_mask;
425	u32 active_ports;
426	u32 small_pkt_int;
427	u8 no_reset;
428	u8 num_tx_rings_p_up;
429	struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
430};
431
432struct mlx4_en_dev {
433	struct mlx4_dev		*dev;
434	struct pci_dev		*pdev;
435	struct mutex		state_lock;
436	struct net_device	*pndev[MLX4_MAX_PORTS + 1];
437	u32			port_cnt;
438	bool			device_up;
439	struct mlx4_en_profile	profile;
440	u32			LSO_support;
441	struct workqueue_struct *workqueue;
442	struct device		*dma_device;
443	void __iomem		*uar_map;
444	struct mlx4_uar		priv_uar;
445	struct mlx4_mr		mr;
446	u32			priv_pdn;
447	spinlock_t		uar_lock;
448	u8			mac_removed[MLX4_MAX_PORTS + 1];
449	unsigned long		last_overflow_check;
450	unsigned long		overflow_period;
451};
452
453
454struct mlx4_en_rss_map {
455	int base_qpn;
456	struct mlx4_qp qps[MAX_RX_RINGS];
457	enum mlx4_qp_state state[MAX_RX_RINGS];
458	struct mlx4_qp indir_qp;
459	enum mlx4_qp_state indir_state;
460};
461
462enum mlx4_en_port_flag {
463	MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */
464	MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */
465};
466
467struct mlx4_en_port_state {
468	int link_state;
469	int link_speed;
470	int transceiver;
471	u32 flags;
472};
473
474enum mlx4_en_addr_list_act {
475	MLX4_ADDR_LIST_NONE,
476	MLX4_ADDR_LIST_REM,
477	MLX4_ADDR_LIST_ADD,
478};
479
480struct mlx4_en_addr_list {
481	struct list_head	list;
482	enum mlx4_en_addr_list_act	action;
483	u8			addr[ETH_ALEN];
484	u64			reg_id;
485	u64			tunnel_reg_id;
486};
487
488#ifdef CONFIG_MLX4_EN_DCB
489/* Minimal TC BW - setting to 0 will block traffic */
490#define MLX4_EN_BW_MIN 1
491#define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
492
493#define MLX4_EN_TC_VENDOR 0
494#define MLX4_EN_TC_ETS 7
495
496#endif
497
498
499enum {
500	MLX4_EN_FLAG_PROMISC		= (1 << 0),
501	MLX4_EN_FLAG_MC_PROMISC		= (1 << 1),
502	/* whether we need to enable hardware loopback by putting dmac
503	 * in Tx WQE
504	 */
505	MLX4_EN_FLAG_ENABLE_HW_LOOPBACK	= (1 << 2),
506	/* whether we need to drop packets that hardware loopback-ed */
507	MLX4_EN_FLAG_RX_FILTER_NEEDED	= (1 << 3),
508	MLX4_EN_FLAG_FORCE_PROMISC	= (1 << 4),
509#ifdef CONFIG_MLX4_EN_DCB
510	MLX4_EN_FLAG_DCB_ENABLED	= (1 << 5)
511#endif
512};
513
514#define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
515#define MLX4_EN_MAC_HASH_IDX 5
516
517struct en_port {
518	struct kobject		kobj;
519	struct mlx4_dev		*dev;
520	u8			port_num;
521	u8			vport_num;
522};
523
524struct mlx4_en_priv {
525	struct mlx4_en_dev *mdev;
526	struct mlx4_en_port_profile *prof;
527	struct net_device *dev;
528	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
529	struct mlx4_en_port_state port_state;
530	spinlock_t stats_lock;
531	/* To allow rules removal while port is going down */
532	struct list_head ethtool_list;
533
534	unsigned long last_moder_packets[MAX_RX_RINGS];
535	unsigned long last_moder_tx_packets;
536	unsigned long last_moder_bytes[MAX_RX_RINGS];
537	unsigned long last_moder_jiffies;
538	int last_moder_time[MAX_RX_RINGS];
539	u16 rx_usecs;
540	u16 rx_frames;
541	u16 tx_usecs;
542	u16 tx_frames;
543	u32 pkt_rate_low;
544	u32 rx_usecs_low;
545	u32 pkt_rate_high;
546	u32 rx_usecs_high;
547	u32 sample_interval;
548	u32 adaptive_rx_coal;
549	u32 msg_enable;
550	u32 loopback_ok;
551	u32 validate_loopback;
552
553	struct mlx4_hwq_resources res;
554	int link_state;
555	int last_link_state;
556	bool port_up;
557	int port;
558	int registered;
559	int gone;
560	int allocated;
561	int stride;
562	unsigned char current_mac[ETH_ALEN + 2];
563        u64 mac;
564	int mac_index;
565	unsigned max_mtu;
566	int base_qpn;
567	int cqe_factor;
568
569	struct mlx4_en_rss_map rss_map;
570	u32 flags;
571	u8 num_tx_rings_p_up;
572	u32 tx_ring_num;
573	u32 rx_ring_num;
574	u32 rx_mb_size;
575
576	struct mlx4_en_tx_ring **tx_ring;
577	struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
578	struct mlx4_en_cq **tx_cq;
579	struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
580	struct mlx4_qp drop_qp;
581	struct work_struct rx_mode_task;
582	struct work_struct watchdog_task;
583	struct work_struct linkstate_task;
584	struct delayed_work stats_task;
585	struct delayed_work service_task;
586	struct mlx4_en_perf_stats pstats;
587	struct mlx4_en_pkt_stats pkstats;
588	struct mlx4_en_pkt_stats pkstats_last;
589	struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES];
590	struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES];
591	struct mlx4_en_flow_stats_rx rx_flowstats;
592	struct mlx4_en_flow_stats_tx tx_flowstats;
593	struct mlx4_en_port_stats port_stats;
594	struct mlx4_en_vport_stats vport_stats;
595	struct mlx4_en_vf_stats vf_stats;
596	struct list_head mc_list;
597	struct list_head uc_list;
598	struct list_head curr_mc_list;
599	struct list_head curr_uc_list;
600	u64 broadcast_id;
601	struct mlx4_en_stat_out_mbox hw_stats;
602	int vids[128];
603	bool wol;
604	struct device *ddev;
605	struct dentry *dev_root;
606	u32 counter_index;
607	eventhandler_tag vlan_attach;
608	eventhandler_tag vlan_detach;
609	struct callout watchdog_timer;
610        struct ifmedia media;
611	volatile int blocked;
612	struct sysctl_oid *conf_sysctl;
613	struct sysctl_oid *stat_sysctl;
614	struct sysctl_ctx_list conf_ctx;
615	struct sysctl_ctx_list stat_ctx;
616
617#ifdef CONFIG_MLX4_EN_DCB
618	struct ieee_ets ets;
619	u16 maxrate[IEEE_8021QAZ_MAX_TCS];
620	u8 dcbx_cap;
621#endif
622#ifdef CONFIG_RFS_ACCEL
623	spinlock_t filters_lock;
624	int last_filter_id;
625	struct list_head filters;
626	struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
627#endif
628	u64 tunnel_reg_id;
629	struct en_port *vf_ports[MLX4_MAX_NUM_VF];
630	unsigned long last_ifq_jiffies;
631	u64 if_counters_rx_errors;
632	u64 if_counters_rx_no_buffer;
633};
634
635enum mlx4_en_wol {
636	MLX4_EN_WOL_MAGIC = (1ULL << 61),
637	MLX4_EN_WOL_ENABLED = (1ULL << 62),
638};
639
640struct mlx4_mac_entry {
641	struct hlist_node hlist;
642	unsigned char mac[ETH_ALEN + 2];
643	u64 reg_id;
644};
645
646static inline struct mlx4_cqe *mlx4_en_get_cqe(u8 *buf, int idx, int cqe_sz)
647{
648	return (struct mlx4_cqe *)(buf + idx * cqe_sz);
649}
650
651#ifdef CONFIG_NET_RX_BUSY_POLL
652static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
653{
654	spin_lock_init(&cq->poll_lock);
655	cq->state = MLX4_EN_CQ_STATE_IDLE;
656}
657
658/* called from the device poll rutine to get ownership of a cq */
659static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
660{
661	int rc = true;
662	spin_lock(&cq->poll_lock);
663	if (cq->state & MLX4_CQ_LOCKED) {
664		WARN_ON(cq->state & MLX4_EN_CQ_STATE_NAPI);
665		cq->state |= MLX4_EN_CQ_STATE_NAPI_YIELD;
666		rc = false;
667	} else
668		/* we don't care if someone yielded */
669		cq->state = MLX4_EN_CQ_STATE_NAPI;
670	spin_unlock(&cq->poll_lock);
671	return rc;
672}
673
674/* returns true is someone tried to get the cq while napi had it */
675static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
676{
677	int rc = false;
678	spin_lock(&cq->poll_lock);
679	WARN_ON(cq->state & (MLX4_EN_CQ_STATE_POLL |
680			       MLX4_EN_CQ_STATE_NAPI_YIELD));
681
682	if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
683		rc = true;
684	cq->state = MLX4_EN_CQ_STATE_IDLE;
685	spin_unlock(&cq->poll_lock);
686	return rc;
687}
688
689/* called from mlx4_en_low_latency_poll() */
690static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
691{
692	int rc = true;
693	spin_lock_bh(&cq->poll_lock);
694	if ((cq->state & MLX4_CQ_LOCKED)) {
695		struct net_device *dev = cq->dev;
696		struct mlx4_en_priv *priv = netdev_priv(dev);
697		struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring];
698
699		cq->state |= MLX4_EN_CQ_STATE_POLL_YIELD;
700		rc = false;
701#ifdef LL_EXTENDED_STATS
702		rx_ring->yields++;
703#endif
704	} else
705		/* preserve yield marks */
706		cq->state |= MLX4_EN_CQ_STATE_POLL;
707	spin_unlock_bh(&cq->poll_lock);
708	return rc;
709}
710
711/* returns true if someone tried to get the cq while it was locked */
712static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
713{
714	int rc = false;
715	spin_lock_bh(&cq->poll_lock);
716	WARN_ON(cq->state & (MLX4_EN_CQ_STATE_NAPI));
717
718	if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
719		rc = true;
720	cq->state = MLX4_EN_CQ_STATE_IDLE;
721	spin_unlock_bh(&cq->poll_lock);
722	return rc;
723}
724
725/* true if a socket is polling, even if it did not get the lock */
726static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq)
727{
728	WARN_ON(!(cq->state & MLX4_CQ_LOCKED));
729	return cq->state & CQ_USER_PEND;
730}
731#else
732static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
733{
734}
735
736static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
737{
738	return true;
739}
740
741static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
742{
743	return false;
744}
745
746static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
747{
748	return false;
749}
750
751static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
752{
753	return false;
754}
755
756static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq)
757{
758	return false;
759}
760#endif /* CONFIG_NET_RX_BUSY_POLL */
761
762#define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
763
764void mlx4_en_destroy_netdev(struct net_device *dev);
765int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
766			struct mlx4_en_port_profile *prof);
767
768int mlx4_en_start_port(struct net_device *dev);
769void mlx4_en_stop_port(struct net_device *dev);
770
771void mlx4_en_free_resources(struct mlx4_en_priv *priv);
772int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
773
774int mlx4_en_pre_config(struct mlx4_en_priv *priv);
775int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
776		      int entries, int ring, enum cq_type mode, int node);
777void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
778int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
779			int cq_idx);
780void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
781int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
782int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
783
784void mlx4_en_tx_irq(struct mlx4_cq *mcq);
785u16 mlx4_en_select_queue(struct net_device *dev, struct mbuf *mb);
786
787int mlx4_en_transmit(struct ifnet *dev, struct mbuf *m);
788int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
789			   struct mlx4_en_tx_ring **pring,
790			   u32 size, u16 stride, int node, int queue_idx);
791void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
792			     struct mlx4_en_tx_ring **pring);
793int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
794			     struct mlx4_en_tx_ring *ring,
795			     int cq, int user_prio);
796void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
797				struct mlx4_en_tx_ring *ring);
798void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
799void mlx4_en_qflush(struct ifnet *dev);
800
801int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
802			   struct mlx4_en_rx_ring **pring,
803			   u32 size, int node);
804void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
805			     struct mlx4_en_rx_ring **pring,
806			     u32 size, u16 stride);
807void mlx4_en_rx_que(void *context, int pending);
808int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
809void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
810				struct mlx4_en_rx_ring *ring);
811int mlx4_en_process_rx_cq(struct net_device *dev,
812			  struct mlx4_en_cq *cq,
813			  int budget);
814void mlx4_en_poll_tx_cq(unsigned long data);
815void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
816		int is_tx, int rss, int qpn, int cqn, int user_prio,
817		struct mlx4_qp_context *context);
818void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
819int mlx4_en_map_buffer(struct mlx4_buf *buf);
820void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
821void mlx4_en_calc_rx_buf(struct net_device *dev);
822
823const u32 *mlx4_en_get_rss_key(struct mlx4_en_priv *priv, u16 *keylen);
824u8 mlx4_en_get_rss_mask(struct mlx4_en_priv *priv);
825int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
826void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
827int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
828void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
829int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
830void mlx4_en_rx_irq(struct mlx4_cq *mcq);
831
832int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
833
834int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
835int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
836int mlx4_en_get_vport_stats(struct mlx4_en_dev *mdev, u8 port);
837void mlx4_en_create_debug_files(struct mlx4_en_priv *priv);
838void mlx4_en_delete_debug_files(struct mlx4_en_priv *priv);
839int mlx4_en_register_debugfs(void);
840void mlx4_en_unregister_debugfs(void);
841
842#ifdef CONFIG_MLX4_EN_DCB
843extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
844extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
845#endif
846
847int mlx4_en_setup_tc(struct net_device *dev, u8 up);
848
849#ifdef CONFIG_RFS_ACCEL
850void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv,
851			     struct mlx4_en_rx_ring *rx_ring);
852#endif
853
854#define MLX4_EN_NUM_SELF_TEST	5
855void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
856void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
857
858/*
859 * Functions for time stamping
860 */
861#define SKBTX_HW_TSTAMP (1 << 0)
862#define SKBTX_IN_PROGRESS (1 << 2)
863
864u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
865
866/* Functions for caching and restoring statistics */
867int mlx4_en_get_sset_count(struct net_device *dev, int sset);
868void mlx4_en_restore_ethtool_stats(struct mlx4_en_priv *priv,
869				    u64 *data);
870
871/*
872 * Globals
873 */
874extern const struct ethtool_ops mlx4_en_ethtool_ops;
875
876/*
877 * Defines for link speed - needed by selftest
878 */
879#define MLX4_EN_LINK_SPEED_1G	1000
880#define MLX4_EN_LINK_SPEED_10G	10000
881#define MLX4_EN_LINK_SPEED_40G	40000
882
883enum {
884        NETIF_MSG_DRV           = 0x0001,
885        NETIF_MSG_PROBE         = 0x0002,
886        NETIF_MSG_LINK          = 0x0004,
887        NETIF_MSG_TIMER         = 0x0008,
888        NETIF_MSG_IFDOWN        = 0x0010,
889        NETIF_MSG_IFUP          = 0x0020,
890        NETIF_MSG_RX_ERR        = 0x0040,
891        NETIF_MSG_TX_ERR        = 0x0080,
892        NETIF_MSG_TX_QUEUED     = 0x0100,
893        NETIF_MSG_INTR          = 0x0200,
894        NETIF_MSG_TX_DONE       = 0x0400,
895        NETIF_MSG_RX_STATUS     = 0x0800,
896        NETIF_MSG_PKTDATA       = 0x1000,
897        NETIF_MSG_HW            = 0x2000,
898        NETIF_MSG_WOL           = 0x4000,
899};
900
901
902/*
903 * printk / logging functions
904 */
905
906#define en_print(level, priv, format, arg...)                   \
907        {                                                       \
908        if ((priv)->registered)                                 \
909                printk(level "%s: %s: " format, DRV_NAME,       \
910                        (priv)->dev->if_xname, ## arg); \
911        else                                                    \
912                printk(level "%s: %s: Port %d: " format,        \
913                        DRV_NAME, dev_name(&(priv)->mdev->pdev->dev), \
914                        (priv)->port, ## arg);                  \
915        }
916
917
918#define en_dbg(mlevel, priv, format, arg...)			\
919do {								\
920	if (NETIF_MSG_##mlevel & priv->msg_enable)		\
921		en_print(KERN_DEBUG, priv, format, ##arg);	\
922} while (0)
923#define en_warn(priv, format, arg...)			\
924	en_print(KERN_WARNING, priv, format, ##arg)
925#define en_err(priv, format, arg...)			\
926	en_print(KERN_ERR, priv, format, ##arg)
927#define en_info(priv, format, arg...)			\
928	en_print(KERN_INFO, priv, format, ## arg)
929
930#define mlx4_err(mdev, format, arg...)			\
931	pr_err("%s %s: " format, DRV_NAME,		\
932	       dev_name(&(mdev)->pdev->dev), ##arg)
933#define mlx4_info(mdev, format, arg...)			\
934	pr_info("%s %s: " format, DRV_NAME,		\
935		dev_name(&(mdev)->pdev->dev), ##arg)
936#define mlx4_warn(mdev, format, arg...)			\
937	pr_warning("%s %s: " format, DRV_NAME,		\
938		   dev_name(&(mdev)->pdev->dev), ##arg)
939
940#endif
941