device.h revision 331769
1/* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33#ifndef MLX4_DEVICE_H 34#define MLX4_DEVICE_H 35 36#include <linux/pci.h> 37#include <linux/completion.h> 38#include <linux/radix-tree.h> 39#include <linux/types.h> 40#include <linux/bitops.h> 41#include <linux/workqueue.h> 42#include <linux/if_ether.h> 43#include <linux/mutex.h> 44 45#include <asm/atomic.h> 46 47#include <linux/clocksource.h> 48 49#define DEFAULT_UAR_PAGE_SHIFT 12 50 51#define MAX_MSIX_P_PORT 17 52#define MAX_MSIX 64 53#define MIN_MSIX_P_PORT 5 54#define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \ 55 (dev_cap).num_ports * MIN_MSIX_P_PORT) 56 57#define MLX4_MAX_100M_UNITS_VAL 255 /* 58 * work around: can't set values 59 * greater then this value when 60 * using 100 Mbps units. 61 */ 62#define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */ 63#define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */ 64#define MLX4_RATELIMIT_DEFAULT 0x00ff 65 66#define MLX4_ROCE_MAX_GIDS 128 67#define MLX4_ROCE_PF_GIDS 16 68 69#define CORE_CLOCK_MASK 0xffffffffffffULL 70 71enum { 72 MLX4_FLAG_MSI_X = 1 << 0, 73 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 74 MLX4_FLAG_MASTER = 1 << 2, 75 MLX4_FLAG_SLAVE = 1 << 3, 76 MLX4_FLAG_SRIOV = 1 << 4, 77 MLX4_FLAG_OLD_REG_MAC = 1 << 6, 78 MLX4_FLAG_BONDED = 1 << 7, 79 MLX4_FLAG_SECURE_HOST = 1 << 8, 80}; 81 82enum { 83 MLX4_PORT_CAP_IS_SM = 1 << 1, 84 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, 85}; 86 87enum { 88 MLX4_MAX_PORTS = 2, 89 MLX4_MAX_PORT_PKEYS = 128, 90 MLX4_MAX_PORT_GIDS = 128 91}; 92 93/* base qkey for use in sriov tunnel-qp/proxy-qp communication. 94 * These qkeys must not be allowed for general use. This is a 64k range, 95 * and to test for violation, we use the mask (protect against future chg). 96 */ 97#define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) 98#define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) 99 100enum { 101 MLX4_BOARD_ID_LEN = 64 102}; 103 104enum { 105 MLX4_MAX_NUM_PF = 16, 106 MLX4_MAX_NUM_VF = 126, 107 MLX4_MAX_NUM_VF_P_PORT = 64, 108 MLX4_MFUNC_MAX = 128, 109 MLX4_MAX_EQ_NUM = 1024, 110 MLX4_MFUNC_EQ_NUM = 4, 111 MLX4_MFUNC_MAX_EQES = 8, 112 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) 113}; 114 115/* Driver supports 3 different device methods to manage traffic steering: 116 * -device managed - High level API for ib and eth flow steering. FW is 117 * managing flow steering tables. 118 * - B0 steering mode - Common low level API for ib and (if supported) eth. 119 * - A0 steering mode - Limited low level API for eth. In case of IB, 120 * B0 mode is in use. 121 */ 122enum { 123 MLX4_STEERING_MODE_A0, 124 MLX4_STEERING_MODE_B0, 125 MLX4_STEERING_MODE_DEVICE_MANAGED 126}; 127 128enum { 129 MLX4_STEERING_DMFS_A0_DEFAULT, 130 MLX4_STEERING_DMFS_A0_DYNAMIC, 131 MLX4_STEERING_DMFS_A0_STATIC, 132 MLX4_STEERING_DMFS_A0_DISABLE, 133 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED 134}; 135 136static inline const char *mlx4_steering_mode_str(int steering_mode) 137{ 138 switch (steering_mode) { 139 case MLX4_STEERING_MODE_A0: 140 return "A0 steering"; 141 142 case MLX4_STEERING_MODE_B0: 143 return "B0 steering"; 144 145 case MLX4_STEERING_MODE_DEVICE_MANAGED: 146 return "Device managed flow steering"; 147 148 default: 149 return "Unrecognize steering mode"; 150 } 151} 152 153enum { 154 MLX4_TUNNEL_OFFLOAD_MODE_NONE, 155 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN 156}; 157 158enum { 159 MLX4_DEV_CAP_FLAG_RC = 1LL << 0, 160 MLX4_DEV_CAP_FLAG_UC = 1LL << 1, 161 MLX4_DEV_CAP_FLAG_UD = 1LL << 2, 162 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, 163 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, 164 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, 165 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 166 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 167 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, 168 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, 169 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, 170 MLX4_DEV_CAP_FLAG_APM = 1LL << 17, 171 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 172 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, 173 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, 174 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, 175 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, 176 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, 177 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, 178 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, 179 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, 180 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, 181 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, 182 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, 183 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, 184 MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52, 185 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53, 186 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, 187 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, 188 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, 189 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 190}; 191 192enum { 193 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, 194 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, 195 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, 196 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, 197 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4, 198 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, 199 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, 200 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, 201 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8, 202 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9, 203 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10, 204 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11, 205 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12, 206 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13, 207 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14, 208 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15, 209 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16, 210 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17, 211 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18, 212 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19, 213 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20, 214 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21, 215 MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22, 216 MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23, 217 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24, 218 MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25, 219 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26, 220 MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27, 221 MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28, 222 MLX4_DEV_CAP_FLAG2_PHV_EN = 1LL << 29, 223 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN = 1LL << 30, 224 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1ULL << 31, 225 MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1ULL << 32, 226 MLX4_DEV_CAP_FLAG2_ROCE_V1_V2 = 1ULL << 33, 227 MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER = 1ULL << 34, 228 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT = 1ULL << 35, 229 MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP = 1ULL << 36, 230 MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT = 1ULL << 37, 231}; 232 233enum { 234 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0, 235 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1 236}; 237 238enum { 239 MLX4_VF_CAP_FLAG_RESET = 1 << 0 240}; 241 242/* bit enums for an 8-bit flags field indicating special use 243 * QPs which require special handling in qp_reserve_range. 244 * Currently, this only includes QPs used by the ETH interface, 245 * where we expect to use blueflame. These QPs must not have 246 * bits 6 and 7 set in their qp number. 247 * 248 * This enum may use only bits 0..7. 249 */ 250enum { 251 MLX4_RESERVE_A0_QP = 1 << 6, 252 MLX4_RESERVE_ETH_BF_QP = 1 << 7, 253}; 254 255enum { 256 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, 257 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1, 258 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2, 259 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3 260}; 261 262enum { 263 MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0 264}; 265 266enum { 267 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0, 268 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1, 269 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2 270}; 271 272 273#define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 274 275enum { 276 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, 277 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, 278 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, 279 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 280 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 281 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 282 MLX4_BMME_FLAG_ROCE_V1_V2 = 1 << 19, 283 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24, 284 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28, 285}; 286 287enum { 288 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP, 289 MLX4_FLAG_ROCE_V1_V2 = MLX4_BMME_FLAG_ROCE_V1_V2 290}; 291 292enum mlx4_event { 293 MLX4_EVENT_TYPE_COMP = 0x00, 294 MLX4_EVENT_TYPE_PATH_MIG = 0x01, 295 MLX4_EVENT_TYPE_COMM_EST = 0x02, 296 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 297 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 298 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 299 MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 300 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 301 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 302 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 303 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 304 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 305 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 306 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 307 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 308 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 309 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 310 MLX4_EVENT_TYPE_CMD = 0x0a, 311 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, 312 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, 313 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, 314 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, 315 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, 316 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, 317 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e, 318 MLX4_EVENT_TYPE_NONE = 0xff, 319}; 320 321enum { 322 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, 323 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 324}; 325 326enum { 327 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1, 328 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2, 329}; 330 331enum { 332 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, 333}; 334 335enum slave_port_state { 336 SLAVE_PORT_DOWN = 0, 337 SLAVE_PENDING_UP, 338 SLAVE_PORT_UP, 339}; 340 341enum slave_port_gen_event { 342 SLAVE_PORT_GEN_EVENT_DOWN = 0, 343 SLAVE_PORT_GEN_EVENT_UP, 344 SLAVE_PORT_GEN_EVENT_NONE, 345}; 346 347enum slave_port_state_event { 348 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 349 MLX4_PORT_STATE_DEV_EVENT_PORT_UP, 350 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, 351 MLX4_PORT_STATE_IB_EVENT_GID_INVALID, 352}; 353 354enum { 355 MLX4_PERM_LOCAL_READ = 1 << 10, 356 MLX4_PERM_LOCAL_WRITE = 1 << 11, 357 MLX4_PERM_REMOTE_READ = 1 << 12, 358 MLX4_PERM_REMOTE_WRITE = 1 << 13, 359 MLX4_PERM_ATOMIC = 1 << 14, 360 MLX4_PERM_BIND_MW = 1 << 15, 361 MLX4_PERM_MASK = 0xFC00 362}; 363 364enum { 365 MLX4_OPCODE_NOP = 0x00, 366 MLX4_OPCODE_SEND_INVAL = 0x01, 367 MLX4_OPCODE_RDMA_WRITE = 0x08, 368 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 369 MLX4_OPCODE_SEND = 0x0a, 370 MLX4_OPCODE_SEND_IMM = 0x0b, 371 MLX4_OPCODE_LSO = 0x0e, 372 MLX4_OPCODE_RDMA_READ = 0x10, 373 MLX4_OPCODE_ATOMIC_CS = 0x11, 374 MLX4_OPCODE_ATOMIC_FA = 0x12, 375 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, 376 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, 377 MLX4_OPCODE_BIND_MW = 0x18, 378 MLX4_OPCODE_FMR = 0x19, 379 MLX4_OPCODE_LOCAL_INVAL = 0x1b, 380 MLX4_OPCODE_CONFIG_CMD = 0x1f, 381 382 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 383 MLX4_RECV_OPCODE_SEND = 0x01, 384 MLX4_RECV_OPCODE_SEND_IMM = 0x02, 385 MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 386 387 MLX4_CQE_OPCODE_ERROR = 0x1e, 388 MLX4_CQE_OPCODE_RESIZE = 0x16, 389}; 390 391enum { 392 MLX4_STAT_RATE_OFFSET = 5 393}; 394 395enum mlx4_protocol { 396 MLX4_PROT_IB_IPV6 = 0, 397 MLX4_PROT_ETH, 398 MLX4_PROT_IB_IPV4, 399 MLX4_PROT_FCOE 400}; 401 402enum { 403 MLX4_MTT_FLAG_PRESENT = 1 404}; 405 406enum mlx4_qp_region { 407 MLX4_QP_REGION_FW = 0, 408 MLX4_QP_REGION_RSS_RAW_ETH, 409 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH, 410 MLX4_QP_REGION_ETH_ADDR, 411 MLX4_QP_REGION_FC_ADDR, 412 MLX4_QP_REGION_FC_EXCH, 413 MLX4_NUM_QP_REGION 414}; 415 416enum mlx4_port_type { 417 MLX4_PORT_TYPE_NONE = 0, 418 MLX4_PORT_TYPE_IB = 1, 419 MLX4_PORT_TYPE_ETH = 2, 420 MLX4_PORT_TYPE_AUTO = 3 421}; 422 423enum mlx4_special_vlan_idx { 424 MLX4_NO_VLAN_IDX = 0, 425 MLX4_VLAN_MISS_IDX, 426 MLX4_VLAN_REGULAR 427}; 428 429enum mlx4_steer_type { 430 MLX4_MC_STEER = 0, 431 MLX4_UC_STEER, 432 MLX4_NUM_STEERS 433}; 434 435enum { 436 MLX4_NUM_FEXCH = 64 * 1024, 437}; 438 439enum { 440 MLX4_MAX_FAST_REG_PAGES = 511, 441}; 442 443enum { 444 /* 445 * Max wqe size for rdma read is 512 bytes, so this 446 * limits our max_sge_rd as the wqe needs to fit: 447 * - ctrl segment (16 bytes) 448 * - rdma segment (16 bytes) 449 * - scatter elements (16 bytes each) 450 */ 451 MLX4_MAX_SGE_RD = (512 - 16 - 16) / 16 452}; 453 454enum { 455 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, 456 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, 457 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, 458 MLX4_DEV_PMC_SUBTYPE_SL_TO_VL_MAP = 0x17, 459}; 460 461/* Port mgmt change event handling */ 462enum { 463 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, 464 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, 465 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, 466 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, 467 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, 468}; 469 470union sl2vl_tbl_to_u64 { 471 u8 sl8[8]; 472 u64 sl64; 473}; 474 475enum { 476 MLX4_DEVICE_STATE_UP = 1 << 0, 477 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1, 478}; 479 480enum { 481 MLX4_INTERFACE_STATE_UP = 1 << 0, 482 MLX4_INTERFACE_STATE_DELETION = 1 << 1, 483}; 484 485#define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ 486 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) 487 488enum mlx4_module_id { 489 MLX4_MODULE_ID_SFP = 0x3, 490 MLX4_MODULE_ID_QSFP = 0xC, 491 MLX4_MODULE_ID_QSFP_PLUS = 0xD, 492 MLX4_MODULE_ID_QSFP28 = 0x11, 493}; 494 495enum { /* rl */ 496 MLX4_QP_RATE_LIMIT_NONE = 0, 497 MLX4_QP_RATE_LIMIT_KBS = 1, 498 MLX4_QP_RATE_LIMIT_MBS = 2, 499 MLX4_QP_RATE_LIMIT_GBS = 3 500}; 501 502struct mlx4_rate_limit_caps { 503 u16 num_rates; /* Number of different rates */ 504 u8 min_unit; 505 u16 min_val; 506 u8 max_unit; 507 u16 max_val; 508}; 509 510static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) 511{ 512 return (major << 32) | (minor << 16) | subminor; 513} 514 515struct mlx4_phys_caps { 516 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; 517 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; 518 u32 num_phys_eqs; 519 u32 base_sqpn; 520 u32 base_proxy_sqpn; 521 u32 base_tunnel_sqpn; 522}; 523 524struct mlx4_caps { 525 u64 fw_ver; 526 u32 function; 527 int num_ports; 528 int vl_cap[MLX4_MAX_PORTS + 1]; 529 int ib_mtu_cap[MLX4_MAX_PORTS + 1]; 530 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; 531 u64 def_mac[MLX4_MAX_PORTS + 1]; 532 int eth_mtu_cap[MLX4_MAX_PORTS + 1]; 533 int gid_table_len[MLX4_MAX_PORTS + 1]; 534 int pkey_table_len[MLX4_MAX_PORTS + 1]; 535 int trans_type[MLX4_MAX_PORTS + 1]; 536 int vendor_oui[MLX4_MAX_PORTS + 1]; 537 int wavelength[MLX4_MAX_PORTS + 1]; 538 u64 trans_code[MLX4_MAX_PORTS + 1]; 539 int local_ca_ack_delay; 540 int num_uars; 541 u32 uar_page_size; 542 int bf_reg_size; 543 int bf_regs_per_page; 544 int max_sq_sg; 545 int max_rq_sg; 546 int num_qps; 547 int max_wqes; 548 int max_sq_desc_sz; 549 int max_rq_desc_sz; 550 int max_qp_init_rdma; 551 int max_qp_dest_rdma; 552 int max_tc_eth; 553 u32 *qp0_qkey; 554 u32 *qp0_proxy; 555 u32 *qp1_proxy; 556 u32 *qp0_tunnel; 557 u32 *qp1_tunnel; 558 int num_srqs; 559 int max_srq_wqes; 560 int max_srq_sge; 561 int reserved_srqs; 562 int num_cqs; 563 int max_cqes; 564 int reserved_cqs; 565 int num_sys_eqs; 566 int num_eqs; 567 int reserved_eqs; 568 int num_comp_vectors; 569 int num_mpts; 570 int max_fmr_maps; 571 int num_mtts; 572 int fmr_reserved_mtts; 573 int reserved_mtts; 574 int reserved_mrws; 575 int reserved_uars; 576 int num_mgms; 577 int num_amgms; 578 int reserved_mcgs; 579 int num_qp_per_mgm; 580 int steering_mode; 581 int dmfs_high_steer_mode; 582 int fs_log_max_ucast_qp_range_size; 583 int num_pds; 584 int reserved_pds; 585 int max_xrcds; 586 int reserved_xrcds; 587 int mtt_entry_sz; 588 u32 max_msg_sz; 589 u32 page_size_cap; 590 u64 flags; 591 u64 flags2; 592 u32 bmme_flags; 593 u32 reserved_lkey; 594 u16 stat_rate_support; 595 u8 port_width_cap[MLX4_MAX_PORTS + 1]; 596 int max_gso_sz; 597 int max_rss_tbl_sz; 598 int reserved_qps_cnt[MLX4_NUM_QP_REGION]; 599 int reserved_qps; 600 int reserved_qps_base[MLX4_NUM_QP_REGION]; 601 int log_num_macs; 602 int log_num_vlans; 603 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 604 u8 supported_type[MLX4_MAX_PORTS + 1]; 605 u8 suggested_type[MLX4_MAX_PORTS + 1]; 606 u8 default_sense[MLX4_MAX_PORTS + 1]; 607 u32 port_mask[MLX4_MAX_PORTS + 1]; 608 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; 609 u32 max_counters; 610 u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; 611 u16 sqp_demux; 612 u32 eqe_size; 613 u32 cqe_size; 614 u8 eqe_factor; 615 u32 userspace_caps; /* userspace must be aware of these */ 616 u32 function_caps; /* VFs must be aware of these */ 617 u16 hca_core_clock; 618 u64 phys_port_id[MLX4_MAX_PORTS + 1]; 619 int tunnel_offload_mode; 620 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1]; 621 u8 phv_bit[MLX4_MAX_PORTS + 1]; 622 u8 alloc_res_qp_mask; 623 u32 dmfs_high_rate_qpn_base; 624 u32 dmfs_high_rate_qpn_range; 625 u32 vf_caps; 626 struct mlx4_rate_limit_caps rl_caps; 627}; 628 629struct mlx4_buf_list { 630 void *buf; 631 dma_addr_t map; 632}; 633 634struct mlx4_buf { 635 struct mlx4_buf_list direct; 636 struct mlx4_buf_list *page_list; 637 int nbufs; 638 int npages; 639 int page_shift; 640}; 641 642struct mlx4_mtt { 643 u32 offset; 644 int order; 645 int page_shift; 646}; 647 648enum { 649 MLX4_DB_PER_PAGE = PAGE_SIZE / 4 650}; 651 652struct mlx4_db_pgdir { 653 struct list_head list; 654 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); 655 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); 656 unsigned long *bits[2]; 657 __be32 *db_page; 658 dma_addr_t db_dma; 659}; 660 661struct mlx4_ib_user_db_page; 662 663struct mlx4_db { 664 __be32 *db; 665 union { 666 struct mlx4_db_pgdir *pgdir; 667 struct mlx4_ib_user_db_page *user_page; 668 } u; 669 dma_addr_t dma; 670 int index; 671 int order; 672}; 673 674struct mlx4_hwq_resources { 675 struct mlx4_db db; 676 struct mlx4_mtt mtt; 677 struct mlx4_buf buf; 678}; 679 680struct mlx4_mr { 681 struct mlx4_mtt mtt; 682 u64 iova; 683 u64 size; 684 u32 key; 685 u32 pd; 686 u32 access; 687 int enabled; 688}; 689 690enum mlx4_mw_type { 691 MLX4_MW_TYPE_1 = 1, 692 MLX4_MW_TYPE_2 = 2, 693}; 694 695struct mlx4_mw { 696 u32 key; 697 u32 pd; 698 enum mlx4_mw_type type; 699 int enabled; 700}; 701 702struct mlx4_fmr { 703 struct mlx4_mr mr; 704 struct mlx4_mpt_entry *mpt; 705 __be64 *mtts; 706 dma_addr_t dma_handle; 707 int max_pages; 708 int max_maps; 709 int maps; 710 u8 page_shift; 711}; 712 713struct mlx4_uar { 714 unsigned long pfn; 715 int index; 716 struct list_head bf_list; 717 unsigned free_bf_bmap; 718 void __iomem *map; 719 void __iomem *bf_map; 720}; 721 722struct mlx4_bf { 723 unsigned int offset; 724 int buf_size; 725 struct mlx4_uar *uar; 726 void __iomem *reg; 727}; 728 729struct mlx4_cq { 730 void (*comp) (struct mlx4_cq *); 731 void (*event) (struct mlx4_cq *, enum mlx4_event); 732 733 struct mlx4_uar *uar; 734 735 u32 cons_index; 736 737 u16 irq; 738 __be32 *set_ci_db; 739 __be32 *arm_db; 740 int arm_sn; 741 742 int cqn; 743 unsigned vector; 744 745 atomic_t refcount; 746 struct completion free; 747 int reset_notify_added; 748 struct list_head reset_notify; 749}; 750 751struct mlx4_qp { 752 void (*event) (struct mlx4_qp *, enum mlx4_event); 753 754 int qpn; 755 756 atomic_t refcount; 757 struct completion free; 758}; 759 760struct mlx4_srq { 761 void (*event) (struct mlx4_srq *, enum mlx4_event); 762 763 int srqn; 764 int max; 765 int max_gs; 766 int wqe_shift; 767 768 atomic_t refcount; 769 struct completion free; 770}; 771 772struct mlx4_av { 773 __be32 port_pd; 774 u8 reserved1; 775 u8 g_slid; 776 __be16 dlid; 777 u8 reserved2; 778 u8 gid_index; 779 u8 stat_rate; 780 u8 hop_limit; 781 __be32 sl_tclass_flowlabel; 782 u8 dgid[16]; 783}; 784 785struct mlx4_eth_av { 786 __be32 port_pd; 787 u8 reserved1; 788 u8 smac_idx; 789 u16 reserved2; 790 u8 reserved3; 791 u8 gid_index; 792 u8 stat_rate; 793 u8 hop_limit; 794 __be32 sl_tclass_flowlabel; 795 u8 dgid[16]; 796 u8 s_mac[6]; 797 u8 reserved4[2]; 798 __be16 vlan; 799 u8 mac[ETH_ALEN]; 800}; 801 802union mlx4_ext_av { 803 struct mlx4_av ib; 804 struct mlx4_eth_av eth; 805}; 806 807/* Counters should be saturate once they reach their maximum value */ 808#define ASSIGN_32BIT_COUNTER(counter, value) do { \ 809 if ((value) > U32_MAX) \ 810 counter = cpu_to_be32(U32_MAX); \ 811 else \ 812 counter = cpu_to_be32(value); \ 813} while (0) 814 815struct mlx4_counter { 816 u8 reserved1[3]; 817 u8 counter_mode; 818 __be32 num_ifc; 819 u32 reserved2[2]; 820 __be64 rx_frames; 821 __be64 rx_bytes; 822 __be64 tx_frames; 823 __be64 tx_bytes; 824}; 825 826struct mlx4_quotas { 827 int qp; 828 int cq; 829 int srq; 830 int mpt; 831 int mtt; 832 int counter; 833 int xrcd; 834}; 835 836struct mlx4_vf_dev { 837 u8 min_port; 838 u8 n_ports; 839}; 840 841enum mlx4_pci_status { 842 MLX4_PCI_STATUS_DISABLED, 843 MLX4_PCI_STATUS_ENABLED, 844}; 845 846struct mlx4_dev_persistent { 847 struct pci_dev *pdev; 848 struct mlx4_dev *dev; 849 int nvfs[MLX4_MAX_PORTS + 1]; 850 int num_vfs; 851 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1]; 852 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1]; 853 struct work_struct catas_work; 854 struct workqueue_struct *catas_wq; 855 struct mutex device_state_mutex; /* protect HW state */ 856 u8 state; 857 struct mutex interface_state_mutex; /* protect SW state */ 858 u8 interface_state; 859 struct mutex pci_status_mutex; /* sync pci state */ 860 enum mlx4_pci_status pci_status; 861}; 862 863struct mlx4_dev { 864 struct mlx4_dev_persistent *persist; 865 unsigned long flags; 866 unsigned long num_slaves; 867 struct mlx4_caps caps; 868 struct mlx4_phys_caps phys_caps; 869 struct mlx4_quotas quotas; 870 struct radix_tree_root qp_table_tree; 871 u8 rev_id; 872 u8 port_random_macs; 873 char board_id[MLX4_BOARD_ID_LEN]; 874 int numa_node; 875 int oper_log_mgm_entry_size; 876 u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; 877 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; 878 struct mlx4_vf_dev *dev_vfs; 879 u8 uar_page_shift; 880}; 881 882struct mlx4_clock_params { 883 u64 offset; 884 u8 bar; 885 u8 size; 886}; 887 888struct mlx4_eqe { 889 u8 reserved1; 890 u8 type; 891 u8 reserved2; 892 u8 subtype; 893 union { 894 u32 raw[6]; 895 struct { 896 __be32 cqn; 897 } __packed comp; 898 struct { 899 u16 reserved1; 900 __be16 token; 901 u32 reserved2; 902 u8 reserved3[3]; 903 u8 status; 904 __be64 out_param; 905 } __packed cmd; 906 struct { 907 __be32 qpn; 908 } __packed qp; 909 struct { 910 __be32 srqn; 911 } __packed srq; 912 struct { 913 __be32 cqn; 914 u32 reserved1; 915 u8 reserved2[3]; 916 u8 syndrome; 917 } __packed cq_err; 918 struct { 919 u32 reserved1[2]; 920 __be32 port; 921 } __packed port_change; 922 struct { 923 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 924 u32 reserved; 925 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; 926 } __packed comm_channel_arm; 927 struct { 928 u8 port; 929 u8 reserved[3]; 930 __be64 mac; 931 } __packed mac_update; 932 struct { 933 __be32 slave_id; 934 } __packed flr_event; 935 struct { 936 __be16 current_temperature; 937 __be16 warning_threshold; 938 } __packed warming; 939 struct { 940 u8 reserved[3]; 941 u8 port; 942 union { 943 struct { 944 __be16 mstr_sm_lid; 945 __be16 port_lid; 946 __be32 changed_attr; 947 u8 reserved[3]; 948 u8 mstr_sm_sl; 949 __be64 gid_prefix; 950 } __packed port_info; 951 struct { 952 __be32 block_ptr; 953 __be32 tbl_entries_mask; 954 } __packed tbl_change_info; 955 struct { 956 u8 sl2vl_table[8]; 957 } __packed sl2vl_tbl_change_info; 958 } params; 959 } __packed port_mgmt_change; 960 struct { 961 u8 reserved[3]; 962 u8 port; 963 u32 reserved1[5]; 964 } __packed bad_cable; 965 } event; 966 u8 slave_id; 967 u8 reserved3[2]; 968 u8 owner; 969} __packed; 970 971struct mlx4_init_port_param { 972 int set_guid0; 973 int set_node_guid; 974 int set_si_guid; 975 u16 mtu; 976 int port_width_cap; 977 u16 vl_cap; 978 u16 max_gid; 979 u16 max_pkey; 980 u64 guid0; 981 u64 node_guid; 982 u64 si_guid; 983}; 984 985#define MAD_IFC_DATA_SZ 192 986/* MAD IFC Mailbox */ 987struct mlx4_mad_ifc { 988 u8 base_version; 989 u8 mgmt_class; 990 u8 class_version; 991 u8 method; 992 __be16 status; 993 __be16 class_specific; 994 __be64 tid; 995 __be16 attr_id; 996 __be16 resv; 997 __be32 attr_mod; 998 __be64 mkey; 999 __be16 dr_slid; 1000 __be16 dr_dlid; 1001 u8 reserved[28]; 1002 u8 data[MAD_IFC_DATA_SZ]; 1003} __packed; 1004 1005#define mlx4_foreach_port(port, dev, type) \ 1006 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 1007 if ((type) == (dev)->caps.port_mask[(port)]) 1008 1009#define mlx4_foreach_ib_transport_port(port, dev) \ 1010 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 1011 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ 1012 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) || \ 1013 ((dev)->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)) 1014 1015#define MLX4_INVALID_SLAVE_ID 0xFF 1016#define MLX4_SINK_COUNTER_INDEX(dev) (dev->caps.max_counters - 1) 1017 1018void handle_port_mgmt_change_event(struct work_struct *work); 1019 1020static inline int mlx4_master_func_num(struct mlx4_dev *dev) 1021{ 1022 return dev->caps.function; 1023} 1024 1025static inline int mlx4_is_master(struct mlx4_dev *dev) 1026{ 1027 return dev->flags & MLX4_FLAG_MASTER; 1028} 1029 1030static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev) 1031{ 1032 return dev->phys_caps.base_sqpn + 8 + 1033 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev); 1034} 1035 1036static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) 1037{ 1038 return (qpn < dev->phys_caps.base_sqpn + 8 + 1039 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) && 1040 qpn >= dev->phys_caps.base_sqpn) || 1041 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]); 1042} 1043 1044static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) 1045{ 1046 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; 1047 1048 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) 1049 return 1; 1050 1051 return 0; 1052} 1053 1054static inline int mlx4_is_mfunc(struct mlx4_dev *dev) 1055{ 1056 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); 1057} 1058 1059static inline int mlx4_is_slave(struct mlx4_dev *dev) 1060{ 1061 return dev->flags & MLX4_FLAG_SLAVE; 1062} 1063 1064static inline int mlx4_is_eth(struct mlx4_dev *dev, int port) 1065{ 1066 return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1; 1067} 1068 1069int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 1070 struct mlx4_buf *buf, gfp_t gfp); 1071void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 1072static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) 1073{ 1074 if (BITS_PER_LONG == 64 || buf->nbufs == 1) 1075 return (u8 *)buf->direct.buf + offset; 1076 else 1077 return (u8 *)buf->page_list[offset >> PAGE_SHIFT].buf + 1078 (offset & (PAGE_SIZE - 1)); 1079} 1080 1081int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 1082void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 1083int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 1084void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 1085 1086int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 1087void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 1088int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); 1089void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); 1090 1091int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 1092 struct mlx4_mtt *mtt); 1093void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1094u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 1095 1096int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 1097 int npages, int page_shift, struct mlx4_mr *mr); 1098int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 1099int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 1100int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, 1101 struct mlx4_mw *mw); 1102void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); 1103int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); 1104int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1105 int start_index, int npages, u64 *page_list); 1106int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1107 struct mlx4_buf *buf, gfp_t gfp); 1108 1109int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order, 1110 gfp_t gfp); 1111void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); 1112 1113int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 1114 int size, int max_direct); 1115void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, 1116 int size); 1117 1118int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 1119 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, 1120 unsigned vector, int collapsed, int timestamp_en); 1121void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 1122int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 1123 int *base, u8 flags); 1124void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 1125 1126int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp, 1127 gfp_t gfp); 1128void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 1129 1130int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, 1131 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); 1132void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 1133int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 1134int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 1135 1136int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 1137int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 1138 1139int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1140 int block_mcast_loopback, enum mlx4_protocol prot); 1141int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1142 enum mlx4_protocol prot); 1143int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1144 u8 port, int block_mcast_loopback, 1145 enum mlx4_protocol protocol, u64 *reg_id); 1146int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1147 enum mlx4_protocol protocol, u64 reg_id); 1148 1149enum { 1150 MLX4_DOMAIN_UVERBS = 0x1000, 1151 MLX4_DOMAIN_ETHTOOL = 0x2000, 1152 MLX4_DOMAIN_RFS = 0x3000, 1153 MLX4_DOMAIN_NIC = 0x5000, 1154}; 1155 1156enum mlx4_net_trans_rule_id { 1157 MLX4_NET_TRANS_RULE_ID_ETH = 0, 1158 MLX4_NET_TRANS_RULE_ID_IB, 1159 MLX4_NET_TRANS_RULE_ID_IPV6, 1160 MLX4_NET_TRANS_RULE_ID_IPV4, 1161 MLX4_NET_TRANS_RULE_ID_TCP, 1162 MLX4_NET_TRANS_RULE_ID_UDP, 1163 MLX4_NET_TRANS_RULE_ID_VXLAN, 1164 MLX4_NET_TRANS_RULE_NUM, /* should be last */ 1165 MLX4_NET_TRANS_RULE_DUMMY = -1, /* force enum to be signed */ 1166}; 1167 1168extern const u16 __sw_id_hw[]; 1169 1170static inline int map_hw_to_sw_id(u16 header_id) 1171{ 1172 1173 int i; 1174 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { 1175 if (header_id == __sw_id_hw[i]) 1176 return i; 1177 } 1178 return -EINVAL; 1179} 1180 1181enum mlx4_net_trans_promisc_mode { 1182 MLX4_FS_REGULAR = 1, 1183 MLX4_FS_ALL_DEFAULT, 1184 MLX4_FS_MC_DEFAULT, 1185 MLX4_FS_MIRROR_RX_PORT, 1186 MLX4_FS_MIRROR_SX_PORT, 1187 MLX4_FS_UC_SNIFFER, 1188 MLX4_FS_MC_SNIFFER, 1189 MLX4_FS_MODE_NUM, /* should be last */ 1190 MLX4_FS_MODE_DUMMY = -1, /* force enum to be signed */ 1191}; 1192 1193struct mlx4_spec_eth { 1194 u8 dst_mac[ETH_ALEN]; 1195 u8 dst_mac_msk[ETH_ALEN]; 1196 u8 src_mac[ETH_ALEN]; 1197 u8 src_mac_msk[ETH_ALEN]; 1198 u8 ether_type_enable; 1199 __be16 ether_type; 1200 __be16 vlan_id_msk; 1201 __be16 vlan_id; 1202}; 1203 1204struct mlx4_spec_tcp_udp { 1205 __be16 dst_port; 1206 __be16 dst_port_msk; 1207 __be16 src_port; 1208 __be16 src_port_msk; 1209}; 1210 1211struct mlx4_spec_ipv4 { 1212 __be32 dst_ip; 1213 __be32 dst_ip_msk; 1214 __be32 src_ip; 1215 __be32 src_ip_msk; 1216}; 1217 1218struct mlx4_spec_ib { 1219 __be32 l3_qpn; 1220 __be32 qpn_msk; 1221 u8 dst_gid[16]; 1222 u8 dst_gid_msk[16]; 1223}; 1224 1225struct mlx4_spec_vxlan { 1226 __be32 vni; 1227 __be32 vni_mask; 1228 1229}; 1230 1231struct mlx4_spec_list { 1232 struct list_head list; 1233 enum mlx4_net_trans_rule_id id; 1234 union { 1235 struct mlx4_spec_eth eth; 1236 struct mlx4_spec_ib ib; 1237 struct mlx4_spec_ipv4 ipv4; 1238 struct mlx4_spec_tcp_udp tcp_udp; 1239 struct mlx4_spec_vxlan vxlan; 1240 }; 1241}; 1242 1243enum mlx4_net_trans_hw_rule_queue { 1244 MLX4_NET_TRANS_Q_FIFO, 1245 MLX4_NET_TRANS_Q_LIFO, 1246}; 1247 1248struct mlx4_net_trans_rule { 1249 struct list_head list; 1250 enum mlx4_net_trans_hw_rule_queue queue_mode; 1251 bool exclusive; 1252 bool allow_loopback; 1253 enum mlx4_net_trans_promisc_mode promisc_mode; 1254 u8 port; 1255 u16 priority; 1256 u32 qpn; 1257}; 1258 1259struct mlx4_net_trans_rule_hw_ctrl { 1260 __be16 prio; 1261 u8 type; 1262 u8 flags; 1263 u8 rsvd1; 1264 u8 funcid; 1265 u8 vep; 1266 u8 port; 1267 __be32 qpn; 1268 __be32 rsvd2; 1269}; 1270 1271struct mlx4_net_trans_rule_hw_ib { 1272 u8 size; 1273 u8 rsvd1; 1274 __be16 id; 1275 u32 rsvd2; 1276 __be32 l3_qpn; 1277 __be32 qpn_mask; 1278 u8 dst_gid[16]; 1279 u8 dst_gid_msk[16]; 1280} __packed; 1281 1282struct mlx4_net_trans_rule_hw_eth { 1283 u8 size; 1284 u8 rsvd; 1285 __be16 id; 1286 u8 rsvd1[6]; 1287 u8 dst_mac[6]; 1288 u16 rsvd2; 1289 u8 dst_mac_msk[6]; 1290 u16 rsvd3; 1291 u8 src_mac[6]; 1292 u16 rsvd4; 1293 u8 src_mac_msk[6]; 1294 u8 rsvd5; 1295 u8 ether_type_enable; 1296 __be16 ether_type; 1297 __be16 vlan_tag_msk; 1298 __be16 vlan_tag; 1299} __packed; 1300 1301struct mlx4_net_trans_rule_hw_tcp_udp { 1302 u8 size; 1303 u8 rsvd; 1304 __be16 id; 1305 __be16 rsvd1[3]; 1306 __be16 dst_port; 1307 __be16 rsvd2; 1308 __be16 dst_port_msk; 1309 __be16 rsvd3; 1310 __be16 src_port; 1311 __be16 rsvd4; 1312 __be16 src_port_msk; 1313} __packed; 1314 1315struct mlx4_net_trans_rule_hw_ipv4 { 1316 u8 size; 1317 u8 rsvd; 1318 __be16 id; 1319 __be32 rsvd1; 1320 __be32 dst_ip; 1321 __be32 dst_ip_msk; 1322 __be32 src_ip; 1323 __be32 src_ip_msk; 1324} __packed; 1325 1326struct mlx4_net_trans_rule_hw_vxlan { 1327 u8 size; 1328 u8 rsvd; 1329 __be16 id; 1330 __be32 rsvd1; 1331 __be32 vni; 1332 __be32 vni_mask; 1333} __packed; 1334 1335struct _rule_hw { 1336 union { 1337 struct { 1338 u8 size; 1339 u8 rsvd; 1340 __be16 id; 1341 }; 1342 struct mlx4_net_trans_rule_hw_eth eth; 1343 struct mlx4_net_trans_rule_hw_ib ib; 1344 struct mlx4_net_trans_rule_hw_ipv4 ipv4; 1345 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; 1346 struct mlx4_net_trans_rule_hw_vxlan vxlan; 1347 }; 1348}; 1349 1350enum { 1351 VXLAN_STEER_BY_OUTER_MAC = 1 << 0, 1352 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1, 1353 VXLAN_STEER_BY_VSID_VNI = 1 << 2, 1354 VXLAN_STEER_BY_INNER_MAC = 1 << 3, 1355 VXLAN_STEER_BY_INNER_VLAN = 1 << 4, 1356}; 1357 1358enum { 1359 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS = 0x2, 1360}; 1361 1362int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, 1363 enum mlx4_net_trans_promisc_mode mode); 1364int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, 1365 enum mlx4_net_trans_promisc_mode mode); 1366int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1367int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1368int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1369int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1370int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 1371 1372int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1373void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1374int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); 1375int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 1376int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, 1377 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); 1378int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, 1379 u8 promisc); 1380int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time); 1381int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port, 1382 u8 ignore_fcs_value); 1383int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable); 1384int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val); 1385int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv); 1386int mlx4_get_is_vlan_offload_disabled(struct mlx4_dev *dev, u8 port, 1387 bool *vlan_offload_disabled); 1388int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx); 1389int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); 1390int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1391void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1392 1393int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 1394 int npages, u64 iova, u32 *lkey, u32 *rkey); 1395int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, 1396 int max_maps, u8 page_shift, struct mlx4_fmr *fmr); 1397int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1398void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 1399 u32 *lkey, u32 *rkey); 1400int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1401int mlx4_SYNC_TPT(struct mlx4_dev *dev); 1402int mlx4_test_interrupt(struct mlx4_dev *dev, int vector); 1403int mlx4_test_async(struct mlx4_dev *dev); 1404int mlx4_query_diag_counters(struct mlx4_dev *dev, u8 op_modifier, 1405 const u32 offset[], u32 value[], 1406 size_t array_len, u8 port); 1407u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port); 1408bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector); 1409int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector); 1410void mlx4_release_eq(struct mlx4_dev *dev, int vec); 1411 1412int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector); 1413int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec); 1414 1415int mlx4_get_phys_port_id(struct mlx4_dev *dev); 1416int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); 1417int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); 1418 1419int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 1420void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 1421int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port); 1422 1423void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, 1424 int port); 1425__be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port); 1426void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port); 1427int mlx4_flow_attach(struct mlx4_dev *dev, 1428 struct mlx4_net_trans_rule *rule, u64 *reg_id); 1429int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); 1430int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev, 1431 enum mlx4_net_trans_promisc_mode flow_type); 1432int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev, 1433 enum mlx4_net_trans_rule_id id); 1434int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id); 1435 1436int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr, 1437 int port, int qpn, u16 prio, u64 *reg_id); 1438 1439void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, 1440 int i, int val); 1441 1442int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); 1443 1444int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); 1445int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); 1446int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); 1447int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr); 1448int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); 1449enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); 1450int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); 1451 1452void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); 1453__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); 1454 1455int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, 1456 int *slave_id); 1457int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, 1458 u8 *gid); 1459 1460int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, 1461 u32 max_range_qpn); 1462 1463s64 mlx4_read_clock(struct mlx4_dev *dev); 1464 1465struct mlx4_active_ports { 1466 DECLARE_BITMAP(ports, MLX4_MAX_PORTS); 1467}; 1468/* Returns a bitmap of the physical ports which are assigned to slave */ 1469struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave); 1470 1471/* Returns the physical port that represents the virtual port of the slave, */ 1472/* or a value < 0 in case of an error. If a slave has 2 ports, the identity */ 1473/* mapping is returned. */ 1474int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port); 1475 1476struct mlx4_slaves_pport { 1477 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX); 1478}; 1479/* Returns a bitmap of all slaves that are assigned to port. */ 1480struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev, 1481 int port); 1482 1483/* Returns a bitmap of all slaves that are assigned exactly to all the */ 1484/* the ports that are set in crit_ports. */ 1485struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv( 1486 struct mlx4_dev *dev, 1487 const struct mlx4_active_ports *crit_ports); 1488 1489/* Returns the slave's virtual port that represents the physical port. */ 1490int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port); 1491 1492int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port); 1493 1494int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port); 1495int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis); 1496int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port); 1497int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2); 1498int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port); 1499int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port); 1500int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port, 1501 int enable); 1502int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, 1503 struct mlx4_mpt_entry ***mpt_entry); 1504int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, 1505 struct mlx4_mpt_entry **mpt_entry); 1506int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry, 1507 u32 pdn); 1508int mlx4_mr_hw_change_access(struct mlx4_dev *dev, 1509 struct mlx4_mpt_entry *mpt_entry, 1510 u32 access); 1511void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev, 1512 struct mlx4_mpt_entry **mpt_entry); 1513void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr); 1514int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr, 1515 u64 iova, u64 size, int npages, 1516 int page_shift, struct mlx4_mpt_entry *mpt_entry); 1517 1518int mlx4_get_module_info(struct mlx4_dev *dev, u8 port, 1519 u16 offset, u16 size, u8 *data); 1520int mlx4_max_tc(struct mlx4_dev *dev); 1521 1522/* Returns true if running in low memory profile (kdump kernel) */ 1523static inline bool mlx4_low_memory_profile(void) 1524{ 1525 return false; 1526} 1527 1528/* ACCESS REG commands */ 1529enum mlx4_access_reg_method { 1530 MLX4_ACCESS_REG_QUERY = 0x1, 1531 MLX4_ACCESS_REG_WRITE = 0x2, 1532}; 1533 1534/* ACCESS PTYS Reg command */ 1535enum mlx4_ptys_proto { 1536 MLX4_PTYS_IB = 1<<0, 1537 MLX4_PTYS_EN = 1<<2, 1538}; 1539 1540struct mlx4_ptys_reg { 1541 u8 resrvd1; 1542 u8 local_port; 1543 u8 resrvd2; 1544 u8 proto_mask; 1545 __be32 resrvd3[2]; 1546 __be32 eth_proto_cap; 1547 __be16 ib_width_cap; 1548 __be16 ib_speed_cap; 1549 __be32 resrvd4; 1550 __be32 eth_proto_admin; 1551 __be16 ib_width_admin; 1552 __be16 ib_speed_admin; 1553 __be32 resrvd5; 1554 __be32 eth_proto_oper; 1555 __be16 ib_width_oper; 1556 __be16 ib_speed_oper; 1557 __be32 resrvd6; 1558 __be32 eth_proto_lp_adv; 1559} __packed; 1560 1561int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, 1562 enum mlx4_access_reg_method method, 1563 struct mlx4_ptys_reg *ptys_reg); 1564 1565int mlx4_get_internal_clock_params(struct mlx4_dev *dev, 1566 struct mlx4_clock_params *params); 1567 1568static inline int mlx4_to_hw_uar_index(struct mlx4_dev *dev, int index) 1569{ 1570 return (index << (PAGE_SHIFT - dev->uar_page_shift)); 1571} 1572 1573static inline int mlx4_get_num_reserved_uar(struct mlx4_dev *dev) 1574{ 1575 /* The first 128 UARs are used for EQ doorbells */ 1576 return (128 >> (PAGE_SHIFT - dev->uar_page_shift)); 1577} 1578#endif /* MLX4_DEVICE_H */ 1579