e1000phyreg.h revision 173133
167217Sn_hibma/* $FreeBSD: head/sys/dev/mii/e1000phyreg.h 173133 2007-10-29 05:50:22Z yongari $ */ 261560Sn_hibma/*- 361560Sn_hibma * Principal Author: Parag Patel 461560Sn_hibma * Copyright (c) 2001 561560Sn_hibma * All rights reserved. 661560Sn_hibma * 761560Sn_hibma * Redistribution and use in source and binary forms, with or without 861560Sn_hibma * modification, are permitted provided that the following conditions 961560Sn_hibma * are met: 1061560Sn_hibma * 1. Redistributions of source code must retain the above copyright 1161560Sn_hibma * notice unmodified, this list of conditions, and the following 1261560Sn_hibma * disclaimer. 1361560Sn_hibma * 2. Redistributions in binary form must reproduce the above copyright 1461560Sn_hibma * notice, this list of conditions and the following disclaimer in the 1561560Sn_hibma * documentation and/or other materials provided with the distribution. 1661560Sn_hibma * 1761560Sn_hibma * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1861560Sn_hibma * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1961560Sn_hibma * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2061560Sn_hibma * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 2161560Sn_hibma * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2261560Sn_hibma * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2361560Sn_hibma * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2461560Sn_hibma * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2561560Sn_hibma * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2661560Sn_hibma * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2761560Sn_hibma * SUCH DAMAGE. 2861560Sn_hibma * 2984224Sdillon * Additonal Copyright (c) 2001 by Traakan Software under same licence. 3084224Sdillon * Secondary Author: Matthew Jacob 3184224Sdillon */ 32205728Skaiw 33113273Smdodd/*- 3461560Sn_hibma * Derived by information released by Intel under the following license: 3561560Sn_hibma * 3661560Sn_hibma * Copyright (c) 1999 - 2001, Intel Corporation 3761560Sn_hibma * 3861560Sn_hibma * All rights reserved. 3961560Sn_hibma * 40113273Smdodd * Redistribution and use in source and binary forms, with or without 4161560Sn_hibma * modification, are permitted provided that the following conditions are met: 4261560Sn_hibma * 4361560Sn_hibma * 1. Redistributions of source code must retain the above copyright notice, 4461560Sn_hibma * this list of conditions and the following disclaimer. 4561560Sn_hibma * 4661560Sn_hibma * 2. Redistributions in binary form must reproduce the above copyright notice, 4761560Sn_hibma * this list of conditions and the following disclaimer in the 4861560Sn_hibma * documentation and/or other materials provided with the distribution. 4961560Sn_hibma * 5061560Sn_hibma * 3. Neither the name of Intel Corporation nor the names of its contributors 5161560Sn_hibma * may be used to endorse or promote products derived from this software 5261560Sn_hibma * without specific prior written permission. 5361560Sn_hibma * 5461560Sn_hibma * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' 5561560Sn_hibma * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 5661560Sn_hibma * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 5761560Sn_hibma * ARE DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 5861560Sn_hibma * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 5961560Sn_hibma * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 6061560Sn_hibma * LOSS OF USE, DATA, OR * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 6161560Sn_hibma * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 6261560Sn_hibma * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 6361560Sn_hibma * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 6461560Sn_hibma * 6561560Sn_hibma */ 6661560Sn_hibma 6761560Sn_hibma/* 6861560Sn_hibma * Marvell E1000 PHY registers 6961560Sn_hibma */ 7061560Sn_hibma 7161560Sn_hibma#define E1000_MAX_REG_ADDRESS 0x1F 7261560Sn_hibma 7361560Sn_hibma#define E1000_CR 0x00 /* control register */ 7461560Sn_hibma#define E1000_CR_SPEED_SELECT_MSB 0x0040 7561560Sn_hibma#define E1000_CR_COLL_TEST_ENABLE 0x0080 7661560Sn_hibma#define E1000_CR_FULL_DUPLEX 0x0100 7761560Sn_hibma#define E1000_CR_RESTART_AUTO_NEG 0x0200 7861560Sn_hibma#define E1000_CR_ISOLATE 0x0400 7961560Sn_hibma#define E1000_CR_POWER_DOWN 0x0800 8061560Sn_hibma#define E1000_CR_AUTO_NEG_ENABLE 0x1000 8161560Sn_hibma#define E1000_CR_SPEED_SELECT_LSB 0x2000 8261560Sn_hibma#define E1000_CR_LOOPBACK 0x4000 8361560Sn_hibma#define E1000_CR_RESET 0x8000 8461560Sn_hibma 8561560Sn_hibma#define E1000_CR_SPEED_1000 0x0040 8661560Sn_hibma#define E1000_CR_SPEED_100 0x2000 8761560Sn_hibma#define E1000_CR_SPEED_10 0x0000 8861560Sn_hibma 8961560Sn_hibma#define E1000_SR 0x01 /* status register */ 9061560Sn_hibma#define E1000_SR_EXTENDED 0x0001 9161560Sn_hibma#define E1000_SR_JABBER_DETECT 0x0002 9261560Sn_hibma#define E1000_SR_LINK_STATUS 0x0004 9361560Sn_hibma#define E1000_SR_AUTO_NEG 0x0008 9461560Sn_hibma#define E1000_SR_REMOTE_FAULT 0x0010 9561560Sn_hibma#define E1000_SR_AUTO_NEG_COMPLETE 0x0020 9661560Sn_hibma#define E1000_SR_PREAMBLE_SUPPRESS 0x0040 9761560Sn_hibma#define E1000_SR_EXTENDED_STATUS 0x0100 9861560Sn_hibma#define E1000_SR_100T2 0x0200 9961560Sn_hibma#define E1000_SR_100T2_FD 0x0400 10061560Sn_hibma#define E1000_SR_10T 0x0800 101113193Smdodd#define E1000_SR_10T_FD 0x1000 10261560Sn_hibma#define E1000_SR_100TX 0x2000 10361560Sn_hibma#define E1000_SR_100TX_FD 0x4000 10461560Sn_hibma#define E1000_SR_100T4 0x8000 10561560Sn_hibma 10661560Sn_hibma#define E1000_ID1 0x02 /* ID register 1 */ 10761560Sn_hibma#define E1000_ID2 0x03 /* ID register 2 */ 10861560Sn_hibma#define E1000_ID_88E1000 0x01410C50 10961560Sn_hibma#define E1000_ID_88E1000S 0x01410C40 11061560Sn_hibma#define E1000_ID_88E1011 0x01410C20 111113193Smdodd#define E1000_ID_MASK 0xFFFFFFF0 11261560Sn_hibma 11361560Sn_hibma#define E1000_AR 0x04 /* autonegotiation advertise reg */ 11461560Sn_hibma#define E1000_AR_SELECTOR_FIELD 0x0001 11561560Sn_hibma#define E1000_AR_10T 0x0020 11661560Sn_hibma#define E1000_AR_10T_FD 0x0040 11761560Sn_hibma#define E1000_AR_100TX 0x0080 11861560Sn_hibma#define E1000_AR_100TX_FD 0x0100 11961560Sn_hibma#define E1000_AR_100T4 0x0200 12061560Sn_hibma#define E1000_AR_PAUSE 0x0400 12161560Sn_hibma#define E1000_AR_ASM_DIR 0x0800 12261560Sn_hibma#define E1000_AR_REMOTE_FAULT 0x2000 12361560Sn_hibma#define E1000_AR_NEXT_PAGE 0x8000 12461560Sn_hibma#define E1000_AR_SPEED_MASK 0x01E0 12561560Sn_hibma 12661560Sn_hibma/* Autonegotiation register bits for fiber cards (Alaska Only!) */ 12761560Sn_hibma#define E1000_FA_1000X_FD 0x0020 12861560Sn_hibma#define E1000_FA_1000X 0x0040 12961560Sn_hibma#define E1000_FA_SYM_PAUSE 0x0080 13061560Sn_hibma#define E1000_FA_ASYM_PAUSE 0x0100 13161560Sn_hibma#define E1000_FA_FAULT1 0x1000 13261560Sn_hibma#define E1000_FA_FAULT2 0x2000 13361560Sn_hibma#define E1000_FA_NEXT_PAGE 0x8000 13461560Sn_hibma 13561560Sn_hibma#define E1000_LPAR 0x05 /* autoneg link partner abilities reg */ 13661560Sn_hibma#define E1000_LPAR_SELECTOR_FIELD 0x0001 13761560Sn_hibma#define E1000_LPAR_10T 0x0020 13861560Sn_hibma#define E1000_LPAR_10T_FD 0x0040 13961560Sn_hibma#define E1000_LPAR_100TX 0x0080 14061560Sn_hibma#define E1000_LPAR_100TX_FD 0x0100 14161560Sn_hibma#define E1000_LPAR_100T4 0x0200 14261560Sn_hibma#define E1000_LPAR_PAUSE 0x0400 14361560Sn_hibma#define E1000_LPAR_ASM_DIR 0x0800 14461560Sn_hibma#define E1000_LPAR_REMOTE_FAULT 0x2000 14561560Sn_hibma#define E1000_LPAR_ACKNOWLEDGE 0x4000 14661560Sn_hibma#define E1000_LPAR_NEXT_PAGE 0x8000 14761560Sn_hibma 14861560Sn_hibma/* autoneg link partner ability register bits for fiber cards (Alaska Only!) */ 14961560Sn_hibma#define E1000_FPAR_1000X_FD 0x0020 15061560Sn_hibma#define E1000_FPAR_1000X 0x0040 15161560Sn_hibma#define E1000_FPAR_SYM_PAUSE 0x0080 15261560Sn_hibma#define E1000_FPAR_ASYM_PAUSE 0x0100 15361560Sn_hibma#define E1000_FPAR_FAULT1 0x1000 15461560Sn_hibma#define E1000_FPAR_FAULT2 0x2000 15561560Sn_hibma#define E1000_FPAR_ACK 0x4000 15661560Sn_hibma#define E1000_FPAR_NEXT_PAGE 0x8000 15761560Sn_hibma 15861560Sn_hibma#define E1000_ER 0x06 /* autoneg expansion reg */ 15961560Sn_hibma#define E1000_ER_LP_NWAY 0x0001 16061560Sn_hibma#define E1000_ER_PAGE_RXD 0x0002 16161560Sn_hibma#define E1000_ER_NEXT_PAGE 0x0004 16261560Sn_hibma#define E1000_ER_LP_NEXT_PAGE 0x0008 16361560Sn_hibma#define E1000_ER_PAR_DETECT_FAULT 0x0100 16461560Sn_hibma 165113193Smdodd#define E1000_NPTX 0x07 /* autoneg next page TX */ 16661560Sn_hibma#define E1000_NPTX_MSG_CODE_FIELD 0x0001 16761560Sn_hibma#define E1000_NPTX_TOGGLE 0x0800 16861560Sn_hibma#define E1000_NPTX_ACKNOWLDGE2 0x1000 16961560Sn_hibma#define E1000_NPTX_MSG_PAGE 0x2000 17065116Sn_hibma#define E1000_NPTX_NEXT_PAGE 0x8000 17161560Sn_hibma 17261560Sn_hibma#define E1000_RNPR 0x08 /* autoneg link-partner (?) next page */ 17361560Sn_hibma#define E1000_RNPR_MSG_CODE_FIELD 0x0001 17461560Sn_hibma#define E1000_RNPR_TOGGLE 0x0800 17561560Sn_hibma#define E1000_RNPR_ACKNOWLDGE2 0x1000 17661560Sn_hibma#define E1000_RNPR_MSG_PAGE 0x2000 17761560Sn_hibma#define E1000_RNPR_ACKNOWLDGE 0x4000 17861560Sn_hibma#define E1000_RNPR_NEXT_PAGE 0x8000 17961560Sn_hibma 18061560Sn_hibma#define E1000_1GCR 0x09 /* 1000T (1G) control reg */ 18161560Sn_hibma#define E1000_1GCR_ASYM_PAUSE 0x0080 18261560Sn_hibma#define E1000_1GCR_1000T 0x0100 18361560Sn_hibma#define E1000_1GCR_1000T_FD 0x0200 18461560Sn_hibma#define E1000_1GCR_REPEATER_DTE 0x0400 18561560Sn_hibma#define E1000_1GCR_MS_VALUE 0x0800 18661560Sn_hibma#define E1000_1GCR_MS_ENABLE 0x1000 18761560Sn_hibma#define E1000_1GCR_TEST_MODE_NORMAL 0x0000 18861560Sn_hibma#define E1000_1GCR_TEST_MODE_1 0x2000 18961560Sn_hibma#define E1000_1GCR_TEST_MODE_2 0x4000 190113193Smdodd#define E1000_1GCR_TEST_MODE_3 0x6000 191113193Smdodd#define E1000_1GCR_TEST_MODE_4 0x8000 192113193Smdodd#define E1000_1GCR_SPEED_MASK 0x0300 19361560Sn_hibma 19461560Sn_hibma#define E1000_1GSR 0x0A /* 1000T (1G) status reg */ 19561560Sn_hibma#define E1000_1GSR_IDLE_ERROR_CNT 0x0000 19661560Sn_hibma#define E1000_1GSR_ASYM_PAUSE_DIR 0x0100 19761560Sn_hibma#define E1000_1GSR_LP 0x0400 19861560Sn_hibma#define E1000_1GSR_LP_FD 0x0800 19965116Sn_hibma#define E1000_1GSR_REMOTE_RX_STATUS 0x1000 20061560Sn_hibma#define E1000_1GSR_LOCAL_RX_STATUS 0x2000 20161560Sn_hibma#define E1000_1GSR_MS_CONFIG_RES 0x4000 20267217Sn_hibma#define E1000_1GSR_MS_CONFIG_FAULT 0x8000 20367217Sn_hibma 20467217Sn_hibma#define E1000_ESR 0x0F /* IEEE extended status reg */ 20567217Sn_hibma#define E1000_ESR_1000T 0x1000 20667217Sn_hibma#define E1000_ESR_1000T_FD 0x2000 20767217Sn_hibma#define E1000_ESR_1000X 0x4000 20867217Sn_hibma#define E1000_ESR_1000X_FD 0x8000 209113193Smdodd 21067217Sn_hibma#define E1000_TX_POLARITY_MASK 0x0100 21167217Sn_hibma#define E1000_TX_NORMAL_POLARITY 0 21267217Sn_hibma 21367217Sn_hibma#define E1000_AUTO_POLARITY_DISABLE 0x0010 21467217Sn_hibma 21567217Sn_hibma#define E1000_SCR 0x10 /* special control register */ 21667217Sn_hibma#define E1000_SCR_JABBER_DISABLE 0x0001 21767217Sn_hibma#define E1000_SCR_POLARITY_REVERSAL 0x0002 21867217Sn_hibma#define E1000_SCR_SQE_TEST 0x0004 21967217Sn_hibma#define E1000_SCR_INT_FIFO_DISABLE 0x0008 22067217Sn_hibma#define E1000_SCR_CLK125_DISABLE 0x0010 221113193Smdodd#define E1000_SCR_MDI_MANUAL_MODE 0x0000 22267217Sn_hibma#define E1000_SCR_MDIX_MANUAL_MODE 0x0020 22367217Sn_hibma#define E1000_SCR_AUTO_X_1000T 0x0040 22467217Sn_hibma#define E1000_SCR_AUTO_X_MODE 0x0060 225113193Smdodd#define E1000_SCR_10BT_EXT_ENABLE 0x0080 22667217Sn_hibma#define E1000_SCR_MII_5BIT_ENABLE 0x0100 22767217Sn_hibma#define E1000_SCR_SCRAMBLER_DISABLE 0x0200 22867217Sn_hibma#define E1000_SCR_FORCE_LINK_GOOD 0x0400 22967217Sn_hibma#define E1000_SCR_ASSERT_CRS_ON_TX 0x0800 23067217Sn_hibma#define E1000_SCR_RX_FIFO_DEPTH_6 0x0000 23167217Sn_hibma#define E1000_SCR_RX_FIFO_DEPTH_8 0x1000 23267217Sn_hibma#define E1000_SCR_RX_FIFO_DEPTH_10 0x2000 23367217Sn_hibma#define E1000_SCR_RX_FIFO_DEPTH_12 0x3000 23467217Sn_hibma#define E1000_SCR_TX_FIFO_DEPTH_6 0x0000 23567217Sn_hibma#define E1000_SCR_TX_FIFO_DEPTH_8 0x4000 23667217Sn_hibma#define E1000_SCR_TX_FIFO_DEPTH_10 0x8000 23767217Sn_hibma#define E1000_SCR_TX_FIFO_DEPTH_12 0xC000 23867217Sn_hibma 23967217Sn_hibma#define E1000_SCR_EN_DETECT_MASK 0x0300 240 241/* 88E1112 page 2 */ 242#define E1000_SCR_MODE_MASK 0x0380 243#define E1000_SCR_MODE_AUTO 0x0180 244#define E1000_SCR_MODE_COPPER 0x0280 245#define E1000_SCR_MODE_1000BX 0x0380 246 247/* 88E1116 page 0 */ 248#define E1000_SCR_POWER_DOWN 0x0004 249/* 88E1116 page 2 */ 250#define E1000_SCR_RGMII_POWER_UP 0x0008 251 252#define E1000_SSR 0x11 /* special status register */ 253#define E1000_SSR_JABBER 0x0001 254#define E1000_SSR_REV_POLARITY 0x0002 255#define E1000_SSR_MDIX 0x0020 256#define E1000_SSR_LINK 0x0400 257#define E1000_SSR_SPD_DPLX_RESOLVED 0x0800 258#define E1000_SSR_PAGE_RCVD 0x1000 259#define E1000_SSR_DUPLEX 0x2000 260#define E1000_SSR_SPEED 0xC000 261#define E1000_SSR_10MBS 0x0000 262#define E1000_SSR_100MBS 0x4000 263#define E1000_SSR_1000MBS 0x8000 264 265#define E1000_IER 0x12 /* interrupt enable reg */ 266#define E1000_IER_JABBER 0x0001 267#define E1000_IER_POLARITY_CHANGE 0x0002 268#define E1000_IER_MDIX_CHANGE 0x0040 269#define E1000_IER_FIFO_OVER_UNDERUN 0x0080 270#define E1000_IER_FALSE_CARRIER 0x0100 271#define E1000_IER_SYMBOL_ERROR 0x0200 272#define E1000_IER_LINK_STAT_CHANGE 0x0400 273#define E1000_IER_AUTO_NEG_COMPLETE 0x0800 274#define E1000_IER_PAGE_RECEIVED 0x1000 275#define E1000_IER_DUPLEX_CHANGED 0x2000 276#define E1000_IER_SPEED_CHANGED 0x4000 277#define E1000_IER_AUTO_NEG_ERR 0x8000 278 279#define E1000_ISR 0x13 /* interrupt status reg */ 280#define E1000_ISR_JABBER 0x0001 281#define E1000_ISR_POLARITY_CHANGE 0x0002 282#define E1000_ISR_MDIX_CHANGE 0x0040 283#define E1000_ISR_FIFO_OVER_UNDERUN 0x0080 284#define E1000_ISR_FALSE_CARRIER 0x0100 285#define E1000_ISR_SYMBOL_ERROR 0x0200 286#define E1000_ISR_LINK_STAT_CHANGE 0x0400 287#define E1000_ISR_AUTO_NEG_COMPLETE 0x0800 288#define E1000_ISR_PAGE_RECEIVED 0x1000 289#define E1000_ISR_DUPLEX_CHANGED 0x2000 290#define E1000_ISR_SPEED_CHANGED 0x4000 291#define E1000_ISR_AUTO_NEG_ERR 0x8000 292 293#define E1000_ESCR 0x14 /* extended special control reg */ 294#define E1000_ESCR_FIBER_LOOPBACK 0x4000 295#define E1000_ESCR_DOWN_NO_IDLE 0x8000 296#define E1000_ESCR_TX_CLK_2_5 0x0060 297#define E1000_ESCR_TX_CLK_25 0x0070 298#define E1000_ESCR_TX_CLK_0 0x0000 299 300#define E1000_RECR 0x15 /* RX error counter reg */ 301 302#define E1000_EADR 0x16 /* extended address reg */ 303 304#define E1000_LCR 0x18 /* LED control reg */ 305#define E1000_LCR_LED_TX 0x0001 306#define E1000_LCR_LED_RX 0x0002 307#define E1000_LCR_LED_DUPLEX 0x0004 308#define E1000_LCR_LINK 0x0008 309#define E1000_LCR_BLINK_42MS 0x0000 310#define E1000_LCR_BLINK_84MS 0x0100 311#define E1000_LCR_BLINK_170MS 0x0200 312#define E1000_LCR_BLINK_340MS 0x0300 313#define E1000_LCR_BLINK_670MS 0x0400 314#define E1000_LCR_PULSE_OFF 0x0000 315#define E1000_LCR_PULSE_21_42MS 0x1000 316#define E1000_LCR_PULSE_42_84MS 0x2000 317#define E1000_LCR_PULSE_84_170MS 0x3000 318#define E1000_LCR_PULSE_170_340MS 0x4000 319#define E1000_LCR_PULSE_340_670MS 0x5000 320#define E1000_LCR_PULSE_670_13S 0x6000 321#define E1000_LCR_PULSE_13_26S 0x7000 322 323/* The following register is found only on the 88E1011 Alaska PHY */ 324#define E1000_ESSR 0x1B /* Extended PHY specific sts */ 325#define E1000_ESSR_FIBER_LINK 0x2000 326#define E1000_ESSR_GMII_COPPER 0x000f 327#define E1000_ESSR_GMII_FIBER 0x0007 328#define E1000_ESSR_TBI_COPPER 0x000d 329#define E1000_ESSR_TBI_FIBER 0x0005 330