if_lmc.h revision 188178
1/* 2 * $FreeBSD: head/sys/dev/lmc/if_lmc.h 188178 2009-02-05 19:37:49Z imp $ 3 * 4 * Copyright (c) 2002-2004 David Boggs. (boggs@boggs.palo-alto.ca.us) 5 * All rights reserved. 6 * 7 * BSD License: 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * GNU General Public License: 31 * 32 * This program is free software; you can redistribute it and/or modify it 33 * under the terms of the GNU General Public License as published by the Free 34 * Software Foundation; either version 2 of the License, or (at your option) 35 * any later version. 36 * 37 * This program is distributed in the hope that it will be useful, but WITHOUT 38 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 39 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 40 * more details. 41 * 42 * You should have received a copy of the GNU General Public License along with 43 * this program; if not, write to the Free Software Foundation, Inc., 59 44 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 45 */ 46 47#ifndef IF_LMC_H 48#define IF_LMC_H 49 50#define DEVICE_NAME "lmc" 51 52/* Linux RPM-style version information */ 53#define DRIVER_MAJOR_VERSION 2005 /* year */ 54#define DRIVER_MINOR_VERSION 9 /* month */ 55#define DRIVER_SUB_VERSION 29 /* day */ 56 57/* netgraph stuff */ 58#define NG_LMC_NODE_TYPE DEVICE_NAME 59#define NGM_LMC_COOKIE 1128054761 /* date -u +'%s' */ 60 61/* Tulip PCI configuration registers */ 62#define TLP_CFID 0x00 /* 0: CFg ID register */ 63#define TLP_CFCS 0x04 /* 1: CFg Command/Status */ 64#define TLP_CFRV 0x08 /* 2: CFg ReVision */ 65#define TLP_CFLT 0x0C /* 3: CFg Latency Timer */ 66#define TLP_CBIO 0x10 /* 4: Cfg Base IO address */ 67#define TLP_CBMA 0x14 /* 5: Cfg Base Mem Addr */ 68#define TLP_CSID 0x2C /* 11: Cfg Subsys ID reg */ 69#define TLP_CFIT 0x3C /* 15: CFg InTerrupt */ 70#define TLP_CFDD 0x40 /* 16: CFg Driver Data */ 71 72#define TLP_CFID_TULIP 0x00091011 /* DEC 21140A Ethernet chip */ 73 74#define TLP_CFCS_MSTR_ABORT 0x20000000 75#define TLP_CFCS_TARG_ABORT 0x10000000 76#define TLP_CFCS_SYS_ERROR 0x00000100 77#define TLP_CFCS_PAR_ERROR 0x00000040 78#define TLP_CFCS_MWI_ENABLE 0x00000010 79#define TLP_CFCS_BUS_MASTER 0x00000004 80#define TLP_CFCS_MEM_ENABLE 0x00000002 81#define TLP_CFCS_IO_ENABLE 0x00000001 82 83#define TLP_CFLT_LATENCY 0x0000FF00 84#define TLP_CFLT_CACHE 0x000000FF 85 86#define TLP_CSID_HSSI 0x00031376 /* LMC 5200 HSSI card */ 87#define TLP_CSID_T3 0x00041376 /* LMC 5245 T3 card */ 88#define TLP_CSID_SSI 0x00051376 /* LMC 1000 SSI card */ 89#define TLP_CSID_T1E1 0x00061376 /* LMC 1200 T1E1 card */ 90#define TLP_CSID_HSSIc 0x00071376 /* LMC 5200 HSSI cPCI */ 91#define TLP_CSID_SDSL 0x00081376 /* LMC 1168 SDSL card */ 92 93#define TLP_CFIT_MAX_LAT 0xFF000000 94 95#define TLP_CFDD_SLEEP 0x80000000 96#define TLP_CFDD_SNOOZE 0x40000000 97 98/* Tulip Control and Status Registers */ 99#define TLP_CSR_STRIDE 8 /* 64 bits */ 100#define TLP_BUS_MODE 0 * TLP_CSR_STRIDE 101#define TLP_TX_POLL 1 * TLP_CSR_STRIDE 102#define TLP_RX_POLL 2 * TLP_CSR_STRIDE 103#define TLP_RX_LIST 3 * TLP_CSR_STRIDE 104#define TLP_TX_LIST 4 * TLP_CSR_STRIDE 105#define TLP_STATUS 5 * TLP_CSR_STRIDE 106#define TLP_OP_MODE 6 * TLP_CSR_STRIDE 107#define TLP_INT_ENBL 7 * TLP_CSR_STRIDE 108#define TLP_MISSED 8 * TLP_CSR_STRIDE 109#define TLP_SROM_MII 9 * TLP_CSR_STRIDE 110#define TLP_BIOS_ROM 10 * TLP_CSR_STRIDE 111#define TLP_TIMER 11 * TLP_CSR_STRIDE 112#define TLP_GPIO 12 * TLP_CSR_STRIDE 113#define TLP_CSR13 13 * TLP_CSR_STRIDE 114#define TLP_CSR14 14 * TLP_CSR_STRIDE 115#define TLP_WDOG 15 * TLP_CSR_STRIDE 116#define TLP_CSR_SIZE 128 /* IO bus space size */ 117 118/* CSR 0 - PCI Bus Mode Register */ 119#define TLP_BUS_WRITE_INVAL 0x01000000 /* DONT USE! */ 120#define TLP_BUS_READ_LINE 0x00800000 121#define TLP_BUS_READ_MULT 0x00200000 122#define TLP_BUS_DESC_BIGEND 0x00100000 123#define TLP_BUS_TAP 0x000E0000 124#define TLP_BUS_CAL 0x0000C000 125#define TLP_BUS_PBL 0x00003F00 126#define TLP_BUS_DATA_BIGEND 0x00000080 127#define TLP_BUS_DSL 0x0000007C 128#define TLP_BUS_ARB 0x00000002 129#define TLP_BUS_RESET 0x00000001 130#define TLP_BUS_CAL_SHIFT 14 131#define TLP_BUS_PBL_SHIFT 8 132 133/* CSR 5 - Status Register */ 134#define TLP_STAT_FATAL_BITS 0x03800000 135#define TLP_STAT_TX_FSM 0x00700000 136#define TLP_STAT_RX_FSM 0x000E0000 137#define TLP_STAT_FATAL_ERROR 0x00002000 138#define TLP_STAT_TX_UNDERRUN 0x00000020 139#define TLP_STAT_FATAL_SHIFT 23 140 141/* CSR 6 - Operating Mode Register */ 142#define TLP_OP_RECEIVE_ALL 0x40000000 143#define TLP_OP_MUST_BE_ONE 0x02000000 144#define TLP_OP_NO_HEART_BEAT 0x00080000 145#define TLP_OP_PORT_SELECT 0x00040000 146#define TLP_OP_TX_THRESH 0x0000C000 147#define TLP_OP_TX_RUN 0x00002000 148#define TLP_OP_LOOP_MODE 0x00000C00 149#define TLP_OP_EXT_LOOP 0x00000800 150#define TLP_OP_INT_LOOP 0x00000400 151#define TLP_OP_FULL_DUPLEX 0x00000200 152#define TLP_OP_PROMISCUOUS 0x00000040 153#define TLP_OP_PASS_BAD_PKT 0x00000008 154#define TLP_OP_RX_RUN 0x00000002 155#define TLP_OP_TR_SHIFT 14 156#define TLP_OP_INIT (TLP_OP_PORT_SELECT | \ 157 TLP_OP_FULL_DUPLEX | \ 158 TLP_OP_MUST_BE_ONE | \ 159 TLP_OP_NO_HEART_BEAT | \ 160 TLP_OP_RECEIVE_ALL | \ 161 TLP_OP_PROMISCUOUS | \ 162 TLP_OP_PASS_BAD_PKT | \ 163 TLP_OP_RX_RUN | \ 164 TLP_OP_TX_RUN) 165 166/* CSR 7 - Interrupt Enable Register */ 167#define TLP_INT_NORMAL_INTR 0x00010000 168#define TLP_INT_ABNRML_INTR 0x00008000 169#define TLP_INT_FATAL_ERROR 0x00002000 170#define TLP_INT_RX_NO_BUFS 0x00000080 171#define TLP_INT_RX_INTR 0x00000040 172#define TLP_INT_TX_UNDERRUN 0x00000020 173#define TLP_INT_TX_INTR 0x00000001 174#define TLP_INT_DISABLE 0 175#define TLP_INT_TX (TLP_INT_NORMAL_INTR | \ 176 TLP_INT_ABNRML_INTR | \ 177 TLP_INT_FATAL_ERROR | \ 178 TLP_INT_TX_UNDERRUN | \ 179 TLP_INT_TX_INTR) 180#define TLP_INT_RX (TLP_INT_NORMAL_INTR | \ 181 TLP_INT_ABNRML_INTR | \ 182 TLP_INT_FATAL_ERROR | \ 183 TLP_INT_RX_NO_BUFS | \ 184 TLP_INT_RX_INTR) 185#define TLP_INT_TXRX (TLP_INT_TX | TLP_INT_RX) 186 187/* CSR 8 - RX Missed Frames & Overrun Register */ 188#define TLP_MISS_OCO 0x10000000 189#define TLP_MISS_OVERRUN 0x0FFE0000 190#define TLP_MISS_MFO 0x00010000 191#define TLP_MISS_MISSED 0x0000FFFF 192#define TLP_OVERRUN_SHIFT 17 193 194/* CSR 9 - SROM & MII & Boot ROM Register */ 195#define TLP_MII_MDIN 0x00080000 196#define TLP_MII_MDOE 0x00040000 197#define TLP_MII_MDOUT 0x00020000 198#define TLP_MII_MDC 0x00010000 199 200#define TLP_BIOS_RD 0x00004000 201#define TLP_BIOS_WR 0x00002000 202#define TLP_BIOS_SEL 0x00001000 203 204#define TLP_SROM_RD 0x00004000 205#define TLP_SROM_SEL 0x00000800 206#define TLP_SROM_DOUT 0x00000008 207#define TLP_SROM_DIN 0x00000004 208#define TLP_SROM_CLK 0x00000002 209#define TLP_SROM_CS 0x00000001 210 211/* CSR 12 - General Purpose IO register */ 212#define TLP_GPIO_DIR 0x00000100 213 214/* CSR 15 - Watchdog Timer Register */ 215#define TLP_WDOG_RX_OFF 0x00000010 216#define TLP_WDOG_TX_OFF 0x00000001 217#define TLP_WDOG_INIT (TLP_WDOG_TX_OFF | \ 218 TLP_WDOG_RX_OFF) 219 220/* GPIO bits common to all cards */ 221#define GPIO_INIT 0x01 /* from Xilinx */ 222#define GPIO_RESET 0x02 /* to Xilinx */ 223/* bits 2 and 3 vary with board type -- see below */ 224#define GPIO_MODE 0x10 /* to Xilinx */ 225#define GPIO_DP 0x20 /* to/from Xilinx */ 226#define GPIO_DATA 0x40 /* serial data */ 227#define GPIO_CLK 0x80 /* serial clock */ 228 229/* HSSI GPIO bits */ 230#define GPIO_HSSI_ST 0x04 /* send timing sense (deprecated) */ 231#define GPIO_HSSI_TXCLK 0x08 /* clock source */ 232 233/* HSSIc GPIO bits */ 234#define GPIO_HSSI_SYNTH 0x04 /* Synth osc chip select */ 235#define GPIO_HSSI_DCE 0x08 /* provide clock on TXCLOCK output */ 236 237/* T3 GPIO bits */ 238#define GPIO_T3_DAC 0x04 /* DAC chip select */ 239#define GPIO_T3_INTEN 0x08 /* Framer Interupt enable */ 240 241/* SSI GPIO bits */ 242#define GPIO_SSI_SYNTH 0x04 /* Synth osc chip select */ 243#define GPIO_SSI_DCE 0x08 /* provide clock on TXCLOCK output */ 244 245/* T1E1 GPIO bits */ 246#define GPIO_T1_INTEN 0x08 /* Framer Interupt enable */ 247 248/* MII register 16 bits common to all cards */ 249/* NB: LEDs for HSSI & SSI are in DIFFERENT bits than for T1E1 & T3; oops */ 250/* NB: CRC32 for HSSI & SSI is in DIFFERENT bit than for T1E1 & T3; oops */ 251#define MII16_LED_ALL 0x0780 /* RW: LED bit mask */ 252#define MII16_FIFO 0x0800 /* RW: 1=reset, 0=not reset */ 253 254/* MII register 16 bits for HSSI */ 255#define MII16_HSSI_TA 0x0001 /* RW: host ready; host->modem */ 256#define MII16_HSSI_CA 0x0002 /* RO: modem ready; modem->host */ 257#define MII16_HSSI_LA 0x0004 /* RW: loopback A; host->modem */ 258#define MII16_HSSI_LB 0x0008 /* RW: loopback B; host->modem */ 259#define MII16_HSSI_LC 0x0010 /* RO: loopback C; modem->host */ 260#define MII16_HSSI_TM 0x0020 /* RO: test mode; modem->host */ 261#define MII16_HSSI_CRC32 0x0040 /* RW: CRC length 16/32 */ 262#define MII16_HSSI_LED_LL 0x0080 /* RW: lower left - green */ 263#define MII16_HSSI_LED_LR 0x0100 /* RW: lower right - green */ 264#define MII16_HSSI_LED_UL 0x0200 /* RW: upper left - green */ 265#define MII16_HSSI_LED_UR 0x0400 /* RW: upper right - red */ 266#define MII16_HSSI_FIFO 0x0800 /* RW: reset fifos */ 267#define MII16_HSSI_FORCECA 0x1000 /* RW: [cPCI] force CA on */ 268#define MII16_HSSI_CLKMUX 0x6000 /* RW: [cPCI] TX clock selection */ 269#define MII16_HSSI_LOOP 0x8000 /* RW: [cPCI] LOOP TX into RX */ 270#define MII16_HSSI_MODEM 0x003F /* TA+CA+LA+LB+LC+TM */ 271 272/* MII register 16 bits for DS3 */ 273#define MII16_DS3_ZERO 0x0001 /* RW: short/long cables */ 274#define MII16_DS3_TRLBK 0x0002 /* RW: loop towards host */ 275#define MII16_DS3_LNLBK 0x0004 /* RW: loop towards net */ 276#define MII16_DS3_RAIS 0x0008 /* RO: LIU receive AIS (depr) */ 277#define MII16_DS3_TAIS 0x0010 /* RW: LIU transmit AIS (depr) */ 278#define MII16_DS3_BIST 0x0020 /* RO: LIU QRSS patt match (depr) */ 279#define MII16_DS3_DLOS 0x0040 /* RO: LIU Digital LOS (depr) */ 280#define MII16_DS3_LED_BLU 0x0080 /* RW: lower right - blue */ 281#define MII16_DS3_LED_YEL 0x0100 /* RW: lower left - yellow */ 282#define MII16_DS3_LED_RED 0x0200 /* RW: upper right - red */ 283#define MII16_DS3_LED_GRN 0x0400 /* RW: upper left - green */ 284#define MII16_DS3_FIFO 0x0800 /* RW: reset fifos */ 285#define MII16_DS3_CRC32 0x1000 /* RW: CRC length 16/32 */ 286#define MII16_DS3_SCRAM 0x2000 /* RW: payload scrambler */ 287#define MII16_DS3_POLY 0x4000 /* RW: 1=Larse, 0=DigLink|Kentrox */ 288#define MII16_DS3_FRAME 0x8000 /* RW: 1=stop txframe pulses */ 289 290/* MII register 16 bits for SSI */ 291#define MII16_SSI_DTR 0x0001 /* RW: DTR host->modem */ 292#define MII16_SSI_DSR 0x0002 /* RO: DSR modem->host */ 293#define MII16_SSI_RTS 0x0004 /* RW: RTS host->modem */ 294#define MII16_SSI_CTS 0x0008 /* RO: CTS modem->host */ 295#define MII16_SSI_DCD 0x0010 /* RW: DCD modem<->host */ 296#define MII16_SSI_RI 0x0020 /* RO: RI modem->host */ 297#define MII16_SSI_CRC32 0x0040 /* RW: CRC length 16/32 */ 298#define MII16_SSI_LED_LL 0x0080 /* RW: lower left - green */ 299#define MII16_SSI_LED_LR 0x0100 /* RW: lower right - green */ 300#define MII16_SSI_LED_UL 0x0200 /* RW: upper left - green */ 301#define MII16_SSI_LED_UR 0x0400 /* RW: upper right - red */ 302#define MII16_SSI_FIFO 0x0800 /* RW: reset fifos */ 303#define MII16_SSI_LL 0x1000 /* RW: LL: host->modem */ 304#define MII16_SSI_RL 0x2000 /* RW: RL: host->modem */ 305#define MII16_SSI_TM 0x4000 /* RO: TM: modem->host */ 306#define MII16_SSI_LOOP 0x8000 /* RW: Loop at ext conn */ 307#define MII16_SSI_MODEM 0x703F /* DTR+DSR+RTS+CTS+DCD+RI+LL+RL+TM */ 308 309/* Mii register 17 has the SSI cable bits */ 310#define MII17_SSI_CABLE_SHIFT 3 /* shift to get cable type */ 311#define MII17_SSI_CABLE_MASK 0x0038 /* RO: mask to get cable type */ 312#define MII17_SSI_PRESCALE 0x0040 /* RW: divide by: 0=16; 1=512 */ 313#define MII17_SSI_ITF 0x0100 /* RW: fill with: 0=flags; 1=ones */ 314#define MII17_SSI_NRZI 0x0400 /* RW: coding: NRZ= 0; NRZI=1 */ 315 316/* MII register 16 bits for T1/E1 */ 317#define MII16_T1_UNUSED1 0x0001 318#define MII16_T1_INVERT 0x0002 /* RW: invert data (for SF/AMI) */ 319#define MII16_T1_XOE 0x0004 /* RW: TX Output Enable; 0=disable */ 320#define MII16_T1_RST 0x0008 /* RW: Bt8370 chip reset */ 321#define MII16_T1_Z 0x0010 /* RW: output impedance T1=1 E1=0 */ 322#define MII16_T1_INTR 0x0020 /* RO: interrupt from Bt8370 */ 323#define MII16_T1_ONESEC 0x0040 /* RO: one second square wave */ 324#define MII16_T1_LED_BLU 0x0080 /* RW: lower right - blue */ 325#define MII16_T1_LED_YEL 0x0100 /* RW: lower left - yellow */ 326#define MII16_T1_LED_RED 0x0200 /* RW: upper right - red */ 327#define MII16_T1_LED_GRN 0x0400 /* RW: upper left - green */ 328#define MII16_T1_FIFO 0x0800 /* RW: reset fifos */ 329#define MII16_T1_CRC32 0x1000 /* RW: CRC length 16/32 */ 330#define MII16_T1_UNUSED2 0xE000 331 332/* T3 framer: RW=Read/Write; RO=Read-Only; RC=Read/Clr; WO=Write-Only */ 333#define T3CSR_STAT0 0x00 /* RO: real-time status */ 334#define T3CSR_CTL1 0x01 /* RW: global control bits */ 335#define T3CSR_FEBE 0x02 /* RC: Far End Block Error Counter */ 336#define T3CSR_CERR 0x03 /* RC: C-bit Parity Error Counter */ 337#define T3CSR_PERR 0x04 /* RC: P-bit Parity Error Counter */ 338#define T3CSR_TX_FEAC 0x05 /* RW: Far End Alarm & Control */ 339#define T3CSR_RX_FEAC 0x06 /* RO: Far End Alarm & Control */ 340#define T3CSR_STAT7 0x07 /* RL: latched real-time status */ 341#define T3CSR_CTL8 0x08 /* RW: extended global ctl bits */ 342#define T3CSR_STAT9 0x09 /* RL: extended status bits */ 343#define T3CSR_FERR 0x0A /* RC: F-bit Error Counter */ 344#define T3CSR_MERR 0x0B /* RC: M-bit Error Counter */ 345#define T3CSR_CTL12 0x0C /* RW: more extended ctl bits */ 346#define T3CSR_DBL_FEAC 0x0D /* RW: TX double FEAC */ 347#define T3CSR_CTL14 0x0E /* RW: even more extended ctl bits */ 348#define T3CSR_FEAC_STK 0x0F /* RO: RX FEAC stack */ 349#define T3CSR_STAT16 0x10 /* RL: extended latched status */ 350#define T3CSR_INTEN 0x11 /* RW: interrupt enable */ 351#define T3CSR_CVLO 0x12 /* RC: coding violation cntr LSB */ 352#define T3CSR_CVHI 0x13 /* RC: coding violation cntr MSB */ 353#define T3CSR_CTL20 0x14 /* RW: yet more extended ctl bits */ 354 355#define CTL1_XTX 0x01 /* Transmit X-bit value */ 356#define CTL1_3LOOP 0x02 /* framer loop back */ 357#define CTL1_SER 0x04 /* SERial interface selected */ 358#define CTL1_M13MODE 0x08 /* M13 frame format */ 359#define CTL1_TXIDL 0x10 /* Transmit Idle signal */ 360#define CTL1_ENAIS 0x20 /* Enable AIS upon LOS */ 361#define CTL1_TXAIS 0x40 /* Transmit Alarm Indication Sig */ 362#define CTL1_NOFEBE 0x80 /* No Far End Block Errors */ 363 364#define CTL5_EMODE 0x80 /* rev B Extended features enabled */ 365#define CTL5_START 0x40 /* transmit the FEAC msg now */ 366 367#define CTL8_FBEC 0x80 /* F-Bit Error Count control */ 368#define CTL8_TBLU 0x20 /* Transmit Blue signal */ 369 370#define STAT9_SEF 0x80 /* Severely Errored Frame */ 371#define STAT9_RBLU 0x20 /* Receive Blue signal */ 372 373#define CTL12_RTPLLEN 0x80 /* Rx-to-Tx Payload Lpbk Lock ENbl */ 374#define CTL12_RTPLOOP 0x40 /* Rx-to-Tx Payload Loopback */ 375#define CTL12_DLCB1 0x08 /* Data Link C-Bits forced to 1 */ 376#define CTL12_C21 0x04 /* C2 forced to 1 */ 377#define CTL12_MCB1 0x02 /* Most C-Bits forced to 1 */ 378 379#define CTL13_DFEXEC 0x40 /* Execute Double FEAC */ 380 381#define CTL14_FEAC10 0x80 /* Transmit FEAC word 10 times */ 382#define CTL14_RGCEN 0x20 /* Receive Gapped Clock Out Enbl */ 383#define CTL14_TGCEN 0x10 /* Timing Gen Gapped Clk Out Enbl */ 384 385#define FEAC_STK_MORE 0x80 /* FEAC stack has more FEACs */ 386#define FEAC_STK_VALID 0x40 /* FEAC stack is valid */ 387#define FEAC_STK_FEAC 0x3F /* FEAC stack FEAC data */ 388 389#define STAT16_XERR 0x01 /* X-bit Error */ 390#define STAT16_SEF 0x02 /* Severely Errored Frame */ 391#define STAT16_RTLOC 0x04 /* Rx/Tx Loss Of Clock */ 392#define STAT16_FEAC 0x08 /* new FEAC msg */ 393#define STAT16_RIDL 0x10 /* channel IDLe signal */ 394#define STAT16_RAIS 0x20 /* Alarm Indication Signal */ 395#define STAT16_ROOF 0x40 /* Out Of Frame sync */ 396#define STAT16_RLOS 0x80 /* Loss Of Signal */ 397 398#define CTL20_CVEN 0x01 /* Coding Violation Counter Enbl */ 399 400/* T1.107 Bit Oriented C-Bit Parity Far End Alarm Control and Status codes */ 401#define T3BOP_OOF 0x00 /* Yellow alarm status */ 402#define T3BOP_LINE_UP 0x07 /* line loopback activate */ 403#define T3BOP_LINE_DOWN 0x1C /* line loopback deactivate */ 404#define T3BOP_LOOP_DS3 0x1B /* loopback full DS3 */ 405#define T3BOP_IDLE 0x1A /* IDLE alarm status */ 406#define T3BOP_AIS 0x16 /* AIS alarm status */ 407#define T3BOP_LOS 0x0E /* LOS alarm status */ 408 409/* T1E1 regs; RW=Read/Write; RO=Read-Only; RC=Read/Clr; WO=Write-Only */ 410#define Bt8370_DID 0x000 /* RO: Device ID */ 411#define Bt8370_CR0 0x001 /* RW; Primary Control Register */ 412#define Bt8370_JAT_CR 0x002 /* RW: Jitter Attenuator CR */ 413#define Bt8370_IRR 0x003 /* RO: Interrupt Request Reg */ 414#define Bt8370_ISR7 0x004 /* RC: Alarm 1 Interrupt Status */ 415#define Bt8370_ISR6 0x005 /* RC: Alarm 2 Interrupt Status */ 416#define Bt8370_ISR5 0x006 /* RC: Error Interrupt Status */ 417#define Bt8370_ISR4 0x007 /* RC; Cntr Ovfl Interrupt Status */ 418#define Bt8370_ISR3 0x008 /* RC: Timer Interrupt Status */ 419#define Bt8370_ISR2 0x009 /* RC: Data Link 1 Int Status */ 420#define Bt8370_ISR1 0x00A /* RC: Data Link 2 Int Status */ 421#define Bt8370_ISR0 0x00B /* RC: Pattrn Interrupt Status */ 422#define Bt8370_IER7 0x00C /* RW: Alarm 1 Interrupt Enable */ 423#define Bt8370_IER6 0x00D /* RW: Alarm 2 Interrupt Enable */ 424#define Bt8370_IER5 0x00E /* RW: Error Interrupt Enable */ 425#define Bt8370_IER4 0x00F /* RW: Cntr Ovfl Interrupt Enable */ 426 427#define Bt8370_IER3 0x010 /* RW: Timer Interrupt Enable */ 428#define Bt8370_IER2 0x011 /* RW: Data Link 1 Int Enable */ 429#define Bt8370_IER1 0x012 /* RW: Data Link 2 Int Enable */ 430#define Bt8370_IER0 0x013 /* RW: Pattern Interrupt Enable */ 431#define Bt8370_LOOP 0x014 /* RW: Loopback Config Reg */ 432#define Bt8370_DL3_TS 0x015 /* RW: External Data Link Channel */ 433#define Bt8370_DL3_BIT 0x016 /* RW: External Data Link Bit */ 434#define Bt8370_FSTAT 0x017 /* RO: Offline Framer Status */ 435#define Bt8370_PIO 0x018 /* RW: Programmable Input/Output */ 436#define Bt8370_POE 0x019 /* RW: Programmable Output Enable */ 437#define Bt8370_CMUX 0x01A /* RW: Clock Input Mux */ 438#define Bt8370_TMUX 0x01B /* RW: Test Mux Config */ 439#define Bt8370_TEST 0x01C /* RW: Test Config */ 440 441#define Bt8370_LIU_CR 0x020 /* RW: Line Intf Unit Config Reg */ 442#define Bt8370_RSTAT 0x021 /* RO; Receive LIU Status */ 443#define Bt8370_RLIU_CR 0x022 /* RW: Receive LIU Config */ 444#define Bt8370_LPF 0x023 /* RW: RPLL Low Pass Filter */ 445#define Bt8370_VGA_MAX 0x024 /* RW: Variable Gain Amplifier Max */ 446#define Bt8370_EQ_DAT 0x025 /* RW: Equalizer Coeff Data Reg */ 447#define Bt8370_EQ_PTR 0x026 /* RW: Equzlizer Coeff Table Ptr */ 448#define Bt8370_DSLICE 0x027 /* RW: Data Slicer Threshold */ 449#define Bt8370_EQ_OUT 0x028 /* RW: Equalizer Output Levels */ 450#define Bt8370_VGA 0x029 /* RO: Variable Gain Ampl Status */ 451#define Bt8370_PRE_EQ 0x02A /* RW: Pre-Equalizer */ 452 453#define Bt8370_COEFF0 0x030 /* RO: LMS Adj Eq Coeff Status */ 454#define Bt8370_GAIN0 0x038 /* RW: Equalizer Gain Thresh */ 455#define Bt8370_GAIN1 0x039 /* RW: Equalizer Gain Thresh */ 456#define Bt8370_GAIN2 0x03A /* RW: Equalizer Gain Thresh */ 457#define Bt8370_GAIN3 0x03B /* RW: Equalizer Gain Thresh */ 458#define Bt8370_GAIN4 0x03C /* RW: Equalizer Gain Thresh */ 459 460#define Bt8370_RCR0 0x040 /* RW: Rx Configuration */ 461#define Bt8370_RPATT 0x041 /* RW: Rx Test Pattern Config */ 462#define Bt8370_RLB 0x042 /* RW: Rx Loopback Code Detr Conf */ 463#define Bt8370_LBA 0x043 /* RW: Loopback Activate Code Patt */ 464#define Bt8370_LBD 0x044 /* RW: Loopback Deact Code Patt */ 465#define Bt8370_RALM 0x045 /* RW: Rx Alarm Signal Config */ 466#define Bt8370_LATCH 0x046 /* RW: Alarm/Err/Cntr Latch Config */ 467#define Bt8370_ALM1 0x047 /* RO: Alarm 1 Status */ 468#define Bt8370_ALM2 0x048 /* RO: Alarm 2 Status */ 469#define Bt8370_ALM3 0x049 /* RO: Alarm 3 Status */ 470 471#define Bt8370_FERR_LO 0x050 /* RC: Framing Bit Error Cntr LSB */ 472#define Bt8370_FERR_HI 0x051 /* RC: Framing Bit Error Cntr MSB */ 473#define Bt8370_CRC_LO 0x052 /* RC: CRC Error Counter LSB */ 474#define Bt8370_CRC_HI 0x053 /* RC: CRC Error Counter MSB */ 475#define Bt8370_LCV_LO 0x054 /* RC: Line Code Viol Counter LSB */ 476#define Bt8370_LCV_HI 0x055 /* RC: Line Code Viol Counter MSB */ 477#define Bt8370_FEBE_LO 0x056 /* RC: Far End Block Err Cntr LSB */ 478#define Bt8370_FEBE_HI 0x057 /* RC: Far End Block Err Cntr MSB */ 479#define Bt8370_BERR_LO 0x058 /* RC: PRBS Bit Error Counter LSB */ 480#define Bt8370_BERR_HI 0x059 /* RC: PRBS Bit Error Counter MSB */ 481#define Bt8370_AERR 0x05A /* RC: SEF/LOF/COFA counter */ 482#define Bt8370_RSA4 0x05B /* RO: Rx Sa4 Byte Buffer */ 483#define Bt8370_RSA5 0x05C /* RO: Rx Sa5 Byte Buffer */ 484#define Bt8370_RSA6 0x05D /* RO: Rx Sa6 Byte Buffer */ 485#define Bt8370_RSA7 0x05E /* RO: Rx Sa7 Byte Buffer */ 486#define Bt8370_RSA8 0x05F /* RO: Rx Sa8 Byte Buffer */ 487 488#define Bt8370_SHAPE0 0x060 /* RW: Tx Pulse Shape Config */ 489#define Bt8370_TLIU_CR 0x068 /* RW: Tx LIU Config Reg */ 490 491#define Bt8370_TCR0 0x070 /* RW: Tx Framer Config */ 492#define Bt8370_TCR1 0x071 /* RW: Txter Configuration */ 493#define Bt8370_TFRM 0x072 /* RW: Tx Frame Format */ 494#define Bt8370_TERROR 0x073 /* RW: Tx Error Insert */ 495#define Bt8370_TMAN 0x074 /* RW: Tx Manual Sa/FEBE Config */ 496#define Bt8370_TALM 0x075 /* RW: Tx Alarm Signal Config */ 497#define Bt8370_TPATT 0x076 /* RW: Tx Test Pattern Config */ 498#define Bt8370_TLB 0x077 /* RW: Tx Inband Loopback Config */ 499#define Bt8370_LBP 0x078 /* RW: Tx Inband Loopback Patt */ 500#define Bt8370_TSA4 0x07B /* RW: Tx Sa4 Byte Buffer */ 501#define Bt8370_TSA5 0x07C /* RW: Tx Sa5 Byte Buffer */ 502#define Bt8370_TSA6 0x07D /* RW: Tx Sa6 Byte Buffer */ 503#define Bt8370_TSA7 0x07E /* RW: Tx Sa7 Byte Buffer */ 504#define Bt8370_TSA8 0x07F /* RW: Tx Sa8 Byte Buffer */ 505 506#define Bt8370_CLAD_CR 0x090 /* RW: Clock Rate Adapter Config */ 507#define Bt8370_CSEL 0x091 /* RW: CLAD Frequency Select */ 508#define Bt8370_CPHASE 0x092 /* RW: CLAD Phase Det Scale Factor */ 509#define Bt8370_CTEST 0x093 /* RW: CLAD Test */ 510 511#define Bt8370_BOP 0x0A0 /* RW: Bit Oriented Protocol Xcvr */ 512#define Bt8370_TBOP 0x0A1 /* RW: Tx BOP Codeword */ 513#define Bt8370_RBOP 0x0A2 /* RO; Rx BOP Codeword */ 514#define Bt8370_BOP_STAT 0x0A3 /* RO: BOP Status */ 515#define Bt8370_DL1_TS 0x0A4 /* RW: DL1 Time Slot Enable */ 516#define Bt8370_DL1_BIT 0x0A5 /* RW: DL1 Bit Enable */ 517#define Bt8370_DL1_CTL 0x0A6 /* RW: DL1 Control */ 518#define Bt8370_RDL1_FFC 0x0A7 /* RW: RDL1 FIFO Fill Control */ 519#define Bt8370_RDL1 0x0A8 /* RO: RDL1 FIFO */ 520#define Bt8370_RDL1_STAT 0x0A9 /* RO: RDL1 Status */ 521#define Bt8370_PRM 0x0AA /* RW: Performance Report Message */ 522#define Bt8370_TDL1_FEC 0x0AB /* RW: TDL1 FIFO Empty Control */ 523#define Bt8370_TDL1_EOM 0x0AC /* WO: TDL1 End Of Message Control */ 524#define Bt8370_TDL1 0x0AD /* RW: TDL1 FIFO */ 525#define Bt8370_TDL1_STAT 0x0AE /* RO: TDL1 Status */ 526#define Bt8370_DL2_TS 0x0AF /* RW: DL2 Time Slot Enable */ 527 528#define Bt8370_DL2_BIT 0x0B0 /* RW: DL2 Bit Enable */ 529#define Bt8370_DL2_CTL 0x0B1 /* RW: DL2 Control */ 530#define Bt8370_RDL2_FFC 0x0B2 /* RW: RDL2 FIFO Fill Control */ 531#define Bt8370_RDL2 0x0B3 /* RO: RDL2 FIFO */ 532#define Bt8370_RDL2_STAT 0x0B4 /* RO: RDL2 Status */ 533#define Bt8370_TDL2_FEC 0x0B6 /* RW: TDL2 FIFO Empty Control */ 534#define Bt8370_TDL2_EOM 0x0B7 /* WO; TDL2 End Of Message Control */ 535#define Bt8370_TDL2 0x0B8 /* RW: TDL2 FIFO */ 536#define Bt8370_TDL2_STAT 0x0B9 /* RO: TDL2 Status */ 537#define Bt8370_DL_TEST1 0x0BA /* RW: DLINK Test Config */ 538#define Bt8370_DL_TEST2 0x0BB /* RW: DLINK Test Status */ 539#define Bt8370_DL_TEST3 0x0BC /* RW: DLINK Test Status */ 540#define Bt8370_DL_TEST4 0x0BD /* RW: DLINK Test Control */ 541#define Bt8370_DL_TEST5 0x0BE /* RW: DLINK Test Control */ 542 543#define Bt8370_SBI_CR 0x0D0 /* RW: System Bus Interface Config */ 544#define Bt8370_RSB_CR 0x0D1 /* RW: Rx System Bus Config */ 545#define Bt8370_RSYNC_BIT 0x0D2 /* RW: Rx System Bus Sync Bit Offs */ 546#define Bt8370_RSYNC_TS 0x0D3 /* RW: Rx System Bus Sync TS Offs */ 547#define Bt8370_TSB_CR 0x0D4 /* RW: Tx System Bus Config */ 548#define Bt8370_TSYNC_BIT 0x0D5 /* RW: Tx System Bus Sync Bit OFfs */ 549#define Bt8370_TSYNC_TS 0x0D6 /* RW: Tx System Bus Sync TS Offs */ 550#define Bt8370_RSIG_CR 0x0D7 /* RW: Rx Siganalling Config */ 551#define Bt8370_RSYNC_FRM 0x0D8 /* RW: Sig Reinsertion Frame Offs */ 552#define Bt8370_SSTAT 0x0D9 /* RO: Slip Buffer Status */ 553#define Bt8370_STACK 0x0DA /* RO: Rx Signalling Stack */ 554#define Bt8370_RPHASE 0x0DB /* RO: RSLIP Phase Status */ 555#define Bt8370_TPHASE 0x0DC /* RO: TSLIP Phase Status */ 556#define Bt8370_PERR 0x0DD /* RO: RAM Parity Status */ 557 558#define Bt8370_SBCn 0x0E0 /* RW: System Bus Per-Channel Ctl */ 559#define Bt8370_TPCn 0x100 /* RW: Tx Per-Channel Control */ 560#define Bt8370_TSIGn 0x120 /* RW: Tx Signalling Buffer */ 561#define Bt8370_TSLIP_LOn 0x140 /* RW: Tx PCM Slip Buffer Lo */ 562#define Bt8370_TSLIP_HIn 0x160 /* RW: Tx PCM Slip Buffer Hi */ 563#define Bt8370_RPCn 0x180 /* RW: Rx Per-Channel Control */ 564#define Bt8370_RSIGn 0x1A0 /* RW: Rx Signalling Buffer */ 565#define Bt8370_RSLIP_LOn 0x1C0 /* RW: Rx PCM Slip Buffer Lo */ 566#define Bt8370_RSLIP_HIn 0x1E0 /* RW: Rx PCM Slip Buffer Hi */ 567 568/* Bt8370_LOOP (0x14) framer loopback control register bits */ 569#define LOOP_ANALOG 0x01 /* inward loop thru LIU */ 570#define LOOP_FRAMER 0x02 /* inward loop thru framer */ 571#define LOOP_LINE 0x04 /* outward loop thru LIU */ 572#define LOOP_PAYLOAD 0x08 /* outward loop of payload */ 573#define LOOP_DUAL 0x06 /* inward framer + outward line */ 574 575/* Bt8370_ALM1 (0x47) receiver alarm status register bits */ 576#define ALM1_SIGFRZ 0x01 /* Rx Signalling Freeze */ 577#define ALM1_RLOF 0x02 /* Rx loss of frame alignment */ 578#define ALM1_RLOS 0x04 /* Rx digital loss of signal */ 579#define ALM1_RALOS 0x08 /* Rx analog loss of signal */ 580#define ALM1_RAIS 0x10 /* Rx Alarm Indication Signal */ 581#define ALM1_RYEL 0x40 /* Rx Yellow alarm indication */ 582#define ALM1_RMYEL 0x80 /* Rx multiframe YELLOW alarm */ 583 584/* Bt8370_ALM3 (0x49) receive framer status register bits */ 585#define ALM3_FRED 0x04 /* Rx Out Of T1/FAS alignment */ 586#define ALM3_MRED 0x08 /* Rx Out Of MFAS alignment */ 587#define ALM3_SRED 0x10 /* Rx Out Of CAS alignment */ 588#define ALM3_SEF 0x20 /* Rx Severely Errored Frame */ 589#define ALM3_RMAIS 0x40 /* Rx TS16 AIS (CAS) */ 590 591/* Bt8370_TALM (0x75) transmit alarm control register bits */ 592#define TALM_TAIS 0x01 /* Tx Alarm Indication Signal */ 593#define TALM_TYEL 0x02 /* Tx Yellow alarm */ 594#define TALM_TMYEL 0x04 /* Tx Multiframe Yellow alarm */ 595#define TALM_AUTO_AIS 0x08 /* auto send AIS on LOS */ 596#define TALM_AUTO_YEL 0x10 /* auto send YEL on LOF */ 597#define TALM_AUTO_MYEL 0x20 /* auto send E1-Y16 on loss-of-CAS */ 598 599/* 8370 BOP (Bit Oriented Protocol) command fragments */ 600#define RBOP_OFF 0x00 /* BOP Rx disabled */ 601#define RBOP_25 0xE0 /* BOP Rx requires 25 BOPs */ 602#define TBOP_OFF 0x00 /* BOP Tx disabled */ 603#define TBOP_25 0x0B /* BOP Tx sends 25 BOPs */ 604#define TBOP_CONT 0x0F /* BOP Tx sends continuously */ 605 606/* T1.403 Bit-Oriented ESF Data-Link Message codes */ 607#define T1BOP_OOF 0x00 /* Yellow alarm status */ 608#define T1BOP_LINE_UP 0x07 /* line loopback activate */ 609#define T1BOP_LINE_DOWN 0x1C /* line loopback deactivate */ 610#define T1BOP_PAY_UP 0x0A /* payload loopback activate */ 611#define T1BOP_PAY_DOWN 0x19 /* payload loopback deactivate */ 612#define T1BOP_NET_UP 0x09 /* network loopback activate */ 613#define T1BOP_NET_DOWN 0x12 /* network loopback deactivate */ 614 615/* Unix & Linux reserve 16 device-private IOCTLs */ 616#if BSD 617# define LMCIOCGSTAT _IOWR('i', 240, struct status) 618# define LMCIOCGCFG _IOWR('i', 241, struct config) 619# define LMCIOCSCFG _IOW('i', 242, struct config) 620# define LMCIOCREAD _IOWR('i', 243, struct ioctl) 621# define LMCIOCWRITE _IOW('i', 244, struct ioctl) 622# define LMCIOCTL _IOWR('i', 245, struct ioctl) 623#elif defined(__linux__) /* sigh */ 624# define LMCIOCGSTAT SIOCDEVPRIVATE+0 625# define LMCIOCGCFG SIOCDEVPRIVATE+1 626# define LMCIOCSCFG SIOCDEVPRIVATE+2 627# define LMCIOCREAD SIOCDEVPRIVATE+3 628# define LMCIOCWRITE SIOCDEVPRIVATE+4 629# define LMCIOCTL SIOCDEVPRIVATE+5 630#endif 631 632struct iohdr /* all LMCIOCs begin with this */ 633 { 634 char ifname[IFNAMSIZ]; /* interface name, e.g. "lmc0" */ 635 u_int32_t cookie; /* interface version number */ 636 u_int16_t direction; /* missing in Linux IOCTL */ 637 u_int16_t length; /* missing in Linux IOCTL */ 638 struct iohdr *iohdr; /* missing in Linux IOCTL */ 639 u_int32_t spare; /* pad this struct to **32 bytes** */ 640 }; 641 642#define DIR_IO 0 643#define DIR_IOW 1 /* copy data user->kernel */ 644#define DIR_IOR 2 /* copy data kernel->user */ 645#define DIR_IOWR 3 /* copy data kernel<->user */ 646 647struct hssi_snmp 648 { 649 u_int16_t sigs; /* MII16_HSSI & MII16_HSSI_MODEM */ 650 }; 651 652struct ssi_snmp 653 { 654 u_int16_t sigs; /* MII16_SSI & MII16_SSI_MODEM */ 655 }; 656 657struct t3_snmp 658 { 659 u_int16_t febe; /* 8 bits - Far End Block err cnt */ 660 u_int16_t lcv; /* 16 bits - BPV err cnt */ 661 u_int16_t pcv; /* 8 bits - P-bit err cnt */ 662 u_int16_t ccv; /* 8 bits - C-bit err cnt */ 663 u_int16_t line; /* line status bit vector */ 664 u_int16_t loop; /* loop status bit vector */ 665 }; 666 667struct t1_snmp 668 { 669 u_int16_t prm[4]; /* T1.403 Performance Report Msg */ 670 u_int16_t febe; /* 10 bits - E1 FAR CRC err cnt */ 671 u_int16_t lcv; /* 16 bits - BPV + EXZ err cnt */ 672 u_int16_t fe; /* 12 bits - Ft/Fs/FPS/FAS err cnt */ 673 u_int16_t crc; /* 10 bits - CRC6/CRC4 err cnt */ 674 u_int16_t line; /* line status bit vector */ 675 u_int16_t loop; /* loop status bit vector */ 676 }; 677 678/* SNMP trunk MIB Send codes */ 679#define TSEND_NORMAL 1 /* Send data (normal or looped) */ 680#define TSEND_LINE 2 /* Send 'line loopback activate' */ 681#define TSEND_PAYLOAD 3 /* Send 'payload loop activate' */ 682#define TSEND_RESET 4 /* Send 'loopback deactivate' */ 683#define TSEND_QRS 5 /* Send Quasi Random Signal */ 684 685/* ANSI T1.403 Performance Report Msg -- once a second from the far end */ 686#define T1PRM_FE 0x8000 /* Frame Sync Bit Error Event >= 1 */ 687#define T1PRM_SE 0x4000 /* Severely Err Framing Event >= 1 */ 688#define T1PRM_LB 0x2000 /* Payload Loopback Activated */ 689#define T1PRM_G1 0x1000 /* CRC Error Event = 1 */ 690#define T1PRM_R 0x0800 /* Reserved */ 691#define T1PRM_G2 0x0400 /* 1 < CRC Error Event <= 5 */ 692#define T1PRM_SEQ 0x0300 /* modulo 4 counter */ 693#define T1PRM_G3 0x0080 /* 5 < CRC Error Event <= 10 */ 694#define T1PRM_LV 0x0040 /* Line Code Violation Event >= 1 */ 695#define T1PRM_G4 0x0020 /* 10 < CRC Error Event <= 100 */ 696#define T1PRM_U 0x0018 /* Under study for synchronization */ 697#define T1PRM_G5 0x0004 /* 100 < CRC Error Event <= 319 */ 698#define T1PRM_SL 0x0002 /* Slip Event >= 1 */ 699#define T1PRM_G6 0x0001 /* CRC Error Event >= 320 */ 700 701/* SNMP Line Status */ 702#define TLINE_NORM 0x0001 /* no alarm present */ 703#define TLINE_RX_RAI 0x0002 /* receiving RAI = Yellow alarm */ 704#define TLINE_TX_RAI 0x0004 /* sending RAI = Yellow alarm */ 705#define TLINE_RX_AIS 0x0008 /* receiving AIS = blue alarm */ 706#define TLINE_TX_AIS 0x0010 /* sending AIS = blue alarm */ 707#define TLINE_LOF 0x0020 /* near end LOF = red alarm */ 708#define TLINE_LOS 0x0040 /* near end loss of Signal */ 709#define TLINE_LOOP 0x0080 /* near end is looped */ 710#define T1LINE_RX_TS16_AIS 0x0100 /* near end receiving TS16 AIS */ 711#define T1LINE_RX_TS16_LOMF 0x0200 /* near end sending TS16 LOMF */ 712#define T1LINE_TX_TS16_LOMF 0x0400 /* near end receiving TS16 LOMF */ 713#define T1LINE_RX_TEST 0x0800 /* near end receiving QRS Signal */ 714#define T1LINE_SEF 0x1000 /* near end severely errored frame */ 715#define T3LINE_RX_IDLE 0x0100 /* near end receiving IDLE signal */ 716#define T3LINE_SEF 0x0200 /* near end severely errored frame */ 717 718/* SNMP Loopback Status */ 719#define TLOOP_NONE 0x01 /* no loopback */ 720#define TLOOP_NEAR_PAYLOAD 0x02 /* near end payload loopback */ 721#define TLOOP_NEAR_LINE 0x04 /* near end line loopback */ 722#define TLOOP_NEAR_OTHER 0x08 /* near end looped somehow */ 723#define TLOOP_NEAR_INWARD 0x10 /* near end looped inward */ 724#define TLOOP_FAR_PAYLOAD 0x20 /* far end payload loopback */ 725#define TLOOP_FAR_LINE 0x40 /* far end line loopback */ 726 727/* event counters record interesting statistics */ 728struct event_cntrs 729 { 730 struct timeval reset_time; /* time when cntrs were reset */ 731 u_int64_t ibytes; /* Rx bytes with good status */ 732 u_int64_t obytes; /* Tx bytes */ 733 u_int64_t ipackets; /* Rx packets with good status */ 734 u_int64_t opackets; /* Tx packets */ 735 u_int32_t ierrors; /* Rx packets with bad status */ 736 u_int32_t oerrors; /* Tx packets with bad status */ 737 u_int32_t idiscards; /* Rx packets discarded */ 738 u_int32_t odiscards; /* Tx packets discarded */ 739 u_int32_t fifo_over; /* Rx fifo overruns */ 740 u_int32_t fifo_under; /* Tx fifo underruns */ 741 u_int32_t missed; /* Rx pkts missed: no DMA descs */ 742 u_int32_t overruns; /* Rx pkts missed: fifo overrun */ 743 u_int32_t fdl_pkts; /* Rx T1 Facility Data Link pkts */ 744 u_int32_t crc_errs; /* Rx T1 frame CRC errors */ 745 u_int32_t lcv_errs; /* Rx T1 T3 Line Coding Violation */ 746 u_int32_t frm_errs; /* Rx T1 T3 Frame bit errors */ 747 u_int32_t febe_errs; /* Rx T1 T3 Far End Bit Errors */ 748 u_int32_t par_errs; /* Rx T3 P-bit parity errors */ 749 u_int32_t cpar_errs; /* Rx T3 C-bit parity errors */ 750 u_int32_t mfrm_errs; /* Rx T3 Multi-frame bit errors */ 751 u_int32_t rxdma; /* Rx out of kernel buffers */ 752 u_int32_t txdma; /* Tx out of DMA desciptors */ 753 u_int32_t lck_watch; /* try_lock conflict in watchdog */ 754 u_int32_t lck_ioctl; /* try_lock conflict in ioctl */ 755 u_int32_t lck_intr; /* try_lock conflict in interrupt */ 756 }; 757 758/* sc->status is the READ ONLY status of the card. */ 759/* Accessed using socket IO control calls or netgraph control messages. */ 760struct status 761 { 762 struct iohdr iohdr; /* common ioctl header */ 763 u_int32_t card_type; /* PCI device number */ 764 u_int16_t ieee[3]; /* IEEE MAC-addr from Tulip SROM */ 765 u_int16_t oper_status; /* actual state: up, down, test */ 766 u_int32_t tx_speed; /* measured TX bits/sec */ 767 u_int32_t cable_type; /* SSI only: cable type */ 768 u_int32_t line_pkg; /* actual line pkg in use */ 769 u_int32_t line_prot; /* actual line proto in use */ 770 u_int32_t ticks; /* incremented by watchdog @ 1 Hz */ 771 struct event_cntrs cntrs; /* event counters */ 772 union 773 { 774 struct hssi_snmp hssi; /* data for RFC-???? HSSI MIB */ 775 struct t3_snmp t3; /* data for RFC-2496 T3 MIB */ 776 struct ssi_snmp ssi; /* data for RFC-1659 RS232 MIB */ 777 struct t1_snmp t1; /* data for RFC-2495 T1 MIB */ 778 } snmp; 779 }; 780 781/* line protocol package codes fnobl */ 782#define PKG_RAWIP 1 /* driver yyyyy */ 783#define PKG_SPPP 2 /* fbsd, nbsd, obsd yyynn */ 784#define PKG_P2P 3 /* bsd/os nnnyn */ 785#define PKG_NG 4 /* fbsd ynnnn */ 786#define PKG_GEN_HDLC 5 /* linux nnnny */ 787 788/* line protocol codes fnobl */ 789#define PROT_PPP 1 /* Point-to-Point Protocol yyyyy */ 790#define PROT_C_HDLC 2 /* Cisco HDLC Protocol yyyyy */ 791#define PROT_FRM_RLY 3 /* Frame Relay Protocol ynnyy */ 792#define PROT_X25 4 /* X.25/LAPB Protocol nnnny */ 793#define PROT_ETH_HDLC 5 /* raw Ether pkts in HDLC nnnny */ 794#define PROT_IP_HDLC 6 /* raw IP4/6 pkts in HDLC yyyyy */ 795 796/* oper_status codes (same as SNMP status codes) */ 797#define STATUS_UP 1 /* may/will tx/rx pkts */ 798#define STATUS_DOWN 2 /* can't/won't tx/rx pkts */ 799#define STATUS_TEST 3 /* currently not used */ 800 801struct synth /* programmable oscillator params */ 802 { 803 unsigned n :7; /* numerator (3..127) */ 804 unsigned m :7; /* denominator (3..127) */ 805 unsigned v :1; /* mul by 1|8 */ 806 unsigned x :2; /* div by 1|2|4|8 */ 807 unsigned r :2; /* div by 1|2|4|8 */ 808 unsigned prescale :13; /* log(final divisor): 2, 4 or 9 */ 809 } __attribute__ ((packed)); 810 811#define SYNTH_FREF 20e6 /* reference xtal = 20 MHz */ 812#define SYNTH_FMIN 50e6 /* internal VCO min 50 MHz */ 813#define SYNTH_FMAX 250e6 /* internal VCO max 250 MHz */ 814 815/* sc->config is the READ/WRITE configuration of the card. */ 816/* Accessed using socket IO control calls or netgraph control messages. */ 817struct config 818 { 819 struct iohdr iohdr; /* common ioctl header */ 820 u_int32_t crc_len; /* ALL: CRC-16 or CRC-32 or none */ 821 u_int32_t loop_back; /* ALL: many kinds of loopbacks */ 822 u_int32_t tx_clk_src; /* T1, HSSI: ST, RT, int, ext */ 823 u_int32_t format; /* T3, T1: ckt framing format */ 824 u_int32_t time_slots; /* T1: 64Kb time slot config */ 825 u_int32_t cable_len; /* T3, T1: cable length in meters */ 826 u_int32_t scrambler; /* T3: payload scrambler config */ 827 u_int32_t dte_dce; /* SSI, HSSIc: drive TXCLK */ 828 struct synth synth; /* SSI, HSSIc: synth oscil params */ 829 u_int32_t rx_gain; /* T1: receiver gain limit 0-50 dB */ 830 u_int32_t tx_pulse; /* T1: transmitter pulse shape */ 831 u_int32_t tx_lbo; /* T1: transmitter atten 0-22.5 dB */ 832 u_int32_t debug; /* ALL: extra printout */ 833 u_int32_t line_pkg; /* ALL: use this line pkg */ 834 u_int32_t line_prot; /* SPPP: use this line proto */ 835 u_int32_t keep_alive; /* SPPP: use keep-alive packets */ 836 }; 837 838#define CFG_CRC_0 0 /* no CRC */ 839#define CFG_CRC_16 2 /* X^16+X^12+X^5+1 (default) */ 840#define CFG_CRC_32 4 /* X^32+X^26+X^23+X^22+X^16+X^12+ */ 841 /* X^11+X^10+X^8+X^7+X^5+X^4+X^2+X+1 */ 842#define CFG_LOOP_NONE 1 /* SNMP don't loop back anything */ 843#define CFG_LOOP_PAYLOAD 2 /* SNMP loop outward thru framer */ 844#define CFG_LOOP_LINE 3 /* SNMP loop outward thru LIU */ 845#define CFG_LOOP_OTHER 4 /* SNMP loop inward thru LIU */ 846#define CFG_LOOP_INWARD 5 /* SNMP loop inward thru framer */ 847#define CFG_LOOP_DUAL 6 /* SNMP loop inward & outward */ 848#define CFG_LOOP_TULIP 16 /* ALL: loop inward thru Tulip */ 849#define CFG_LOOP_PINS 17 /* HSSIc, SSI: loop inward-pins */ 850#define CFG_LOOP_LL 18 /* HSSI, SSI: assert LA/LL mdm pin */ 851#define CFG_LOOP_RL 19 /* HSSI, SSI: assert LB/RL mdm pin */ 852 853#define CFG_CLKMUX_ST 1 /* TX clk <- Send timing */ 854#define CFG_CLKMUX_INT 2 /* TX clk <- internal source */ 855#define CFG_CLKMUX_RT 3 /* TX clk <- Receive (loop) timing */ 856#define CFG_CLKMUX_EXT 4 /* TX clk <- ext connector */ 857 858/* values 0-31 are Bt8370 CR0 register values (LSB is zero if E1). */ 859/* values 32-99 are reserved for other T1E1 formats, (even number if E1) */ 860/* values 100 and up are used for T3 frame formats. */ 861#define CFG_FORMAT_T1SF 9 /* T1-SF AMI */ 862#define CFG_FORMAT_T1ESF 27 /* T1-ESF+CRC B8ZS X^6+X+1 */ 863#define CFG_FORMAT_E1FAS 0 /* E1-FAS HDB3 TS0 */ 864#define CFG_FORMAT_E1FASCRC 8 /* E1-FAS+CRC HDB3 TS0 X^4+X+1 */ 865#define CFG_FORMAT_E1FASCAS 16 /* E1-FAS +CAS HDB3 TS0 & TS16 */ 866#define CFG_FORMAT_E1FASCRCCAS 24 /* E1-FAS+CRC+CAS HDB3 TS0 & TS16 */ 867#define CFG_FORMAT_E1NONE 32 /* E1-NO framing HDB3 */ 868#define CFG_FORMAT_T3CPAR 100 /* T3-C-Bit par B3ZS */ 869#define CFG_FORMAT_T3M13 101 /* T3-M13 format B3ZS */ 870 871/* format aliases that improve code readability */ 872#define FORMAT_T1ANY ((sc->config.format & 1)==1) 873#define FORMAT_E1ANY ((sc->config.format & 1)==0) 874#define FORMAT_E1CAS ((sc->config.format & 0x11)==0x10) 875#define FORMAT_E1CRC ((sc->config.format & 0x09)==0x08) 876#define FORMAT_E1NONE (sc->config.format == CFG_FORMAT_E1NONE) 877#define FORMAT_T1ESF (sc->config.format == CFG_FORMAT_T1ESF) 878#define FORMAT_T1SF (sc->config.format == CFG_FORMAT_T1SF) 879#define FORMAT_T3CPAR (sc->config.format == CFG_FORMAT_T3CPAR) 880 881#define CFG_SCRAM_OFF 1 /* DS3 payload scrambler off */ 882#define CFG_SCRAM_DL_KEN 2 /* DS3 DigitalLink/Kentrox X^43+1 */ 883#define CFG_SCRAM_LARS 3 /* DS3 Larscom X^20+X^17+1 w/28ZS */ 884 885#define CFG_DTE 1 /* HSSIc, SSI: rcv TXCLK; rcv DCD */ 886#define CFG_DCE 2 /* HSSIc, SSI: drv TXCLK; drv DCD */ 887 888#define CFG_GAIN_SHORT 0x24 /* 0-20 dB of equalized gain */ 889#define CFG_GAIN_MEDIUM 0x2C /* 0-30 dB of equalized gain */ 890#define CFG_GAIN_LONG 0x34 /* 0-40 dB of equalized gain */ 891#define CFG_GAIN_EXTEND 0x3F /* 0-64 dB of equalized gain */ 892#define CFG_GAIN_AUTO 0xFF /* auto-set based on cable length */ 893 894#define CFG_PULSE_T1DSX0 0 /* T1 DSX 0- 40 meters */ 895#define CFG_PULSE_T1DSX1 2 /* T1 DSX 40- 80 meters */ 896#define CFG_PULSE_T1DSX2 4 /* T1 DSX 80-120 meters */ 897#define CFG_PULSE_T1DSX3 6 /* T1 DSX 120-160 meters */ 898#define CFG_PULSE_T1DSX4 8 /* T1 DSX 160-200 meters */ 899#define CFG_PULSE_E1COAX 10 /* E1 75 ohm coax pair */ 900#define CFG_PULSE_E1TWIST 12 /* E1 120 ohm twisted pairs */ 901#define CFG_PULSE_T1CSU 14 /* T1 CSU 200-2000 meters; set LBO */ 902#define CFG_PULSE_AUTO 0xFF /* auto-set based on cable length */ 903 904#define CFG_LBO_0DB 0 /* T1CSU LBO = 0.0 dB; FCC opt A */ 905#define CFG_LBO_7DB 16 /* T1CSU LBO = 7.5 dB; FCC opt B */ 906#define CFG_LBO_15DB 32 /* T1CSU LBO = 15.0 dB; FCC opt C */ 907#define CFG_LBO_22DB 48 /* T1CSU LBO = 22.5 dB; final span */ 908#define CFG_LBO_AUTO 0xFF /* auto-set based on cable length */ 909 910struct ioctl 911 { 912 struct iohdr iohdr; /* common ioctl header */ 913 u_int32_t cmd; /* command */ 914 u_int32_t address; /* command address */ 915 u_int32_t data; /* command data */ 916 char *ucode; /* user-land address of ucode */ 917 }; 918 919#define IOCTL_RW_PCI 1 /* RW: Tulip PCI config registers */ 920#define IOCTL_RW_CSR 2 /* RW: Tulip Control & Status Regs */ 921#define IOCTL_RW_SROM 3 /* RW: Tulip Serial Rom */ 922#define IOCTL_RW_BIOS 4 /* RW: Tulip Boot rom */ 923#define IOCTL_RW_MII 5 /* RW: MII registers */ 924#define IOCTL_RW_FRAME 6 /* RW: Framer registers */ 925#define IOCTL_WO_SYNTH 7 /* WO: Synthesized oscillator */ 926#define IOCTL_WO_DAC 8 /* WO: Digital/Analog Converter */ 927 928#define IOCTL_XILINX_RESET 16 /* reset Xilinx: all FFs set to 0 */ 929#define IOCTL_XILINX_ROM 17 /* load Xilinx program from ROM */ 930#define IOCTL_XILINX_FILE 18 /* load Xilinx program from file */ 931 932#define IOCTL_SET_STATUS 50 /* set mdm ctrl bits (internal use)*/ 933#define IOCTL_SNMP_SEND 51 /* trunk MIB send code */ 934#define IOCTL_SNMP_LOOP 52 /* trunk MIB loop configuration */ 935#define IOCTL_SNMP_SIGS 53 /* RS232-like modem control sigs */ 936#define IOCTL_RESET_CNTRS 54 /* reset event counters */ 937 938/* storage for these strings is allocated here! */ 939const char *ssi_cables[] = 940 { 941 "V.10/EIA423", 942 "V.11/EIA530A", 943 "RESERVED", 944 "X.21", 945 "V.35", 946 "V.36/EIA449", 947 "V.28/EIA232", 948 "NO CABLE", 949 NULL, 950 }; 951 952/***************************************************************************/ 953/* Declarations above here are shared with the user lmcconfig program. */ 954/* Declarations below here are private to the kernel device driver. */ 955/***************************************************************************/ 956 957#if (_KERNEL || KERNEL || __KERNEL__) 958 959#define SNDQ_MAXLEN 32 /* packets awaiting transmission */ 960#define DESCS_PER_PKT 4 /* DMA descriptors per TX pkt */ 961#define NUM_TX_DESCS (DESCS_PER_PKT * SNDQ_MAXLEN) 962/* Increase DESCS_PER_PKT if status.cntrs.txdma increments. */ 963 964/* A Tulip DMA descriptor can point to two chunks of memory. 965 * Each chunk has a max length of 2047 bytes (ask the VMS guys...). 966 * 2047 isn't a multiple of a cache line size (32 bytes typically). 967 * So back off to 2048-32 = 2016 bytes per chunk (2 chunks per descr). 968 */ 969#define MAX_CHUNK_LEN 2016 970#define MAX_DESC_LEN (2 * MAX_CHUNK_LEN) 971 972/* Tulip DMA descriptor; THIS STRUCT MUST MATCH THE HARDWARE */ 973struct dma_desc 974 { 975 u_int32_t status; /* hardware->to->software */ 976#if (BYTE_ORDER == LITTLE_ENDIAN) /* left-to-right packing by compiler */ 977 unsigned length1:11; /* buffer1 length */ 978 unsigned length2:11; /* buffer2 length */ 979 unsigned control:10; /* software->to->hardware */ 980#else /* right-to-left packing by compiler */ 981 unsigned control:10; /* software->to->hardware */ 982 unsigned length2:11; /* buffer2 length */ 983 unsigned length1:11; /* buffer1 length */ 984#endif 985 u_int32_t address1; /* buffer1 bus address */ 986 u_int32_t address2; /* buffer2 bus address */ 987#if (defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__)) 988 bus_dmamap_t map; /* bus dmamap for this descriptor */ 989# define TLP_BUS_DSL_VAL (sizeof(bus_dmamap_t) & TLP_BUS_DSL) 990#else 991# define TLP_BUS_DSL_VAL 0 992#endif 993 } __attribute__ ((packed)); 994 995/* Tulip DMA descriptor status bits */ 996#define TLP_DSTS_OWNER 0x80000000 997#define TLP_DSTS_RX_DESC_ERR 0x00004000 998#define TLP_DSTS_RX_FIRST_DESC 0x00000200 999#define TLP_DSTS_RX_LAST_DESC 0x00000100 1000#define TLP_DSTS_RX_MII_ERR 0x00000008 1001#define TLP_DSTS_RX_DRIBBLE 0x00000004 1002#define TLP_DSTS_TX_UNDERRUN 0x00000002 1003#define TLP_DSTS_RX_OVERRUN 0x00000001 /* not documented in rev AF */ 1004#define TLP_DSTS_RX_BAD (TLP_DSTS_RX_MII_ERR | \ 1005 TLP_DSTS_RX_DRIBBLE | \ 1006 TLP_DSTS_RX_DESC_ERR | \ 1007 TLP_DSTS_RX_OVERRUN) 1008 1009/* Tulip DMA descriptor control bits */ 1010#define TLP_DCTL_TX_INTERRUPT 0x0200 1011#define TLP_DCTL_TX_LAST_SEG 0x0100 1012#define TLP_DCTL_TX_FIRST_SEG 0x0080 1013#define TLP_DCTL_TX_NO_CRC 0x0010 1014#define TLP_DCTL_END_RING 0x0008 1015#define TLP_DCTL_TX_NO_PAD 0x0002 1016 1017/* DMA descriptors are kept in a ring. 1018 * Ring is empty when (read == write). 1019 * Ring is full when (read == wrap(write+1)), 1020 * The ring also contains a tailq of data buffers. 1021 */ 1022struct desc_ring 1023 { 1024 struct dma_desc *read; /* next descriptor to be read */ 1025 struct dma_desc *write; /* next descriptor to be written */ 1026 struct dma_desc *first; /* first descriptor in ring */ 1027 struct dma_desc *last; /* last descriptor in ring */ 1028 struct dma_desc *temp; /* temporary write pointer for tx */ 1029 u_int32_t dma_addr; /* bus address for desc array */ 1030 int size_descs; /* bus_dmamap_sync needs this */ 1031 int num_descs; /* used to set rx quota */ 1032#ifdef __linux__ 1033 struct sk_buff *head; /* tail-queue of skbuffs */ 1034 struct sk_buff *tail; 1035#elif BSD 1036 struct mbuf *head; /* tail-queue of mbufs */ 1037 struct mbuf *tail; 1038# if (defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__)) 1039 bus_dma_tag_t tag; /* bus_dma tag for desc array */ 1040 bus_dmamap_t map; /* bus_dma map for desc array */ 1041 bus_dma_segment_t segs[2]; /* bus_dmamap_load() or bus_dmamem_alloc() */ 1042 int nsegs; /* bus_dmamap_load() or bus_dmamem_alloc() */ 1043# endif 1044#endif 1045 }; 1046 1047/* break circular definition */ 1048typedef struct softc softc_t; 1049 1050/* card-dependent methods */ 1051struct card 1052 { 1053 void (* config)(softc_t *); 1054 void (* ident)(softc_t *); 1055 int (* watchdog)(softc_t *); /* must not sleep */ 1056 int (* ioctl)(softc_t *, struct ioctl *); /* can sleep */ 1057 }; 1058 1059/* flag bits in sc->flags */ 1060#define FLAG_IFNET 0x00000002 /* IFNET is attached */ 1061#define FLAG_NETDEV 0x00000004 /* NETDEV is registered */ 1062#define FLAG_NETGRAPH 0x00000008 /* NETGRAPH is attached */ 1063 1064/* Accessing Tulip CSRs: 1065 * There are two ways: IO instruction (default) and memory reference. 1066 * IO refs are used if IOREF_CSR is defined; otherwise memory refs are used. 1067 * MEMORY REFERENCES DO NOT WORK in BSD/OS: page faults happen. 1068 */ 1069#define IOREF_CSR 1 /* access Tulip CSRs with IO cycles if 1 */ 1070 1071#if (defined(__FreeBSD__) && defined(DEVICE_POLLING)) 1072# define DEV_POLL 1 1073#else 1074# define DEV_POLL 0 1075#endif 1076 1077#if defined(ALTQ) && ALTQ 1078# define ALTQ_PRESENT 1 1079#else 1080# define ALTQ_PRESENT 0 1081#endif 1082 1083/* This is the instance data, or "software context" for the device driver. */ 1084/* NetBSD, OpenBSD and BSD/OS want struct device first in the softc. */ 1085/* FreeBSD wants struct ifnet first in the softc. */ 1086struct softc 1087 { 1088#if (defined(__NetBSD__) || defined(__OpenBSD__)) 1089 struct device dev; /* base device -- must be first in softc */ 1090 pcitag_t pa_tag; /* pci_conf_read/write need this */ 1091 pci_chipset_tag_t pa_pc; /* pci_conf_read/write need this */ 1092 bus_dma_tag_t pa_dmat; /* bus_dma needs this */ 1093 bus_space_tag_t csr_tag; /* bus_space needs this */ 1094 bus_space_handle_t csr_handle;/* bus_space needs this */ 1095 pci_intr_handle_t intr_handle;/* interrupt handle */ 1096 void *irq_cookie; /* pci_intr_disestablish needs this */ 1097 void *sdh_cookie; /* shutdownhook_disestablish needs this */ 1098 struct simplelock top_lock; /* lock card->watchdog vs core_ioctl */ 1099 struct simplelock bottom_lock;/* lock for buf queues & descriptor rings */ 1100 struct mbuf *tx_mbuf; /* hang mbuf here while building dma descs */ 1101#endif /* __NetBSD__ || __OpenBSD__ */ 1102 1103#ifdef __bsdi__ 1104 struct device dev; /* base device -- must be first in softc */ 1105 struct isadev id; /* bus resource */ 1106 struct intrhand ih; /* interrupt vectoring */ 1107 struct atshutdown ats; /* shutdown hook */ 1108 pci_devaddr_t cfgbase; /* base address of PCI config regs */ 1109 u_int16_t csr_iobase; /* io base address of Tulip CSRs */ 1110 u_int32_t *csr_membase; /* kv mem base address of Tulip CSRs */ 1111 struct simplelock top_lock; /* lock card->watchdog vs core_ioctl */ 1112 struct simplelock bottom_lock;/* lock for buf queues & descriptor rings */ 1113 struct mbuf *tx_mbuf; /* hang mbuf here while building dma descs */ 1114#endif /* __bsdi__ */ 1115 1116 /* State for kernel-resident Line Protocols */ 1117#if IFNET 1118 struct ifnet *ifp; 1119 struct ifmedia ifm; /* hooks for ifconfig(8) */ 1120# if NSPPP 1121# if (__FreeBSD_version < 600000) 1122 struct sppp spppcom; /* must be first in sc for fbsd < 6 */ 1123# endif 1124 struct sppp *sppp; 1125# elif P2P 1126 struct p2pcom p2pcom; 1127 struct p2pcom *p2p; 1128# elif (__FreeBSD_version < 600000) 1129 struct ifnet ifnet; /* must be first in sc for fbsd < 6 */ 1130# endif 1131#endif 1132 1133#ifdef __linux__ 1134# if GEN_HDLC 1135 hdlc_device *hdlc_dev; /* state for HDLC code */ 1136 sync_serial_settings hdlc_settings; /* state set by sethdlc program */ 1137# else 1138 struct net_device_stats net_stats; /* linux_stats storage */ 1139# endif 1140#endif 1141 1142#if NETGRAPH 1143 struct callout ng_callout; /* ng_watchdog needs this */ 1144 node_p ng_node; /* pointer to our node struct */ 1145 hook_p ng_hook; /* non-zero means NETGRAPH owns device */ 1146# if (__FreeBSD_version >= 503000) 1147 struct ifaltq ng_sndq; 1148 struct ifaltq ng_fastq; 1149# else 1150 struct ifqueue ng_sndq; 1151 struct ifqueue ng_fastq; 1152# endif 1153#endif 1154 1155#ifdef __FreeBSD__ 1156 struct device *dev; /* base device pointer */ 1157 bus_space_tag_t csr_tag; /* bus_space needs this */ 1158 bus_space_handle_t csr_handle;/* bus_space_needs this */ 1159 void *irq_cookie; /* bus_teardown_intr needs this */ 1160 struct resource *irq_res; /* bus_release_resource needs this */ 1161 int irq_res_id; /* bus_release_resource needs this */ 1162 struct resource *csr_res; /* bus_release_resource needs this */ 1163 int csr_res_id; /* bus_release resource needs this */ 1164 int csr_res_type; /* bus_release resource needs this */ 1165 struct mbuf *tx_mbuf; /* hang mbuf here while building dma descs */ 1166# ifdef DEVICE_POLLING 1167 int quota; /* used for incoming packet flow control */ 1168# endif 1169# if (__FreeBSD_version >= 500000) 1170 struct mtx top_mtx; /* lock card->watchdog vs core_ioctl */ 1171 struct mtx bottom_mtx; /* lock for buf queues & descriptor rings */ 1172# else /* FreeBSD-4 */ 1173 int top_spl; /* lock card->watchdog vs core_ioctl */ 1174 int bottom_spl; /* lock for buf queues & descriptor rings */ 1175# endif 1176#endif /* __FreeBSD__ */ 1177 1178#ifdef __linux__ 1179 struct pci_dev *pci_dev; /* READ/WRITE_PCI_CFG macros need this */ 1180 struct net_device *net_dev; /* NAME_UNIT macro needs this */ 1181 struct timer_list wd_timer; /* timer calls watchdog() once a second */ 1182 u_int32_t csr_iobase; /* io base address of Tulip CSRs */ 1183 void *csr_membase; /* kv mem base address of Tulip CSRs */ 1184 struct sk_buff *tx_skb; /* hang skb here while building dma descs */ 1185 int quota; /* used for incoming packet flow control */ 1186 struct semaphore top_lock; /* lock card->watchdog vs core_ioctl */ 1187 spinlock_t bottom_lock; /* lock for buf queues & descriptor rings */ 1188#endif /* __linux__ */ 1189 1190 /* Top-half state used by all card types; lock with top_lock, */ 1191 const char *dev_desc; /* string describing type of board */ 1192 struct status status; /* driver status lmcconfig can read */ 1193 struct config config; /* driver config lmcconfig can read/write */ 1194 struct card *card; /* card methods: config, ioctl, watchdog */ 1195 u_int32_t gpio_dir; /* s/w copy of GPIO direction register */ 1196 u_int16_t led_state; /* last value written to mii16 */ 1197 u_int32_t flags; /* driver-global flags */ 1198 1199 /* Top-half state used by card-specific watchdogs; lock with top_lock. */ 1200 u_int32_t last_mii16; /* SSI, HSSI: MII reg 16 one second ago */ 1201 u_int32_t last_stat16; /* T3: framer reg 16 one second ago */ 1202 u_int32_t last_alm1; /* T1E1: framer reg 47 one second ago */ 1203 u_int32_t last_FEAC; /* last FEAC msg code received */ 1204 u_int32_t loop_timer; /* seconds until loopback expires */ 1205 1206 /* Bottom-half state used by the interrupt code; lock with bottom_lock. */ 1207 struct desc_ring txring; /* tx descriptor ring state */ 1208 struct desc_ring rxring; /* rx descriptor ring state */ 1209 }; /* end of softc */ 1210 1211/* Hide the minor differences between OS versions */ 1212 1213#ifdef __FreeBSD__ 1214 typedef void intr_return_t; 1215# define READ_PCI_CFG(sc, addr) pci_read_config ((sc)->dev, addr, 4) 1216# define WRITE_PCI_CFG(sc, addr, data) pci_write_config((sc)->dev, addr, data, 4) 1217# define READ_CSR(csr) bus_space_read_4 (sc->csr_tag, sc->csr_handle, csr) 1218# define WRITE_CSR(csr, val) bus_space_write_4(sc->csr_tag, sc->csr_handle, csr, val) 1219# define NAME_UNIT device_get_nameunit(sc->dev) 1220# define DRIVER_DEBUG ((sc->config.debug) || (sc->ifp->if_flags & IFF_DEBUG)) 1221# if (__FreeBSD_version >= 500000) 1222# define TOP_TRYLOCK mtx_trylock(&sc->top_mtx) 1223# define TOP_UNLOCK mtx_unlock (&sc->top_mtx) 1224# define BOTTOM_TRYLOCK mtx_trylock(&sc->bottom_mtx) 1225# define BOTTOM_UNLOCK mtx_unlock (&sc->bottom_mtx) 1226# if (__FreeBSD_version >= 700000) 1227# define CHECK_CAP priv_check(curthread, PRIV_DRIVER) 1228# else 1229# define CHECK_CAP suser(curthread) 1230# endif 1231# else /* FreeBSD-4 */ 1232# define TOP_TRYLOCK (sc->top_spl = splimp()) 1233# define TOP_UNLOCK splx(sc->top_spl) 1234# define BOTTOM_TRYLOCK 1 /* giant_lock protects */ 1235# define BOTTOM_UNLOCK /* nothing */ 1236# define CHECK_CAP suser(curproc) 1237# endif 1238# define DISABLE_INTR /* nothing */ 1239# define ENABLE_INTR /* nothing */ 1240# define IRQ_NONE /* nothing */ 1241# define IRQ_HANDLED /* nothing */ 1242# define IFP2SC(ifp) (ifp)->if_softc 1243# define COPY_BREAK MHLEN 1244# define SLEEP(usecs) tsleep(sc, PCATCH | PZERO, DEVICE_NAME, 1+(usecs/tick)) 1245# define DMA_SYNC(map, size, flags) bus_dmamap_sync(ring->tag, map, flags) 1246# define DMA_LOAD(map, addr, size) bus_dmamap_load(ring->tag, map, addr, size, fbsd_dmamap_load, ring, 0) 1247# if (NBPFILTER != 0) 1248# if (__FreeBSD_version >= 500000) 1249# define LMC_BPF_MTAP(mbuf) BPF_MTAP(sc->ifp, mbuf) 1250# else /* FreeBSD-4 */ 1251# define LMC_BPF_MTAP(mbuf) if (sc->ifp->if_bpf) bpf_mtap(sc->ifp, mbuf) 1252# endif 1253# define LMC_BPF_ATTACH(dlt, len) bpfattach(sc->ifp, dlt, len) 1254# define LMC_BPF_DETACH bpfdetach(sc->ifp) 1255# endif 1256# if (__FreeBSD_version >= 500000) 1257# define IF_DROP(ifq) _IF_DROP(ifq) 1258# define IF_QFULL(ifq) _IF_QFULL(ifq) 1259# endif 1260# if (__FreeBSD_version < 500000) 1261# define INTR_MPSAFE 0 1262# define BUS_DMA_COHERENT 0 1263# endif 1264# if (__FreeBSD_version >= 600000) 1265# define IFF_RUNNING IFF_DRV_RUNNING 1266# endif 1267#endif /* __FreeBSD__ */ 1268 1269#ifdef __NetBSD__ 1270 typedef int intr_return_t; 1271# define READ_PCI_CFG(sc, addr) pci_conf_read ((sc)->pa_pc, (sc)->pa_tag, addr) 1272# define WRITE_PCI_CFG(sc, addr, data) pci_conf_write((sc)->pa_pc, (sc)->pa_tag, addr, data) 1273# define READ_CSR(csr) bus_space_read_4 (sc->csr_tag, sc->csr_handle, csr) 1274# define WRITE_CSR(csr, val) bus_space_write_4(sc->csr_tag, sc->csr_handle, csr, val) 1275# define NAME_UNIT sc->dev.dv_xname 1276# define DRIVER_DEBUG ((sc->config.debug) || (sc->ifp->if_flags & IFF_DEBUG)) 1277# define TOP_TRYLOCK simple_lock_try(&sc->top_lock) 1278# define TOP_UNLOCK simple_unlock (&sc->top_lock) 1279# define BOTTOM_TRYLOCK simple_lock_try(&sc->bottom_lock) 1280# define BOTTOM_UNLOCK simple_unlock (&sc->bottom_lock) 1281# define CHECK_CAP suser(curproc->p_ucred, &curproc->p_acflag) 1282# define DISABLE_INTR int spl = splnet() 1283# define ENABLE_INTR splx(spl) 1284# define IRQ_NONE 0 1285# define IRQ_HANDLED 1 1286# define IFP2SC(ifp) (ifp)->if_softc 1287# define COPY_BREAK MHLEN 1288# define SLEEP(usecs) tsleep(sc, PCATCH | PZERO, DEVICE_NAME, 1+(usecs/tick)) 1289# define DMA_SYNC(map, size, flags) bus_dmamap_sync(ring->tag, map, 0, size, flags) 1290# define DMA_LOAD(map, addr, size) bus_dmamap_load(ring->tag, map, addr, size, 0, BUS_DMA_NOWAIT) 1291# if (NBPFILTER != 0) 1292# define LMC_BPF_MTAP(mbuf) if (sc->ifp->if_bpf) bpf_mtap(sc->ifp->if_bpf, mbuf) 1293# define LMC_BPF_ATTACH(dlt, len) bpfattach(sc->ifp, dlt, len) 1294# define LMC_BPF_DETACH bpfdetach(sc->ifp) 1295# endif 1296#endif /* __NetBSD__ */ 1297 1298#ifdef __OpenBSD__ 1299 typedef int intr_return_t; 1300# define READ_PCI_CFG(sc, addr) pci_conf_read ((sc)->pa_pc, (sc)->pa_tag, addr) 1301# define WRITE_PCI_CFG(sc, addr, data) pci_conf_write((sc)->pa_pc, (sc)->pa_tag, addr, data) 1302# define READ_CSR(csr) bus_space_read_4 (sc->csr_tag, sc->csr_handle, csr) 1303# define WRITE_CSR(csr, val) bus_space_write_4(sc->csr_tag, sc->csr_handle, csr, val) 1304# define NAME_UNIT sc->dev.dv_xname 1305# define DRIVER_DEBUG ((sc->config.debug) || (sc->ifp->if_flags & IFF_DEBUG)) 1306# define TOP_TRYLOCK simple_lock_try(&sc->top_lock) 1307# define TOP_UNLOCK simple_unlock (&sc->top_lock) 1308# define BOTTOM_TRYLOCK simple_lock_try(&sc->bottom_lock) 1309# define BOTTOM_UNLOCK simple_unlock (&sc->bottom_lock) 1310# define CHECK_CAP suser(curproc, 0) 1311# define DISABLE_INTR int spl = splnet() 1312# define ENABLE_INTR splx(spl) 1313# define IRQ_NONE 0 1314# define IRQ_HANDLED 1 1315# define IFP2SC(ifp) (ifp)->if_softc 1316# define COPY_BREAK MHLEN 1317# define SLEEP(usecs) tsleep(sc, PCATCH | PZERO, DEVICE_NAME, 1+(usecs/tick)) 1318# define DMA_SYNC(map, size, flags) bus_dmamap_sync(ring->tag, map, 0, size, flags) 1319# define DMA_LOAD(map, addr, size) bus_dmamap_load(ring->tag, map, addr, size, 0, BUS_DMA_NOWAIT) 1320# if (NBPFILTER != 0) 1321# define LMC_BPF_MTAP(mbuf) if (sc->ifp->if_bpf) bpf_mtap(sc->ifp->if_bpf, mbuf) 1322# define LMC_BPF_ATTACH(dlt, len) bpfattach(&sc->ifp->if_bpf, sc->ifp, dlt, len) 1323# define LMC_BPF_DETACH bpfdetach(sc->ifp) 1324# endif 1325#endif /* __OpenBSD__ */ 1326 1327#ifdef __bsdi__ 1328 typedef int intr_return_t; 1329# define READ_PCI_CFG(sc, addr) pci_inl(&(sc)->cfgbase, addr) 1330# define WRITE_PCI_CFG(sc, addr, data) pci_outl(&(sc)->cfgbase, addr, data) 1331# if IOREF_CSR 1332# define READ_CSR(csr) inl(sc->csr_iobase+(csr)) 1333# define WRITE_CSR(csr, val) outl(sc->csr_iobase+(csr), (val)) 1334# else 1335# error Memory refs to Tulip CSRs cause page faults in BSD/OS 1336# define READ_CSR(csr) (0 + *(sc->csr_membase+(csr))) 1337# define WRITE_CSR(csr, val) ((void)(*(sc->csr_membase+(csr)) = (val))) 1338# endif 1339# define NAME_UNIT sc->dev.dv_xname 1340# define DRIVER_DEBUG ((sc->config.debug) || (sc->ifp->if_flags & IFF_DEBUG)) 1341# define TOP_TRYLOCK simple_lock_try(&sc->top_lock) 1342# define TOP_UNLOCK simple_unlock (&sc->top_lock) 1343# define BOTTOM_TRYLOCK simple_lock_try(&sc->bottom_lock) 1344# define BOTTOM_UNLOCK simple_unlock (&sc->bottom_lock) 1345# define CHECK_CAP suser(PCPU(curproc)->p_ucred, &PCPU(curproc)->p_acflag) 1346# define DISABLE_INTR int spl = splimp() 1347# define ENABLE_INTR splx(spl) 1348# define IRQ_NONE 1 /* XXX 0 */ 1349# define IRQ_HANDLED 1 1350# define IFP2SC(ifp) (ifp)->if_softc 1351# define COPY_BREAK MHLEN 1352# define SLEEP(usecs) tsleep(sc, PCATCH | PZERO, DEVICE_NAME, 1+(usecs/tick)) 1353# define DMA_SYNC(map, size, flags) /* nothing */ 1354# define DMA_LOAD(map, addr, size) 0 1355# define bus_dmamap_unload(tag, map) /* nothing */ 1356# define bus_dmamap_destroy(tag, map) /* nothing */ 1357# if (NBPFILTER != 0) 1358# define LMC_BPF_MTAP(mbuf) if (sc->ifp->if_bpf) bpf_mtap(sc->ifp->if_bpf, mbuf) 1359# define LMC_BPF_ATTACH(dlt, len) bpfattach(&sc->ifp->if_bpf, sc->ifp, dlt, len) 1360# define LMC_BPF_DETACH /* bpfdetach(sc->ifp) */ 1361# endif 1362# define memcpy(dst, src, len) bcopy(src, dst, len) 1363# define if_detach(ifp) /* nothing */ 1364 1365/* BSD/OS-4.1 doesn't have a back pointer to softc in struct ifnet, */ 1366/* and it passes a unit number not a struct ifnet* to watchdog. */ 1367# if (_BSDI_VERSION <= 199910) 1368 extern struct cfdriver lmccd; 1369# undef IFP2SC 1370# define UNIT2SC(unit) ((softc_t *)lmccd.cd_devs[unit]) 1371# define IFP2SC(ifp) (UNIT2SC((ifp)->if_unit)) 1372# endif 1373#endif /* __bsdi__ */ 1374 1375#ifdef __linux__ 1376static u_int32_t /* inline? so rare it doesn't matter */ 1377READ_PCI_CFG(softc_t *sc, u_int32_t addr) 1378 { 1379 u_int32_t data; 1380 pci_read_config_dword(sc->pci_dev, addr, &data); 1381 return data; 1382 } 1383# define WRITE_PCI_CFG(sc, addr, data) pci_write_config_dword(sc->pci_dev, addr, data) 1384# if IOREF_CSR 1385# define READ_CSR(csr) inl((sc->csr_iobase+(csr))) 1386# define WRITE_CSR(csr, val) outl((val),(sc->csr_iobase+(csr))) 1387# else 1388# define READ_CSR(csr) readl((sc->csr_membase+(csr))) 1389# define WRITE_CSR(csr, val) writel((val),(sc->csr_membase+(csr))) 1390# endif 1391# define NAME_UNIT sc->net_dev->name 1392# define DRIVER_DEBUG ((sc->config.debug) || (sc->net_dev->flags & IFF_DEBUG)) 1393# define TOP_TRYLOCK ((down_trylock(&sc->top_lock)==0) ? 1:0) 1394# define TOP_UNLOCK up(&sc->top_lock) 1395# define BOTTOM_TRYLOCK spin_trylock_bh(&sc->bottom_lock) 1396# define BOTTOM_UNLOCK spin_unlock_bh(&sc->bottom_lock) 1397# define CHECK_CAP capable(CAP_NET_ADMIN)? 0 : -EPERM 1398# define DISABLE_INTR /* nothing */ 1399# define ENABLE_INTR /* nothing */ 1400# define COPY_BREAK 200 1401# define DELAY(usecs) udelay(usecs) 1402# define SLEEP(usecs) do { set_current_state(TASK_INTERRUPTIBLE);\ 1403 schedule_timeout(1+(usecs*HZ)/1000000UL); } while (0) 1404# define printf printk 1405# define copyin(u, k, len) copy_from_user(k, u, len) 1406# define microtime(time) do_gettimeofday(time) 1407# define malloc(len, t, f) kmalloc(len, GFP_KERNEL) 1408# define free(addr, t) kfree(addr) 1409# define LITTLE_ENDIAN 4321 1410# define BIG_ENDIAN 1234 1411# if defined(__LITTLE_ENDIAN) 1412# define BYTE_ORDER LITTLE_ENDIAN 1413# elif defined(__BIG_ENDIAN) 1414# define BYTE_ORDER BIG_ENDIAN 1415# else 1416# error "asm/byteorder.h is wrong" 1417# endif 1418# if (GEN_HDLC == 0) 1419# define dev_to_hdlc(net_dev) net_dev 1420# define hdlc_set_carrier(val, net_dev) /* nothing */ 1421# endif 1422#endif /* __linux__ */ 1423 1424#if (NBPFILTER == 0) 1425# define LMC_BPF_MTAP(mbuf) /* nothing */ 1426# define LMC_BPF_ATTACH(dlt, len) /* nothing */ 1427# define LMC_BPF_DETACH /* nothing */ 1428#endif 1429 1430#if (defined(__bsdi__) || /* unconditionally */ \ 1431 (defined(__FreeBSD__) && (__FreeBSD_version < 503000)) || \ 1432 (defined(__NetBSD__) && (__NetBSD_Version__ < 106000000)) || \ 1433 (defined(__OpenBSD__) && ( OpenBSD < 200111))) 1434# define IFQ_ENQUEUE(ifq, m, pa, err) \ 1435do { \ 1436 if (pa==0); /* suppress warning */ \ 1437 if (IF_QFULL(ifq)) \ 1438 { \ 1439 IF_DROP(ifq); \ 1440 m_freem(m); \ 1441 err = ENOBUFS; \ 1442 } \ 1443 else \ 1444 { \ 1445 IF_ENQUEUE(ifq, m); \ 1446 err = 0; \ 1447 } \ 1448 } while (0) 1449# define IFQ_DEQUEUE(ifq, m) do { IF_DEQUEUE((ifq), m) } while (0) 1450# define IFQ_IS_EMPTY(ifq) ((ifq)->ifq_head == NULL) 1451# define IFQ_SET_MAXLEN(ifq, len) (ifq)->ifq_maxlen = len 1452# define IFQ_SET_READY(ifq) /* nothing */ 1453# define IFQ_PURGE(ifq) \ 1454do { \ 1455 while ((ifq)->ifq_head != NULL) \ 1456 { \ 1457 struct mbuf *m; \ 1458 IF_DEQUEUE(ifq, m); \ 1459 m_freem(m); \ 1460 } \ 1461 } while (0) 1462#endif 1463 1464#define HSSI_DESC "SBE/LMC HSSI Card" 1465#define T3_DESC "SBE/LMC T3 Card" 1466#define SSI_DESC "SBE/LMC SSI Card" 1467#define T1E1_DESC "SBE/LMC T1E1 Card" 1468 1469/* procedure prototypes */ 1470 1471static void shift_srom_bits(softc_t *, u_int32_t, u_int32_t); 1472static u_int16_t read_srom(softc_t *, u_int8_t); 1473static void write_srom(softc_t *, u_int8_t, u_int16_t); 1474 1475static u_int8_t read_bios(softc_t *, u_int32_t); 1476static void write_bios_phys(softc_t *, u_int32_t, u_int8_t); 1477static void write_bios(softc_t *, u_int32_t, u_int8_t); 1478static void erase_bios(softc_t *); 1479 1480static void shift_mii_bits(softc_t *, u_int32_t, u_int32_t); 1481static u_int16_t read_mii(softc_t *, u_int8_t); 1482static void write_mii(softc_t *, u_int8_t, u_int16_t); 1483 1484static void set_mii16_bits(softc_t *, u_int16_t); 1485static void clr_mii16_bits(softc_t *, u_int16_t); 1486static void set_mii17_bits(softc_t *, u_int16_t); 1487static void clr_mii17_bits(softc_t *, u_int16_t); 1488 1489static void led_off(softc_t *, u_int16_t); 1490static void led_on(softc_t *, u_int16_t); 1491static void led_inv(softc_t *, u_int16_t); 1492 1493static void write_framer(softc_t *, u_int16_t, u_int8_t); 1494static u_int8_t read_framer(softc_t *, u_int16_t); 1495 1496static void make_gpio_input(softc_t *, u_int32_t); 1497static void make_gpio_output(softc_t *, u_int32_t); 1498static u_int32_t read_gpio(softc_t *); 1499static void set_gpio_bits(softc_t *, u_int32_t); 1500static void clr_gpio_bits(softc_t *, u_int32_t); 1501 1502static void reset_xilinx(softc_t *); 1503static void load_xilinx_from_rom(softc_t *); 1504static int load_xilinx_from_file(softc_t *, char *, u_int32_t); 1505 1506static void shift_synth_bits(softc_t *, u_int32_t, u_int32_t); 1507static void write_synth(softc_t *, struct synth *); 1508 1509static void write_dac(softc_t *, u_int16_t); 1510 1511static void hssi_config(softc_t *); 1512static void hssi_ident(softc_t *); 1513static int hssi_watchdog(softc_t *); 1514static int hssi_ioctl(softc_t *, struct ioctl *); 1515 1516static void t3_config(softc_t *); 1517static void t3_ident(softc_t *); 1518static int t3_watchdog(softc_t *); 1519static void t3_send_dbl_feac(softc_t *, int, int); 1520static int t3_ioctl(softc_t *, struct ioctl *); 1521 1522static void ssi_config(softc_t *); 1523static void ssi_ident(softc_t *); 1524static int ssi_watchdog(softc_t *); 1525static int ssi_ioctl(softc_t *, struct ioctl *); 1526 1527static void t1_config(softc_t *); 1528static void t1_ident(softc_t *); 1529static int t1_watchdog(softc_t *); 1530static void t1_send_bop(softc_t *, int); 1531static int t1_ioctl(softc_t *, struct ioctl *); 1532 1533#if IFNET 1534# if ((defined(__FreeBSD__) && (__FreeBSD_version < 500000)) ||\ 1535 defined(__NetBSD__) || defined(__OpenBSD__) || defined(__bsdi__)) 1536static void netisr_dispatch(int, struct mbuf *); 1537# endif 1538static void lmc_raw_input(struct ifnet *, struct mbuf *); 1539#endif /* IFNET */ 1540 1541#if BSD 1542static void mbuf_enqueue(struct desc_ring *, struct mbuf *); 1543static struct mbuf* mbuf_dequeue(struct desc_ring *); 1544# ifdef __FreeBSD__ 1545static void fbsd_dmamap_load(void *, bus_dma_segment_t *, int, int); 1546# endif 1547static int create_ring(softc_t *, struct desc_ring *, int); 1548static void destroy_ring(softc_t *, struct desc_ring *); 1549static int rxintr_cleanup(softc_t *); 1550static int rxintr_setup(softc_t *); 1551static int txintr_cleanup(softc_t *); 1552static int txintr_setup_mbuf(softc_t *, struct mbuf *); 1553static int txintr_setup(softc_t *); 1554#endif /* BSD */ 1555 1556#ifdef __linux__ 1557static void skbuff_enqueue(struct desc_ring *, struct sk_buff *); 1558static struct sk_buff* skbuff_dequeue(struct desc_ring *); 1559static int create_ring(softc_t *, struct desc_ring *, int); 1560static void destroy_ring(softc_t *, struct desc_ring *); 1561static int rxintr_cleanup(softc_t *); 1562static int rxintr_setup(softc_t *); 1563static int txintr_cleanup(softc_t *sc); 1564static int txintr_setup_frag(softc_t *, char *, int); 1565static int txintr_setup_skb(softc_t *, struct sk_buff *); 1566static int txintr_setup(softc_t *); 1567#endif /* __linux__ */ 1568 1569static void check_intr_status(softc_t *); 1570static void core_interrupt(void *, int); 1571static void user_interrupt(softc_t *, int); 1572#if BSD 1573# if (defined(__FreeBSD__) && defined(DEVICE_POLLING)) 1574static void fbsd_poll(struct ifnet *, enum poll_cmd, int); 1575# endif 1576static intr_return_t bsd_interrupt(void *); 1577#endif /* BSD */ 1578 1579static void set_status(softc_t *, int); 1580#if P2P 1581static int p2p_getmdm(struct p2pcom *, caddr_t); 1582static int p2p_mdmctl(struct p2pcom *, int); 1583#endif 1584#if NSPPP 1585static void sppp_tls(struct sppp *); 1586static void sppp_tlf(struct sppp *); 1587#endif 1588 1589static void config_proto(softc_t *, struct config *); 1590static int core_ioctl(softc_t *, u_long, caddr_t); 1591static void core_watchdog(softc_t *); 1592 1593#if IFNET 1594static int lmc_raw_ioctl(struct ifnet *, u_long, caddr_t); 1595static int lmc_ifnet_ioctl(struct ifnet *, u_long, caddr_t); 1596static void lmc_ifnet_start(struct ifnet *); 1597static int lmc_raw_output(struct ifnet *, struct mbuf *, 1598 struct sockaddr *, struct rtentry *); 1599static void lmc_ifnet_watchdog(struct ifnet *); 1600# ifdef __OpenBSD__ 1601static int ifmedia_change(struct ifnet *); 1602static void ifmedia_status(struct ifnet *, struct ifmediareq *); 1603# endif /* __OpenBSD__ */ 1604static void setup_ifnet(struct ifnet *); 1605static int lmc_ifnet_attach(softc_t *); 1606static void lmc_ifnet_detach(softc_t *); 1607#endif /* IFNET */ 1608 1609#if NETGRAPH 1610# if (__FreeBSD_version >= 500000) 1611static int ng_constructor(node_p); 1612# else /* FreeBSD-4 */ 1613static int ng_constructor(node_p *); 1614# endif 1615# if (__FreeBSD_version >= 500000) 1616static int ng_rcvmsg(node_p, item_p, hook_p); 1617# else /* FreeBSD-4 */ 1618static int ng_rcvmsg(node_p, struct ng_mesg *, 1619 const char *, struct ng_mesg **); 1620# endif 1621static int ng_shutdown(node_p); 1622static int ng_newhook(node_p, hook_p, const char *); 1623static int ng_connect(hook_p); 1624# if (__FreeBSD_version >= 500000) 1625static int ng_rcvdata(hook_p, item_p); 1626# else /* FreeBSD-4 */ 1627static int ng_rcvdata(hook_p, struct mbuf *, meta_p); 1628# endif 1629static int ng_disconnect(hook_p); 1630# if (IFNET == 0) 1631static void ng_watchdog(void *); 1632# endif 1633static int ng_attach(softc_t *); 1634static void ng_detach(softc_t *); 1635#endif /* NETGRAPH */ 1636 1637static int startup_card(softc_t *); 1638static void shutdown_card(void *); 1639static int attach_card(softc_t *, const char *); 1640static void detach_card(softc_t *); 1641 1642#ifdef __FreeBSD__ 1643static int fbsd_probe(device_t); 1644static int fbsd_detach(device_t); 1645static int fbsd_shutdown(device_t); 1646static int fbsd_attach(device_t); 1647#endif /* __FreeBSD__ */ 1648 1649#ifdef __NetBSD__ 1650static int nbsd_match(struct device *t, struct cfdata *, void *); 1651static int nbsd_detach(struct device *, int); 1652static void nbsd_attach(struct device *, struct device *, void *); 1653static int lkm_nbsd_match(struct pci_attach_args *); 1654int if_lmc_lkmentry(struct lkm_table *, int, int); 1655#endif /* __NetBSD__ */ 1656 1657#ifdef __OpenBSD__ 1658static int obsd_match(struct device *, void *, void *); 1659static int obsd_detach(struct device *, int); 1660static void obsd_attach(struct device *, struct device *, void *); 1661int if_lmc_lkmentry(struct lkm_table *, int, int); 1662#endif /* __OpenBSD__ */ 1663 1664#ifdef __bsdi__ 1665static int bsdi_match(pci_devaddr_t *); 1666static int bsdi_probe(struct device *, struct cfdata *, void *); 1667static void bsdi_attach(struct device *, struct device *, void *); 1668#endif /* __bsdi__ */ 1669 1670#ifdef __linux__ 1671static irqreturn_t linux_interrupt(int, void *, struct pt_regs *); 1672static int linux_poll(struct net_device *, int *); 1673static int linux_start(struct sk_buff *, struct net_device *); 1674static void linux_timeout(struct net_device *); 1675static int linux_ioctl(struct net_device *, struct ifreq *, int); 1676static struct net_device_stats * linux_stats(struct net_device *); 1677static void linux_watchdog(unsigned long); 1678static int linux_stop(struct net_device *); 1679static int linux_open(struct net_device *); 1680# if GEN_HDLC 1681static int hdlc_attach(struct net_device *, 1682 unsigned short, unsigned short); 1683# endif 1684static void __exit linux_remove(struct pci_dev *); 1685static void setup_netdev(struct net_device *); 1686static int __init linux_probe(struct pci_dev *, const struct pci_device_id *); 1687#endif /* __linux__ */ 1688 1689#endif /* KERNEL */ 1690 1691#endif /* IF_LMC_H */ 1692