cn23xx_pf_regs.h revision 325618
1/* 2 * BSD LICENSE 3 * 4 * Copyright(c) 2017 Cavium, Inc.. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Cavium, Inc. nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33/*$FreeBSD: stable/11/sys/dev/liquidio/base/cn23xx_pf_regs.h 325618 2017-11-09 19:52:56Z sbruno $*/ 34 35/* \file cn23xx_pf_regs.h 36 * \brief Host Driver: Register Address and Register Mask values for 37 * CN23XX devices. 38 */ 39 40#ifndef __CN23XX_PF_REGS_H__ 41#define __CN23XX_PF_REGS_H__ 42 43#define LIO_CN23XX_CFG_PCIE_DEVCTL 0x78 44#define LIO_CN23XX_CFG_PCIE_UNCORRECT_ERR_MASK 0x108 45#define LIO_CN23XX_CFG_PCIE_CORRECT_ERR_STATUS 0x110 46#define LIO_CN23XX_CFG_PCIE_DEVCTL_MASK 0x00040000 47 48#define LIO_CN23XX_PCIE_SRIOV_FDL 0x188 49#define LIO_CN23XX_PCIE_SRIOV_FDL_BIT_POS 0x10 50#define LIO_CN23XX_PCIE_SRIOV_FDL_MASK 0xFF 51 52/* ############## BAR0 Registers ################ */ 53 54#define LIO_CN23XX_SLI_CTL_PORT_START 0x286E0 55#define LIO_CN23XX_PORT_OFFSET 0x10 56 57#define LIO_CN23XX_SLI_CTL_PORT(p) \ 58 (LIO_CN23XX_SLI_CTL_PORT_START + \ 59 ((p) * LIO_CN23XX_PORT_OFFSET)) 60 61/* 2 scatch registers (64-bit) */ 62#define LIO_CN23XX_SLI_WINDOW_CTL 0x282E0 63#define LIO_CN23XX_SLI_SCRATCH1 0x283C0 64#define LIO_CN23XX_SLI_SCRATCH2 0x283D0 65#define LIO_CN23XX_SLI_WINDOW_CTL_DEFAULT 0x200000ULL 66 67/* 1 registers (64-bit) - SLI_CTL_STATUS */ 68#define LIO_CN23XX_SLI_CTL_STATUS 0x28570 69 70/* 71 * SLI Packet Input Jabber Register (64 bit register) 72 * <31:0> for Byte count for limiting sizes of packet sizes 73 * that are allowed for sli packet inbound packets. 74 * the default value is 0xFA00(=64000). 75 */ 76#define LIO_CN23XX_SLI_PKT_IN_JABBER 0x29170 77 78#define LIO_CN23XX_SLI_WIN_WR_ADDR_LO 0x20000 79#define LIO_CN23XX_SLI_WIN_WR_ADDR64 LIO_CN23XX_SLI_WIN_WR_ADDR_LO 80 81#define LIO_CN23XX_SLI_WIN_RD_ADDR_LO 0x20010 82#define LIO_CN23XX_SLI_WIN_RD_ADDR_HI 0x20014 83#define LIO_CN23XX_SLI_WIN_RD_ADDR64 LIO_CN23XX_SLI_WIN_RD_ADDR_LO 84 85#define LIO_CN23XX_SLI_WIN_WR_DATA_LO 0x20020 86#define LIO_CN23XX_SLI_WIN_WR_DATA_HI 0x20024 87#define LIO_CN23XX_SLI_WIN_WR_DATA64 LIO_CN23XX_SLI_WIN_WR_DATA_LO 88 89#define LIO_CN23XX_SLI_WIN_RD_DATA_LO 0x20040 90#define LIO_CN23XX_SLI_WIN_RD_DATA_HI 0x20044 91#define LIO_CN23XX_SLI_WIN_RD_DATA64 LIO_CN23XX_SLI_WIN_RD_DATA_LO 92 93#define LIO_CN23XX_SLI_WIN_WR_MASK_REG 0x20030 94#define LIO_CN23XX_SLI_MAC_CREDIT_CNT 0x23D70 95 96/* 97 * 4 registers (64-bit) for mapping IOQs to MACs(PEMs)- 98 * SLI_PKT_MAC(0..3)_PF(0..1)_RINFO 99 */ 100#define LIO_CN23XX_SLI_PKT_MAC_RINFO_START64 0x29030 101 102/*1 register (64-bit) to determine whether IOQs are in reset. */ 103#define LIO_CN23XX_SLI_PKT_IOQ_RING_RST 0x291E0 104 105/* Each Input Queue register is at a 16-byte Offset in BAR0 */ 106#define LIO_CN23XX_IQ_OFFSET 0x20000 107 108#define LIO_CN23XX_MAC_RINFO_OFFSET 0x20 109#define LIO_CN23XX_PF_RINFO_OFFSET 0x10 110 111#define LIO_CN23XX_SLI_PKT_MAC_RINFO64(mac, pf) \ 112 (LIO_CN23XX_SLI_PKT_MAC_RINFO_START64 + \ 113 ((mac) * LIO_CN23XX_MAC_RINFO_OFFSET) + \ 114 ((pf) * LIO_CN23XX_PF_RINFO_OFFSET)) 115 116/* mask for total rings, setting TRS to base */ 117#define LIO_CN23XX_PKT_MAC_CTL_RINFO_TRS BIT_ULL(16) 118 119/* Starting bit of the TRS field in LIO_CN23XX_SLI_PKT_MAC_RINFO64 register */ 120#define LIO_CN23XX_PKT_MAC_CTL_RINFO_TRS_BIT_POS 16 121 122/*###################### REQUEST QUEUE #########################*/ 123 124/* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */ 125#define LIO_CN23XX_SLI_PKT_IN_DONE_CNTS_START64 0x10040 126 127/* 64 registers for Input Queues Start Addr - SLI_PKT0_INSTR_BADDR */ 128#define LIO_CN23XX_SLI_PKT_INSTR_BADDR_START64 0x10010 129 130/* 64 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */ 131#define LIO_CN23XX_SLI_PKT_INSTR_BADDR_DBELL_START 0x10020 132 133/* 64 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */ 134#define LIO_CN23XX_SLI_PKT_INSTR_FIFO_RSIZE_START 0x10030 135 136/* 137 * 64 registers (64-bit) - ES, RO, NS, Arbitration for Input Queue Data & 138 * gather list fetches. SLI_PKT(0..63)_INPUT_CONTROL. 139 */ 140#define LIO_CN23XX_SLI_PKT_INPUT_CONTROL_START64 0x10000 141 142/*------- Request Queue Macros ---------*/ 143#define LIO_CN23XX_SLI_IQ_PKT_CONTROL64(iq) \ 144 (LIO_CN23XX_SLI_PKT_INPUT_CONTROL_START64 + \ 145 ((iq) * LIO_CN23XX_IQ_OFFSET)) 146 147#define LIO_CN23XX_SLI_IQ_BASE_ADDR64(iq) \ 148 (LIO_CN23XX_SLI_PKT_INSTR_BADDR_START64 + \ 149 ((iq) * LIO_CN23XX_IQ_OFFSET)) 150 151#define LIO_CN23XX_SLI_IQ_SIZE(iq) \ 152 (LIO_CN23XX_SLI_PKT_INSTR_FIFO_RSIZE_START + \ 153 ((iq) * LIO_CN23XX_IQ_OFFSET)) 154 155#define LIO_CN23XX_SLI_IQ_DOORBELL(iq) \ 156 (LIO_CN23XX_SLI_PKT_INSTR_BADDR_DBELL_START + \ 157 ((iq) * LIO_CN23XX_IQ_OFFSET)) 158 159#define LIO_CN23XX_SLI_IQ_INSTR_COUNT64(iq) \ 160 (LIO_CN23XX_SLI_PKT_IN_DONE_CNTS_START64 + \ 161 ((iq) * LIO_CN23XX_IQ_OFFSET)) 162 163/*------------------ Masks ----------------*/ 164#define LIO_CN23XX_PKT_INPUT_CTL_VF_NUM BIT_ULL(32) 165#define LIO_CN23XX_PKT_INPUT_CTL_MAC_NUM BIT(29) 166/* 167 * Number of instructions to be read in one MAC read request. 168 * setting to Max value(4) 169 */ 170#define LIO_CN23XX_PKT_INPUT_CTL_RDSIZE (3 << 25) 171#define LIO_CN23XX_PKT_INPUT_CTL_IS_64B BIT(24) 172#define LIO_CN23XX_PKT_INPUT_CTL_RST BIT(23) 173#define LIO_CN23XX_PKT_INPUT_CTL_QUIET BIT(28) 174#define LIO_CN23XX_PKT_INPUT_CTL_RING_ENB BIT(22) 175#define LIO_CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP BIT(6) 176#define LIO_CN23XX_PKT_INPUT_CTL_USE_CSR BIT(4) 177#define LIO_CN23XX_PKT_INPUT_CTL_GATHER_ES_64B_SWAP (2) 178 179#define LIO_CN23XX_PKT_INPUT_CTL_PF_NUM_POS (45) 180/* These bits[43:32] select the function number within the PF */ 181#define LIO_CN23XX_PKT_INPUT_CTL_MAC_NUM_POS (29) 182#define LIO_CN23XX_PKT_IN_DONE_WMARK_MASK (0xFFFFULL) 183#define LIO_CN23XX_PKT_IN_DONE_WMARK_BIT_POS (32) 184#define LIO_CN23XX_PKT_IN_DONE_CNT_MASK 0x00000000FFFFFFFFULL 185 186#if BYTE_ORDER == LITTLE_ENDIAN 187#define LIO_CN23XX_PKT_INPUT_CTL_MASK \ 188 (LIO_CN23XX_PKT_INPUT_CTL_RDSIZE | \ 189 LIO_CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP | \ 190 LIO_CN23XX_PKT_INPUT_CTL_USE_CSR) 191#else /* BYTE_ORDER != LITTLE_ENDIAN */ 192#define LIO_CN23XX_PKT_INPUT_CTL_MASK \ 193 (LIO_CN23XX_PKT_INPUT_CTL_RDSIZE | \ 194 LIO_CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP | \ 195 LIO_CN23XX_PKT_INPUT_CTL_USE_CSR | \ 196 LIO_CN23XX_PKT_INPUT_CTL_GATHER_ES_64B_SWAP) 197#endif /* BYTE_ORDER == LITTLE_ENDIAN */ 198 199/*############################ OUTPUT QUEUE #########################*/ 200 201/* 64 registers for Output queue control - SLI_PKT(0..63)_OUTPUT_CONTROL */ 202#define LIO_CN23XX_SLI_PKT_OUTPUT_CONTROL_START 0x10050 203 204/* 64 registers for Output queue buffer and info size - SLI_PKT0_OUT_SIZE */ 205#define LIO_CN23XX_SLI_PKT_OUT_SIZE 0x10060 206 207/* 64 registers for Output Queue Start Addr - SLI_PKT0_SLIST_BADDR */ 208#define LIO_CN23XX_SLI_SLIST_BADDR_START64 0x10070 209 210/* 64 registers for Output Queue Packet Credits - SLI_PKT0_SLIST_BAOFF_DBELL */ 211#define LIO_CN23XX_SLI_PKT_SLIST_BAOFF_DBELL_START 0x10080 212 213/* 64 registers for Output Queue size - SLI_PKT0_SLIST_FIFO_RSIZE */ 214#define LIO_CN23XX_SLI_PKT_SLIST_FIFO_RSIZE_START 0x10090 215 216/* 64 registers for Output Queue Packet Count - SLI_PKT0_CNTS */ 217#define LIO_CN23XX_SLI_PKT_CNTS_START 0x100B0 218 219/* 64 registers for Output Queue INT Levels - SLI_PKT0_INT_LEVELS */ 220#define LIO_CN23XX_SLI_PKT_INT_LEVELS_START64 0x100A0 221 222/* Each Output Queue register is at a 16-byte Offset in BAR0 */ 223#define LIO_CN23XX_OQ_OFFSET 0x20000 224 225/* 1 (64-bit register) for Output Queue backpressure across all rings. */ 226#define LIO_CN23XX_SLI_OQ_WMARK 0x29180 227 228/* Global pkt control register */ 229#define LIO_CN23XX_SLI_GBL_CONTROL 0x29210 230 231/* Backpressure enable register for PF0 */ 232#define LIO_CN23XX_SLI_OUT_BP_EN_W1S 0x29260 233 234/* Backpressure enable register for PF1 */ 235#define LIO_CN23XX_SLI_OUT_BP_EN2_W1S 0x29270 236 237/*------- Output Queue Macros ---------*/ 238 239#define LIO_CN23XX_SLI_OQ_PKT_CONTROL(oq) \ 240 (LIO_CN23XX_SLI_PKT_OUTPUT_CONTROL_START + \ 241 ((oq) * LIO_CN23XX_OQ_OFFSET)) 242 243#define LIO_CN23XX_SLI_OQ_BASE_ADDR64(oq) \ 244 (LIO_CN23XX_SLI_SLIST_BADDR_START64 + \ 245 ((oq) * LIO_CN23XX_OQ_OFFSET)) 246 247#define LIO_CN23XX_SLI_OQ_SIZE(oq) \ 248 (LIO_CN23XX_SLI_PKT_SLIST_FIFO_RSIZE_START + \ 249 ((oq) * LIO_CN23XX_OQ_OFFSET)) 250 251#define LIO_CN23XX_SLI_OQ_BUFF_INFO_SIZE(oq) \ 252 (LIO_CN23XX_SLI_PKT_OUT_SIZE + \ 253 ((oq) * LIO_CN23XX_OQ_OFFSET)) 254 255#define LIO_CN23XX_SLI_OQ_PKTS_SENT(oq) \ 256 (LIO_CN23XX_SLI_PKT_CNTS_START + \ 257 ((oq) * LIO_CN23XX_OQ_OFFSET)) 258 259#define LIO_CN23XX_SLI_OQ_PKTS_CREDIT(oq) \ 260 (LIO_CN23XX_SLI_PKT_SLIST_BAOFF_DBELL_START + \ 261 ((oq) * LIO_CN23XX_OQ_OFFSET)) 262 263#define LIO_CN23XX_SLI_OQ_PKT_INT_LEVELS(oq) \ 264 (LIO_CN23XX_SLI_PKT_INT_LEVELS_START64 + \ 265 ((oq) * LIO_CN23XX_OQ_OFFSET)) 266 267/*------------------ Masks ----------------*/ 268#define LIO_CN23XX_PKT_OUTPUT_CTL_TENB BIT(13) 269#define LIO_CN23XX_PKT_OUTPUT_CTL_CENB BIT(12) 270#define LIO_CN23XX_PKT_OUTPUT_CTL_IPTR BIT(11) 271#define LIO_CN23XX_PKT_OUTPUT_CTL_ES BIT(9) 272#define LIO_CN23XX_PKT_OUTPUT_CTL_NSR BIT(8) 273#define LIO_CN23XX_PKT_OUTPUT_CTL_ROR BIT(7) 274#define LIO_CN23XX_PKT_OUTPUT_CTL_DPTR BIT(6) 275#define LIO_CN23XX_PKT_OUTPUT_CTL_BMODE BIT(5) 276#define LIO_CN23XX_PKT_OUTPUT_CTL_ES_P BIT(3) 277#define LIO_CN23XX_PKT_OUTPUT_CTL_NSR_P BIT(2) 278#define LIO_CN23XX_PKT_OUTPUT_CTL_ROR_P BIT(1) 279#define LIO_CN23XX_PKT_OUTPUT_CTL_RING_ENB BIT(0) 280 281/*######################## MSIX TABLE #########################*/ 282 283#define LIO_CN23XX_MSIX_TABLE_ADDR_START 0x0 284#define CN23XX_MSIX_TABLE_DATA_START 0x8 285#define CN23XX_MSIX_TABLE_SIZE 0x10 286 287#define CN23XX_MSIX_TABLE_ADDR(idx) \ 288 (LIO_CN23XX_MSIX_TABLE_ADDR_START + \ 289 ((idx) * LIO_CN23XX_MSIX_TABLE_SIZE)) 290 291#define CN23XX_MSIX_TABLE_DATA(idx) \ 292 (LIO_CN23XX_MSIX_TABLE_DATA_START + \ 293 ((idx) * LIO_CN23XX_MSIX_TABLE_SIZE)) 294 295/*######################## INTERRUPTS #########################*/ 296#define LIO_CN23XX_MAC_INT_OFFSET 0x20 297#define LIO_CN23XX_PF_INT_OFFSET 0x10 298 299/* 1 register (64-bit) for Interrupt Summary */ 300#define LIO_CN23XX_SLI_INT_SUM64 0x27000 301 302/* 4 registers (64-bit) for Interrupt Enable for each Port */ 303#define LIO_CN23XX_SLI_INT_ENB64 0x27080 304 305#define LIO_CN23XX_SLI_MAC_PF_INT_SUM64(mac, pf) \ 306 (LIO_CN23XX_SLI_INT_SUM64 + \ 307 ((mac) * LIO_CN23XX_MAC_INT_OFFSET) + \ 308 ((pf) * LIO_CN23XX_PF_INT_OFFSET)) 309 310#define LIO_CN23XX_SLI_MAC_PF_INT_ENB64(mac, pf) \ 311 (LIO_CN23XX_SLI_INT_ENB64 + \ 312 ((mac) * LIO_CN23XX_MAC_INT_OFFSET) + \ 313 ((pf) * LIO_CN23XX_PF_INT_OFFSET)) 314 315/* 1 register (64-bit) to indicate which Output Queue reached pkt threshold */ 316#define LIO_CN23XX_SLI_PKT_CNT_INT 0x29130 317 318/* 1 register (64-bit) to indicate which Output Queue reached time threshold */ 319#define LIO_CN23XX_SLI_PKT_TIME_INT 0x29140 320 321/*------------------ Interrupt Masks ----------------*/ 322 323#define LIO_CN23XX_INTR_PO_INT BIT_ULL(63) 324#define LIO_CN23XX_INTR_PI_INT BIT_ULL(62) 325#define LIO_CN23XX_INTR_RESEND BIT_ULL(60) 326 327#define LIO_CN23XX_INTR_CINT_ENB BIT_ULL(48) 328 329#define LIO_CN23XX_INTR_MIO_INT BIT(1) 330#define LIO_CN23XX_INTR_PKT_TIME BIT(5) 331#define LIO_CN23XX_INTR_M0UPB0_ERR BIT(8) 332#define LIO_CN23XX_INTR_M0UPWI_ERR BIT(9) 333#define LIO_CN23XX_INTR_M0UNB0_ERR BIT(10) 334#define LIO_CN23XX_INTR_M0UNWI_ERR BIT(11) 335 336#define LIO_CN23XX_INTR_DMA0_FORCE BIT_ULL(32) 337#define LIO_CN23XX_INTR_DMA1_FORCE BIT_ULL(33) 338 339#define LIO_CN23XX_INTR_DMA0_TIME BIT_ULL(36) 340#define LIO_CN23XX_INTR_DMA1_TIME BIT_ULL(37) 341 342#define LIO_CN23XX_INTR_DMAPF_ERR BIT_ULL(59) 343 344#define LIO_CN23XX_INTR_PKTPF_ERR BIT_ULL(61) 345#define LIO_CN23XX_INTR_PPPF_ERR BIT_ULL(63) 346 347#define LIO_CN23XX_INTR_DMA0_DATA (LIO_CN23XX_INTR_DMA0_TIME) 348#define LIO_CN23XX_INTR_DMA1_DATA (LIO_CN23XX_INTR_DMA1_TIME) 349 350#define LIO_CN23XX_INTR_DMA_DATA \ 351 (LIO_CN23XX_INTR_DMA0_DATA | LIO_CN23XX_INTR_DMA1_DATA) 352 353/* By fault only TIME based */ 354#define LIO_CN23XX_INTR_PKT_DATA (LIO_CN23XX_INTR_PKT_TIME) 355 356/* Sum of interrupts for error events */ 357#define LIO_CN23XX_INTR_ERR \ 358 (LIO_CN23XX_INTR_M0UPB0_ERR | \ 359 LIO_CN23XX_INTR_M0UPWI_ERR | \ 360 LIO_CN23XX_INTR_M0UNB0_ERR | \ 361 LIO_CN23XX_INTR_M0UNWI_ERR | \ 362 LIO_CN23XX_INTR_DMAPF_ERR | \ 363 LIO_CN23XX_INTR_PKTPF_ERR | \ 364 LIO_CN23XX_INTR_PPPF_ERR) 365 366/* Programmed Mask for Interrupt Sum */ 367#define LIO_CN23XX_INTR_MASK \ 368 (LIO_CN23XX_INTR_DMA_DATA | \ 369 LIO_CN23XX_INTR_DMA0_FORCE | \ 370 LIO_CN23XX_INTR_DMA1_FORCE | \ 371 LIO_CN23XX_INTR_MIO_INT | \ 372 LIO_CN23XX_INTR_ERR) 373 374/* 4 Registers (64 - bit) */ 375#define LIO_CN23XX_SLI_S2M_PORT_CTL_START 0x23D80 376#define LIO_CN23XX_SLI_S2M_PORTX_CTL(port) \ 377 (LIO_CN23XX_SLI_S2M_PORT_CTL_START + \ 378 ((port) * 0x10)) 379 380#define LIO_CN23XX_SLI_MAC_NUMBER 0x20050 381 382/* 383 * PEM(0..3)_BAR1_INDEX(0..15)address is defined as 384 * addr = (0x00011800C0000100 |port <<24 |idx <<3 ) 385 * Here, port is PEM(0..3) & idx is INDEX(0..15) 386 */ 387#define LIO_CN23XX_PEM_BAR1_INDEX_START 0x00011800C0000100ULL 388#define LIO_CN23XX_PEM_OFFSET 24 389#define LIO_CN23XX_BAR1_INDEX_OFFSET 3 390 391#define LIO_CN23XX_PEM_BAR1_INDEX_REG(port, idx) \ 392 (LIO_CN23XX_PEM_BAR1_INDEX_START + \ 393 ((port) << LIO_CN23XX_PEM_OFFSET) + \ 394 ((idx) << LIO_CN23XX_BAR1_INDEX_OFFSET)) 395 396/*############################ DPI #########################*/ 397/* 4 Registers (64-bit) */ 398#define LIO_CN23XX_DPI_SLI_PRT_CFG_START 0x0001df0000000900ULL 399#define LIO_CN23XX_DPI_SLI_PRTX_CFG(port) \ 400 ((IO_CN23XX_DPI_SLI_PRT_CFG_START + \ 401 ((port) * 0x8)) 402 403/*############################ RST #########################*/ 404 405#define LIO_CN23XX_RST_BOOT 0x0001180006001600ULL 406#define LIO_CN23XX_RST_SOFT_RST 0x0001180006001680ULL 407 408#define LIO_CN23XX_LMC0_RESET_CTL 0x0001180088000180ULL 409#define LIO_CN23XX_LMC0_RESET_CTL_DDR3RST_MASK 0x0000000000000001ULL 410 411#endif /* __CN23XX_PF_REGS_H__ */ 412