1325618Ssbruno/* 2325618Ssbruno * BSD LICENSE 3325618Ssbruno * 4325618Ssbruno * Copyright(c) 2017 Cavium, Inc.. All rights reserved. 5325618Ssbruno * All rights reserved. 6325618Ssbruno * 7325618Ssbruno * Redistribution and use in source and binary forms, with or without 8325618Ssbruno * modification, are permitted provided that the following conditions 9325618Ssbruno * are met: 10325618Ssbruno * 11325618Ssbruno * * Redistributions of source code must retain the above copyright 12325618Ssbruno * notice, this list of conditions and the following disclaimer. 13325618Ssbruno * * Redistributions in binary form must reproduce the above copyright 14325618Ssbruno * notice, this list of conditions and the following disclaimer in 15325618Ssbruno * the documentation and/or other materials provided with the 16325618Ssbruno * distribution. 17325618Ssbruno * * Neither the name of Cavium, Inc. nor the names of its 18325618Ssbruno * contributors may be used to endorse or promote products derived 19325618Ssbruno * from this software without specific prior written permission. 20325618Ssbruno * 21325618Ssbruno * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22325618Ssbruno * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23325618Ssbruno * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24325618Ssbruno * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25325618Ssbruno * OWNER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26325618Ssbruno * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27325618Ssbruno * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28325618Ssbruno * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29325618Ssbruno * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30325618Ssbruno * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31325618Ssbruno * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32325618Ssbruno */ 33325618Ssbruno/*$FreeBSD: stable/11/sys/dev/liquidio/base/cn23xx_pf_device.c 325618 2017-11-09 19:52:56Z sbruno $*/ 34325618Ssbruno 35325618Ssbruno#include "lio_bsd.h" 36325618Ssbruno#include "lio_common.h" 37325618Ssbruno#include "lio_droq.h" 38325618Ssbruno#include "lio_iq.h" 39325618Ssbruno#include "lio_response_manager.h" 40325618Ssbruno#include "lio_device.h" 41325618Ssbruno#include "cn23xx_pf_device.h" 42325618Ssbruno#include "lio_main.h" 43325618Ssbruno#include "lio_rss.h" 44325618Ssbruno 45325618Ssbrunostatic int 46325618Ssbrunolio_cn23xx_pf_soft_reset(struct octeon_device *oct) 47325618Ssbruno{ 48325618Ssbruno 49325618Ssbruno lio_write_csr64(oct, LIO_CN23XX_SLI_WIN_WR_MASK_REG, 0xFF); 50325618Ssbruno 51325618Ssbruno lio_dev_dbg(oct, "BIST enabled for CN23XX soft reset\n"); 52325618Ssbruno 53325618Ssbruno lio_write_csr64(oct, LIO_CN23XX_SLI_SCRATCH1, 0x1234ULL); 54325618Ssbruno 55325618Ssbruno /* Initiate chip-wide soft reset */ 56325618Ssbruno lio_pci_readq(oct, LIO_CN23XX_RST_SOFT_RST); 57325618Ssbruno lio_pci_writeq(oct, 1, LIO_CN23XX_RST_SOFT_RST); 58325618Ssbruno 59325618Ssbruno /* Wait for 100ms as Octeon resets. */ 60325618Ssbruno lio_mdelay(100); 61325618Ssbruno 62325618Ssbruno if (lio_read_csr64(oct, LIO_CN23XX_SLI_SCRATCH1)) { 63325618Ssbruno lio_dev_err(oct, "Soft reset failed\n"); 64325618Ssbruno return (1); 65325618Ssbruno } 66325618Ssbruno 67325618Ssbruno lio_dev_dbg(oct, "Reset completed\n"); 68325618Ssbruno 69325618Ssbruno /* restore the reset value */ 70325618Ssbruno lio_write_csr64(oct, LIO_CN23XX_SLI_WIN_WR_MASK_REG, 0xFF); 71325618Ssbruno 72325618Ssbruno return (0); 73325618Ssbruno} 74325618Ssbruno 75325618Ssbrunostatic void 76325618Ssbrunolio_cn23xx_pf_enable_error_reporting(struct octeon_device *oct) 77325618Ssbruno{ 78325618Ssbruno uint32_t corrtable_err_status, uncorrectable_err_mask, regval; 79325618Ssbruno 80325618Ssbruno regval = lio_read_pci_cfg(oct, LIO_CN23XX_CFG_PCIE_DEVCTL); 81325618Ssbruno if (regval & LIO_CN23XX_CFG_PCIE_DEVCTL_MASK) { 82325618Ssbruno uncorrectable_err_mask = 0; 83325618Ssbruno corrtable_err_status = 0; 84325618Ssbruno uncorrectable_err_mask = 85325618Ssbruno lio_read_pci_cfg(oct, 86325618Ssbruno LIO_CN23XX_CFG_PCIE_UNCORRECT_ERR_MASK); 87325618Ssbruno corrtable_err_status = 88325618Ssbruno lio_read_pci_cfg(oct, 89325618Ssbruno LIO_CN23XX_CFG_PCIE_CORRECT_ERR_STATUS); 90325618Ssbruno lio_dev_err(oct, "PCI-E Fatal error detected;\n" 91325618Ssbruno "\tdev_ctl_status_reg = 0x%08x\n" 92325618Ssbruno "\tuncorrectable_error_mask_reg = 0x%08x\n" 93325618Ssbruno "\tcorrectable_error_status_reg = 0x%08x\n", 94325618Ssbruno regval, uncorrectable_err_mask, 95325618Ssbruno corrtable_err_status); 96325618Ssbruno } 97325618Ssbruno 98325618Ssbruno regval |= 0xf; /* Enable Link error reporting */ 99325618Ssbruno 100325618Ssbruno lio_dev_dbg(oct, "Enabling PCI-E error reporting..\n"); 101325618Ssbruno lio_write_pci_cfg(oct, LIO_CN23XX_CFG_PCIE_DEVCTL, regval); 102325618Ssbruno} 103325618Ssbruno 104325618Ssbrunostatic uint32_t 105325618Ssbrunolio_cn23xx_pf_coprocessor_clock(struct octeon_device *oct) 106325618Ssbruno{ 107325618Ssbruno /* 108325618Ssbruno * Bits 29:24 of RST_BOOT[PNR_MUL] holds the ref.clock MULTIPLIER 109325618Ssbruno * for SLI. 110325618Ssbruno */ 111325618Ssbruno 112325618Ssbruno /* TBD: get the info in Hand-shake */ 113325618Ssbruno return (((lio_pci_readq(oct, LIO_CN23XX_RST_BOOT) >> 24) & 0x3f) * 50); 114325618Ssbruno} 115325618Ssbruno 116325618Ssbrunouint32_t 117325618Ssbrunolio_cn23xx_pf_get_oq_ticks(struct octeon_device *oct, uint32_t time_intr_in_us) 118325618Ssbruno{ 119325618Ssbruno /* This gives the SLI clock per microsec */ 120325618Ssbruno uint32_t oqticks_per_us = lio_cn23xx_pf_coprocessor_clock(oct); 121325618Ssbruno 122325618Ssbruno oct->pfvf_hsword.coproc_tics_per_us = oqticks_per_us; 123325618Ssbruno 124325618Ssbruno /* This gives the clock cycles per millisecond */ 125325618Ssbruno oqticks_per_us *= 1000; 126325618Ssbruno 127325618Ssbruno /* This gives the oq ticks (1024 core clock cycles) per millisecond */ 128325618Ssbruno oqticks_per_us /= 1024; 129325618Ssbruno 130325618Ssbruno /* 131325618Ssbruno * time_intr is in microseconds. The next 2 steps gives the oq ticks 132325618Ssbruno * corresponding to time_intr. 133325618Ssbruno */ 134325618Ssbruno oqticks_per_us *= time_intr_in_us; 135325618Ssbruno oqticks_per_us /= 1000; 136325618Ssbruno 137325618Ssbruno return (oqticks_per_us); 138325618Ssbruno} 139325618Ssbruno 140325618Ssbrunostatic void 141325618Ssbrunolio_cn23xx_pf_setup_global_mac_regs(struct octeon_device *oct) 142325618Ssbruno{ 143325618Ssbruno uint64_t reg_val; 144325618Ssbruno uint16_t mac_no = oct->pcie_port; 145325618Ssbruno uint16_t pf_num = oct->pf_num; 146325618Ssbruno /* programming SRN and TRS for each MAC(0..3) */ 147325618Ssbruno 148325618Ssbruno lio_dev_dbg(oct, "%s: Using pcie port %d\n", __func__, mac_no); 149325618Ssbruno /* By default, mapping all 64 IOQs to a single MACs */ 150325618Ssbruno 151325618Ssbruno reg_val = 152325618Ssbruno lio_read_csr64(oct, LIO_CN23XX_SLI_PKT_MAC_RINFO64(mac_no, pf_num)); 153325618Ssbruno 154325618Ssbruno /* setting SRN <6:0> */ 155325618Ssbruno reg_val = pf_num * LIO_CN23XX_PF_MAX_RINGS; 156325618Ssbruno 157325618Ssbruno /* setting TRS <23:16> */ 158325618Ssbruno reg_val = reg_val | 159325618Ssbruno (oct->sriov_info.trs << LIO_CN23XX_PKT_MAC_CTL_RINFO_TRS_BIT_POS); 160325618Ssbruno 161325618Ssbruno /* write these settings to MAC register */ 162325618Ssbruno lio_write_csr64(oct, LIO_CN23XX_SLI_PKT_MAC_RINFO64(mac_no, pf_num), 163325618Ssbruno reg_val); 164325618Ssbruno 165325618Ssbruno lio_dev_dbg(oct, "SLI_PKT_MAC(%d)_PF(%d)_RINFO : 0x%016llx\n", mac_no, 166325618Ssbruno pf_num, 167325618Ssbruno LIO_CAST64(lio_read_csr64(oct, 168325618Ssbruno LIO_CN23XX_SLI_PKT_MAC_RINFO64(mac_no, 169325618Ssbruno pf_num)))); 170325618Ssbruno} 171325618Ssbruno 172325618Ssbrunostatic int 173325618Ssbrunolio_cn23xx_pf_reset_io_queues(struct octeon_device *oct) 174325618Ssbruno{ 175325618Ssbruno uint64_t d64; 176325618Ssbruno uint32_t ern, loop = BUSY_READING_REG_PF_LOOP_COUNT; 177325618Ssbruno uint32_t q_no, srn; 178325618Ssbruno int ret_val = 0; 179325618Ssbruno 180325618Ssbruno srn = oct->sriov_info.pf_srn; 181325618Ssbruno ern = srn + oct->sriov_info.num_pf_rings; 182325618Ssbruno 183325618Ssbruno /* As per HRM reg description, s/w cant write 0 to ENB. */ 184325618Ssbruno /* to make the queue off, need to set the RST bit. */ 185325618Ssbruno 186325618Ssbruno /* Reset the Enable bit for all the 64 IQs. */ 187325618Ssbruno for (q_no = srn; q_no < ern; q_no++) { 188325618Ssbruno /* set RST bit to 1. This bit applies to both IQ and OQ */ 189325618Ssbruno d64 = lio_read_csr64(oct, 190325618Ssbruno LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no)); 191325618Ssbruno d64 = d64 | LIO_CN23XX_PKT_INPUT_CTL_RST; 192325618Ssbruno lio_write_csr64(oct, 193325618Ssbruno LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no), d64); 194325618Ssbruno } 195325618Ssbruno 196325618Ssbruno /* wait until the RST bit is clear or the RST and quiet bits are set */ 197325618Ssbruno for (q_no = srn; q_no < ern; q_no++) { 198325618Ssbruno volatile uint64_t reg_val = 199325618Ssbruno lio_read_csr64(oct, 200325618Ssbruno LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no)); 201325618Ssbruno while ((reg_val & LIO_CN23XX_PKT_INPUT_CTL_RST) && 202325618Ssbruno !(reg_val & LIO_CN23XX_PKT_INPUT_CTL_QUIET) && 203325618Ssbruno loop) { 204325618Ssbruno reg_val = lio_read_csr64(oct, 205325618Ssbruno LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no)); 206325618Ssbruno loop--; 207325618Ssbruno } 208325618Ssbruno 209325618Ssbruno if (!loop) { 210325618Ssbruno lio_dev_err(oct, 211325618Ssbruno "clearing the reset reg failed or setting the quiet reg failed for qno: %u\n", 212325618Ssbruno q_no); 213325618Ssbruno return (-1); 214325618Ssbruno } 215325618Ssbruno 216325618Ssbruno reg_val &= ~LIO_CN23XX_PKT_INPUT_CTL_RST; 217325618Ssbruno lio_write_csr64(oct, LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no), 218325618Ssbruno reg_val); 219325618Ssbruno 220325618Ssbruno reg_val = lio_read_csr64(oct, 221325618Ssbruno LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no)); 222325618Ssbruno if (reg_val & LIO_CN23XX_PKT_INPUT_CTL_RST) { 223325618Ssbruno lio_dev_err(oct, "clearing the reset failed for qno: %u\n", 224325618Ssbruno q_no); 225325618Ssbruno ret_val = -1; 226325618Ssbruno } 227325618Ssbruno } 228325618Ssbruno 229325618Ssbruno return (ret_val); 230325618Ssbruno} 231325618Ssbruno 232325618Ssbrunostatic int 233325618Ssbrunolio_cn23xx_pf_setup_global_input_regs(struct octeon_device *oct) 234325618Ssbruno{ 235325618Ssbruno struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip; 236325618Ssbruno struct lio_instr_queue *iq; 237325618Ssbruno uint64_t intr_threshold; 238325618Ssbruno uint64_t pf_num, reg_val; 239325618Ssbruno uint32_t q_no, ern, srn; 240325618Ssbruno 241325618Ssbruno pf_num = oct->pf_num; 242325618Ssbruno 243325618Ssbruno srn = oct->sriov_info.pf_srn; 244325618Ssbruno ern = srn + oct->sriov_info.num_pf_rings; 245325618Ssbruno 246325618Ssbruno if (lio_cn23xx_pf_reset_io_queues(oct)) 247325618Ssbruno return (-1); 248325618Ssbruno 249325618Ssbruno /* 250325618Ssbruno * Set the MAC_NUM and PVF_NUM in IQ_PKT_CONTROL reg 251325618Ssbruno * for all queues.Only PF can set these bits. 252325618Ssbruno * bits 29:30 indicate the MAC num. 253325618Ssbruno * bits 32:47 indicate the PVF num. 254325618Ssbruno */ 255325618Ssbruno for (q_no = 0; q_no < ern; q_no++) { 256325618Ssbruno reg_val = oct->pcie_port << 257325618Ssbruno LIO_CN23XX_PKT_INPUT_CTL_MAC_NUM_POS; 258325618Ssbruno 259325618Ssbruno reg_val |= pf_num << LIO_CN23XX_PKT_INPUT_CTL_PF_NUM_POS; 260325618Ssbruno 261325618Ssbruno lio_write_csr64(oct, LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no), 262325618Ssbruno reg_val); 263325618Ssbruno } 264325618Ssbruno 265325618Ssbruno /* 266325618Ssbruno * Select ES, RO, NS, RDSIZE,DPTR Fomat#0 for 267325618Ssbruno * pf queues 268325618Ssbruno */ 269325618Ssbruno for (q_no = srn; q_no < ern; q_no++) { 270325618Ssbruno uint32_t inst_cnt_reg; 271325618Ssbruno 272325618Ssbruno iq = oct->instr_queue[q_no]; 273325618Ssbruno if (iq != NULL) 274325618Ssbruno inst_cnt_reg = iq->inst_cnt_reg; 275325618Ssbruno else 276325618Ssbruno inst_cnt_reg = LIO_CN23XX_SLI_IQ_INSTR_COUNT64(q_no); 277325618Ssbruno 278325618Ssbruno reg_val = 279325618Ssbruno lio_read_csr64(oct, LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no)); 280325618Ssbruno 281325618Ssbruno reg_val |= LIO_CN23XX_PKT_INPUT_CTL_MASK; 282325618Ssbruno 283325618Ssbruno lio_write_csr64(oct, LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no), 284325618Ssbruno reg_val); 285325618Ssbruno 286325618Ssbruno /* Set WMARK level for triggering PI_INT */ 287325618Ssbruno /* intr_threshold = LIO_CN23XX_DEF_IQ_INTR_THRESHOLD & */ 288325618Ssbruno intr_threshold = LIO_GET_IQ_INTR_PKT_CFG(cn23xx->conf) & 289325618Ssbruno LIO_CN23XX_PKT_IN_DONE_WMARK_MASK; 290325618Ssbruno 291325618Ssbruno lio_write_csr64(oct, inst_cnt_reg, 292325618Ssbruno (lio_read_csr64(oct, inst_cnt_reg) & 293325618Ssbruno ~(LIO_CN23XX_PKT_IN_DONE_WMARK_MASK << 294325618Ssbruno LIO_CN23XX_PKT_IN_DONE_WMARK_BIT_POS)) | 295325618Ssbruno (intr_threshold << 296325618Ssbruno LIO_CN23XX_PKT_IN_DONE_WMARK_BIT_POS)); 297325618Ssbruno } 298325618Ssbruno return (0); 299325618Ssbruno} 300325618Ssbruno 301325618Ssbrunostatic void 302325618Ssbrunolio_cn23xx_pf_setup_global_output_regs(struct octeon_device *oct) 303325618Ssbruno{ 304325618Ssbruno struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip; 305325618Ssbruno uint64_t time_threshold; 306325618Ssbruno uint32_t ern, q_no, reg_val, srn; 307325618Ssbruno 308325618Ssbruno srn = oct->sriov_info.pf_srn; 309325618Ssbruno ern = srn + oct->sriov_info.num_pf_rings; 310325618Ssbruno 311325618Ssbruno if (LIO_GET_IS_SLI_BP_ON_CFG(cn23xx->conf)) { 312325618Ssbruno lio_write_csr64(oct, LIO_CN23XX_SLI_OQ_WMARK, 32); 313325618Ssbruno } else { 314325618Ssbruno /* Set Output queue watermark to 0 to disable backpressure */ 315325618Ssbruno lio_write_csr64(oct, LIO_CN23XX_SLI_OQ_WMARK, 0); 316325618Ssbruno } 317325618Ssbruno 318325618Ssbruno for (q_no = srn; q_no < ern; q_no++) { 319325618Ssbruno reg_val = lio_read_csr32(oct, 320325618Ssbruno LIO_CN23XX_SLI_OQ_PKT_CONTROL(q_no)); 321325618Ssbruno 322325618Ssbruno /* set IPTR & DPTR */ 323325618Ssbruno reg_val |= LIO_CN23XX_PKT_OUTPUT_CTL_DPTR; 324325618Ssbruno 325325618Ssbruno /* reset BMODE */ 326325618Ssbruno reg_val &= ~(LIO_CN23XX_PKT_OUTPUT_CTL_BMODE); 327325618Ssbruno 328325618Ssbruno /* 329325618Ssbruno * No Relaxed Ordering, No Snoop, 64-bit Byte swap for 330325618Ssbruno * Output Queue ScatterList reset ROR_P, NSR_P 331325618Ssbruno */ 332325618Ssbruno reg_val &= ~(LIO_CN23XX_PKT_OUTPUT_CTL_ROR_P); 333325618Ssbruno reg_val &= ~(LIO_CN23XX_PKT_OUTPUT_CTL_NSR_P); 334325618Ssbruno 335325618Ssbruno#if BYTE_ORDER == LITTLE_ENDIAN 336325618Ssbruno reg_val &= ~(LIO_CN23XX_PKT_OUTPUT_CTL_ES_P); 337325618Ssbruno#else /* BYTE_ORDER != LITTLE_ENDIAN */ 338325618Ssbruno reg_val |= (LIO_CN23XX_PKT_OUTPUT_CTL_ES_P); 339325618Ssbruno#endif /* BYTE_ORDER == LITTLE_ENDIAN */ 340325618Ssbruno 341325618Ssbruno /* 342325618Ssbruno * No Relaxed Ordering, No Snoop, 64-bit Byte swap for 343325618Ssbruno * Output Queue Data reset ROR, NSR 344325618Ssbruno */ 345325618Ssbruno reg_val &= ~(LIO_CN23XX_PKT_OUTPUT_CTL_ROR); 346325618Ssbruno reg_val &= ~(LIO_CN23XX_PKT_OUTPUT_CTL_NSR); 347325618Ssbruno /* set the ES bit */ 348325618Ssbruno reg_val |= (LIO_CN23XX_PKT_OUTPUT_CTL_ES); 349325618Ssbruno 350325618Ssbruno /* write all the selected settings */ 351325618Ssbruno lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_PKT_CONTROL(q_no), 352325618Ssbruno reg_val); 353325618Ssbruno 354325618Ssbruno /* 355325618Ssbruno * Enabling these interrupt in oct->fn_list.enable_interrupt() 356325618Ssbruno * routine which called after IOQ init. 357325618Ssbruno * Set up interrupt packet and time thresholds 358325618Ssbruno * for all the OQs 359325618Ssbruno */ 360325618Ssbruno time_threshold =lio_cn23xx_pf_get_oq_ticks( 361325618Ssbruno oct, (uint32_t)LIO_GET_OQ_INTR_TIME_CFG(cn23xx->conf)); 362325618Ssbruno 363325618Ssbruno lio_write_csr64(oct, LIO_CN23XX_SLI_OQ_PKT_INT_LEVELS(q_no), 364325618Ssbruno (LIO_GET_OQ_INTR_PKT_CFG(cn23xx->conf) | 365325618Ssbruno (time_threshold << 32))); 366325618Ssbruno } 367325618Ssbruno 368325618Ssbruno /* Setting the water mark level for pko back pressure * */ 369325618Ssbruno lio_write_csr64(oct, LIO_CN23XX_SLI_OQ_WMARK, 0x40); 370325618Ssbruno 371325618Ssbruno /* Enable channel-level backpressure */ 372325618Ssbruno if (oct->pf_num) 373325618Ssbruno lio_write_csr64(oct, LIO_CN23XX_SLI_OUT_BP_EN2_W1S, 374325618Ssbruno 0xffffffffffffffffULL); 375325618Ssbruno else 376325618Ssbruno lio_write_csr64(oct, LIO_CN23XX_SLI_OUT_BP_EN_W1S, 377325618Ssbruno 0xffffffffffffffffULL); 378325618Ssbruno} 379325618Ssbruno 380325618Ssbrunostatic int 381325618Ssbrunolio_cn23xx_pf_setup_device_regs(struct octeon_device *oct) 382325618Ssbruno{ 383325618Ssbruno 384325618Ssbruno lio_cn23xx_pf_enable_error_reporting(oct); 385325618Ssbruno 386325618Ssbruno /* program the MAC(0..3)_RINFO before setting up input/output regs */ 387325618Ssbruno lio_cn23xx_pf_setup_global_mac_regs(oct); 388325618Ssbruno 389325618Ssbruno if (lio_cn23xx_pf_setup_global_input_regs(oct)) 390325618Ssbruno return (-1); 391325618Ssbruno 392325618Ssbruno lio_cn23xx_pf_setup_global_output_regs(oct); 393325618Ssbruno 394325618Ssbruno /* 395325618Ssbruno * Default error timeout value should be 0x200000 to avoid host hang 396325618Ssbruno * when reads invalid register 397325618Ssbruno */ 398325618Ssbruno lio_write_csr64(oct, LIO_CN23XX_SLI_WINDOW_CTL, 399325618Ssbruno LIO_CN23XX_SLI_WINDOW_CTL_DEFAULT); 400325618Ssbruno 401325618Ssbruno /* set SLI_PKT_IN_JABBER to handle large VXLAN packets */ 402325618Ssbruno lio_write_csr64(oct, LIO_CN23XX_SLI_PKT_IN_JABBER, 403325618Ssbruno LIO_CN23XX_MAX_INPUT_JABBER); 404325618Ssbruno return (0); 405325618Ssbruno} 406325618Ssbruno 407325618Ssbrunostatic void 408325618Ssbrunolio_cn23xx_pf_setup_iq_regs(struct octeon_device *oct, uint32_t iq_no) 409325618Ssbruno{ 410325618Ssbruno struct lio_instr_queue *iq = oct->instr_queue[iq_no]; 411325618Ssbruno uint64_t pkt_in_done; 412325618Ssbruno 413325618Ssbruno iq_no += oct->sriov_info.pf_srn; 414325618Ssbruno 415325618Ssbruno /* Write the start of the input queue's ring and its size */ 416325618Ssbruno lio_write_csr64(oct, LIO_CN23XX_SLI_IQ_BASE_ADDR64(iq_no), 417325618Ssbruno iq->base_addr_dma); 418325618Ssbruno lio_write_csr32(oct, LIO_CN23XX_SLI_IQ_SIZE(iq_no), iq->max_count); 419325618Ssbruno 420325618Ssbruno /* 421325618Ssbruno * Remember the doorbell & instruction count register addr 422325618Ssbruno * for this queue 423325618Ssbruno */ 424325618Ssbruno iq->doorbell_reg = LIO_CN23XX_SLI_IQ_DOORBELL(iq_no); 425325618Ssbruno iq->inst_cnt_reg = LIO_CN23XX_SLI_IQ_INSTR_COUNT64(iq_no); 426325618Ssbruno lio_dev_dbg(oct, "InstQ[%d]:dbell reg @ 0x%x instcnt_reg @ 0x%x\n", 427325618Ssbruno iq_no, iq->doorbell_reg, iq->inst_cnt_reg); 428325618Ssbruno 429325618Ssbruno /* 430325618Ssbruno * Store the current instruction counter (used in flush_iq 431325618Ssbruno * calculation) 432325618Ssbruno */ 433325618Ssbruno pkt_in_done = lio_read_csr64(oct, iq->inst_cnt_reg); 434325618Ssbruno 435325618Ssbruno if (oct->msix_on) { 436325618Ssbruno /* Set CINT_ENB to enable IQ interrupt */ 437325618Ssbruno lio_write_csr64(oct, iq->inst_cnt_reg, 438325618Ssbruno (pkt_in_done | LIO_CN23XX_INTR_CINT_ENB)); 439325618Ssbruno } else { 440325618Ssbruno /* 441325618Ssbruno * Clear the count by writing back what we read, but don't 442325618Ssbruno * enable interrupts 443325618Ssbruno */ 444325618Ssbruno lio_write_csr64(oct, iq->inst_cnt_reg, pkt_in_done); 445325618Ssbruno } 446325618Ssbruno 447325618Ssbruno iq->reset_instr_cnt = 0; 448325618Ssbruno} 449325618Ssbruno 450325618Ssbrunostatic void 451325618Ssbrunolio_cn23xx_pf_setup_oq_regs(struct octeon_device *oct, uint32_t oq_no) 452325618Ssbruno{ 453325618Ssbruno struct lio_droq *droq = oct->droq[oq_no]; 454325618Ssbruno struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip; 455325618Ssbruno uint64_t cnt_threshold; 456325618Ssbruno uint64_t time_threshold; 457325618Ssbruno uint32_t reg_val; 458325618Ssbruno 459325618Ssbruno oq_no += oct->sriov_info.pf_srn; 460325618Ssbruno 461325618Ssbruno lio_write_csr64(oct, LIO_CN23XX_SLI_OQ_BASE_ADDR64(oq_no), 462325618Ssbruno droq->desc_ring_dma); 463325618Ssbruno lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_SIZE(oq_no), droq->max_count); 464325618Ssbruno 465325618Ssbruno lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_BUFF_INFO_SIZE(oq_no), 466325618Ssbruno droq->buffer_size); 467325618Ssbruno 468325618Ssbruno /* pkt_sent and pkts_credit regs */ 469325618Ssbruno droq->pkts_sent_reg = LIO_CN23XX_SLI_OQ_PKTS_SENT(oq_no); 470325618Ssbruno droq->pkts_credit_reg = LIO_CN23XX_SLI_OQ_PKTS_CREDIT(oq_no); 471325618Ssbruno 472325618Ssbruno if (!oct->msix_on) { 473325618Ssbruno /* 474325618Ssbruno * Enable this output queue to generate Packet Timer 475325618Ssbruno * Interrupt 476325618Ssbruno */ 477325618Ssbruno reg_val = 478325618Ssbruno lio_read_csr32(oct, LIO_CN23XX_SLI_OQ_PKT_CONTROL(oq_no)); 479325618Ssbruno reg_val |= LIO_CN23XX_PKT_OUTPUT_CTL_TENB; 480325618Ssbruno lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_PKT_CONTROL(oq_no), 481325618Ssbruno reg_val); 482325618Ssbruno 483325618Ssbruno /* 484325618Ssbruno * Enable this output queue to generate Packet Count 485325618Ssbruno * Interrupt 486325618Ssbruno */ 487325618Ssbruno reg_val = 488325618Ssbruno lio_read_csr32(oct, LIO_CN23XX_SLI_OQ_PKT_CONTROL(oq_no)); 489325618Ssbruno reg_val |= LIO_CN23XX_PKT_OUTPUT_CTL_CENB; 490325618Ssbruno lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_PKT_CONTROL(oq_no), 491325618Ssbruno reg_val); 492325618Ssbruno } else { 493325618Ssbruno time_threshold = lio_cn23xx_pf_get_oq_ticks(oct, 494325618Ssbruno (uint32_t)LIO_GET_OQ_INTR_TIME_CFG(cn23xx->conf)); 495325618Ssbruno cnt_threshold = (uint32_t)LIO_GET_OQ_INTR_PKT_CFG(cn23xx->conf); 496325618Ssbruno 497325618Ssbruno lio_write_csr64(oct, LIO_CN23XX_SLI_OQ_PKT_INT_LEVELS(oq_no), 498325618Ssbruno ((time_threshold << 32 | cnt_threshold))); 499325618Ssbruno } 500325618Ssbruno} 501325618Ssbruno 502325618Ssbruno 503325618Ssbrunostatic int 504325618Ssbrunolio_cn23xx_pf_enable_io_queues(struct octeon_device *oct) 505325618Ssbruno{ 506325618Ssbruno uint64_t reg_val; 507325618Ssbruno uint32_t ern, loop = BUSY_READING_REG_PF_LOOP_COUNT; 508325618Ssbruno uint32_t q_no, srn; 509325618Ssbruno 510325618Ssbruno srn = oct->sriov_info.pf_srn; 511325618Ssbruno ern = srn + oct->num_iqs; 512325618Ssbruno 513325618Ssbruno for (q_no = srn; q_no < ern; q_no++) { 514325618Ssbruno /* set the corresponding IQ IS_64B bit */ 515325618Ssbruno if (oct->io_qmask.iq64B & BIT_ULL(q_no - srn)) { 516325618Ssbruno reg_val = lio_read_csr64(oct, 517325618Ssbruno LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no)); 518325618Ssbruno reg_val = reg_val | LIO_CN23XX_PKT_INPUT_CTL_IS_64B; 519325618Ssbruno lio_write_csr64(oct, 520325618Ssbruno LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no), 521325618Ssbruno reg_val); 522325618Ssbruno } 523325618Ssbruno /* set the corresponding IQ ENB bit */ 524325618Ssbruno if (oct->io_qmask.iq & BIT_ULL(q_no - srn)) { 525325618Ssbruno /* 526325618Ssbruno * IOQs are in reset by default in PEM2 mode, 527325618Ssbruno * clearing reset bit 528325618Ssbruno */ 529325618Ssbruno reg_val = lio_read_csr64(oct, 530325618Ssbruno LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no)); 531325618Ssbruno 532325618Ssbruno if (reg_val & LIO_CN23XX_PKT_INPUT_CTL_RST) { 533325618Ssbruno while ((reg_val & 534325618Ssbruno LIO_CN23XX_PKT_INPUT_CTL_RST) && 535325618Ssbruno !(reg_val & 536325618Ssbruno LIO_CN23XX_PKT_INPUT_CTL_QUIET) && 537325618Ssbruno loop) { 538325618Ssbruno reg_val = lio_read_csr64(oct, 539325618Ssbruno LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no)); 540325618Ssbruno loop--; 541325618Ssbruno } 542325618Ssbruno if (!loop) { 543325618Ssbruno lio_dev_err(oct, "clearing the reset reg failed or setting the quiet reg failed for qno: %u\n", 544325618Ssbruno q_no); 545325618Ssbruno return (-1); 546325618Ssbruno } 547325618Ssbruno reg_val = reg_val & 548325618Ssbruno ~LIO_CN23XX_PKT_INPUT_CTL_RST; 549325618Ssbruno lio_write_csr64(oct, 550325618Ssbruno LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no), 551325618Ssbruno reg_val); 552325618Ssbruno 553325618Ssbruno reg_val = lio_read_csr64(oct, 554325618Ssbruno LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no)); 555325618Ssbruno if (reg_val & LIO_CN23XX_PKT_INPUT_CTL_RST) { 556325618Ssbruno lio_dev_err(oct, "clearing the reset failed for qno: %u\n", 557325618Ssbruno q_no); 558325618Ssbruno return (-1); 559325618Ssbruno } 560325618Ssbruno } 561325618Ssbruno reg_val = lio_read_csr64(oct, 562325618Ssbruno LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no)); 563325618Ssbruno reg_val = reg_val | LIO_CN23XX_PKT_INPUT_CTL_RING_ENB; 564325618Ssbruno lio_write_csr64(oct, 565325618Ssbruno LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no), 566325618Ssbruno reg_val); 567325618Ssbruno } 568325618Ssbruno } 569325618Ssbruno for (q_no = srn; q_no < ern; q_no++) { 570325618Ssbruno uint32_t reg_val; 571325618Ssbruno /* set the corresponding OQ ENB bit */ 572325618Ssbruno if (oct->io_qmask.oq & BIT_ULL(q_no - srn)) { 573325618Ssbruno reg_val = lio_read_csr32(oct, 574325618Ssbruno LIO_CN23XX_SLI_OQ_PKT_CONTROL(q_no)); 575325618Ssbruno reg_val = reg_val | LIO_CN23XX_PKT_OUTPUT_CTL_RING_ENB; 576325618Ssbruno lio_write_csr32(oct, 577325618Ssbruno LIO_CN23XX_SLI_OQ_PKT_CONTROL(q_no), 578325618Ssbruno reg_val); 579325618Ssbruno } 580325618Ssbruno } 581325618Ssbruno return (0); 582325618Ssbruno} 583325618Ssbruno 584325618Ssbrunostatic void 585325618Ssbrunolio_cn23xx_pf_disable_io_queues(struct octeon_device *oct) 586325618Ssbruno{ 587325618Ssbruno volatile uint64_t d64; 588325618Ssbruno volatile uint32_t d32; 589325618Ssbruno int loop; 590325618Ssbruno unsigned int q_no; 591325618Ssbruno uint32_t ern, srn; 592325618Ssbruno 593325618Ssbruno srn = oct->sriov_info.pf_srn; 594325618Ssbruno ern = srn + oct->num_iqs; 595325618Ssbruno 596325618Ssbruno /* Disable Input Queues. */ 597325618Ssbruno for (q_no = srn; q_no < ern; q_no++) { 598325618Ssbruno loop = lio_ms_to_ticks(1000); 599325618Ssbruno 600325618Ssbruno /* start the Reset for a particular ring */ 601325618Ssbruno d64 = lio_read_csr64(oct, 602325618Ssbruno LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no)); 603325618Ssbruno d64 &= ~LIO_CN23XX_PKT_INPUT_CTL_RING_ENB; 604325618Ssbruno d64 |= LIO_CN23XX_PKT_INPUT_CTL_RST; 605325618Ssbruno lio_write_csr64(oct, LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no), 606325618Ssbruno d64); 607325618Ssbruno 608325618Ssbruno /* 609325618Ssbruno * Wait until hardware indicates that the particular IQ 610325618Ssbruno * is out of reset. 611325618Ssbruno */ 612325618Ssbruno d64 = lio_read_csr64(oct, LIO_CN23XX_SLI_PKT_IOQ_RING_RST); 613325618Ssbruno while (!(d64 & BIT_ULL(q_no)) && loop--) { 614325618Ssbruno d64 = lio_read_csr64(oct, 615325618Ssbruno LIO_CN23XX_SLI_PKT_IOQ_RING_RST); 616325618Ssbruno lio_sleep_timeout(1); 617325618Ssbruno loop--; 618325618Ssbruno } 619325618Ssbruno 620325618Ssbruno /* Reset the doorbell register for this Input Queue. */ 621325618Ssbruno lio_write_csr32(oct, LIO_CN23XX_SLI_IQ_DOORBELL(q_no), 622325618Ssbruno 0xFFFFFFFF); 623325618Ssbruno while (((lio_read_csr64(oct, 624325618Ssbruno LIO_CN23XX_SLI_IQ_DOORBELL(q_no))) != 625325618Ssbruno 0ULL) && loop--) { 626325618Ssbruno lio_sleep_timeout(1); 627325618Ssbruno } 628325618Ssbruno } 629325618Ssbruno 630325618Ssbruno /* Disable Output Queues. */ 631325618Ssbruno for (q_no = srn; q_no < ern; q_no++) { 632325618Ssbruno loop = lio_ms_to_ticks(1000); 633325618Ssbruno 634325618Ssbruno /* 635325618Ssbruno * Wait until hardware indicates that the particular IQ 636325618Ssbruno * is out of reset.It given that SLI_PKT_RING_RST is 637325618Ssbruno * common for both IQs and OQs 638325618Ssbruno */ 639325618Ssbruno d64 = lio_read_csr64(oct, LIO_CN23XX_SLI_PKT_IOQ_RING_RST); 640325618Ssbruno while (!(d64 & BIT_ULL(q_no)) && loop--) { 641325618Ssbruno d64 = lio_read_csr64(oct, 642325618Ssbruno LIO_CN23XX_SLI_PKT_IOQ_RING_RST); 643325618Ssbruno lio_sleep_timeout(1); 644325618Ssbruno loop--; 645325618Ssbruno } 646325618Ssbruno 647325618Ssbruno /* Reset the doorbell register for this Output Queue. */ 648325618Ssbruno lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_PKTS_CREDIT(q_no), 649325618Ssbruno 0xFFFFFFFF); 650325618Ssbruno while ((lio_read_csr64(oct, 651325618Ssbruno LIO_CN23XX_SLI_OQ_PKTS_CREDIT(q_no)) != 652325618Ssbruno 0ULL) && loop--) { 653325618Ssbruno lio_sleep_timeout(1); 654325618Ssbruno } 655325618Ssbruno 656325618Ssbruno /* clear the SLI_PKT(0..63)_CNTS[CNT] reg value */ 657325618Ssbruno d32 = lio_read_csr32(oct, LIO_CN23XX_SLI_OQ_PKTS_SENT(q_no)); 658325618Ssbruno lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_PKTS_SENT(q_no), d32); 659325618Ssbruno } 660325618Ssbruno} 661325618Ssbruno 662325618Ssbrunostatic uint64_t 663325618Ssbrunolio_cn23xx_pf_msix_interrupt_handler(void *dev) 664325618Ssbruno{ 665325618Ssbruno struct lio_ioq_vector *ioq_vector = (struct lio_ioq_vector *)dev; 666325618Ssbruno struct octeon_device *oct = ioq_vector->oct_dev; 667325618Ssbruno struct lio_droq *droq = oct->droq[ioq_vector->droq_index]; 668325618Ssbruno uint64_t pkts_sent; 669325618Ssbruno uint64_t ret = 0; 670325618Ssbruno 671325618Ssbruno if (droq == NULL) { 672325618Ssbruno lio_dev_err(oct, "23XX bringup FIXME: oct pfnum:%d ioq_vector->ioq_num :%d droq is NULL\n", 673325618Ssbruno oct->pf_num, ioq_vector->ioq_num); 674325618Ssbruno return (0); 675325618Ssbruno } 676325618Ssbruno pkts_sent = lio_read_csr64(oct, droq->pkts_sent_reg); 677325618Ssbruno 678325618Ssbruno /* 679325618Ssbruno * If our device has interrupted, then proceed. Also check 680325618Ssbruno * for all f's if interrupt was triggered on an error 681325618Ssbruno * and the PCI read fails. 682325618Ssbruno */ 683325618Ssbruno if (!pkts_sent || (pkts_sent == 0xFFFFFFFFFFFFFFFFULL)) 684325618Ssbruno return (ret); 685325618Ssbruno 686325618Ssbruno /* Write count reg in sli_pkt_cnts to clear these int. */ 687325618Ssbruno if (pkts_sent & LIO_CN23XX_INTR_PO_INT) 688325618Ssbruno ret |= LIO_MSIX_PO_INT; 689325618Ssbruno 690325618Ssbruno if (pkts_sent & LIO_CN23XX_INTR_PI_INT) 691325618Ssbruno /* We will clear the count when we update the read_index. */ 692325618Ssbruno ret |= LIO_MSIX_PI_INT; 693325618Ssbruno 694325618Ssbruno /* 695325618Ssbruno * Never need to handle msix mbox intr for pf. They arrive on the last 696325618Ssbruno * msix 697325618Ssbruno */ 698325618Ssbruno return (ret); 699325618Ssbruno} 700325618Ssbruno 701325618Ssbrunostatic void 702325618Ssbrunolio_cn23xx_pf_interrupt_handler(void *dev) 703325618Ssbruno{ 704325618Ssbruno struct octeon_device *oct = (struct octeon_device *)dev; 705325618Ssbruno struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip; 706325618Ssbruno uint64_t intr64; 707325618Ssbruno 708325618Ssbruno lio_dev_dbg(oct, "In %s octeon_dev @ %p\n", __func__, oct); 709325618Ssbruno intr64 = lio_read_csr64(oct, cn23xx->intr_sum_reg64); 710325618Ssbruno 711325618Ssbruno oct->int_status = 0; 712325618Ssbruno 713325618Ssbruno if (intr64 & LIO_CN23XX_INTR_ERR) 714325618Ssbruno lio_dev_err(oct, "Error Intr: 0x%016llx\n", 715325618Ssbruno LIO_CAST64(intr64)); 716325618Ssbruno 717325618Ssbruno if (oct->msix_on != LIO_FLAG_MSIX_ENABLED) { 718325618Ssbruno if (intr64 & LIO_CN23XX_INTR_PKT_DATA) 719325618Ssbruno oct->int_status |= LIO_DEV_INTR_PKT_DATA; 720325618Ssbruno } 721325618Ssbruno 722325618Ssbruno if (intr64 & (LIO_CN23XX_INTR_DMA0_FORCE)) 723325618Ssbruno oct->int_status |= LIO_DEV_INTR_DMA0_FORCE; 724325618Ssbruno 725325618Ssbruno if (intr64 & (LIO_CN23XX_INTR_DMA1_FORCE)) 726325618Ssbruno oct->int_status |= LIO_DEV_INTR_DMA1_FORCE; 727325618Ssbruno 728325618Ssbruno /* Clear the current interrupts */ 729325618Ssbruno lio_write_csr64(oct, cn23xx->intr_sum_reg64, intr64); 730325618Ssbruno} 731325618Ssbruno 732325618Ssbrunostatic void 733325618Ssbrunolio_cn23xx_pf_bar1_idx_setup(struct octeon_device *oct, uint64_t core_addr, 734325618Ssbruno uint32_t idx, int valid) 735325618Ssbruno{ 736325618Ssbruno volatile uint64_t bar1; 737325618Ssbruno uint64_t reg_adr; 738325618Ssbruno 739325618Ssbruno if (!valid) { 740325618Ssbruno reg_adr = lio_pci_readq(oct, 741325618Ssbruno LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, 742325618Ssbruno idx)); 743325618Ssbruno bar1 = reg_adr; 744325618Ssbruno lio_pci_writeq(oct, (bar1 & 0xFFFFFFFEULL), 745325618Ssbruno LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, 746325618Ssbruno idx)); 747325618Ssbruno reg_adr = lio_pci_readq(oct, 748325618Ssbruno LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, 749325618Ssbruno idx)); 750325618Ssbruno bar1 = reg_adr; 751325618Ssbruno return; 752325618Ssbruno } 753325618Ssbruno /* 754325618Ssbruno * The PEM(0..3)_BAR1_INDEX(0..15)[ADDR_IDX]<23:4> stores 755325618Ssbruno * bits <41:22> of the Core Addr 756325618Ssbruno */ 757325618Ssbruno lio_pci_writeq(oct, (((core_addr >> 22) << 4) | LIO_PCI_BAR1_MASK), 758325618Ssbruno LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx)); 759325618Ssbruno 760325618Ssbruno bar1 = lio_pci_readq(oct, LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, 761325618Ssbruno idx)); 762325618Ssbruno} 763325618Ssbruno 764325618Ssbrunostatic void 765325618Ssbrunolio_cn23xx_pf_bar1_idx_write(struct octeon_device *oct, uint32_t idx, 766325618Ssbruno uint32_t mask) 767325618Ssbruno{ 768325618Ssbruno 769325618Ssbruno lio_pci_writeq(oct, mask, 770325618Ssbruno LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx)); 771325618Ssbruno} 772325618Ssbruno 773325618Ssbrunostatic uint32_t 774325618Ssbrunolio_cn23xx_pf_bar1_idx_read(struct octeon_device *oct, uint32_t idx) 775325618Ssbruno{ 776325618Ssbruno 777325618Ssbruno return ((uint32_t)lio_pci_readq(oct, 778325618Ssbruno LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, 779325618Ssbruno idx))); 780325618Ssbruno} 781325618Ssbruno 782325618Ssbruno/* always call with lock held */ 783325618Ssbrunostatic uint32_t 784325618Ssbrunolio_cn23xx_pf_update_read_index(struct lio_instr_queue *iq) 785325618Ssbruno{ 786325618Ssbruno struct octeon_device *oct = iq->oct_dev; 787325618Ssbruno uint32_t new_idx; 788325618Ssbruno uint32_t last_done; 789325618Ssbruno uint32_t pkt_in_done = lio_read_csr32(oct, iq->inst_cnt_reg); 790325618Ssbruno 791325618Ssbruno last_done = pkt_in_done - iq->pkt_in_done; 792325618Ssbruno iq->pkt_in_done = pkt_in_done; 793325618Ssbruno 794325618Ssbruno /* 795325618Ssbruno * Modulo of the new index with the IQ size will give us 796325618Ssbruno * the new index. The iq->reset_instr_cnt is always zero for 797325618Ssbruno * cn23xx, so no extra adjustments are needed. 798325618Ssbruno */ 799325618Ssbruno new_idx = (iq->octeon_read_index + 800325618Ssbruno ((uint32_t)(last_done & LIO_CN23XX_PKT_IN_DONE_CNT_MASK))) % 801325618Ssbruno iq->max_count; 802325618Ssbruno 803325618Ssbruno return (new_idx); 804325618Ssbruno} 805325618Ssbruno 806325618Ssbrunostatic void 807325618Ssbrunolio_cn23xx_pf_enable_interrupt(struct octeon_device *oct, uint8_t intr_flag) 808325618Ssbruno{ 809325618Ssbruno struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip; 810325618Ssbruno uint64_t intr_val = 0; 811325618Ssbruno 812325618Ssbruno /* Divide the single write to multiple writes based on the flag. */ 813325618Ssbruno /* Enable Interrupt */ 814325618Ssbruno if (intr_flag == OCTEON_ALL_INTR) { 815325618Ssbruno lio_write_csr64(oct, cn23xx->intr_enb_reg64, 816325618Ssbruno cn23xx->intr_mask64); 817325618Ssbruno } else if (intr_flag & OCTEON_OUTPUT_INTR) { 818325618Ssbruno intr_val = lio_read_csr64(oct, cn23xx->intr_enb_reg64); 819325618Ssbruno intr_val |= LIO_CN23XX_INTR_PKT_DATA; 820325618Ssbruno lio_write_csr64(oct, cn23xx->intr_enb_reg64, intr_val); 821325618Ssbruno } 822325618Ssbruno} 823325618Ssbruno 824325618Ssbrunostatic void 825325618Ssbrunolio_cn23xx_pf_disable_interrupt(struct octeon_device *oct, uint8_t intr_flag) 826325618Ssbruno{ 827325618Ssbruno struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip; 828325618Ssbruno uint64_t intr_val = 0; 829325618Ssbruno 830325618Ssbruno /* Disable Interrupts */ 831325618Ssbruno if (intr_flag == OCTEON_ALL_INTR) { 832325618Ssbruno lio_write_csr64(oct, cn23xx->intr_enb_reg64, 0); 833325618Ssbruno } else if (intr_flag & OCTEON_OUTPUT_INTR) { 834325618Ssbruno intr_val = lio_read_csr64(oct, cn23xx->intr_enb_reg64); 835325618Ssbruno intr_val &= ~LIO_CN23XX_INTR_PKT_DATA; 836325618Ssbruno lio_write_csr64(oct, cn23xx->intr_enb_reg64, intr_val); 837325618Ssbruno } 838325618Ssbruno} 839325618Ssbruno 840325618Ssbrunostatic void 841325618Ssbrunolio_cn23xx_pf_get_pcie_qlmport(struct octeon_device *oct) 842325618Ssbruno{ 843325618Ssbruno oct->pcie_port = (lio_read_csr32(oct, 844325618Ssbruno LIO_CN23XX_SLI_MAC_NUMBER)) & 0xff; 845325618Ssbruno 846325618Ssbruno lio_dev_dbg(oct, "CN23xx uses PCIE Port %d\n", 847325618Ssbruno oct->pcie_port); 848325618Ssbruno} 849325618Ssbruno 850325618Ssbrunostatic void 851325618Ssbrunolio_cn23xx_pf_get_pf_num(struct octeon_device *oct) 852325618Ssbruno{ 853325618Ssbruno uint32_t fdl_bit; 854325618Ssbruno 855325618Ssbruno /* Read Function Dependency Link reg to get the function number */ 856325618Ssbruno fdl_bit = lio_read_pci_cfg(oct, LIO_CN23XX_PCIE_SRIOV_FDL); 857325618Ssbruno oct->pf_num = ((fdl_bit >> LIO_CN23XX_PCIE_SRIOV_FDL_BIT_POS) & 858325618Ssbruno LIO_CN23XX_PCIE_SRIOV_FDL_MASK); 859325618Ssbruno} 860325618Ssbruno 861325618Ssbrunostatic void 862325618Ssbrunolio_cn23xx_pf_setup_reg_address(struct octeon_device *oct) 863325618Ssbruno{ 864325618Ssbruno struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip; 865325618Ssbruno 866325618Ssbruno oct->reg_list.pci_win_wr_addr = LIO_CN23XX_SLI_WIN_WR_ADDR64; 867325618Ssbruno 868325618Ssbruno oct->reg_list.pci_win_rd_addr_hi = LIO_CN23XX_SLI_WIN_RD_ADDR_HI; 869325618Ssbruno oct->reg_list.pci_win_rd_addr_lo = LIO_CN23XX_SLI_WIN_RD_ADDR64; 870325618Ssbruno oct->reg_list.pci_win_rd_addr = LIO_CN23XX_SLI_WIN_RD_ADDR64; 871325618Ssbruno 872325618Ssbruno oct->reg_list.pci_win_wr_data_hi = LIO_CN23XX_SLI_WIN_WR_DATA_HI; 873325618Ssbruno oct->reg_list.pci_win_wr_data_lo = LIO_CN23XX_SLI_WIN_WR_DATA_LO; 874325618Ssbruno oct->reg_list.pci_win_wr_data = LIO_CN23XX_SLI_WIN_WR_DATA64; 875325618Ssbruno 876325618Ssbruno oct->reg_list.pci_win_rd_data = LIO_CN23XX_SLI_WIN_RD_DATA64; 877325618Ssbruno 878325618Ssbruno lio_cn23xx_pf_get_pcie_qlmport(oct); 879325618Ssbruno 880325618Ssbruno cn23xx->intr_mask64 = LIO_CN23XX_INTR_MASK; 881325618Ssbruno if (!oct->msix_on) 882325618Ssbruno cn23xx->intr_mask64 |= LIO_CN23XX_INTR_PKT_TIME; 883325618Ssbruno 884325618Ssbruno cn23xx->intr_sum_reg64 = 885325618Ssbruno LIO_CN23XX_SLI_MAC_PF_INT_SUM64(oct->pcie_port, oct->pf_num); 886325618Ssbruno cn23xx->intr_enb_reg64 = 887325618Ssbruno LIO_CN23XX_SLI_MAC_PF_INT_ENB64(oct->pcie_port, oct->pf_num); 888325618Ssbruno} 889325618Ssbruno 890325618Ssbrunostatic int 891325618Ssbrunolio_cn23xx_pf_sriov_config(struct octeon_device *oct) 892325618Ssbruno{ 893325618Ssbruno struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip; 894325618Ssbruno uint32_t num_pf_rings, total_rings, max_rings; 895325618Ssbruno cn23xx->conf = (struct lio_config *)lio_get_config_info(oct, LIO_23XX); 896325618Ssbruno 897325618Ssbruno max_rings = LIO_CN23XX_PF_MAX_RINGS; 898325618Ssbruno 899325618Ssbruno if (oct->sriov_info.num_pf_rings) { 900325618Ssbruno num_pf_rings = oct->sriov_info.num_pf_rings; 901325618Ssbruno if (num_pf_rings > max_rings) { 902325618Ssbruno num_pf_rings = min(mp_ncpus, max_rings); 903325618Ssbruno lio_dev_warn(oct, "num_queues_per_pf requested %u is more than available rings (%u). Reducing to %u\n", 904325618Ssbruno oct->sriov_info.num_pf_rings, 905325618Ssbruno max_rings, num_pf_rings); 906325618Ssbruno } 907325618Ssbruno } else { 908325618Ssbruno#ifdef RSS 909325618Ssbruno num_pf_rings = min(rss_getnumbuckets(), mp_ncpus); 910325618Ssbruno#else 911325618Ssbruno num_pf_rings = min(mp_ncpus, max_rings); 912325618Ssbruno#endif 913325618Ssbruno 914325618Ssbruno } 915325618Ssbruno 916325618Ssbruno total_rings = num_pf_rings; 917325618Ssbruno oct->sriov_info.trs = total_rings; 918325618Ssbruno oct->sriov_info.pf_srn = total_rings - num_pf_rings; 919325618Ssbruno oct->sriov_info.num_pf_rings = num_pf_rings; 920325618Ssbruno 921325618Ssbruno lio_dev_dbg(oct, "trs:%d pf_srn:%d num_pf_rings:%d\n", 922325618Ssbruno oct->sriov_info.trs, oct->sriov_info.pf_srn, 923325618Ssbruno oct->sriov_info.num_pf_rings); 924325618Ssbruno 925325618Ssbruno return (0); 926325618Ssbruno} 927325618Ssbruno 928325618Ssbrunoint 929325618Ssbrunolio_cn23xx_pf_setup_device(struct octeon_device *oct) 930325618Ssbruno{ 931325618Ssbruno uint64_t BAR0, BAR1; 932325618Ssbruno uint32_t data32; 933325618Ssbruno 934325618Ssbruno data32 = lio_read_pci_cfg(oct, 0x10); 935325618Ssbruno BAR0 = (uint64_t)(data32 & ~0xf); 936325618Ssbruno data32 = lio_read_pci_cfg(oct, 0x14); 937325618Ssbruno BAR0 |= ((uint64_t)data32 << 32); 938325618Ssbruno data32 = lio_read_pci_cfg(oct, 0x18); 939325618Ssbruno BAR1 = (uint64_t)(data32 & ~0xf); 940325618Ssbruno data32 = lio_read_pci_cfg(oct, 0x1c); 941325618Ssbruno BAR1 |= ((uint64_t)data32 << 32); 942325618Ssbruno 943325618Ssbruno if (!BAR0 || !BAR1) { 944325618Ssbruno if (!BAR0) 945325618Ssbruno lio_dev_err(oct, "Device BAR0 unassigned\n"); 946325618Ssbruno 947325618Ssbruno if (!BAR1) 948325618Ssbruno lio_dev_err(oct, "Device BAR1 unassigned\n"); 949325618Ssbruno 950325618Ssbruno return (1); 951325618Ssbruno } 952325618Ssbruno 953325618Ssbruno if (lio_map_pci_barx(oct, 0)) 954325618Ssbruno return (1); 955325618Ssbruno 956325618Ssbruno if (lio_map_pci_barx(oct, 1)) { 957325618Ssbruno lio_dev_err(oct, "%s CN23XX BAR1 map failed\n", __func__); 958325618Ssbruno lio_unmap_pci_barx(oct, 0); 959325618Ssbruno return (1); 960325618Ssbruno } 961325618Ssbruno 962325618Ssbruno lio_cn23xx_pf_get_pf_num(oct); 963325618Ssbruno 964325618Ssbruno if (lio_cn23xx_pf_sriov_config(oct)) { 965325618Ssbruno lio_unmap_pci_barx(oct, 0); 966325618Ssbruno lio_unmap_pci_barx(oct, 1); 967325618Ssbruno return (1); 968325618Ssbruno } 969325618Ssbruno lio_write_csr64(oct, LIO_CN23XX_SLI_MAC_CREDIT_CNT, 970325618Ssbruno 0x3F802080802080ULL); 971325618Ssbruno 972325618Ssbruno oct->fn_list.setup_iq_regs = lio_cn23xx_pf_setup_iq_regs; 973325618Ssbruno oct->fn_list.setup_oq_regs = lio_cn23xx_pf_setup_oq_regs; 974325618Ssbruno oct->fn_list.process_interrupt_regs = lio_cn23xx_pf_interrupt_handler; 975325618Ssbruno oct->fn_list.msix_interrupt_handler = 976325618Ssbruno lio_cn23xx_pf_msix_interrupt_handler; 977325618Ssbruno 978325618Ssbruno oct->fn_list.soft_reset = lio_cn23xx_pf_soft_reset; 979325618Ssbruno oct->fn_list.setup_device_regs = lio_cn23xx_pf_setup_device_regs; 980325618Ssbruno oct->fn_list.update_iq_read_idx = lio_cn23xx_pf_update_read_index; 981325618Ssbruno 982325618Ssbruno oct->fn_list.bar1_idx_setup = lio_cn23xx_pf_bar1_idx_setup; 983325618Ssbruno oct->fn_list.bar1_idx_write = lio_cn23xx_pf_bar1_idx_write; 984325618Ssbruno oct->fn_list.bar1_idx_read = lio_cn23xx_pf_bar1_idx_read; 985325618Ssbruno 986325618Ssbruno oct->fn_list.enable_interrupt = lio_cn23xx_pf_enable_interrupt; 987325618Ssbruno oct->fn_list.disable_interrupt = lio_cn23xx_pf_disable_interrupt; 988325618Ssbruno 989325618Ssbruno oct->fn_list.enable_io_queues = lio_cn23xx_pf_enable_io_queues; 990325618Ssbruno oct->fn_list.disable_io_queues = lio_cn23xx_pf_disable_io_queues; 991325618Ssbruno 992325618Ssbruno lio_cn23xx_pf_setup_reg_address(oct); 993325618Ssbruno 994325618Ssbruno oct->coproc_clock_rate = 1000000ULL * 995325618Ssbruno lio_cn23xx_pf_coprocessor_clock(oct); 996325618Ssbruno 997325618Ssbruno return (0); 998325618Ssbruno} 999325618Ssbruno 1000325618Ssbrunoint 1001325618Ssbrunolio_cn23xx_pf_fw_loaded(struct octeon_device *oct) 1002325618Ssbruno{ 1003325618Ssbruno uint64_t val; 1004325618Ssbruno 1005325618Ssbruno val = lio_read_csr64(oct, LIO_CN23XX_SLI_SCRATCH2); 1006325618Ssbruno return ((val >> SCR2_BIT_FW_LOADED) & 1ULL); 1007325618Ssbruno} 1008325618Ssbruno 1009