if_jmereg.h revision 215847
12311Sjkh/*- 22311Sjkh * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 32311Sjkh * All rights reserved. 42311Sjkh * 52311Sjkh * Redistribution and use in source and binary forms, with or without 62311Sjkh * modification, are permitted provided that the following conditions 72311Sjkh * are met: 82311Sjkh * 1. Redistributions of source code must retain the above copyright 92311Sjkh * notice unmodified, this list of conditions, and the following 102311Sjkh * disclaimer. 112311Sjkh * 2. Redistributions in binary form must reproduce the above copyright 122311Sjkh * notice, this list of conditions and the following disclaimer in the 132311Sjkh * documentation and/or other materials provided with the distribution. 142311Sjkh * 152311Sjkh * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 165176Sache * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 172311Sjkh * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 182311Sjkh * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 192311Sjkh * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2029452Scharnier * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2129452Scharnier * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 222311Sjkh * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 232311Sjkh * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 242311Sjkh * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 252311Sjkh * SUCH DAMAGE. 262311Sjkh * 272311Sjkh * $FreeBSD: head/sys/dev/jme/if_jmereg.h 215847 2010-11-26 01:48:29Z yongari $ 282311Sjkh */ 292311Sjkh 302311Sjkh#ifndef _IF_JMEREG_H 312311Sjkh#define _IF_JMEREG_H 322311Sjkh 332311Sjkh/* 342311Sjkh * JMicron Inc. PCI vendor ID 352311Sjkh */ 362311Sjkh#define VENDORID_JMICRON 0x197B 372311Sjkh 382311Sjkh/* 392311Sjkh * JMC250 PCI device ID 402311Sjkh */ 412311Sjkh#define DEVICEID_JMC250 0x0250 422311Sjkh#define DEVICEREVID_JMC250_A0 0x00 432311Sjkh#define DEVICEREVID_JMC250_A2 0x11 442311Sjkh 452311Sjkh/* 462311Sjkh * JMC260 PCI device ID 472311Sjkh */ 482311Sjkh#define DEVICEID_JMC260 0x0260 492311Sjkh#define DEVICEREVID_JMC260_A0 0x00 502311Sjkh 512311Sjkh#define DEVICEID_JMC2XX_MASK 0x0FF0 522311Sjkh 532311Sjkh/* JMC250 PCI configuration register. */ 542311Sjkh#define JME_PCI_BAR0 0x10 /* 16KB memory window. */ 552311Sjkh 562311Sjkh#define JME_PCI_BAR1 0x18 /* 128bytes I/O window. */ 572311Sjkh 582311Sjkh#define JME_PCI_BAR2 0x1C /* 256bytes I/O window. */ 592311Sjkh 602311Sjkh#define JME_PCI_BAR3 0x20 /* 64KB memory window. */ 612311Sjkh 622311Sjkh#define JME_PCI_EROM 0x30 632311Sjkh 642311Sjkh#define JME_PCI_DBG 0x9C 652311Sjkh 662311Sjkh#define JME_PCI_SPI 0xB0 672311Sjkh 682311Sjkh#define SPI_ENB 0x00000010 692311Sjkh#define SPI_SO_STATUS 0x00000008 702311Sjkh#define SPI_SI_CTRL 0x00000004 712311Sjkh#define SPI_SCK_CTRL 0x00000002 722311Sjkh#define SPI_CS_N_CTRL 0x00000001 732311Sjkh 742311Sjkh#define JME_PCI_PHYCFG0 0xC0 752311Sjkh 762311Sjkh#define JME_PCI_PHYCFG1 0xC4 7729452Scharnier 7829452Scharnier#define JME_PCI_PHYCFG2 0xC8 7929452Scharnier 8029452Scharnier#define JME_PCI_PHYCFG3 0xCC 812311Sjkh 822311Sjkh#define JME_PCI_PIPECTL1 0xD0 832311Sjkh 842311Sjkh#define JME_PCI_PIPECTL2 0xD4 852311Sjkh 862311Sjkh/* PCIe link error/status. */ 872311Sjkh#define JME_PCI_LES 0xD8 882311Sjkh 892311Sjkh/* propeietary register 0. */ 902311Sjkh#define JME_PCI_PE0 0xE0 912311Sjkh#define PE0_SPI_EXIST 0x00200000 922311Sjkh#define PE0_PME_D0 0x00100000 932311Sjkh#define PE0_PME_D3H 0x00080000 942311Sjkh#define PE0_PME_SPI_PAD 0x00040000 952311Sjkh#define PE0_MASK_ASPM 0x00020000 962311Sjkh#define PE0_EEPROM_RW_DIS 0x00008000 972311Sjkh#define PE0_PCI_INTA 0x00001000 982311Sjkh#define PE0_PCI_INTB 0x00002000 992311Sjkh#define PE0_PCI_INTC 0x00003000 1002311Sjkh#define PE0_PCI_INTD 0x00004000 1012311Sjkh#define PE0_PCI_SVSSID_WR_ENB 0x00000800 1022311Sjkh#define PE0_MSIX_SIZE_8 0x00000700 1032311Sjkh#define PE0_MSIX_SIZE_7 0x00000600 1042311Sjkh#define PE0_MSIX_SIZE_6 0x00000500 1052311Sjkh#define PE0_MSIX_SIZE_5 0x00000400 10629452Scharnier#define PE0_MSIX_SIZE_4 0x00000300 1072311Sjkh#define PE0_MSIX_SIZE_3 0x00000200 1082311Sjkh#define PE0_MSIX_SIZE_2 0x00000100 1092311Sjkh#define PE0_MSIX_SIZE_1 0x00000000 1102311Sjkh#define PE0_MSIX_SIZE_DEF 0x00000700 1112311Sjkh#define PE0_MSIX_CAP_DIS 0x00000080 1122311Sjkh#define PE0_MSI_PVMC_ENB 0x00000040 1132311Sjkh#define PE0_LCAP_EXIT_LAT_MASK 0x00000038 1142311Sjkh#define PE0_LCAP_EXIT_LAT_DEF 0x00000038 1152311Sjkh#define PE0_PM_AUXC_MASK 0x00000007 1162311Sjkh#define PE0_PM_AUXC_DEF 0x00000007 1172311Sjkh 1182311Sjkh#define JME_PCI_PE1 0xE4 1192311Sjkh 1202311Sjkh#define JME_PCI_PHYTEST 0xF8 12129452Scharnier 12229452Scharnier#define JME_PCI_GPR 0xFC 1232311Sjkh 1242311Sjkh/* 1252311Sjkh * JMC Register Map. 1262311Sjkh * ----------------------------------------------------------------------- 1272311Sjkh * Register Size IO space Memory space 1288857Srgrimes * ----------------------------------------------------------------------- 1292311Sjkh * Tx/Rx MAC registers 128 bytes BAR1 + 0x00 ~ BAR0 + 0x00 ~ 1302311Sjkh * BAR1 + 0x7F BAR0 + 0x7F 1312311Sjkh * ----------------------------------------------------------------------- 1322311Sjkh * PHY registers 128 bytes BAR2 + 0x00 ~ BAR0 + 0x400 ~ 1332311Sjkh * BAR2 + 0x7F BAR0 + 0x47F 1342311Sjkh * ----------------------------------------------------------------------- 1352311Sjkh * Misc registers 128 bytes BAR2 + 0x80 ~ BAR0 + 0x800 ~ 13629452Scharnier * BAR2 + 0x7F BAR0 + 0x87F 13729452Scharnier * ----------------------------------------------------------------------- 13820573Spst * To simplify register access fuctions and to get better performance 13920573Spst * this driver doesn't support IO space access. It could be implemented 1402311Sjkh * as a function which selects appropriate BARs to access requested 1412311Sjkh * register. 1422311Sjkh */ 14324428Simp 1442311Sjkh/* Tx control and status. */ 1452311Sjkh#define JME_TXCSR 0x0000 1462311Sjkh#define TXCSR_QWEIGHT_MASK 0x0F000000 1472311Sjkh#define TXCSR_QWEIGHT_SHIFT 24 1482311Sjkh#define TXCSR_TXQ_SEL_MASK 0x00070000 1492311Sjkh#define TXCSR_TXQ_SEL_SHIFT 16 1502311Sjkh#define TXCSR_TXQ_START 0x00000001 15129452Scharnier#define TXCSR_TXQ_START_SHIFT 8 1522311Sjkh#define TXCSR_FIFO_THRESH_4QW 0x00000000 15329452Scharnier#define TXCSR_FIFO_THRESH_8QW 0x00000040 15420573Spst#define TXCSR_FIFO_THRESH_12QW 0x00000080 15520573Spst#define TXCSR_FIFO_THRESH_16QW 0x000000C0 1562311Sjkh#define TXCSR_DMA_SIZE_64 0x00000000 1572311Sjkh#define TXCSR_DMA_SIZE_128 0x00000010 1582311Sjkh#define TXCSR_DMA_SIZE_256 0x00000020 1592311Sjkh#define TXCSR_DMA_SIZE_512 0x00000030 1602311Sjkh#define TXCSR_DMA_BURST 0x00000004 1612311Sjkh#define TXCSR_TX_SUSPEND 0x00000002 1622311Sjkh#define TXCSR_TX_ENB 0x00000001 1632311Sjkh#define TXCSR_TXQ0 0 1642311Sjkh#define TXCSR_TXQ1 1 1652311Sjkh#define TXCSR_TXQ2 2 1662311Sjkh#define TXCSR_TXQ3 3 1672311Sjkh#define TXCSR_TXQ4 4 1682311Sjkh#define TXCSR_TXQ5 5 1692311Sjkh#define TXCSR_TXQ6 6 1702311Sjkh#define TXCSR_TXQ7 7 1712311Sjkh#define TXCSR_TXQ_WEIGHT(x) \ 1722311Sjkh (((x) << TXCSR_QWEIGHT_SHIFT) & TXCSR_QWEIGHT_MASK) 1732311Sjkh#define TXCSR_TXQ_WEIGHT_MIN 0 1742311Sjkh#define TXCSR_TXQ_WEIGHT_MAX 15 1752311Sjkh#define TXCSR_TXQ_N_SEL(x) \ 1762311Sjkh (((x) << TXCSR_TXQ_SEL_SHIFT) & TXCSR_TXQ_SEL_MASK) 1772311Sjkh#define TXCSR_TXQ_N_START(x) \ 1782311Sjkh (TXCSR_TXQ_START << (TXCSR_TXQ_START_SHIFT + (x))) 1792311Sjkh 1802311Sjkh/* Tx queue descriptor base address. 16bytes alignment required. */ 1812311Sjkh#define JME_TXDBA_LO 0x0004 1822311Sjkh#define JME_TXDBA_HI 0x0008 1832311Sjkh 1842311Sjkh/* Tx queue descriptor count. multiple of 16(max = 1024). */ 1852311Sjkh#define JME_TXQDC 0x000C 18620573Spst#define TXQDC_MASK 0x0000007F0 18720573Spst 18820573Spst/* Tx queue next descriptor address. */ 1892311Sjkh#define JME_TXNDA 0x0010 1902311Sjkh#define TXNDA_ADDR_MASK 0xFFFFFFF0 1912311Sjkh#define TXNDA_DESC_EMPTY 0x00000008 1922311Sjkh#define TXNDA_DESC_VALID 0x00000004 1932311Sjkh#define TXNDA_DESC_WAIT 0x00000002 1942311Sjkh#define TXNDA_DESC_FETCH 0x00000001 1952311Sjkh 1962311Sjkh/* Tx MAC control ans status. */ 1972311Sjkh#define JME_TXMAC 0x0014 1982311Sjkh#define TXMAC_IFG2_MASK 0xC0000000 1992311Sjkh#define TXMAC_IFG2_DEFAULT 0x40000000 2002311Sjkh#define TXMAC_IFG1_MASK 0x30000000 2012311Sjkh#define TXMAC_IFG1_DEFAULT 0x20000000 2022311Sjkh#define TXMAC_PAUSE_CNT_MASK 0x00FF0000 2032311Sjkh#define TXMAC_THRESH_1_PKT 0x00000300 2042311Sjkh#define TXMAC_THRESH_1_2_PKT 0x00000200 2052311Sjkh#define TXMAC_THRESH_1_4_PKT 0x00000100 2062311Sjkh#define TXMAC_THRESH_1_8_PKT 0x00000000 2072311Sjkh#define TXMAC_FRAME_BURST 0x00000080 2082311Sjkh#define TXMAC_CARRIER_EXT 0x00000040 2092311Sjkh#define TXMAC_IFG_ENB 0x00000020 21029452Scharnier#define TXMAC_BACKOFF 0x00000010 21129452Scharnier#define TXMAC_CARRIER_SENSE 0x00000008 21229452Scharnier#define TXMAC_COLL_ENB 0x00000004 21329452Scharnier#define TXMAC_CRC_ENB 0x00000002 21429452Scharnier#define TXMAC_PAD_ENB 0x00000001 21529452Scharnier 2162311Sjkh/* Tx pause frame control. */ 2172311Sjkh#define JME_TXPFC 0x0018 2182311Sjkh#define TXPFC_VLAN_TAG_MASK 0xFFFF0000 2192311Sjkh#define TXPFC_VLAN_TAG_SHIFT 16 2202311Sjkh#define TXPFC_VLAN_ENB 0x00008000 2212311Sjkh#define TXPFC_PAUSE_ENB 0x00000001 2222311Sjkh 2232311Sjkh/* Tx timer/retry at half duplex. */ 2242311Sjkh#define JME_TXTRHD 0x001C 2252311Sjkh#define TXTRHD_RT_PERIOD_ENB 0x80000000 2262311Sjkh#define TXTRHD_RT_PERIOD_MASK 0x7FFFFF00 2272311Sjkh#define TXTRHD_RT_PERIOD_SHIFT 8 2282311Sjkh#define TXTRHD_RT_LIMIT_ENB 0x00000080 2292311Sjkh#define TXTRHD_RT_LIMIT_MASK 0x0000007F 2302311Sjkh#define TXTRHD_RT_LIMIT_SHIFT 0 2312311Sjkh#define TXTRHD_RT_PERIOD_DEFAULT 8192 2322311Sjkh#define TXTRHD_RT_LIMIT_DEFAULT 8 2332311Sjkh 23429452Scharnier/* Rx control & status. */ 2352311Sjkh#define JME_RXCSR 0x0020 23629452Scharnier#define RXCSR_FIFO_FTHRESH_16T 0x00000000 2372311Sjkh#define RXCSR_FIFO_FTHRESH_32T 0x10000000 2382311Sjkh#define RXCSR_FIFO_FTHRESH_64T 0x20000000 2392311Sjkh#define RXCSR_FIFO_FTHRESH_128T 0x30000000 2402311Sjkh#define RXCSR_FIFO_FTHRESH_MASK 0x30000000 2412311Sjkh#define RXCSR_FIFO_THRESH_16QW 0x00000000 2422311Sjkh#define RXCSR_FIFO_THRESH_32QW 0x04000000 2432311Sjkh#define RXCSR_FIFO_THRESH_64QW 0x08000000 /* JMC250/JMC260 REVFM < 2 */ 2442311Sjkh#define RXCSR_FIFO_THRESH_128QW 0x0C000000 /* JMC250/JMC260 REVFM < 2 */ 2452311Sjkh#define RXCSR_FIFO_THRESH_MASK 0x0C000000 2462311Sjkh#define RXCSR_DMA_SIZE_16 0x00000000 2472311Sjkh#define RXCSR_DMA_SIZE_32 0x01000000 2482311Sjkh#define RXCSR_DMA_SIZE_64 0x02000000 2492311Sjkh#define RXCSR_DMA_SIZE_128 0x03000000 2502311Sjkh#define RXCSR_RXQ_SEL_MASK 0x00030000 2512311Sjkh#define RXCSR_RXQ_SEL_SHIFT 16 2522311Sjkh#define RXCSR_DESC_RT_GAP_MASK 0x0000F000 2532311Sjkh#define RXCSR_DESC_RT_GAP_SHIFT 12 2542311Sjkh#define RXCSR_DESC_RT_GAP_256 0x00000000 2552311Sjkh#define RXCSR_DESC_RT_GAP_512 0x00001000 25629452Scharnier#define RXCSR_DESC_RT_GAP_1024 0x00002000 2572311Sjkh#define RXCSR_DESC_RT_GAP_2048 0x00003000 25829452Scharnier#define RXCSR_DESC_RT_GAP_4096 0x00004000 2592311Sjkh#define RXCSR_DESC_RT_GAP_8192 0x00005000 2602311Sjkh#define RXCSR_DESC_RT_GAP_16384 0x00006000 2612311Sjkh#define RXCSR_DESC_RT_GAP_32768 0x00007000 2622311Sjkh#define RXCSR_DESC_RT_CNT_MASK 0x00000F00 2632311Sjkh#define RXCSR_DESC_RT_CNT_SHIFT 8 2642311Sjkh#define RXCSR_PASS_WAKEUP_PKT 0x00000040 2652311Sjkh#define RXCSR_PASS_MAGIC_PKT 0x00000020 2662311Sjkh#define RXCSR_PASS_RUNT_PKT 0x00000010 2672311Sjkh#define RXCSR_PASS_BAD_PKT 0x00000008 2682311Sjkh#define RXCSR_RXQ_START 0x00000004 2692311Sjkh#define RXCSR_RX_SUSPEND 0x00000002 2702311Sjkh#define RXCSR_RX_ENB 0x00000001 2712311Sjkh 2722311Sjkh#define RXCSR_RXQ_N_SEL(x) ((x) << RXCSR_RXQ_SEL_SHIFT) 2732311Sjkh#define RXCSR_RXQ0 0 2742311Sjkh#define RXCSR_RXQ1 1 2752311Sjkh#define RXCSR_RXQ2 2 2762311Sjkh#define RXCSR_RXQ3 3 2772311Sjkh#define RXCSR_DESC_RT_CNT(x) \ 2782311Sjkh (((x) << RXCSR_DESC_RT_CNT_SHIFT) & RXCSR_DESC_RT_CNT_MASK) 2792311Sjkh#define RXCSR_DESC_RT_CNT_DEFAULT 0 2802311Sjkh 2812311Sjkh/* Rx queue descriptor base address. 16bytes alignment needed. */ 28220573Spst#define JME_RXDBA_LO 0x0024 2832311Sjkh#define JME_RXDBA_HI 0x0028 2842311Sjkh 2852311Sjkh/* Rx queue descriptor count. multiple of 16(max = 1024). */ 2862311Sjkh#define JME_RXQDC 0x002C 28729452Scharnier#define RXQDC_MASK 0x0000007F0 28829452Scharnier 28929452Scharnier/* Rx queue next descriptor address. */ 29029452Scharnier#define JME_RXNDA 0x0030 29129452Scharnier#define RXNDA_ADDR_MASK 0xFFFFFFF0 2922311Sjkh#define RXNDA_DESC_EMPTY 0x00000008 2932311Sjkh#define RXNDA_DESC_VALID 0x00000004 29420573Spst#define RXNDA_DESC_WAIT 0x00000002 29520573Spst#define RXNDA_DESC_FETCH 0x00000001 29620573Spst 29729452Scharnier/* Rx MAC control and status. */ 29820573Spst#define JME_RXMAC 0x0034 2992311Sjkh#define RXMAC_RSS_UNICAST 0x00000000 3002311Sjkh#define RXMAC_RSS_UNI_MULTICAST 0x00010000 30120573Spst#define RXMAC_RSS_UNI_MULTI_BROADCAST 0x00020000 3022311Sjkh#define RXMAC_RSS_ALLFRAME 0x00030000 3032311Sjkh#define RXMAC_PROMISC 0x00000800 3042311Sjkh#define RXMAC_BROADCAST 0x00000400 3052311Sjkh#define RXMAC_MULTICAST 0x00000200 3062311Sjkh#define RXMAC_UNICAST 0x00000100 30729452Scharnier#define RXMAC_ALLMULTI 0x00000080 3082311Sjkh#define RXMAC_MULTICAST_FILTER 0x00000040 3092311Sjkh#define RXMAC_COLL_DET_ENB 0x00000020 3105176Sache#define RXMAC_FC_ENB 0x00000008 31129452Scharnier#define RXMAC_VLAN_ENB 0x00000004 3122311Sjkh#define RXMAC_PAD_10BYTES 0x00000002 3132311Sjkh#define RXMAC_CSUM_ENB 0x00000001 3142311Sjkh 3152311Sjkh/* Rx unicast MAC address. */ 3162311Sjkh#define JME_PAR0 0x0038 3172311Sjkh#define JME_PAR1 0x003C 3182311Sjkh 3192311Sjkh/* Rx multicast address hash table. */ 3202311Sjkh#define JME_MAR0 0x0040 3212311Sjkh#define JME_MAR1 0x0044 3222311Sjkh 3232311Sjkh/* Wakeup frame output data port. */ 3242311Sjkh#define JME_WFODP 0x0048 3252311Sjkh 3262311Sjkh/* Wakeup frame output interface. */ 3272311Sjkh#define JME_WFOI 0x004C 3282311Sjkh#define WFOI_MASK_0_31 0x00000000 3292311Sjkh#define WFOI_MASK_31_63 0x00000010 3302311Sjkh#define WFOI_MASK_64_95 0x00000020 3312311Sjkh#define WFOI_MASK_96_127 0x00000030 3322311Sjkh#define WFOI_MASK_SEL 0x00000008 3332311Sjkh#define WFOI_CRC_SEL 0x00000000 3342311Sjkh#define WFOI_WAKEUP_FRAME_MASK 0x00000007 3352311Sjkh#define WFOI_WAKEUP_FRAME_SEL(x) ((x) & WFOI_WAKEUP_FRAME_MASK) 3362311Sjkh 3372311Sjkh/* Station management interface. */ 3382311Sjkh#define JME_SMI 0x0050 3392311Sjkh#define SMI_DATA_MASK 0xFFFF0000 34029452Scharnier#define SMI_DATA_SHIFT 16 34129452Scharnier#define SMI_REG_ADDR_MASK 0x0000F800 3422311Sjkh#define SMI_REG_ADDR_SHIFT 11 3435176Sache#define SMI_PHY_ADDR_MASK 0x000007C0 34429452Scharnier#define SMI_PHY_ADDR_SHIFT 6 3452311Sjkh#define SMI_OP_WRITE 0x00000020 3462311Sjkh#define SMI_OP_READ 0x00000000 3472311Sjkh#define SMI_OP_EXECUTE 0x00000010 3482311Sjkh#define SMI_MDIO 0x00000008 3492311Sjkh#define SMI_MDOE 0x00000004 3502311Sjkh#define SMI_MDC 0x00000002 3512311Sjkh#define SMI_MDEN 0x00000001 3522311Sjkh#define SMI_REG_ADDR(x) \ 3532311Sjkh (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK) 3542311Sjkh#define SMI_PHY_ADDR(x) \ 3552311Sjkh (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK) 3562311Sjkh 3572311Sjkh/* Global host control. */ 3582311Sjkh#define JME_GHC 0x0054 3592311Sjkh#define GHC_LOOPBACK 0x80000000 3602311Sjkh#define GHC_RESET 0x40000000 3612311Sjkh#define GHC_RX_DMA_PWR_DIS 0x04000000 /* JMC250 REVFM >= 2 */ 3622311Sjkh#define GHC_FIFO_RD_PWR_DIS 0x02000000 /* JMC250 REVFM >= 2 */ 3632311Sjkh#define GHC_FIFO_WR_PWR_DIS 0x01000000 /* JMC250 REVFM >= 2 */ 3642311Sjkh#define GHC_TX_OFFLD_CLK_100 0x00800000 /* JMC250/JMC260 REVFM >= 2 */ 3652311Sjkh#define GHC_TX_OFFLD_CLK_1000 0x00400000 /* JMC250/JMC260 REVFM >= 2 */ 36629452Scharnier#define GHC_TX_OFFLD_CLK_DIS 0x00000000 /* JMC250/JMC260 REVFM >= 2 */ 3672311Sjkh#define GHC_TX_MAC_CLK_100 0x00200000 /* JMC250/JMC260 REVFM >= 2 */ 3682311Sjkh#define GHC_TX_MAC_CLK_1000 0x00100000 /* JMC250/JMC260 REVFM >= 2 */ 3692311Sjkh#define GHC_TX_MAC_CLK_DIS 0x00000000 /* JMC250/JMC260 REVFM >= 2 */ 37029452Scharnier#define GHC_AUTO_PHY_STAT_DIS 0x00000080 /* JMC250/JMC260 REVFM >= 2 */ 37129452Scharnier#define GHC_FULL_DUPLEX 0x00000040 37229452Scharnier#define GHC_SPEED_UNKNOWN 0x00000000 37329452Scharnier#define GHC_SPEED_10 0x00000010 37429452Scharnier#define GHC_SPEED_100 0x00000020 37529452Scharnier#define GHC_SPEED_1000 0x00000030 37615161Sscrappy#define GHC_SPEED_MASK 0x00000030 37729452Scharnier#define GHC_LINK_OFF 0x00000004 3782311Sjkh#define GHC_LINK_ON 0x00000002 3792311Sjkh#define GHC_LINK_STAT_POLLING 0x00000001 3802311Sjkh 3812311Sjkh/* Power management control and status. */ 3822311Sjkh#define JME_PMCS 0x0060 3832311Sjkh#define PMCS_WAKEUP_FRAME_7 0x80000000 3842311Sjkh#define PMCS_WAKEUP_FRAME_6 0x40000000 38515161Sscrappy#define PMCS_WAKEUP_FRAME_5 0x20000000 38615161Sscrappy#define PMCS_WAKEUP_FRAME_4 0x10000000 38715161Sscrappy#define PMCS_WAKEUP_FRAME_3 0x08000000 38815161Sscrappy#define PMCS_WAKEUP_FRAME_2 0x04000000 38915161Sscrappy#define PMCS_WAKEUP_FRAME_1 0x02000000 3902311Sjkh#define PMCS_WAKEUP_FRAME_0 0x01000000 39115161Sscrappy#define PMCS_LINK_FAIL 0x00040000 39215161Sscrappy#define PMCS_LINK_RISING 0x00020000 39315161Sscrappy#define PMCS_MAGIC_FRAME 0x00010000 39415161Sscrappy#define PMCS_WAKEUP_FRAME_7_ENB 0x00008000 3952311Sjkh#define PMCS_WAKEUP_FRAME_6_ENB 0x00004000 39629452Scharnier#define PMCS_WAKEUP_FRAME_5_ENB 0x00002000 3972311Sjkh#define PMCS_WAKEUP_FRAME_4_ENB 0x00001000 3982311Sjkh#define PMCS_WAKEUP_FRAME_3_ENB 0x00000800 3992311Sjkh#define PMCS_WAKEUP_FRAME_2_ENB 0x00000400 40029452Scharnier#define PMCS_WAKEUP_FRAME_1_ENB 0x00000200 4012311Sjkh#define PMCS_WAKEUP_FRAME_0_ENB 0x00000100 4022311Sjkh#define PMCS_LINK_FAIL_ENB 0x00000004 4032311Sjkh#define PMCS_LINK_RISING_ENB 0x00000002 40429452Scharnier#define PMCS_MAGIC_FRAME_ENB 0x00000001 40529452Scharnier#define PMCS_WOL_ENB_MASK 0x0000FFFF 4062311Sjkh 4072311Sjkh/* 4085176Sache * Statistic registers control and status. 40929452Scharnier * These statistics registers are valid only for JMC250/JMC260 REVFM >= 2. 4102311Sjkh */ 4112311Sjkh#define JME_STATCSR 0x0064 4122311Sjkh#define STATCSR_RXMPT_DIS 0x00000080 41329452Scharnier#define STATCSR_OFLOW_DIS 0x00000040 4142311Sjkh#define STATCSR_MIIRXER_DIS 0x00000020 4152311Sjkh#define STATCSR_CRCERR_DIS 0x00000010 41629452Scharnier#define STATCSR_RXBAD_DIS 0x00000008 4175176Sache#define STATCSR_RXGOOD_DIS 0x00000004 41829452Scharnier#define STATCSR_TXBAD_DIS 0x00000002 4195176Sache#define STATCSR_TXGOOD_DIS 0x00000001 4205176Sache 4212311Sjkh#define JME_STAT_TXGOOD 0x0068 4222311Sjkh 4232311Sjkh#define JME_STAT_RXGOOD 0x006C 4242311Sjkh 4252311Sjkh#define JME_STAT_CRCMII 0x0070 4262311Sjkh#define STAT_RX_CRC_ERR_MASK 0xFFFF0000 4272311Sjkh#define STAT_RX_MII_ERR_MASK 0x0000FFFF 4282311Sjkh#define STAT_RX_CRC_ERR_SHIFT 16 4292311Sjkh#define STAT_RX_MII_ERR_SHIFT 0 4302311Sjkh 4312311Sjkh#define JME_STAT_RXERR 0x0074 4322311Sjkh#define STAT_RXERR_OFLOW_MASK 0xFFFF0000 4332311Sjkh#define STAT_RXERR_MPTY_MASK 0x0000FFFF 4342311Sjkh#define STAT_RXERR_OFLOW_SHIFT 16 4352311Sjkh#define STAT_RXERR_MPTY_SHIFT 0 4362311Sjkh 4372311Sjkh#define JME_STAT_RESERVED1 0x0078 4382311Sjkh 4392311Sjkh#define JME_STAT_FAIL 0x007C 4402311Sjkh#define STAT_FAIL_RX_MASK 0xFFFF0000 4412311Sjkh#define STAT_FAIL_TX_MASK 0x0000FFFF 44229452Scharnier#define STAT_FAIL_RX_SHIFT 16 4432311Sjkh#define STAT_FAIL_TX_SHIFT 0 4442311Sjkh 44529452Scharnier/* Giga PHY & EEPROM registers. */ 4462311Sjkh#define JME_PHY_EEPROM_BASE_ADDR 0x0400 4472311Sjkh 4482311Sjkh#define JME_GIGAR0LO 0x0400 4492311Sjkh#define JME_GIGAR0HI 0x0404 4502311Sjkh#define JME_GIGARALO 0x0408 4512311Sjkh#define JME_GIGARAHI 0x040C 4522311Sjkh#define JME_GIGARBLO 0x0410 4532311Sjkh#define JME_GIGARBHI 0x0414 4548857Srgrimes#define JME_GIGARCLO 0x0418 4552311Sjkh#define JME_GIGARCHI 0x041C 4562311Sjkh#define JME_GIGARDLO 0x0420 4572311Sjkh#define JME_GIGARDHI 0x0424 4582311Sjkh 4592311Sjkh/* BIST status and control. */ 4602311Sjkh#define JME_GIGACSR 0x0428 4612311Sjkh#define GIGACSR_STATUS 0x40000000 4622311Sjkh#define GIGACSR_CTRL_MASK 0x30000000 4632311Sjkh#define GIGACSR_CTRL_DEFAULT 0x30000000 4642311Sjkh#define GIGACSR_TX_CLK_MASK 0x0F000000 4652311Sjkh#define GIGACSR_RX_CLK_MASK 0x00F00000 4662311Sjkh#define GIGACSR_TX_CLK_INV 0x00080000 4672311Sjkh#define GIGACSR_RX_CLK_INV 0x00040000 46820573Spst#define GIGACSR_PHY_RST 0x00010000 46929452Scharnier#define GIGACSR_IRQ_N_O 0x00001000 47020573Spst#define GIGACSR_BIST_OK 0x00000200 47120573Spst#define GIGACSR_BIST_DONE 0x00000100 47220573Spst#define GIGACSR_BIST_LED_ENB 0x00000010 4732311Sjkh#define GIGACSR_BIST_MASK 0x00000003 4742311Sjkh 4752311Sjkh/* PHY Link Status. */ 47629452Scharnier#define JME_LNKSTS 0x0430 4772311Sjkh#define LINKSTS_SPEED_10 0x00000000 4782311Sjkh#define LINKSTS_SPEED_100 0x00004000 4792311Sjkh#define LINKSTS_SPEED_1000 0x00008000 4802311Sjkh#define LINKSTS_FULL_DUPLEX 0x00002000 4812311Sjkh#define LINKSTS_PAGE_RCVD 0x00001000 4822311Sjkh#define LINKSTS_SPDDPX_RESOLVED 0x00000800 4832311Sjkh#define LINKSTS_UP 0x00000400 4842311Sjkh#define LINKSTS_ANEG_COMP 0x00000200 4852311Sjkh#define LINKSTS_MDI_CROSSOVR 0x00000040 4862311Sjkh#define LINKSTS_LPAR_PAUSE_ASYM 0x00000002 4872311Sjkh#define LINKSTS_LPAR_PAUSE 0x00000001 4882311Sjkh 4892311Sjkh/* SMB control and status. */ 4902311Sjkh#define JME_SMBCSR 0x0440 4912311Sjkh#define SMBCSR_SLAVE_ADDR_MASK 0x7F000000 4922311Sjkh#define SMBCSR_WR_DATA_NACK 0x00040000 4935176Sache#define SMBCSR_CMD_NACK 0x00020000 4942311Sjkh#define SMBCSR_RELOAD 0x00010000 4952311Sjkh#define SMBCSR_CMD_ADDR_MASK 0x0000FF00 4962311Sjkh#define SMBCSR_SCL_STAT 0x00000080 4972311Sjkh#define SMBCSR_SDA_STAT 0x00000040 49829452Scharnier#define SMBCSR_EEPROM_PRESENT 0x00000020 4992311Sjkh#define SMBCSR_INIT_LD_DONE 0x00000010 5002311Sjkh#define SMBCSR_HW_BUSY_MASK 0x0000000F 5012311Sjkh#define SMBCSR_HW_IDLE 0x00000000 5022311Sjkh 5032311Sjkh/* SMB interface. */ 5042311Sjkh#define JME_SMBINTF 0x0444 5052311Sjkh#define SMBINTF_RD_DATA_MASK 0xFF000000 5062311Sjkh#define SMBINTF_RD_DATA_SHIFT 24 5072311Sjkh#define SMBINTF_WR_DATA_MASK 0x00FF0000 5082311Sjkh#define SMBINTF_WR_DATA_SHIFT 16 5092311Sjkh#define SMBINTF_ADDR_MASK 0x0000FF00 5102311Sjkh#define SMBINTF_ADDR_SHIFT 8 5112311Sjkh#define SMBINTF_RD 0x00000020 5122311Sjkh#define SMBINTF_WR 0x00000000 5132311Sjkh#define SMBINTF_CMD_TRIGGER 0x00000010 5142311Sjkh#define SMBINTF_BUSY 0x00000010 5152311Sjkh#define SMBINTF_FAST_MODE 0x00000008 5162311Sjkh#define SMBINTF_GPIO_SCL 0x00000004 5172311Sjkh#define SMBINTF_GPIO_SDA 0x00000002 5182311Sjkh#define SMBINTF_GPIO_ENB 0x00000001 5192311Sjkh 5202311Sjkh#define JME_EEPROM_SIG0 0x55 5212311Sjkh#define JME_EEPROM_SIG1 0xAA 5222311Sjkh#define JME_EEPROM_DESC_BYTES 3 5232311Sjkh#define JME_EEPROM_DESC_END 0x80 5242311Sjkh#define JME_EEPROM_FUNC_MASK 0x70 5252311Sjkh#define JME_EEPROM_FUNC_SHIFT 4 5262311Sjkh#define JME_EEPROM_PAGE_MASK 0x0F 5272311Sjkh#define JME_EEPROM_PAGE_SHIFT 0 52829452Scharnier 5292311Sjkh#define JME_EEPROM_FUNC0 0 5302311Sjkh/* PCI configuration space. */ 5312311Sjkh#define JME_EEPROM_PAGE_BAR0 0 5322311Sjkh/* 128 bytes I/O window. */ 5332311Sjkh#define JME_EEPROM_PAGE_BAR1 1 5342311Sjkh/* 256 bytes I/O window. */ 5352311Sjkh#define JME_EEPROM_PAGE_BAR2 2 5362311Sjkh 5372311Sjkh#define JME_EEPROM_END 0xFF 5382311Sjkh 53929452Scharnier#define JME_EEPROM_MKDESC(f, p) \ 5402311Sjkh ((((f) & JME_EEPROM_FUNC_MASK) << JME_EEPROM_FUNC_SHIFT) | \ 5412311Sjkh (((p) & JME_EEPROM_PAGE_MASK) << JME_EEPROM_PAGE_SHIFT)) 5422311Sjkh 5432311Sjkh/* 3-wire EEPROM interface. Obsolete interface, use SMBCSR. */ 5442311Sjkh#define JME_EEPINTF 0x0448 5452311Sjkh#define EEPINTF_DATA_MASK 0xFFFF0000 5462311Sjkh#define EEPINTF_DATA_SHIFT 16 5472311Sjkh#define EEPINTF_ADDR_MASK 0x0000FC00 5482311Sjkh#define EEPINTF_ADDR_SHIFT 10 5492311Sjkh#define EEPRINTF_OP_MASK 0x00000300 55029452Scharnier#define EEPINTF_OP_EXECUTE 0x00000080 5512311Sjkh#define EEPINTF_DATA_OUT 0x00000008 5522311Sjkh#define EEPINTF_DATA_IN 0x00000004 5532311Sjkh#define EEPINTF_CLK 0x00000002 5542311Sjkh#define EEPINTF_SEL 0x00000001 5552311Sjkh 55629452Scharnier/* 3-wire EEPROM control and status. Obsolete interface, use SMBCSR. */ 5572311Sjkh#define JME_EEPCSR 0x044C 5582311Sjkh#define EEPCSR_EEPROM_RELOAD 0x00000002 5592311Sjkh#define EEPCSR_EEPROM_PRESENT 0x00000001 5602311Sjkh 5612311Sjkh/* Misc registers. */ 5622311Sjkh#define JME_MISC_BASE_ADDR 0x800 56329452Scharnier 5642311Sjkh/* Timer control and status. */ 5652311Sjkh#define JME_TMCSR 0x0800 5662311Sjkh#define TMCSR_SW_INTR 0x80000000 5672311Sjkh#define TMCSR_TIMER_INTR 0x10000000 5682311Sjkh#define TMCSR_TIMER_ENB 0x01000000 5692311Sjkh#define TMCSR_TIMER_COUNT_MASK 0x00FFFFFF 5702311Sjkh 5712311Sjkh/* GPIO control and status. */ 5722311Sjkh#define JME_GPIO 0x0804 5732311Sjkh#define GPIO_4_SPI_IN 0x80000000 5742311Sjkh#define GPIO_3_SPI_IN 0x40000000 5752311Sjkh#define GPIO_4_SPI_OUT 0x20000000 5762311Sjkh#define GPIO_4_SPI_OUT_ENB 0x10000000 5772311Sjkh#define GPIO_3_SPI_OUT 0x08000000 5782311Sjkh#define GPIO_3_SPI_OUT_ENB 0x04000000 5792311Sjkh#define GPIO_3_4_LED 0x00000000 5802311Sjkh#define GPIO_3_4_GPIO 0x02000000 5812311Sjkh#define GPIO_2_CLKREQN_IN 0x00100000 5822311Sjkh#define GPIO_2_CLKREQN_OUT 0x00040000 5832311Sjkh#define GPIO_2_CLKREQN_OUT_ENB 0x00020000 58429452Scharnier#define GPIO_1_LED42_IN 0x00001000 5852311Sjkh#define GPIO_1_LED42_OUT 0x00000400 5862311Sjkh#define GPIO_1_LED42_OUT_ENB 0x00000200 5872311Sjkh#define GPIO_1_LED42_ENB 0x00000100 5882311Sjkh#define GPIO_0_SDA_IN 0x00000010 58929452Scharnier#define GPIO_0_SDA_OUT 0x00000004 5902311Sjkh#define GPIO_0_SDA_OUT_ENB 0x00000002 5912311Sjkh#define GPIO_0_SDA_ENB 0x00000001 5922311Sjkh 5932311Sjkh/* General purpose register 0. */ 594#define JME_GPREG0 0x0808 595#define GPREG0_SH_POST_DW7_DIS 0x80000000 596#define GPREG0_SH_POST_DW6_DIS 0x40000000 597#define GPREG0_SH_POST_DW5_DIS 0x20000000 598#define GPREG0_SH_POST_DW4_DIS 0x10000000 599#define GPREG0_SH_POST_DW3_DIS 0x08000000 600#define GPREG0_SH_POST_DW2_DIS 0x04000000 601#define GPREG0_SH_POST_DW1_DIS 0x02000000 602#define GPREG0_SH_POST_DW0_DIS 0x01000000 603#define GPREG0_DMA_RD_REQ_8 0x00000000 604#define GPREG0_DMA_RD_REQ_6 0x00100000 605#define GPREG0_DMA_RD_REQ_5 0x00200000 606#define GPREG0_DMA_RD_REQ_4 0x00300000 607#define GPREG0_POST_DW0_ENB 0x00040000 608#define GPREG0_PCC_CLR_DIS 0x00020000 609#define GPREG0_FORCE_SCL_OUT 0x00010000 610#define GPREG0_DL_RSTB_DIS 0x00008000 611#define GPREG0_STICKY_RESET 0x00004000 612#define GPREG0_DL_RSTB_CFG_DIS 0x00002000 613#define GPREG0_LINK_CHG_POLL 0x00001000 614#define GPREG0_LINK_CHG_DIRECT 0x00000000 615#define GPREG0_MSI_GEN_SEL 0x00000800 616#define GPREG0_SMB_PAD_PU_DIS 0x00000400 617#define GPREG0_PCC_UNIT_16US 0x00000000 618#define GPREG0_PCC_UNIT_256US 0x00000100 619#define GPREG0_PCC_UNIT_US 0x00000200 620#define GPREG0_PCC_UNIT_MS 0x00000300 621#define GPREG0_PCC_UNIT_MASK 0x00000300 622#define GPREG0_INTR_EVENT_ENB 0x00000080 623#define GPREG0_PME_ENB 0x00000020 624#define GPREG0_PHY_ADDR_MASK 0x0000001F 625#define GPREG0_PHY_ADDR_SHIFT 0 626#define GPREG0_PHY_ADDR 1 627 628/* General purpose register 1. */ 629#define JME_GPREG1 0x080C 630#define GPREG1_RSS_IPV6_10_100 0x00000040 /* JMC250 A2 */ 631#define GPREG1_HDPX_FIX 0x00000020 /* JMC250 A2 */ 632#define GPREG1_INTDLY_UNIT_16US 0x00000018 /* JMC250 A1, A2 */ 633#define GPREG1_INTDLY_UNIT_1US 0x00000010 /* JMC250 A1, A2 */ 634#define GPREG1_INTDLY_UNIT_256NS 0x00000008 /* JMC250 A1, A2 */ 635#define GPREG1_INTDLY_UNIT_16NS 0x00000000 /* JMC250 A1, A2 */ 636#define GPREG1_INTDLY_MASK 0x00000007 637 638/* MSIX entry number of interrupt source. */ 639#define JME_MSINUM_BASE 0x0810 640#define JME_MSINUM_END 0x081F 641#define MSINUM_MASK 0x7FFFFFFF 642#define MSINUM_ENTRY_MASK 7 643#define MSINUM_REG_INDEX(x) ((x) / 8) 644#define MSINUM_INTR_SOURCE(x, y) \ 645 (((x) & MSINUM_ENTRY_MASK) << (((y) & 7) * 4)) 646#define MSINUM_NUM_INTR_SOURCE 32 647 648/* Interrupt event status. */ 649#define JME_INTR_STATUS 0x0820 650#define INTR_SW 0x80000000 651#define INTR_TIMER 0x40000000 652#define INTR_LINKCHG 0x20000000 653#define INTR_PAUSE 0x10000000 654#define INTR_MAGIC_PKT 0x08000000 655#define INTR_WAKEUP_PKT 0x04000000 656#define INTR_RXQ0_COAL_TO 0x02000000 657#define INTR_RXQ1_COAL_TO 0x01000000 658#define INTR_RXQ2_COAL_TO 0x00800000 659#define INTR_RXQ3_COAL_TO 0x00400000 660#define INTR_TXQ_COAL_TO 0x00200000 661#define INTR_RXQ0_COAL 0x00100000 662#define INTR_RXQ1_COAL 0x00080000 663#define INTR_RXQ2_COAL 0x00040000 664#define INTR_RXQ3_COAL 0x00020000 665#define INTR_TXQ_COAL 0x00010000 666#define INTR_RXQ3_DESC_EMPTY 0x00008000 667#define INTR_RXQ2_DESC_EMPTY 0x00004000 668#define INTR_RXQ1_DESC_EMPTY 0x00002000 669#define INTR_RXQ0_DESC_EMPTY 0x00001000 670#define INTR_RXQ3_COMP 0x00000800 671#define INTR_RXQ2_COMP 0x00000400 672#define INTR_RXQ1_COMP 0x00000200 673#define INTR_RXQ0_COMP 0x00000100 674#define INTR_TXQ7_COMP 0x00000080 675#define INTR_TXQ6_COMP 0x00000040 676#define INTR_TXQ5_COMP 0x00000020 677#define INTR_TXQ4_COMP 0x00000010 678#define INTR_TXQ3_COMP 0x00000008 679#define INTR_TXQ2_COMP 0x00000004 680#define INTR_TXQ1_COMP 0x00000002 681#define INTR_TXQ0_COMP 0x00000001 682 683#define INTR_RXQ_COAL_TO \ 684 (INTR_RXQ0_COAL_TO | INTR_RXQ1_COAL_TO | \ 685 INTR_RXQ2_COAL_TO | INTR_RXQ3_COAL_TO) 686 687#define INTR_RXQ_COAL \ 688 (INTR_RXQ0_COAL | INTR_RXQ1_COAL | INTR_RXQ2_COAL | \ 689 INTR_RXQ3_COAL) 690 691#define INTR_RXQ_COMP \ 692 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 693 INTR_RXQ3_COMP) 694 695#define INTR_RXQ_DESC_EMPTY \ 696 (INTR_RXQ0_DESC_EMPTY | INTR_RXQ1_DESC_EMPTY | \ 697 INTR_RXQ2_DESC_EMPTY | INTR_RXQ3_DESC_EMPTY) 698 699#define INTR_RXQ_COMP \ 700 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 701 INTR_RXQ3_COMP) 702 703#define INTR_TXQ_COMP \ 704 (INTR_TXQ0_COMP | INTR_TXQ1_COMP | INTR_TXQ2_COMP | \ 705 INTR_TXQ3_COMP | INTR_TXQ4_COMP | INTR_TXQ5_COMP | \ 706 INTR_TXQ6_COMP | INTR_TXQ7_COMP) 707 708#define JME_INTRS \ 709 (INTR_RXQ_COAL_TO | INTR_TXQ_COAL_TO | INTR_RXQ_COAL | \ 710 INTR_TXQ_COAL | INTR_RXQ_DESC_EMPTY) 711 712#define N_INTR_SW 31 713#define N_INTR_TIMER 30 714#define N_INTR_LINKCHG 29 715#define N_INTR_PAUSE 28 716#define N_INTR_MAGIC_PKT 27 717#define N_INTR_WAKEUP_PKT 26 718#define N_INTR_RXQ0_COAL_TO 25 719#define N_INTR_RXQ1_COAL_TO 24 720#define N_INTR_RXQ2_COAL_TO 23 721#define N_INTR_RXQ3_COAL_TO 22 722#define N_INTR_TXQ_COAL_TO 21 723#define N_INTR_RXQ0_COAL 20 724#define N_INTR_RXQ1_COAL 19 725#define N_INTR_RXQ2_COAL 18 726#define N_INTR_RXQ3_COAL 17 727#define N_INTR_TXQ_COAL 16 728#define N_INTR_RXQ3_DESC_EMPTY 15 729#define N_INTR_RXQ2_DESC_EMPTY 14 730#define N_INTR_RXQ1_DESC_EMPTY 13 731#define N_INTR_RXQ0_DESC_EMPTY 12 732#define N_INTR_RXQ3_COMP 11 733#define N_INTR_RXQ2_COMP 10 734#define N_INTR_RXQ1_COMP 9 735#define N_INTR_RXQ0_COMP 8 736#define N_INTR_TXQ7_COMP 7 737#define N_INTR_TXQ6_COMP 6 738#define N_INTR_TXQ5_COMP 5 739#define N_INTR_TXQ4_COMP 4 740#define N_INTR_TXQ3_COMP 3 741#define N_INTR_TXQ2_COMP 2 742#define N_INTR_TXQ1_COMP 1 743#define N_INTR_TXQ0_COMP 0 744 745/* Interrupt request status. */ 746#define JME_INTR_REQ_STATUS 0x0824 747 748/* Interrupt enable - setting port. */ 749#define JME_INTR_MASK_SET 0x0828 750 751/* Interrupt enable - clearing port. */ 752#define JME_INTR_MASK_CLR 0x082C 753 754/* Packet completion coalescing control of Rx queue 0, 1, 2 and 3. */ 755#define JME_PCCRX0 0x0830 756#define JME_PCCRX1 0x0834 757#define JME_PCCRX2 0x0838 758#define JME_PCCRX3 0x083C 759#define PCCRX_COAL_TO_MASK 0xFFFF0000 760#define PCCRX_COAL_TO_SHIFT 16 761#define PCCRX_COAL_PKT_MASK 0x0000FF00 762#define PCCRX_COAL_PKT_SHIFT 8 763 764#define PCCRX_COAL_TO_MIN 1 765#define PCCRX_COAL_TO_DEFAULT 100 766#define PCCRX_COAL_TO_MAX 65535 767 768#define PCCRX_COAL_PKT_MIN 1 769#define PCCRX_COAL_PKT_DEFAULT 2 770#define PCCRX_COAL_PKT_MAX 255 771 772/* Packet completion coalescing control of Tx queue. */ 773#define JME_PCCTX 0x0840 774#define PCCTX_COAL_TO_MASK 0xFFFF0000 775#define PCCTX_COAL_TO_SHIFT 16 776#define PCCTX_COAL_PKT_MASK 0x0000FF00 777#define PCCTX_COAL_PKT_SHIFT 8 778#define PCCTX_COAL_TXQ7 0x00000080 779#define PCCTX_COAL_TXQ6 0x00000040 780#define PCCTX_COAL_TXQ5 0x00000020 781#define PCCTX_COAL_TXQ4 0x00000010 782#define PCCTX_COAL_TXQ3 0x00000008 783#define PCCTX_COAL_TXQ2 0x00000004 784#define PCCTX_COAL_TXQ1 0x00000002 785#define PCCTX_COAL_TXQ0 0x00000001 786 787#define PCCTX_COAL_TO_MIN 1 788#define PCCTX_COAL_TO_DEFAULT 100 789#define PCCTX_COAL_TO_MAX 65535 790 791#define PCCTX_COAL_PKT_MIN 1 792#define PCCTX_COAL_PKT_DEFAULT 8 793#define PCCTX_COAL_PKT_MAX 255 794 795/* Chip mode and FPGA version. */ 796#define JME_CHIPMODE 0x0844 797#define CHIPMODE_FPGA_REV_MASK 0xFFFF0000 798#define CHIPMODE_FPGA_REV_SHIFT 16 799#define CHIPMODE_NOT_FPGA 0 800#define CHIPMODE_REV_MASK 0x0000FF00 801#define CHIPMODE_REV_SHIFT 8 802#define CHIPMODE_MODE_48P 0x0000000C 803#define CHIPMODE_MODE_64P 0x00000004 804#define CHIPMODE_MODE_128P_MAC 0x00000003 805#define CHIPMODE_MODE_128P_DBG 0x00000002 806#define CHIPMODE_MODE_128P_PHY 0x00000000 807/* Chip full mask revision. */ 808#define CHIPMODE_REVFM(x) ((x) & 0x0F) 809/* Chip ECO revision. */ 810#define CHIPMODE_REVECO(x) (((x) >> 4) & 0x0F) 811 812/* Shadow status base address high/low. */ 813#define JME_SHBASE_ADDR_HI 0x0848 814#define JME_SHBASE_ADDR_LO 0x084C 815#define SHBASE_ADDR_LO_MASK 0xFFFFFFE0 816#define SHBASE_POST_FORCE 0x00000002 817#define SHBASE_POST_ENB 0x00000001 818 819/* Timer 1 and 2. */ 820#define JME_TIMER1 0x0870 821#define JME_TIMER2 0x0874 822#define TIMER_ENB 0x01000000 823#define TIMER_CNT_MASK 0x00FFFFFF 824#define TIMER_CNT_SHIFT 0 825#define TIMER_UNIT 1024 /* 1024us */ 826 827/* Aggresive power mode control. */ 828#define JME_APMC 0x087C 829#define APMC_PCIE_SDOWN_STAT 0x80000000 830#define APMC_PCIE_SDOWN_ENB 0x40000000 831#define APMC_PSEUDO_HOT_PLUG 0x20000000 832#define APMC_EXT_PLUGIN_ENB 0x04000000 833#define APMC_EXT_PLUGIN_CTL_MSK 0x03000000 834#define APMC_DIS_SRAM 0x00000004 835#define APMC_DIS_CLKPM 0x00000002 836#define APMC_DIS_CLKTX 0x00000001 837 838/* Packet completion coalesing status of Rx queue 0, 1, 2 and 3. */ 839#define JME_PCCSRX_BASE 0x0880 840#define JME_PCCSRX_END 0x088F 841#define PCCSRX_REG(x) (JME_PCCSRX_BASE + ((x) * 4)) 842#define PCCSRX_TO_MASK 0xFFFF0000 843#define PCCSRX_TO_SHIFT 16 844#define PCCSRX_PKT_CNT_MASK 0x0000FF00 845#define PCCSRX_PKT_CNT_SHIFT 8 846 847/* Packet completion coalesing status of Tx queue. */ 848#define JME_PCCSTX 0x0890 849#define PCCSTX_TO_MASK 0xFFFF0000 850#define PCCSTX_TO_SHIFT 16 851#define PCCSTX_PKT_CNT_MASK 0x0000FF00 852#define PCCSTX_PKT_CNT_SHIFT 8 853 854/* Tx queues empty indicator. */ 855#define JME_TXQEMPTY 0x0894 856#define TXQEMPTY_TXQ7 0x00000080 857#define TXQEMPTY_TXQ6 0x00000040 858#define TXQEMPTY_TXQ5 0x00000020 859#define TXQEMPTY_TXQ4 0x00000010 860#define TXQEMPTY_TXQ3 0x00000008 861#define TXQEMPTY_TXQ2 0x00000004 862#define TXQEMPTY_TXQ1 0x00000002 863#define TXQEMPTY_TXQ0 0x00000001 864#define TXQEMPTY_N_TXQ(x, y) ((x) & (0x01 << (y))) 865 866/* RSS control registers. */ 867#define JME_RSS_BASE 0x0C00 868 869#define JME_RSSC 0x0C00 870#define RSSC_HASH_LEN_MASK 0x0000E000 871#define RSSC_HASH_64_ENTRY 0x0000A000 872#define RSSC_HASH_128_ENTRY 0x0000E000 873#define RSSC_HASH_NONE 0x00001000 874#define RSSC_HASH_IPV6 0x00000800 875#define RSSC_HASH_IPV4 0x00000400 876#define RSSC_HASH_IPV6_TCP 0x00000200 877#define RSSC_HASH_IPV4_TCP 0x00000100 878#define RSSC_NCPU_MASK 0x000000F8 879#define RSSC_NCPU_SHIFT 3 880#define RSSC_DIS_RSS 0x00000000 881#define RSSC_2RXQ_ENB 0x00000001 882#define RSSS_4RXQ_ENB 0x00000002 883 884/* CPU vector. */ 885#define JME_RSSCPU 0x0C04 886#define RSSCPU_N_SEL(x) ((1 << (x)) 887 888/* RSS Hash value. */ 889#define JME_RSSHASH 0x0C10 890 891#define JME_RSSHASH_STAT 0x0C14 892 893#define JME_RSS_RDATA0 0x0C18 894 895#define JME_RSS_RDATA1 0x0C1C 896 897/* RSS secret key. */ 898#define JME_RSSKEY_BASE 0x0C40 899#define JME_RSSKEY_LAST 0x0C64 900#define JME_RSSKEY_END 0x0C67 901#define HASHKEY_NBYTES 40 902#define RSSKEY_REG(x) (JME_RSSKEY_LAST - (4 * ((x) / 4))) 903#define RSSKEY_VALUE(x, y) ((x) << (24 - 8 * ((y) % 4))) 904 905/* RSS indirection table entries. */ 906#define JME_RSSTBL_BASE 0x0C80 907#define JME_RSSTBL_END 0x0CFF 908#define RSSTBL_NENTRY 128 909#define RSSTBL_REG(x) (JME_RSSTBL_BASE + ((x) / 4)) 910#define RSSTBL_VALUE(x, y) ((x) << (8 * ((y) % 4))) 911 912/* MSI-X table. */ 913#define JME_MSIX_BASE_ADDR 0x2000 914 915#define JME_MSIX_BASE 0x2000 916#define JME_MSIX_END 0x207F 917#define JME_MSIX_NENTRY 8 918#define MSIX_REG(x) (JME_MSIX_BASE + ((x) * 0x10)) 919#define MSIX_ADDR_HI_OFF 0x00 920#define MSIX_ADDR_LO_OFF 0x04 921#define MSIX_ADDR_LO_MASK 0xFFFFFFFC 922#define MSIX_DATA_OFF 0x08 923#define MSIX_VECTOR_OFF 0x0C 924#define MSIX_VECTOR_RSVD 0x80000000 925#define MSIX_VECTOR_DIS 0x00000001 926 927/* MSI-X PBA. */ 928#define JME_MSIX_PBA_BASE_ADDR 0x3000 929 930#define JME_MSIX_PBA 0x3000 931#define MSIX_PBA_RSVD_MASK 0xFFFFFF00 932#define MSIX_PBA_RSVD_SHIFT 8 933#define MSIX_PBA_PEND_MASK 0x000000FF 934#define MSIX_PBA_PEND_SHIFT 0 935#define MSIX_PBA_PEND_ENTRY7 0x00000080 936#define MSIX_PBA_PEND_ENTRY6 0x00000040 937#define MSIX_PBA_PEND_ENTRY5 0x00000020 938#define MSIX_PBA_PEND_ENTRY4 0x00000010 939#define MSIX_PBA_PEND_ENTRY3 0x00000008 940#define MSIX_PBA_PEND_ENTRY2 0x00000004 941#define MSIX_PBA_PEND_ENTRY1 0x00000002 942#define MSIX_PBA_PEND_ENTRY0 0x00000001 943 944#define JME_PHY_OUI 0x001B8C 945#define JME_PHY_MODEL 0x21 946#define JME_PHY_REV 0x01 947#define JME_PHY_ADDR 1 948 949/* JMC250 shadow status block. */ 950struct jme_ssb { 951 uint32_t dw0; 952 uint32_t dw1; 953 uint32_t dw2; 954 uint32_t dw3; 955 uint32_t dw4; 956 uint32_t dw5; 957 uint32_t dw6; 958 uint32_t dw7; 959}; 960 961/* JMC250 descriptor structures. */ 962struct jme_desc { 963 uint32_t flags; 964 uint32_t buflen; 965 uint32_t addr_hi; 966 uint32_t addr_lo; 967}; 968 969#define JME_TD_OWN 0x80000000 970#define JME_TD_INTR 0x40000000 971#define JME_TD_64BIT 0x20000000 972#define JME_TD_TCPCSUM 0x10000000 973#define JME_TD_UDPCSUM 0x08000000 974#define JME_TD_IPCSUM 0x04000000 975#define JME_TD_TSO 0x02000000 976#define JME_TD_VLAN_TAG 0x01000000 977#define JME_TD_VLAN_MASK 0x0000FFFF 978 979#define JME_TD_MSS_MASK 0xFFFC0000 980#define JME_TD_MSS_SHIFT 18 981#define JME_TD_BUF_LEN_MASK 0x0000FFFF 982#define JME_TD_BUF_LEN_SHIFT 0 983 984#define JME_TD_FRAME_LEN_MASK 0x0000FFFF 985#define JME_TD_FRAME_LEN_SHIFT 0 986 987/* 988 * Only the first Tx descriptor of a packet is updated 989 * after packet transmission. 990 */ 991#define JME_TD_TMOUT 0x20000000 992#define JME_TD_RETRY_EXP 0x10000000 993#define JME_TD_COLLISION 0x08000000 994#define JME_TD_UNDERRUN 0x04000000 995#define JME_TD_EHDR_SIZE_MASK 0x000000FF 996#define JME_TD_EHDR_SIZE_SHIFT 0 997 998#define JME_TD_SEG_CNT_MASK 0xFFFF0000 999#define JME_TD_SEG_CNT_SHIFT 16 1000#define JME_TD_RETRY_CNT_MASK 0x0000FFFF 1001#define JME_TD_RETRY_CNT_SHIFT 0 1002 1003#define JME_RD_OWN 0x80000000 1004#define JME_RD_INTR 0x40000000 1005#define JME_RD_64BIT 0x20000000 1006 1007#define JME_RD_BUF_LEN_MASK 0x0000FFFF 1008#define JME_RD_BUF_LEN_SHIFT 0 1009 1010/* 1011 * Only the first Rx descriptor of a packet is updated 1012 * after packet reception. 1013 */ 1014#define JME_RD_MORE_FRAG 0x20000000 1015#define JME_RD_TCP 0x10000000 1016#define JME_RD_UDP 0x08000000 1017#define JME_RD_IPCSUM 0x04000000 1018#define JME_RD_TCPCSUM 0x02000000 1019#define JME_RD_UDPCSUM 0x01000000 1020#define JME_RD_VLAN_TAG 0x00800000 1021#define JME_RD_IPV4 0x00400000 1022#define JME_RD_IPV6 0x00200000 1023#define JME_RD_PAUSE 0x00100000 1024#define JME_RD_MAGIC 0x00080000 1025#define JME_RD_WAKEUP 0x00040000 1026#define JME_RD_BCAST 0x00030000 1027#define JME_RD_MCAST 0x00020000 1028#define JME_RD_UCAST 0x00010000 1029#define JME_RD_VLAN_MASK 0x0000FFFF 1030#define JME_RD_VLAN_SHIFT 0 1031 1032#define JME_RD_VALID 0x80000000 1033#define JME_RD_CNT_MASK 0x7F000000 1034#define JME_RD_CNT_SHIFT 24 1035#define JME_RD_GIANT 0x00800000 1036#define JME_RD_GMII_ERR 0x00400000 1037#define JME_RD_NBL_RCVD 0x00200000 1038#define JME_RD_COLL 0x00100000 1039#define JME_RD_ABORT 0x00080000 1040#define JME_RD_RUNT 0x00040000 1041#define JME_RD_FIFO_OVRN 0x00020000 1042#define JME_RD_CRC_ERR 0x00010000 1043#define JME_RD_FRAME_LEN_MASK 0x0000FFFF 1044 1045#define JME_RX_ERR_STAT \ 1046 (JME_RD_GIANT | JME_RD_GMII_ERR | JME_RD_NBL_RCVD | \ 1047 JME_RD_COLL | JME_RD_ABORT | JME_RD_RUNT | \ 1048 JME_RD_FIFO_OVRN | JME_RD_CRC_ERR) 1049 1050#define JME_RD_ERR_MASK 0x00FF0000 1051#define JME_RD_ERR_SHIFT 16 1052#define JME_RX_ERR(x) (((x) & JME_RD_ERR_MASK) >> JME_RD_ERR_SHIFT) 1053#define JME_RX_ERR_BITS "\20" \ 1054 "\1CRCERR\2FIFOOVRN\3RUNT\4ABORT" \ 1055 "\5COLL\6NBLRCVD\7GMIIERR\10" 1056 1057#define JME_RX_NSEGS(x) (((x) & JME_RD_CNT_MASK) >> JME_RD_CNT_SHIFT) 1058#define JME_RX_BYTES(x) ((x) & JME_RD_FRAME_LEN_MASK) 1059#define JME_RX_PAD_BYTES 10 1060 1061#define JME_RD_RSS_HASH_VALUE 0xFFFFFFFF 1062 1063#define JME_RD_RSS_HASH_MASK 0x00003F00 1064#define JME_RD_RSS_HASH_SHIFT 8 1065#define JME_RD_RSS_HASH_NONE 0x00000000 1066#define JME_RD_RSS_HASH_IPV4 0x00000100 1067#define JME_RD_RSS_HASH_IPV4TCP 0x00000200 1068#define JME_RD_RSS_HASH_IPV6 0x00000400 1069#define JME_RD_RSS_HASH_IPV6TCP 0x00001000 1070#define JME_RD_HASH_FN_NONE 0x00000000 1071#define JME_RD_HASH_FN_TOEPLITZ 0x00000001 1072 1073#endif 1074