if_jmereg.h revision 185597
1179337Syongari/*- 2179337Syongari * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3179337Syongari * All rights reserved. 4179337Syongari * 5179337Syongari * Redistribution and use in source and binary forms, with or without 6179337Syongari * modification, are permitted provided that the following conditions 7179337Syongari * are met: 8179337Syongari * 1. Redistributions of source code must retain the above copyright 9179337Syongari * notice unmodified, this list of conditions, and the following 10179337Syongari * disclaimer. 11179337Syongari * 2. Redistributions in binary form must reproduce the above copyright 12179337Syongari * notice, this list of conditions and the following disclaimer in the 13179337Syongari * documentation and/or other materials provided with the distribution. 14179337Syongari * 15179337Syongari * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16179337Syongari * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17179337Syongari * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18179337Syongari * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19179337Syongari * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20179337Syongari * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21179337Syongari * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22179337Syongari * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23179337Syongari * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24179337Syongari * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25179337Syongari * SUCH DAMAGE. 26179337Syongari * 27179337Syongari * $FreeBSD: head/sys/dev/jme/if_jmereg.h 185597 2008-12-04 02:16:53Z yongari $ 28179337Syongari */ 29179337Syongari 30179337Syongari#ifndef _IF_JMEREG_H 31179337Syongari#define _IF_JMEREG_H 32179337Syongari 33179337Syongari/* 34179337Syongari * JMicron Inc. PCI vendor ID 35179337Syongari */ 36179337Syongari#define VENDORID_JMICRON 0x197B 37179337Syongari 38179337Syongari/* 39179337Syongari * JMC250 PCI device ID 40179337Syongari */ 41179337Syongari#define DEVICEID_JMC250 0x0250 42182888Syongari#define DEVICEREVID_JMC250_A0 0x00 43182888Syongari#define DEVICEREVID_JMC250_A2 0x11 44179337Syongari 45179337Syongari/* 46179337Syongari * JMC260 PCI device ID 47179337Syongari */ 48179337Syongari#define DEVICEID_JMC260 0x0260 49182888Syongari#define DEVICEREVID_JMC260_A0 0x00 50179337Syongari 51183814Syongari#define DEVICEID_JMC2XX_MASK 0x0FF0 52183814Syongari 53179337Syongari/* JMC250 PCI configuration register. */ 54179337Syongari#define JME_PCI_BAR0 0x10 /* 16KB memory window. */ 55179337Syongari 56179337Syongari#define JME_PCI_BAR1 0x18 /* 128bytes I/O window. */ 57179337Syongari 58179337Syongari#define JME_PCI_BAR2 0x1C /* 256bytes I/O window. */ 59179337Syongari 60179337Syongari#define JME_PCI_BAR3 0x20 /* 64KB memory window. */ 61179337Syongari 62179337Syongari#define JME_PCI_EROM 0x30 63179337Syongari 64179337Syongari#define JME_PCI_DBG 0x9C 65179337Syongari 66179337Syongari#define JME_PCI_SPI 0xB0 67179337Syongari 68179337Syongari#define SPI_ENB 0x00000010 69179337Syongari#define SPI_SO_STATUS 0x00000008 70179337Syongari#define SPI_SI_CTRL 0x00000004 71179337Syongari#define SPI_SCK_CTRL 0x00000002 72179337Syongari#define SPI_CS_N_CTRL 0x00000001 73179337Syongari 74179337Syongari#define JME_PCI_PHYCFG0 0xC0 75179337Syongari 76179337Syongari#define JME_PCI_PHYCFG1 0xC4 77179337Syongari 78179337Syongari#define JME_PCI_PHYCFG2 0xC8 79179337Syongari 80179337Syongari#define JME_PCI_PHYCFG3 0xCC 81179337Syongari 82179337Syongari#define JME_PCI_PIPECTL1 0xD0 83179337Syongari 84179337Syongari#define JME_PCI_PIPECTL2 0xD4 85179337Syongari 86179337Syongari/* PCIe link error/status. */ 87179337Syongari#define JME_PCI_LES 0xD8 88179337Syongari 89179337Syongari/* propeietary register 0. */ 90179337Syongari#define JME_PCI_PE0 0xE0 91179337Syongari#define PE0_SPI_EXIST 0x00200000 92179337Syongari#define PE0_PME_D0 0x00100000 93179337Syongari#define PE0_PME_D3H 0x00080000 94179337Syongari#define PE0_PME_SPI_PAD 0x00040000 95179337Syongari#define PE0_MASK_ASPM 0x00020000 96179337Syongari#define PE0_EEPROM_RW_DIS 0x00008000 97179337Syongari#define PE0_PCI_INTA 0x00001000 98179337Syongari#define PE0_PCI_INTB 0x00002000 99179337Syongari#define PE0_PCI_INTC 0x00003000 100179337Syongari#define PE0_PCI_INTD 0x00004000 101179337Syongari#define PE0_PCI_SVSSID_WR_ENB 0x00000800 102179337Syongari#define PE0_MSIX_SIZE_8 0x00000700 103179337Syongari#define PE0_MSIX_SIZE_7 0x00000600 104179337Syongari#define PE0_MSIX_SIZE_6 0x00000500 105179337Syongari#define PE0_MSIX_SIZE_5 0x00000400 106179337Syongari#define PE0_MSIX_SIZE_4 0x00000300 107179337Syongari#define PE0_MSIX_SIZE_3 0x00000200 108179337Syongari#define PE0_MSIX_SIZE_2 0x00000100 109179337Syongari#define PE0_MSIX_SIZE_1 0x00000000 110179337Syongari#define PE0_MSIX_SIZE_DEF 0x00000700 111179337Syongari#define PE0_MSIX_CAP_DIS 0x00000080 112179337Syongari#define PE0_MSI_PVMC_ENB 0x00000040 113179337Syongari#define PE0_LCAP_EXIT_LAT_MASK 0x00000038 114179337Syongari#define PE0_LCAP_EXIT_LAT_DEF 0x00000038 115179337Syongari#define PE0_PM_AUXC_MASK 0x00000007 116179337Syongari#define PE0_PM_AUXC_DEF 0x00000007 117179337Syongari 118179337Syongari#define JME_PCI_PE1 0xE4 119179337Syongari 120179337Syongari#define JME_PCI_PHYTEST 0xF8 121179337Syongari 122179337Syongari#define JME_PCI_GPR 0xFC 123179337Syongari 124179337Syongari/* 125179337Syongari * JMC Register Map. 126179337Syongari * ----------------------------------------------------------------------- 127179337Syongari * Register Size IO space Memory space 128179337Syongari * ----------------------------------------------------------------------- 129179337Syongari * Tx/Rx MAC registers 128 bytes BAR1 + 0x00 ~ BAR0 + 0x00 ~ 130179337Syongari * BAR1 + 0x7F BAR0 + 0x7F 131179337Syongari * ----------------------------------------------------------------------- 132179337Syongari * PHY registers 128 bytes BAR2 + 0x00 ~ BAR0 + 0x400 ~ 133179337Syongari * BAR2 + 0x7F BAR0 + 0x47F 134179337Syongari * ----------------------------------------------------------------------- 135179337Syongari * Misc registers 128 bytes BAR2 + 0x80 ~ BAR0 + 0x800 ~ 136179337Syongari * BAR2 + 0x7F BAR0 + 0x87F 137179337Syongari * ----------------------------------------------------------------------- 138179337Syongari * To simplify register access fuctions and to get better performance 139179337Syongari * this driver doesn't support IO space access. It could be implemented 140179337Syongari * as a function which selects appropriate BARs to access requested 141179337Syongari * register. 142179337Syongari */ 143179337Syongari 144179337Syongari/* Tx control and status. */ 145179337Syongari#define JME_TXCSR 0x0000 146179337Syongari#define TXCSR_QWEIGHT_MASK 0x0F000000 147179337Syongari#define TXCSR_QWEIGHT_SHIFT 24 148179337Syongari#define TXCSR_TXQ_SEL_MASK 0x00070000 149179337Syongari#define TXCSR_TXQ_SEL_SHIFT 16 150179337Syongari#define TXCSR_TXQ_START 0x00000001 151179337Syongari#define TXCSR_TXQ_START_SHIFT 8 152179337Syongari#define TXCSR_FIFO_THRESH_4QW 0x00000000 153179337Syongari#define TXCSR_FIFO_THRESH_8QW 0x00000040 154179337Syongari#define TXCSR_FIFO_THRESH_12QW 0x00000080 155179337Syongari#define TXCSR_FIFO_THRESH_16QW 0x000000C0 156179337Syongari#define TXCSR_DMA_SIZE_64 0x00000000 157179337Syongari#define TXCSR_DMA_SIZE_128 0x00000010 158179337Syongari#define TXCSR_DMA_SIZE_256 0x00000020 159179337Syongari#define TXCSR_DMA_SIZE_512 0x00000030 160179337Syongari#define TXCSR_DMA_BURST 0x00000004 161179337Syongari#define TXCSR_TX_SUSPEND 0x00000002 162179337Syongari#define TXCSR_TX_ENB 0x00000001 163179337Syongari#define TXCSR_TXQ0 0 164179337Syongari#define TXCSR_TXQ1 1 165179337Syongari#define TXCSR_TXQ2 2 166179337Syongari#define TXCSR_TXQ3 3 167179337Syongari#define TXCSR_TXQ4 4 168179337Syongari#define TXCSR_TXQ5 5 169179337Syongari#define TXCSR_TXQ6 6 170179337Syongari#define TXCSR_TXQ7 7 171179337Syongari#define TXCSR_TXQ_WEIGHT(x) \ 172179337Syongari (((x) << TXCSR_QWEIGHT_SHIFT) & TXCSR_QWEIGHT_MASK) 173179337Syongari#define TXCSR_TXQ_WEIGHT_MIN 0 174179337Syongari#define TXCSR_TXQ_WEIGHT_MAX 15 175179337Syongari#define TXCSR_TXQ_N_SEL(x) \ 176179337Syongari (((x) << TXCSR_TXQ_SEL_SHIFT) & TXCSR_TXQ_SEL_MASK) 177179337Syongari#define TXCSR_TXQ_N_START(x) \ 178179337Syongari (TXCSR_TXQ_START << (TXCSR_TXQ_START_SHIFT + (x))) 179179337Syongari 180179337Syongari/* Tx queue descriptor base address. 16bytes alignment required. */ 181179337Syongari#define JME_TXDBA_LO 0x0004 182179337Syongari#define JME_TXDBA_HI 0x0008 183179337Syongari 184179337Syongari/* Tx queue descriptor count. multiple of 16(max = 1024). */ 185179337Syongari#define JME_TXQDC 0x000C 186179337Syongari#define TXQDC_MASK 0x0000007F0 187179337Syongari 188179337Syongari/* Tx queue next descriptor address. */ 189179337Syongari#define JME_TXNDA 0x0010 190179337Syongari#define TXNDA_ADDR_MASK 0xFFFFFFF0 191179337Syongari#define TXNDA_DESC_EMPTY 0x00000008 192179337Syongari#define TXNDA_DESC_VALID 0x00000004 193179337Syongari#define TXNDA_DESC_WAIT 0x00000002 194179337Syongari#define TXNDA_DESC_FETCH 0x00000001 195179337Syongari 196179337Syongari/* Tx MAC control ans status. */ 197179337Syongari#define JME_TXMAC 0x0014 198179337Syongari#define TXMAC_IFG2_MASK 0xC0000000 199179337Syongari#define TXMAC_IFG2_DEFAULT 0x40000000 200179337Syongari#define TXMAC_IFG1_MASK 0x30000000 201179337Syongari#define TXMAC_IFG1_DEFAULT 0x20000000 202185597Syongari#define TXMAC_PAUSE_CNT_MASK 0x00FF0000 203179337Syongari#define TXMAC_THRESH_1_PKT 0x00000300 204179337Syongari#define TXMAC_THRESH_1_2_PKT 0x00000200 205179337Syongari#define TXMAC_THRESH_1_4_PKT 0x00000100 206179337Syongari#define TXMAC_THRESH_1_8_PKT 0x00000000 207179337Syongari#define TXMAC_FRAME_BURST 0x00000080 208179337Syongari#define TXMAC_CARRIER_EXT 0x00000040 209179337Syongari#define TXMAC_IFG_ENB 0x00000020 210179337Syongari#define TXMAC_BACKOFF 0x00000010 211179337Syongari#define TXMAC_CARRIER_SENSE 0x00000008 212179337Syongari#define TXMAC_COLL_ENB 0x00000004 213179337Syongari#define TXMAC_CRC_ENB 0x00000002 214179337Syongari#define TXMAC_PAD_ENB 0x00000001 215179337Syongari 216179337Syongari/* Tx pause frame control. */ 217179337Syongari#define JME_TXPFC 0x0018 218179337Syongari#define TXPFC_VLAN_TAG_MASK 0xFFFF0000 219179337Syongari#define TXPFC_VLAN_TAG_SHIFT 16 220179337Syongari#define TXPFC_VLAN_ENB 0x00008000 221179337Syongari#define TXPFC_PAUSE_ENB 0x00000001 222179337Syongari 223179337Syongari/* Tx timer/retry at half duplex. */ 224179337Syongari#define JME_TXTRHD 0x001C 225179337Syongari#define TXTRHD_RT_PERIOD_ENB 0x80000000 226179337Syongari#define TXTRHD_RT_PERIOD_MASK 0x7FFFFF00 227179337Syongari#define TXTRHD_RT_PERIOD_SHIFT 8 228179337Syongari#define TXTRHD_RT_LIMIT_ENB 0x00000080 229179337Syongari#define TXTRHD_RT_LIMIT_MASK 0x0000007F 230179337Syongari#define TXTRHD_RT_LIMIT_SHIFT 0 231179337Syongari#define TXTRHD_RT_PERIOD_DEFAULT 8192 232179337Syongari#define TXTRHD_RT_LIMIT_DEFAULT 8 233179337Syongari 234179337Syongari/* Rx control & status. */ 235179337Syongari#define JME_RXCSR 0x0020 236179337Syongari#define RXCSR_FIFO_FTHRESH_16T 0x00000000 237179337Syongari#define RXCSR_FIFO_FTHRESH_32T 0x10000000 238179337Syongari#define RXCSR_FIFO_FTHRESH_64T 0x20000000 239179337Syongari#define RXCSR_FIFO_FTHRESH_128T 0x30000000 240179337Syongari#define RXCSR_FIFO_FTHRESH_MASK 0x30000000 241179337Syongari#define RXCSR_FIFO_THRESH_16QW 0x00000000 242179337Syongari#define RXCSR_FIFO_THRESH_32QW 0x04000000 243185596Syongari#define RXCSR_FIFO_THRESH_64QW 0x08000000 /* JMC250/JMC260 REVFM < 2 */ 244185596Syongari#define RXCSR_FIFO_THRESH_128QW 0x0C000000 /* JMC250/JMC260 REVFM < 2 */ 245179337Syongari#define RXCSR_FIFO_THRESH_MASK 0x0C000000 246179337Syongari#define RXCSR_DMA_SIZE_16 0x00000000 247179337Syongari#define RXCSR_DMA_SIZE_32 0x01000000 248179337Syongari#define RXCSR_DMA_SIZE_64 0x02000000 249179337Syongari#define RXCSR_DMA_SIZE_128 0x03000000 250179337Syongari#define RXCSR_RXQ_SEL_MASK 0x00030000 251179337Syongari#define RXCSR_RXQ_SEL_SHIFT 16 252179337Syongari#define RXCSR_DESC_RT_GAP_MASK 0x0000F000 253179337Syongari#define RXCSR_DESC_RT_GAP_SHIFT 12 254179337Syongari#define RXCSR_DESC_RT_GAP_256 0x00000000 255179337Syongari#define RXCSR_DESC_RT_GAP_512 0x00001000 256179337Syongari#define RXCSR_DESC_RT_GAP_1024 0x00002000 257179337Syongari#define RXCSR_DESC_RT_GAP_2048 0x00003000 258179337Syongari#define RXCSR_DESC_RT_GAP_4096 0x00004000 259179337Syongari#define RXCSR_DESC_RT_GAP_8192 0x00005000 260179337Syongari#define RXCSR_DESC_RT_GAP_16384 0x00006000 261179337Syongari#define RXCSR_DESC_RT_GAP_32768 0x00007000 262179337Syongari#define RXCSR_DESC_RT_CNT_MASK 0x00000F00 263179337Syongari#define RXCSR_DESC_RT_CNT_SHIFT 8 264179337Syongari#define RXCSR_PASS_WAKEUP_PKT 0x00000040 265179337Syongari#define RXCSR_PASS_MAGIC_PKT 0x00000020 266179337Syongari#define RXCSR_PASS_RUNT_PKT 0x00000010 267179337Syongari#define RXCSR_PASS_BAD_PKT 0x00000008 268179337Syongari#define RXCSR_RXQ_START 0x00000004 269179337Syongari#define RXCSR_RX_SUSPEND 0x00000002 270179337Syongari#define RXCSR_RX_ENB 0x00000001 271179337Syongari 272179337Syongari#define RXCSR_RXQ_N_SEL(x) ((x) << RXCSR_RXQ_SEL_SHIFT) 273179337Syongari#define RXCSR_RXQ0 0 274179337Syongari#define RXCSR_RXQ1 1 275179337Syongari#define RXCSR_RXQ2 2 276179337Syongari#define RXCSR_RXQ3 3 277179337Syongari#define RXCSR_DESC_RT_CNT(x) \ 278179337Syongari ((((x) / 4) << RXCSR_DESC_RT_CNT_SHIFT) & RXCSR_DESC_RT_CNT_MASK) 279179337Syongari#define RXCSR_DESC_RT_CNT_DEFAULT 32 280179337Syongari 281179337Syongari/* Rx queue descriptor base address. 16bytes alignment needed. */ 282179337Syongari#define JME_RXDBA_LO 0x0024 283179337Syongari#define JME_RXDBA_HI 0x0028 284179337Syongari 285179337Syongari/* Rx queue descriptor count. multiple of 16(max = 1024). */ 286179337Syongari#define JME_RXQDC 0x002C 287179337Syongari#define RXQDC_MASK 0x0000007F0 288179337Syongari 289179337Syongari/* Rx queue next descriptor address. */ 290179337Syongari#define JME_RXNDA 0x0030 291179337Syongari#define RXNDA_ADDR_MASK 0xFFFFFFF0 292179337Syongari#define RXNDA_DESC_EMPTY 0x00000008 293179337Syongari#define RXNDA_DESC_VALID 0x00000004 294179337Syongari#define RXNDA_DESC_WAIT 0x00000002 295179337Syongari#define RXNDA_DESC_FETCH 0x00000001 296179337Syongari 297179337Syongari/* Rx MAC control and status. */ 298179337Syongari#define JME_RXMAC 0x0034 299179337Syongari#define RXMAC_RSS_UNICAST 0x00000000 300179337Syongari#define RXMAC_RSS_UNI_MULTICAST 0x00010000 301179337Syongari#define RXMAC_RSS_UNI_MULTI_BROADCAST 0x00020000 302179337Syongari#define RXMAC_RSS_ALLFRAME 0x00030000 303179337Syongari#define RXMAC_PROMISC 0x00000800 304179337Syongari#define RXMAC_BROADCAST 0x00000400 305179337Syongari#define RXMAC_MULTICAST 0x00000200 306179337Syongari#define RXMAC_UNICAST 0x00000100 307179337Syongari#define RXMAC_ALLMULTI 0x00000080 308179337Syongari#define RXMAC_MULTICAST_FILTER 0x00000040 309179337Syongari#define RXMAC_COLL_DET_ENB 0x00000020 310179337Syongari#define RXMAC_FC_ENB 0x00000008 311179337Syongari#define RXMAC_VLAN_ENB 0x00000004 312179337Syongari#define RXMAC_PAD_10BYTES 0x00000002 313179337Syongari#define RXMAC_CSUM_ENB 0x00000001 314179337Syongari 315179337Syongari/* Rx unicast MAC address. */ 316179337Syongari#define JME_PAR0 0x0038 317179337Syongari#define JME_PAR1 0x003C 318179337Syongari 319179337Syongari/* Rx multicast address hash table. */ 320179337Syongari#define JME_MAR0 0x0040 321179337Syongari#define JME_MAR1 0x0044 322179337Syongari 323179337Syongari/* Wakeup frame output data port. */ 324179337Syongari#define JME_WFODP 0x0048 325179337Syongari 326179337Syongari/* Wakeup frame output interface. */ 327179337Syongari#define JME_WFOI 0x004C 328179337Syongari#define WFOI_MASK_0_31 0x00000000 329179337Syongari#define WFOI_MASK_31_63 0x00000010 330179337Syongari#define WFOI_MASK_64_95 0x00000020 331179337Syongari#define WFOI_MASK_96_127 0x00000030 332179337Syongari#define WFOI_MASK_SEL 0x00000008 333179337Syongari#define WFOI_CRC_SEL 0x00000000 334179337Syongari#define WFOI_WAKEUP_FRAME_MASK 0x00000007 335179337Syongari#define WFOI_WAKEUP_FRAME_SEL(x) ((x) & WFOI_WAKEUP_FRAME_MASK) 336179337Syongari 337179337Syongari/* Station management interface. */ 338179337Syongari#define JME_SMI 0x0050 339179337Syongari#define SMI_DATA_MASK 0xFFFF0000 340179337Syongari#define SMI_DATA_SHIFT 16 341179337Syongari#define SMI_REG_ADDR_MASK 0x0000F800 342179337Syongari#define SMI_REG_ADDR_SHIFT 11 343179337Syongari#define SMI_PHY_ADDR_MASK 0x000007C0 344179337Syongari#define SMI_PHY_ADDR_SHIFT 6 345179337Syongari#define SMI_OP_WRITE 0x00000020 346179337Syongari#define SMI_OP_READ 0x00000000 347179337Syongari#define SMI_OP_EXECUTE 0x00000010 348179337Syongari#define SMI_MDIO 0x00000008 349179337Syongari#define SMI_MDOE 0x00000004 350179337Syongari#define SMI_MDC 0x00000002 351179337Syongari#define SMI_MDEN 0x00000001 352179337Syongari#define SMI_REG_ADDR(x) \ 353179337Syongari (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK) 354179337Syongari#define SMI_PHY_ADDR(x) \ 355179337Syongari (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK) 356179337Syongari 357179337Syongari/* Global host control. */ 358179337Syongari#define JME_GHC 0x0054 359179337Syongari#define GHC_LOOPBACK 0x80000000 360179337Syongari#define GHC_RESET 0x40000000 361185596Syongari#define GHC_RX_DMA_PWR_DIS 0x04000000 /* JMC250 REVFM >= 2 */ 362185596Syongari#define GHC_FIFO_RD_PWR_DIS 0x02000000 /* JMC250 REVFM >= 2 */ 363185596Syongari#define GHC_FIFO_WR_PWR_DIS 0x01000000 /* JMC250 REVFM >= 2 */ 364185596Syongari#define GHC_TX_OFFLD_CLK_100 0x00800000 /* JMC250/JMC260 REVFM >= 2 */ 365185596Syongari#define GHC_TX_OFFLD_CLK_1000 0x00400000 /* JMC250/JMC260 REVFM >= 2 */ 366185596Syongari#define GHC_TX_OFFLD_CLK_DIS 0x00000000 /* JMC250/JMC260 REVFM >= 2 */ 367185596Syongari#define GHC_TX_MAC_CLK_100 0x00200000 /* JMC250/JMC260 REVFM >= 2 */ 368185596Syongari#define GHC_TX_MAC_CLK_1000 0x00100000 /* JMC250/JMC260 REVFM >= 2 */ 369185596Syongari#define GHC_TX_MAC_CLK_DIS 0x00000000 /* JMC250/JMC260 REVFM >= 2 */ 370185596Syongari#define GHC_AUTO_PHY_STAT_DIS 0x00000080 /* JMC250/JMC260 REVFM >= 2 */ 371179337Syongari#define GHC_FULL_DUPLEX 0x00000040 372179337Syongari#define GHC_SPEED_UNKNOWN 0x00000000 373179337Syongari#define GHC_SPEED_10 0x00000010 374179337Syongari#define GHC_SPEED_100 0x00000020 375179337Syongari#define GHC_SPEED_1000 0x00000030 376179337Syongari#define GHC_SPEED_MASK 0x00000030 377179337Syongari#define GHC_LINK_OFF 0x00000004 378179337Syongari#define GHC_LINK_ON 0x00000002 379179337Syongari#define GHC_LINK_STAT_POLLING 0x00000001 380179337Syongari 381179337Syongari/* Power management control and status. */ 382179337Syongari#define JME_PMCS 0x0060 383179337Syongari#define PMCS_WAKEUP_FRAME_7 0x80000000 384179337Syongari#define PMCS_WAKEUP_FRAME_6 0x40000000 385179337Syongari#define PMCS_WAKEUP_FRAME_5 0x20000000 386179337Syongari#define PMCS_WAKEUP_FRAME_4 0x10000000 387179337Syongari#define PMCS_WAKEUP_FRAME_3 0x08000000 388179337Syongari#define PMCS_WAKEUP_FRAME_2 0x04000000 389179337Syongari#define PMCS_WAKEUP_FRAME_1 0x02000000 390179337Syongari#define PMCS_WAKEUP_FRAME_0 0x01000000 391179337Syongari#define PMCS_LINK_FAIL 0x00040000 392179337Syongari#define PMCS_LINK_RISING 0x00020000 393179337Syongari#define PMCS_MAGIC_FRAME 0x00010000 394179337Syongari#define PMCS_WAKEUP_FRAME_7_ENB 0x00008000 395179337Syongari#define PMCS_WAKEUP_FRAME_6_ENB 0x00004000 396179337Syongari#define PMCS_WAKEUP_FRAME_5_ENB 0x00002000 397179337Syongari#define PMCS_WAKEUP_FRAME_4_ENB 0x00001000 398179337Syongari#define PMCS_WAKEUP_FRAME_3_ENB 0x00000800 399179337Syongari#define PMCS_WAKEUP_FRAME_2_ENB 0x00000400 400179337Syongari#define PMCS_WAKEUP_FRAME_1_ENB 0x00000200 401179337Syongari#define PMCS_WAKEUP_FRAME_0_ENB 0x00000100 402179337Syongari#define PMCS_LINK_FAIL_ENB 0x00000004 403179337Syongari#define PMCS_LINK_RISING_ENB 0x00000002 404179337Syongari#define PMCS_MAGIC_FRAME_ENB 0x00000001 405179337Syongari#define PMCS_WOL_ENB_MASK 0x0000FFFF 406179337Syongari 407185597Syongari/* 408185597Syongari * Statistic registers control and status. 409185597Syongari * These statistics registers are valid only for JMC250/JMC260 REVFM >= 2. 410185597Syongari */ 411185597Syongari#define JME_STATCSR 0x0064 412185597Syongari#define STATCSR_RXMPT_DIS 0x00000080 413185597Syongari#define STATCSR_OFLOW_DIS 0x00000040 414185597Syongari#define STATCSR_MIIRXER_DIS 0x00000020 415185597Syongari#define STATCSR_CRCERR_DIS 0x00000010 416185597Syongari#define STATCSR_RXBAD_DIS 0x00000008 417185597Syongari#define STATCSR_RXGOOD_DIS 0x00000004 418185597Syongari#define STATCSR_TXBAD_DIS 0x00000002 419185597Syongari#define STATCSR_TXGOOD_DIS 0x00000001 420185597Syongari 421185597Syongari#define JME_STAT_TXGOOD 0x0068 422185597Syongari 423185597Syongari#define JME_STAT_RXGOOD 0x006C 424185597Syongari 425185597Syongari#define JME_STAT_CRCMII 0x0070 426185597Syongari#define STAT_RX_CRC_ERR_MASK 0xFFFF0000 427185597Syongari#define STAT_RX_MII_ERR_MASK 0x0000FFFF 428185597Syongari#define STAT_RX_CRC_ERR_SHIFT 16 429185597Syongari#define STAT_RX_MII_ERR_SHIFT 0 430185597Syongari 431185597Syongari#define JME_STAT_RXERR 0x0074 432185597Syongari#define STAT_RXERR_OFLOW_MASK 0xFFFF0000 433185597Syongari#define STAT_RXERR_MPTY_MASK 0x0000FFFF 434185597Syongari#define STAT_RXERR_OFLOW_SHIFT 16 435185597Syongari#define STAT_RXERR_MPTY_SHIFT 0 436185597Syongari 437185597Syongari#define JME_STAT_RESERVED1 0x0078 438185597Syongari 439185597Syongari#define JME_STAT_FAIL 0x007C 440185597Syongari#define STAT_FAIL_RX_MASK 0xFFFF0000 441185597Syongari#define STAT_FAIL_TX_MASK 0x0000FFFF 442185597Syongari#define STAT_FAIL_RX_SHIFT 16 443185597Syongari#define STAT_FAIL_TX_SHIFT 0 444185597Syongari 445179337Syongari/* Giga PHY & EEPROM registers. */ 446179337Syongari#define JME_PHY_EEPROM_BASE_ADDR 0x0400 447179337Syongari 448179337Syongari#define JME_GIGAR0LO 0x0400 449179337Syongari#define JME_GIGAR0HI 0x0404 450179337Syongari#define JME_GIGARALO 0x0408 451179337Syongari#define JME_GIGARAHI 0x040C 452179337Syongari#define JME_GIGARBLO 0x0410 453179337Syongari#define JME_GIGARBHI 0x0414 454179337Syongari#define JME_GIGARCLO 0x0418 455179337Syongari#define JME_GIGARCHI 0x041C 456179337Syongari#define JME_GIGARDLO 0x0420 457179337Syongari#define JME_GIGARDHI 0x0424 458179337Syongari 459179337Syongari/* BIST status and control. */ 460179337Syongari#define JME_GIGACSR 0x0428 461179337Syongari#define GIGACSR_STATUS 0x40000000 462179337Syongari#define GIGACSR_CTRL_MASK 0x30000000 463179337Syongari#define GIGACSR_CTRL_DEFAULT 0x30000000 464179337Syongari#define GIGACSR_TX_CLK_MASK 0x0F000000 465179337Syongari#define GIGACSR_RX_CLK_MASK 0x00F00000 466179337Syongari#define GIGACSR_TX_CLK_INV 0x00080000 467179337Syongari#define GIGACSR_RX_CLK_INV 0x00040000 468179337Syongari#define GIGACSR_PHY_RST 0x00010000 469179337Syongari#define GIGACSR_IRQ_N_O 0x00001000 470179337Syongari#define GIGACSR_BIST_OK 0x00000200 471179337Syongari#define GIGACSR_BIST_DONE 0x00000100 472179337Syongari#define GIGACSR_BIST_LED_ENB 0x00000010 473179337Syongari#define GIGACSR_BIST_MASK 0x00000003 474179337Syongari 475179337Syongari/* PHY Link Status. */ 476179337Syongari#define JME_LNKSTS 0x0430 477179337Syongari#define LINKSTS_SPEED_10 0x00000000 478179337Syongari#define LINKSTS_SPEED_100 0x00004000 479179337Syongari#define LINKSTS_SPEED_1000 0x00008000 480179337Syongari#define LINKSTS_FULL_DUPLEX 0x00002000 481179337Syongari#define LINKSTS_PAGE_RCVD 0x00001000 482179337Syongari#define LINKSTS_SPDDPX_RESOLVED 0x00000800 483179337Syongari#define LINKSTS_UP 0x00000400 484179337Syongari#define LINKSTS_ANEG_COMP 0x00000200 485179337Syongari#define LINKSTS_MDI_CROSSOVR 0x00000040 486179337Syongari#define LINKSTS_LPAR_PAUSE_ASYM 0x00000002 487179337Syongari#define LINKSTS_LPAR_PAUSE 0x00000001 488179337Syongari 489179337Syongari/* SMB control and status. */ 490179337Syongari#define JME_SMBCSR 0x0440 491179337Syongari#define SMBCSR_SLAVE_ADDR_MASK 0x7F000000 492179337Syongari#define SMBCSR_WR_DATA_NACK 0x00040000 493179337Syongari#define SMBCSR_CMD_NACK 0x00020000 494179337Syongari#define SMBCSR_RELOAD 0x00010000 495179337Syongari#define SMBCSR_CMD_ADDR_MASK 0x0000FF00 496179337Syongari#define SMBCSR_SCL_STAT 0x00000080 497179337Syongari#define SMBCSR_SDA_STAT 0x00000040 498179337Syongari#define SMBCSR_EEPROM_PRESENT 0x00000020 499179337Syongari#define SMBCSR_INIT_LD_DONE 0x00000010 500179337Syongari#define SMBCSR_HW_BUSY_MASK 0x0000000F 501179337Syongari#define SMBCSR_HW_IDLE 0x00000000 502179337Syongari 503179337Syongari/* SMB interface. */ 504179337Syongari#define JME_SMBINTF 0x0444 505179337Syongari#define SMBINTF_RD_DATA_MASK 0xFF000000 506179337Syongari#define SMBINTF_RD_DATA_SHIFT 24 507179337Syongari#define SMBINTF_WR_DATA_MASK 0x00FF0000 508179337Syongari#define SMBINTF_WR_DATA_SHIFT 16 509179337Syongari#define SMBINTF_ADDR_MASK 0x0000FF00 510179337Syongari#define SMBINTF_ADDR_SHIFT 8 511179337Syongari#define SMBINTF_RD 0x00000020 512179337Syongari#define SMBINTF_WR 0x00000000 513179337Syongari#define SMBINTF_CMD_TRIGGER 0x00000010 514179337Syongari#define SMBINTF_BUSY 0x00000010 515179337Syongari#define SMBINTF_FAST_MODE 0x00000008 516179337Syongari#define SMBINTF_GPIO_SCL 0x00000004 517179337Syongari#define SMBINTF_GPIO_SDA 0x00000002 518179337Syongari#define SMBINTF_GPIO_ENB 0x00000001 519179337Syongari 520179337Syongari#define JME_EEPROM_SIG0 0x55 521179337Syongari#define JME_EEPROM_SIG1 0xAA 522179337Syongari#define JME_EEPROM_DESC_BYTES 3 523179337Syongari#define JME_EEPROM_DESC_END 0x80 524179337Syongari#define JME_EEPROM_FUNC_MASK 0x70 525179337Syongari#define JME_EEPROM_FUNC_SHIFT 4 526179337Syongari#define JME_EEPROM_PAGE_MASK 0x0F 527179337Syongari#define JME_EEPROM_PAGE_SHIFT 0 528179337Syongari 529179337Syongari#define JME_EEPROM_FUNC0 0 530179337Syongari/* PCI configuration space. */ 531179337Syongari#define JME_EEPROM_PAGE_BAR0 0 532179337Syongari/* 128 bytes I/O window. */ 533179337Syongari#define JME_EEPROM_PAGE_BAR1 1 534179337Syongari/* 256 bytes I/O window. */ 535179337Syongari#define JME_EEPROM_PAGE_BAR2 2 536179337Syongari 537179337Syongari#define JME_EEPROM_END 0xFF 538179337Syongari 539179337Syongari#define JME_EEPROM_MKDESC(f, p) \ 540179337Syongari ((((f) & JME_EEPROM_FUNC_MASK) << JME_EEPROM_FUNC_SHIFT) | \ 541179337Syongari (((p) & JME_EEPROM_PAGE_MASK) << JME_EEPROM_PAGE_SHIFT)) 542179337Syongari 543179337Syongari/* 3-wire EEPROM interface. Obsolete interface, use SMBCSR. */ 544179337Syongari#define JME_EEPINTF 0x0448 545179337Syongari#define EEPINTF_DATA_MASK 0xFFFF0000 546179337Syongari#define EEPINTF_DATA_SHIFT 16 547179337Syongari#define EEPINTF_ADDR_MASK 0x0000FC00 548179337Syongari#define EEPINTF_ADDR_SHIFT 10 549179337Syongari#define EEPRINTF_OP_MASK 0x00000300 550179337Syongari#define EEPINTF_OP_EXECUTE 0x00000080 551179337Syongari#define EEPINTF_DATA_OUT 0x00000008 552179337Syongari#define EEPINTF_DATA_IN 0x00000004 553179337Syongari#define EEPINTF_CLK 0x00000002 554179337Syongari#define EEPINTF_SEL 0x00000001 555179337Syongari 556179337Syongari/* 3-wire EEPROM control and status. Obsolete interface, use SMBCSR. */ 557179337Syongari#define JME_EEPCSR 0x044C 558179337Syongari#define EEPCSR_EEPROM_RELOAD 0x00000002 559179337Syongari#define EEPCSR_EEPROM_PRESENT 0x00000001 560179337Syongari 561179337Syongari/* Misc registers. */ 562179337Syongari#define JME_MISC_BASE_ADDR 0x800 563179337Syongari 564179337Syongari/* Timer control and status. */ 565179337Syongari#define JME_TMCSR 0x0800 566179337Syongari#define TMCSR_SW_INTR 0x80000000 567179337Syongari#define TMCSR_TIMER_INTR 0x10000000 568179337Syongari#define TMCSR_TIMER_ENB 0x01000000 569179337Syongari#define TMCSR_TIMER_COUNT_MASK 0x00FFFFFF 570179337Syongari 571179337Syongari/* GPIO control and status. */ 572179337Syongari#define JME_GPIO 0x0804 573179337Syongari#define GPIO_4_SPI_IN 0x80000000 574179337Syongari#define GPIO_3_SPI_IN 0x40000000 575179337Syongari#define GPIO_4_SPI_OUT 0x20000000 576179337Syongari#define GPIO_4_SPI_OUT_ENB 0x10000000 577179337Syongari#define GPIO_3_SPI_OUT 0x08000000 578179337Syongari#define GPIO_3_SPI_OUT_ENB 0x04000000 579179337Syongari#define GPIO_3_4_LED 0x00000000 580179337Syongari#define GPIO_3_4_GPIO 0x02000000 581179337Syongari#define GPIO_2_CLKREQN_IN 0x00100000 582179337Syongari#define GPIO_2_CLKREQN_OUT 0x00040000 583179337Syongari#define GPIO_2_CLKREQN_OUT_ENB 0x00020000 584179337Syongari#define GPIO_1_LED42_IN 0x00001000 585179337Syongari#define GPIO_1_LED42_OUT 0x00000400 586179337Syongari#define GPIO_1_LED42_OUT_ENB 0x00000200 587179337Syongari#define GPIO_1_LED42_ENB 0x00000100 588179337Syongari#define GPIO_0_SDA_IN 0x00000010 589179337Syongari#define GPIO_0_SDA_OUT 0x00000004 590179337Syongari#define GPIO_0_SDA_OUT_ENB 0x00000002 591179337Syongari#define GPIO_0_SDA_ENB 0x00000001 592179337Syongari 593179337Syongari/* General purpose register 0. */ 594179337Syongari#define JME_GPREG0 0x0808 595179337Syongari#define GPREG0_SH_POST_DW7_DIS 0x80000000 596179337Syongari#define GPREG0_SH_POST_DW6_DIS 0x40000000 597179337Syongari#define GPREG0_SH_POST_DW5_DIS 0x20000000 598179337Syongari#define GPREG0_SH_POST_DW4_DIS 0x10000000 599179337Syongari#define GPREG0_SH_POST_DW3_DIS 0x08000000 600179337Syongari#define GPREG0_SH_POST_DW2_DIS 0x04000000 601179337Syongari#define GPREG0_SH_POST_DW1_DIS 0x02000000 602179337Syongari#define GPREG0_SH_POST_DW0_DIS 0x01000000 603179337Syongari#define GPREG0_DMA_RD_REQ_8 0x00000000 604179337Syongari#define GPREG0_DMA_RD_REQ_6 0x00100000 605179337Syongari#define GPREG0_DMA_RD_REQ_5 0x00200000 606179337Syongari#define GPREG0_DMA_RD_REQ_4 0x00300000 607179337Syongari#define GPREG0_POST_DW0_ENB 0x00040000 608179337Syongari#define GPREG0_PCC_CLR_DIS 0x00020000 609179337Syongari#define GPREG0_FORCE_SCL_OUT 0x00010000 610179337Syongari#define GPREG0_DL_RSTB_DIS 0x00008000 611179337Syongari#define GPREG0_STICKY_RESET 0x00004000 612179337Syongari#define GPREG0_DL_RSTB_CFG_DIS 0x00002000 613179337Syongari#define GPREG0_LINK_CHG_POLL 0x00001000 614179337Syongari#define GPREG0_LINK_CHG_DIRECT 0x00000000 615179337Syongari#define GPREG0_MSI_GEN_SEL 0x00000800 616179337Syongari#define GPREG0_SMB_PAD_PU_DIS 0x00000400 617179337Syongari#define GPREG0_PCC_UNIT_16US 0x00000000 618179337Syongari#define GPREG0_PCC_UNIT_256US 0x00000100 619179337Syongari#define GPREG0_PCC_UNIT_US 0x00000200 620179337Syongari#define GPREG0_PCC_UNIT_MS 0x00000300 621179337Syongari#define GPREG0_PCC_UNIT_MASK 0x00000300 622179337Syongari#define GPREG0_INTR_EVENT_ENB 0x00000080 623179337Syongari#define GPREG0_PME_ENB 0x00000020 624179337Syongari#define GPREG0_PHY_ADDR_MASK 0x0000001F 625179337Syongari#define GPREG0_PHY_ADDR_SHIFT 0 626179337Syongari#define GPREG0_PHY_ADDR 1 627179337Syongari 628183264Syongari/* General purpose register 1. */ 629179337Syongari#define JME_GPREG1 0x080C 630183264Syongari#define GPREG1_RSS_IPV6_10_100 0x00000040 /* JMC250 A2 */ 631183264Syongari#define GPREG1_HDPX_FIX 0x00000020 /* JMC250 A2 */ 632183264Syongari#define GPREG1_INTDLY_UNIT_16US 0x00000018 /* JMC250 A1, A2 */ 633183264Syongari#define GPREG1_INTDLY_UNIT_1US 0x00000010 /* JMC250 A1, A2 */ 634183264Syongari#define GPREG1_INTDLY_UNIT_256NS 0x00000008 /* JMC250 A1, A2 */ 635183264Syongari#define GPREG1_INTDLY_UNIT_16NS 0x00000000 /* JMC250 A1, A2 */ 636183264Syongari#define GPREG1_INTDLY_MASK 0x00000007 637179337Syongari 638179337Syongari/* MSIX entry number of interrupt source. */ 639179337Syongari#define JME_MSINUM_BASE 0x0810 640179337Syongari#define JME_MSINUM_END 0x081F 641179337Syongari#define MSINUM_MASK 0x7FFFFFFF 642179337Syongari#define MSINUM_ENTRY_MASK 7 643179337Syongari#define MSINUM_REG_INDEX(x) ((x) / 8) 644179337Syongari#define MSINUM_INTR_SOURCE(x, y) \ 645179337Syongari (((x) & MSINUM_ENTRY_MASK) << (((y) & 7) * 4)) 646179337Syongari#define MSINUM_NUM_INTR_SOURCE 32 647179337Syongari 648179337Syongari/* Interrupt event status. */ 649179337Syongari#define JME_INTR_STATUS 0x0820 650179337Syongari#define INTR_SW 0x80000000 651179337Syongari#define INTR_TIMER 0x40000000 652179337Syongari#define INTR_LINKCHG 0x20000000 653179337Syongari#define INTR_PAUSE 0x10000000 654179337Syongari#define INTR_MAGIC_PKT 0x08000000 655179337Syongari#define INTR_WAKEUP_PKT 0x04000000 656179337Syongari#define INTR_RXQ0_COAL_TO 0x02000000 657179337Syongari#define INTR_RXQ1_COAL_TO 0x01000000 658179337Syongari#define INTR_RXQ2_COAL_TO 0x00800000 659179337Syongari#define INTR_RXQ3_COAL_TO 0x00400000 660179337Syongari#define INTR_TXQ_COAL_TO 0x00200000 661179337Syongari#define INTR_RXQ0_COAL 0x00100000 662179337Syongari#define INTR_RXQ1_COAL 0x00080000 663179337Syongari#define INTR_RXQ2_COAL 0x00040000 664179337Syongari#define INTR_RXQ3_COAL 0x00020000 665179337Syongari#define INTR_TXQ_COAL 0x00010000 666179337Syongari#define INTR_RXQ3_DESC_EMPTY 0x00008000 667179337Syongari#define INTR_RXQ2_DESC_EMPTY 0x00004000 668179337Syongari#define INTR_RXQ1_DESC_EMPTY 0x00002000 669179337Syongari#define INTR_RXQ0_DESC_EMPTY 0x00001000 670179337Syongari#define INTR_RXQ3_COMP 0x00000800 671179337Syongari#define INTR_RXQ2_COMP 0x00000400 672179337Syongari#define INTR_RXQ1_COMP 0x00000200 673179337Syongari#define INTR_RXQ0_COMP 0x00000100 674179337Syongari#define INTR_TXQ7_COMP 0x00000080 675179337Syongari#define INTR_TXQ6_COMP 0x00000040 676179337Syongari#define INTR_TXQ5_COMP 0x00000020 677179337Syongari#define INTR_TXQ4_COMP 0x00000010 678179337Syongari#define INTR_TXQ3_COMP 0x00000008 679179337Syongari#define INTR_TXQ2_COMP 0x00000004 680179337Syongari#define INTR_TXQ1_COMP 0x00000002 681179337Syongari#define INTR_TXQ0_COMP 0x00000001 682179337Syongari 683179337Syongari#define INTR_RXQ_COAL_TO \ 684179337Syongari (INTR_RXQ0_COAL_TO | INTR_RXQ1_COAL_TO | \ 685179337Syongari INTR_RXQ2_COAL_TO | INTR_RXQ3_COAL_TO) 686179337Syongari 687179337Syongari#define INTR_RXQ_COAL \ 688179337Syongari (INTR_RXQ0_COAL | INTR_RXQ1_COAL | INTR_RXQ2_COAL | \ 689179337Syongari INTR_RXQ3_COAL) 690179337Syongari 691179337Syongari#define INTR_RXQ_COMP \ 692179337Syongari (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 693179337Syongari INTR_RXQ3_COMP) 694179337Syongari 695179337Syongari#define INTR_RXQ_DESC_EMPTY \ 696179337Syongari (INTR_RXQ0_DESC_EMPTY | INTR_RXQ1_DESC_EMPTY | \ 697179337Syongari INTR_RXQ2_DESC_EMPTY | INTR_RXQ3_DESC_EMPTY) 698179337Syongari 699179337Syongari#define INTR_RXQ_COMP \ 700179337Syongari (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 701179337Syongari INTR_RXQ3_COMP) 702179337Syongari 703179337Syongari#define INTR_TXQ_COMP \ 704179337Syongari (INTR_TXQ0_COMP | INTR_TXQ1_COMP | INTR_TXQ2_COMP | \ 705179337Syongari INTR_TXQ3_COMP | INTR_TXQ4_COMP | INTR_TXQ5_COMP | \ 706179337Syongari INTR_TXQ6_COMP | INTR_TXQ7_COMP) 707179337Syongari 708179337Syongari#define JME_INTRS \ 709179337Syongari (INTR_RXQ_COAL_TO | INTR_TXQ_COAL_TO | INTR_RXQ_COAL | \ 710179337Syongari INTR_TXQ_COAL | INTR_RXQ_DESC_EMPTY) 711179337Syongari 712179337Syongari#define N_INTR_SW 31 713179337Syongari#define N_INTR_TIMER 30 714179337Syongari#define N_INTR_LINKCHG 29 715179337Syongari#define N_INTR_PAUSE 28 716179337Syongari#define N_INTR_MAGIC_PKT 27 717179337Syongari#define N_INTR_WAKEUP_PKT 26 718179337Syongari#define N_INTR_RXQ0_COAL_TO 25 719179337Syongari#define N_INTR_RXQ1_COAL_TO 24 720179337Syongari#define N_INTR_RXQ2_COAL_TO 23 721179337Syongari#define N_INTR_RXQ3_COAL_TO 22 722179337Syongari#define N_INTR_TXQ_COAL_TO 21 723179337Syongari#define N_INTR_RXQ0_COAL 20 724179337Syongari#define N_INTR_RXQ1_COAL 19 725179337Syongari#define N_INTR_RXQ2_COAL 18 726179337Syongari#define N_INTR_RXQ3_COAL 17 727179337Syongari#define N_INTR_TXQ_COAL 16 728179337Syongari#define N_INTR_RXQ3_DESC_EMPTY 15 729179337Syongari#define N_INTR_RXQ2_DESC_EMPTY 14 730179337Syongari#define N_INTR_RXQ1_DESC_EMPTY 13 731179337Syongari#define N_INTR_RXQ0_DESC_EMPTY 12 732179337Syongari#define N_INTR_RXQ3_COMP 11 733179337Syongari#define N_INTR_RXQ2_COMP 10 734179337Syongari#define N_INTR_RXQ1_COMP 9 735179337Syongari#define N_INTR_RXQ0_COMP 8 736179337Syongari#define N_INTR_TXQ7_COMP 7 737179337Syongari#define N_INTR_TXQ6_COMP 6 738179337Syongari#define N_INTR_TXQ5_COMP 5 739179337Syongari#define N_INTR_TXQ4_COMP 4 740179337Syongari#define N_INTR_TXQ3_COMP 3 741179337Syongari#define N_INTR_TXQ2_COMP 2 742179337Syongari#define N_INTR_TXQ1_COMP 1 743179337Syongari#define N_INTR_TXQ0_COMP 0 744179337Syongari 745179337Syongari/* Interrupt request status. */ 746179337Syongari#define JME_INTR_REQ_STATUS 0x0824 747179337Syongari 748179337Syongari/* Interrupt enable - setting port. */ 749179337Syongari#define JME_INTR_MASK_SET 0x0828 750179337Syongari 751179337Syongari/* Interrupt enable - clearing port. */ 752179337Syongari#define JME_INTR_MASK_CLR 0x082C 753179337Syongari 754179337Syongari/* Packet completion coalescing control of Rx queue 0, 1, 2 and 3. */ 755179337Syongari#define JME_PCCRX0 0x0830 756179337Syongari#define JME_PCCRX1 0x0834 757179337Syongari#define JME_PCCRX2 0x0838 758179337Syongari#define JME_PCCRX3 0x083C 759179337Syongari#define PCCRX_COAL_TO_MASK 0xFFFF0000 760179337Syongari#define PCCRX_COAL_TO_SHIFT 16 761179337Syongari#define PCCRX_COAL_PKT_MASK 0x0000FF00 762179337Syongari#define PCCRX_COAL_PKT_SHIFT 8 763179337Syongari 764179337Syongari#define PCCRX_COAL_TO_MIN 1 765179337Syongari#define PCCRX_COAL_TO_DEFAULT 100 766179337Syongari#define PCCRX_COAL_TO_MAX 65535 767179337Syongari 768179337Syongari#define PCCRX_COAL_PKT_MIN 1 769179337Syongari#define PCCRX_COAL_PKT_DEFAULT 2 770179337Syongari#define PCCRX_COAL_PKT_MAX 255 771179337Syongari 772179337Syongari/* Packet completion coalescing control of Tx queue. */ 773179337Syongari#define JME_PCCTX 0x0840 774179337Syongari#define PCCTX_COAL_TO_MASK 0xFFFF0000 775179337Syongari#define PCCTX_COAL_TO_SHIFT 16 776179337Syongari#define PCCTX_COAL_PKT_MASK 0x0000FF00 777179337Syongari#define PCCTX_COAL_PKT_SHIFT 8 778179337Syongari#define PCCTX_COAL_TXQ7 0x00000080 779179337Syongari#define PCCTX_COAL_TXQ6 0x00000040 780179337Syongari#define PCCTX_COAL_TXQ5 0x00000020 781179337Syongari#define PCCTX_COAL_TXQ4 0x00000010 782179337Syongari#define PCCTX_COAL_TXQ3 0x00000008 783179337Syongari#define PCCTX_COAL_TXQ2 0x00000004 784179337Syongari#define PCCTX_COAL_TXQ1 0x00000002 785179337Syongari#define PCCTX_COAL_TXQ0 0x00000001 786179337Syongari 787179337Syongari#define PCCTX_COAL_TO_MIN 1 788179337Syongari#define PCCTX_COAL_TO_DEFAULT 100 789179337Syongari#define PCCTX_COAL_TO_MAX 65535 790179337Syongari 791179337Syongari#define PCCTX_COAL_PKT_MIN 1 792179337Syongari#define PCCTX_COAL_PKT_DEFAULT 8 793179337Syongari#define PCCTX_COAL_PKT_MAX 255 794179337Syongari 795179337Syongari/* Chip mode and FPGA version. */ 796179337Syongari#define JME_CHIPMODE 0x0844 797179337Syongari#define CHIPMODE_FPGA_REV_MASK 0xFFFF0000 798179337Syongari#define CHIPMODE_FPGA_REV_SHIFT 16 799179337Syongari#define CHIPMODE_NOT_FPGA 0 800179337Syongari#define CHIPMODE_REV_MASK 0x0000FF00 801179337Syongari#define CHIPMODE_REV_SHIFT 8 802179337Syongari#define CHIPMODE_MODE_48P 0x0000000C 803179337Syongari#define CHIPMODE_MODE_64P 0x00000004 804179337Syongari#define CHIPMODE_MODE_128P_MAC 0x00000003 805179337Syongari#define CHIPMODE_MODE_128P_DBG 0x00000002 806179337Syongari#define CHIPMODE_MODE_128P_PHY 0x00000000 807185596Syongari/* Chip full mask revision. */ 808185596Syongari#define CHIPMODE_REVFM(x) ((x) & 0x0F) 809185596Syongari/* Chip ECO revision. */ 810185596Syongari#define CHIPMODE_REVECO(x) (((x) >> 4) & 0x0F) 811179337Syongari 812179337Syongari/* Shadow status base address high/low. */ 813179337Syongari#define JME_SHBASE_ADDR_HI 0x0848 814179337Syongari#define JME_SHBASE_ADDR_LO 0x084C 815179337Syongari#define SHBASE_ADDR_LO_MASK 0xFFFFFFE0 816179337Syongari#define SHBASE_POST_FORCE 0x00000002 817179337Syongari#define SHBASE_POST_ENB 0x00000001 818179337Syongari 819179337Syongari/* Timer 1 and 2. */ 820179337Syongari#define JME_TIMER1 0x0870 821179337Syongari#define JME_TIMER2 0x0874 822179337Syongari#define TIMER_ENB 0x01000000 823179337Syongari#define TIMER_CNT_MASK 0x00FFFFFF 824179337Syongari#define TIMER_CNT_SHIFT 0 825179337Syongari#define TIMER_UNIT 1024 /* 1024us */ 826179337Syongari 827179337Syongari/* Aggresive power mode control. */ 828179337Syongari#define JME_APMC 0x087C 829179337Syongari#define APMC_PCIE_SDOWN_STAT 0x80000000 830179337Syongari#define APMC_PCIE_SDOWN_ENB 0x40000000 831179337Syongari#define APMC_PSEUDO_HOT_PLUG 0x20000000 832179337Syongari#define APMC_EXT_PLUGIN_ENB 0x04000000 833179337Syongari#define APMC_EXT_PLUGIN_CTL_MSK 0x03000000 834179337Syongari#define APMC_DIS_SRAM 0x00000004 835179337Syongari#define APMC_DIS_CLKPM 0x00000002 836179337Syongari#define APMC_DIS_CLKTX 0x00000001 837179337Syongari 838179337Syongari/* Packet completion coalesing status of Rx queue 0, 1, 2 and 3. */ 839179337Syongari#define JME_PCCSRX_BASE 0x0880 840179337Syongari#define JME_PCCSRX_END 0x088F 841179337Syongari#define PCCSRX_REG(x) (JME_PCCSRX_BASE + ((x) * 4)) 842179337Syongari#define PCCSRX_TO_MASK 0xFFFF0000 843179337Syongari#define PCCSRX_TO_SHIFT 16 844179337Syongari#define PCCSRX_PKT_CNT_MASK 0x0000FF00 845179337Syongari#define PCCSRX_PKT_CNT_SHIFT 8 846179337Syongari 847179337Syongari/* Packet completion coalesing status of Tx queue. */ 848179337Syongari#define JME_PCCSTX 0x0890 849179337Syongari#define PCCSTX_TO_MASK 0xFFFF0000 850179337Syongari#define PCCSTX_TO_SHIFT 16 851179337Syongari#define PCCSTX_PKT_CNT_MASK 0x0000FF00 852179337Syongari#define PCCSTX_PKT_CNT_SHIFT 8 853179337Syongari 854179337Syongari/* Tx queues empty indicator. */ 855179337Syongari#define JME_TXQEMPTY 0x0894 856179337Syongari#define TXQEMPTY_TXQ7 0x00000080 857179337Syongari#define TXQEMPTY_TXQ6 0x00000040 858179337Syongari#define TXQEMPTY_TXQ5 0x00000020 859179337Syongari#define TXQEMPTY_TXQ4 0x00000010 860179337Syongari#define TXQEMPTY_TXQ3 0x00000008 861179337Syongari#define TXQEMPTY_TXQ2 0x00000004 862179337Syongari#define TXQEMPTY_TXQ1 0x00000002 863179337Syongari#define TXQEMPTY_TXQ0 0x00000001 864179337Syongari#define TXQEMPTY_N_TXQ(x, y) ((x) & (0x01 << (y))) 865179337Syongari 866179337Syongari/* RSS control registers. */ 867179337Syongari#define JME_RSS_BASE 0x0C00 868179337Syongari 869179337Syongari#define JME_RSSC 0x0C00 870179337Syongari#define RSSC_HASH_LEN_MASK 0x0000E000 871179337Syongari#define RSSC_HASH_64_ENTRY 0x0000A000 872179337Syongari#define RSSC_HASH_128_ENTRY 0x0000E000 873179337Syongari#define RSSC_HASH_NONE 0x00001000 874179337Syongari#define RSSC_HASH_IPV6 0x00000800 875179337Syongari#define RSSC_HASH_IPV4 0x00000400 876179337Syongari#define RSSC_HASH_IPV6_TCP 0x00000200 877179337Syongari#define RSSC_HASH_IPV4_TCP 0x00000100 878179337Syongari#define RSSC_NCPU_MASK 0x000000F8 879179337Syongari#define RSSC_NCPU_SHIFT 3 880179337Syongari#define RSSC_DIS_RSS 0x00000000 881179337Syongari#define RSSC_2RXQ_ENB 0x00000001 882179337Syongari#define RSSS_4RXQ_ENB 0x00000002 883179337Syongari 884179337Syongari/* CPU vector. */ 885179337Syongari#define JME_RSSCPU 0x0C04 886179337Syongari#define RSSCPU_N_SEL(x) ((1 << (x)) 887179337Syongari 888179337Syongari/* RSS Hash value. */ 889179337Syongari#define JME_RSSHASH 0x0C10 890179337Syongari 891179337Syongari#define JME_RSSHASH_STAT 0x0C14 892179337Syongari 893179337Syongari#define JME_RSS_RDATA0 0x0C18 894179337Syongari 895179337Syongari#define JME_RSS_RDATA1 0x0C1C 896179337Syongari 897179337Syongari/* RSS secret key. */ 898179337Syongari#define JME_RSSKEY_BASE 0x0C40 899179337Syongari#define JME_RSSKEY_LAST 0x0C64 900179337Syongari#define JME_RSSKEY_END 0x0C67 901179337Syongari#define HASHKEY_NBYTES 40 902179337Syongari#define RSSKEY_REG(x) (JME_RSSKEY_LAST - (4 * ((x) / 4))) 903179337Syongari#define RSSKEY_VALUE(x, y) ((x) << (24 - 8 * ((y) % 4))) 904179337Syongari 905179337Syongari/* RSS indirection table entries. */ 906179337Syongari#define JME_RSSTBL_BASE 0x0C80 907179337Syongari#define JME_RSSTBL_END 0x0CFF 908179337Syongari#define RSSTBL_NENTRY 128 909179337Syongari#define RSSTBL_REG(x) (JME_RSSTBL_BASE + ((x) / 4)) 910179337Syongari#define RSSTBL_VALUE(x, y) ((x) << (8 * ((y) % 4))) 911179337Syongari 912179337Syongari/* MSI-X table. */ 913179337Syongari#define JME_MSIX_BASE_ADDR 0x2000 914179337Syongari 915179337Syongari#define JME_MSIX_BASE 0x2000 916179337Syongari#define JME_MSIX_END 0x207F 917179337Syongari#define JME_MSIX_NENTRY 8 918179337Syongari#define MSIX_REG(x) (JME_MSIX_BASE + ((x) * 0x10)) 919179337Syongari#define MSIX_ADDR_HI_OFF 0x00 920179337Syongari#define MSIX_ADDR_LO_OFF 0x04 921179337Syongari#define MSIX_ADDR_LO_MASK 0xFFFFFFFC 922179337Syongari#define MSIX_DATA_OFF 0x08 923179337Syongari#define MSIX_VECTOR_OFF 0x0C 924179337Syongari#define MSIX_VECTOR_RSVD 0x80000000 925179337Syongari#define MSIX_VECTOR_DIS 0x00000001 926179337Syongari 927179337Syongari/* MSI-X PBA. */ 928179337Syongari#define JME_MSIX_PBA_BASE_ADDR 0x3000 929179337Syongari 930179337Syongari#define JME_MSIX_PBA 0x3000 931179337Syongari#define MSIX_PBA_RSVD_MASK 0xFFFFFF00 932179337Syongari#define MSIX_PBA_RSVD_SHIFT 8 933179337Syongari#define MSIX_PBA_PEND_MASK 0x000000FF 934179337Syongari#define MSIX_PBA_PEND_SHIFT 0 935179337Syongari#define MSIX_PBA_PEND_ENTRY7 0x00000080 936179337Syongari#define MSIX_PBA_PEND_ENTRY6 0x00000040 937179337Syongari#define MSIX_PBA_PEND_ENTRY5 0x00000020 938179337Syongari#define MSIX_PBA_PEND_ENTRY4 0x00000010 939179337Syongari#define MSIX_PBA_PEND_ENTRY3 0x00000008 940179337Syongari#define MSIX_PBA_PEND_ENTRY2 0x00000004 941179337Syongari#define MSIX_PBA_PEND_ENTRY1 0x00000002 942179337Syongari#define MSIX_PBA_PEND_ENTRY0 0x00000001 943179337Syongari 944179337Syongari#define JME_PHY_OUI 0x001B8C 945179337Syongari#define JME_PHY_MODEL 0x21 946179337Syongari#define JME_PHY_REV 0x01 947179337Syongari#define JME_PHY_ADDR 1 948179337Syongari 949179337Syongari/* JMC250 shadow status block. */ 950179337Syongaristruct jme_ssb { 951179337Syongari uint32_t dw0; 952179337Syongari uint32_t dw1; 953179337Syongari uint32_t dw2; 954179337Syongari uint32_t dw3; 955179337Syongari uint32_t dw4; 956179337Syongari uint32_t dw5; 957179337Syongari uint32_t dw6; 958179337Syongari uint32_t dw7; 959179337Syongari}; 960179337Syongari 961179337Syongari/* JMC250 descriptor structures. */ 962179337Syongaristruct jme_desc { 963179337Syongari uint32_t flags; 964179337Syongari uint32_t buflen; 965179337Syongari uint32_t addr_hi; 966179337Syongari uint32_t addr_lo; 967179337Syongari}; 968179337Syongari 969179337Syongari#define JME_TD_OWN 0x80000000 970179337Syongari#define JME_TD_INTR 0x40000000 971179337Syongari#define JME_TD_64BIT 0x20000000 972179337Syongari#define JME_TD_TCPCSUM 0x10000000 973179337Syongari#define JME_TD_UDPCSUM 0x08000000 974179337Syongari#define JME_TD_IPCSUM 0x04000000 975179337Syongari#define JME_TD_TSO 0x02000000 976179337Syongari#define JME_TD_VLAN_TAG 0x01000000 977179337Syongari#define JME_TD_VLAN_MASK 0x0000FFFF 978179337Syongari 979179337Syongari#define JME_TD_MSS_MASK 0xFFFC0000 980179337Syongari#define JME_TD_MSS_SHIFT 18 981179337Syongari#define JME_TD_BUF_LEN_MASK 0x0000FFFF 982179337Syongari#define JME_TD_BUF_LEN_SHIFT 0 983179337Syongari 984179337Syongari#define JME_TD_FRAME_LEN_MASK 0x0000FFFF 985179337Syongari#define JME_TD_FRAME_LEN_SHIFT 0 986179337Syongari 987179337Syongari/* 988179337Syongari * Only the first Tx descriptor of a packet is updated 989179337Syongari * after packet transmission. 990179337Syongari */ 991179337Syongari#define JME_TD_TMOUT 0x20000000 992179337Syongari#define JME_TD_RETRY_EXP 0x10000000 993179337Syongari#define JME_TD_COLLISION 0x08000000 994179337Syongari#define JME_TD_UNDERRUN 0x04000000 995179337Syongari#define JME_TD_EHDR_SIZE_MASK 0x000000FF 996179337Syongari#define JME_TD_EHDR_SIZE_SHIFT 0 997179337Syongari 998179337Syongari#define JME_TD_SEG_CNT_MASK 0xFFFF0000 999179337Syongari#define JME_TD_SEG_CNT_SHIFT 16 1000179337Syongari#define JME_TD_RETRY_CNT_MASK 0x0000FFFF 1001179337Syongari#define JME_TD_RETRY_CNT_SHIFT 0 1002179337Syongari 1003179337Syongari#define JME_RD_OWN 0x80000000 1004179337Syongari#define JME_RD_INTR 0x40000000 1005179337Syongari#define JME_RD_64BIT 0x20000000 1006179337Syongari 1007179337Syongari#define JME_RD_BUF_LEN_MASK 0x0000FFFF 1008179337Syongari#define JME_RD_BUF_LEN_SHIFT 0 1009179337Syongari 1010179337Syongari/* 1011179337Syongari * Only the first Rx descriptor of a packet is updated 1012179337Syongari * after packet reception. 1013179337Syongari */ 1014179337Syongari#define JME_RD_MORE_FRAG 0x20000000 1015179337Syongari#define JME_RD_TCP 0x10000000 1016179337Syongari#define JME_RD_UDP 0x08000000 1017179337Syongari#define JME_RD_IPCSUM 0x04000000 1018179337Syongari#define JME_RD_TCPCSUM 0x02000000 1019179337Syongari#define JME_RD_UDPCSUM 0x01000000 1020179337Syongari#define JME_RD_VLAN_TAG 0x00800000 1021179337Syongari#define JME_RD_IPV4 0x00400000 1022179337Syongari#define JME_RD_IPV6 0x00200000 1023179337Syongari#define JME_RD_PAUSE 0x00100000 1024179337Syongari#define JME_RD_MAGIC 0x00080000 1025179337Syongari#define JME_RD_WAKEUP 0x00040000 1026179337Syongari#define JME_RD_BCAST 0x00030000 1027179337Syongari#define JME_RD_MCAST 0x00020000 1028179337Syongari#define JME_RD_UCAST 0x00010000 1029179337Syongari#define JME_RD_VLAN_MASK 0x0000FFFF 1030179337Syongari#define JME_RD_VLAN_SHIFT 0 1031179337Syongari 1032179337Syongari#define JME_RD_VALID 0x80000000 1033179337Syongari#define JME_RD_CNT_MASK 0x7F000000 1034179337Syongari#define JME_RD_CNT_SHIFT 24 1035179337Syongari#define JME_RD_GIANT 0x00800000 1036179337Syongari#define JME_RD_GMII_ERR 0x00400000 1037179337Syongari#define JME_RD_NBL_RCVD 0x00200000 1038179337Syongari#define JME_RD_COLL 0x00100000 1039179337Syongari#define JME_RD_ABORT 0x00080000 1040179337Syongari#define JME_RD_RUNT 0x00040000 1041179337Syongari#define JME_RD_FIFO_OVRN 0x00020000 1042179337Syongari#define JME_RD_CRC_ERR 0x00010000 1043179337Syongari#define JME_RD_FRAME_LEN_MASK 0x0000FFFF 1044179337Syongari 1045179337Syongari#define JME_RX_ERR_STAT \ 1046179337Syongari (JME_RD_GIANT | JME_RD_GMII_ERR | JME_RD_NBL_RCVD | \ 1047179337Syongari JME_RD_COLL | JME_RD_ABORT | JME_RD_RUNT | \ 1048179337Syongari JME_RD_FIFO_OVRN | JME_RD_CRC_ERR) 1049179337Syongari 1050179337Syongari#define JME_RD_ERR_MASK 0x00FF0000 1051179337Syongari#define JME_RD_ERR_SHIFT 16 1052179337Syongari#define JME_RX_ERR(x) (((x) & JME_RD_ERR_MASK) >> JME_RD_ERR_SHIFT) 1053179337Syongari#define JME_RX_ERR_BITS "\20" \ 1054179337Syongari "\1CRCERR\2FIFOOVRN\3RUNT\4ABORT" \ 1055179337Syongari "\5COLL\6NBLRCVD\7GMIIERR\10" 1056179337Syongari 1057179337Syongari#define JME_RX_NSEGS(x) (((x) & JME_RD_CNT_MASK) >> JME_RD_CNT_SHIFT) 1058179337Syongari#define JME_RX_BYTES(x) ((x) & JME_RD_FRAME_LEN_MASK) 1059179337Syongari#define JME_RX_PAD_BYTES 10 1060179337Syongari 1061179337Syongari#define JME_RD_RSS_HASH_VALUE 0xFFFFFFFF 1062179337Syongari 1063179337Syongari#define JME_RD_RSS_HASH_MASK 0x00003F00 1064179337Syongari#define JME_RD_RSS_HASH_SHIFT 8 1065179337Syongari#define JME_RD_RSS_HASH_NONE 0x00000000 1066179337Syongari#define JME_RD_RSS_HASH_IPV4 0x00000100 1067179337Syongari#define JME_RD_RSS_HASH_IPV4TCP 0x00000200 1068179337Syongari#define JME_RD_RSS_HASH_IPV6 0x00000400 1069179337Syongari#define JME_RD_RSS_HASH_IPV6TCP 0x00001000 1070179337Syongari#define JME_RD_HASH_FN_NONE 0x00000000 1071179337Syongari#define JME_RD_HASH_FN_TOEPLITZ 0x00000001 1072179337Syongari 1073179337Syongari#endif 1074