if_jmereg.h revision 182888
1179337Syongari/*-
2179337Syongari * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3179337Syongari * All rights reserved.
4179337Syongari *
5179337Syongari * Redistribution and use in source and binary forms, with or without
6179337Syongari * modification, are permitted provided that the following conditions
7179337Syongari * are met:
8179337Syongari * 1. Redistributions of source code must retain the above copyright
9179337Syongari *    notice unmodified, this list of conditions, and the following
10179337Syongari *    disclaimer.
11179337Syongari * 2. Redistributions in binary form must reproduce the above copyright
12179337Syongari *    notice, this list of conditions and the following disclaimer in the
13179337Syongari *    documentation and/or other materials provided with the distribution.
14179337Syongari *
15179337Syongari * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16179337Syongari * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17179337Syongari * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18179337Syongari * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19179337Syongari * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20179337Syongari * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21179337Syongari * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22179337Syongari * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23179337Syongari * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24179337Syongari * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25179337Syongari * SUCH DAMAGE.
26179337Syongari *
27179337Syongari * $FreeBSD: head/sys/dev/jme/if_jmereg.h 182888 2008-09-09 10:19:48Z yongari $
28179337Syongari */
29179337Syongari
30179337Syongari#ifndef	_IF_JMEREG_H
31179337Syongari#define	_IF_JMEREG_H
32179337Syongari
33179337Syongari/*
34179337Syongari * JMicron Inc. PCI vendor ID
35179337Syongari */
36179337Syongari#define	VENDORID_JMICRON	0x197B
37179337Syongari
38179337Syongari/*
39179337Syongari * JMC250 PCI device ID
40179337Syongari */
41179337Syongari#define	DEVICEID_JMC250		0x0250
42182888Syongari#define	DEVICEREVID_JMC250_A0	0x00
43182888Syongari#define	DEVICEREVID_JMC250_A2	0x11
44179337Syongari
45179337Syongari/*
46179337Syongari * JMC260 PCI device ID
47179337Syongari */
48179337Syongari#define	DEVICEID_JMC260		0x0260
49182888Syongari#define	DEVICEREVID_JMC260_A0	0x00
50179337Syongari
51179337Syongari/* JMC250 PCI configuration register. */
52179337Syongari#define	JME_PCI_BAR0		0x10	/* 16KB memory window. */
53179337Syongari
54179337Syongari#define	JME_PCI_BAR1		0x18	/* 128bytes I/O window. */
55179337Syongari
56179337Syongari#define	JME_PCI_BAR2		0x1C	/* 256bytes I/O window. */
57179337Syongari
58179337Syongari#define	JME_PCI_BAR3		0x20	/* 64KB memory window. */
59179337Syongari
60179337Syongari#define	JME_PCI_EROM		0x30
61179337Syongari
62179337Syongari#define	JME_PCI_DBG		0x9C
63179337Syongari
64179337Syongari#define	JME_PCI_SPI		0xB0
65179337Syongari
66179337Syongari#define	SPI_ENB			0x00000010
67179337Syongari#define	SPI_SO_STATUS		0x00000008
68179337Syongari#define	SPI_SI_CTRL		0x00000004
69179337Syongari#define	SPI_SCK_CTRL		0x00000002
70179337Syongari#define	SPI_CS_N_CTRL		0x00000001
71179337Syongari
72179337Syongari#define	JME_PCI_PHYCFG0		0xC0
73179337Syongari
74179337Syongari#define	JME_PCI_PHYCFG1		0xC4
75179337Syongari
76179337Syongari#define	JME_PCI_PHYCFG2		0xC8
77179337Syongari
78179337Syongari#define	JME_PCI_PHYCFG3		0xCC
79179337Syongari
80179337Syongari#define	JME_PCI_PIPECTL1	0xD0
81179337Syongari
82179337Syongari#define	JME_PCI_PIPECTL2	0xD4
83179337Syongari
84179337Syongari/* PCIe link error/status. */
85179337Syongari#define	JME_PCI_LES		0xD8
86179337Syongari
87179337Syongari/* propeietary register 0. */
88179337Syongari#define	JME_PCI_PE0		0xE0
89179337Syongari#define	PE0_SPI_EXIST		0x00200000
90179337Syongari#define	PE0_PME_D0		0x00100000
91179337Syongari#define	PE0_PME_D3H		0x00080000
92179337Syongari#define	PE0_PME_SPI_PAD		0x00040000
93179337Syongari#define	PE0_MASK_ASPM		0x00020000
94179337Syongari#define	PE0_EEPROM_RW_DIS	0x00008000
95179337Syongari#define	PE0_PCI_INTA		0x00001000
96179337Syongari#define	PE0_PCI_INTB		0x00002000
97179337Syongari#define	PE0_PCI_INTC		0x00003000
98179337Syongari#define	PE0_PCI_INTD		0x00004000
99179337Syongari#define	PE0_PCI_SVSSID_WR_ENB	0x00000800
100179337Syongari#define	PE0_MSIX_SIZE_8		0x00000700
101179337Syongari#define	PE0_MSIX_SIZE_7		0x00000600
102179337Syongari#define	PE0_MSIX_SIZE_6		0x00000500
103179337Syongari#define	PE0_MSIX_SIZE_5		0x00000400
104179337Syongari#define	PE0_MSIX_SIZE_4		0x00000300
105179337Syongari#define	PE0_MSIX_SIZE_3		0x00000200
106179337Syongari#define	PE0_MSIX_SIZE_2		0x00000100
107179337Syongari#define	PE0_MSIX_SIZE_1		0x00000000
108179337Syongari#define	PE0_MSIX_SIZE_DEF	0x00000700
109179337Syongari#define	PE0_MSIX_CAP_DIS	0x00000080
110179337Syongari#define	PE0_MSI_PVMC_ENB	0x00000040
111179337Syongari#define	PE0_LCAP_EXIT_LAT_MASK	0x00000038
112179337Syongari#define	PE0_LCAP_EXIT_LAT_DEF	0x00000038
113179337Syongari#define	PE0_PM_AUXC_MASK	0x00000007
114179337Syongari#define	PE0_PM_AUXC_DEF		0x00000007
115179337Syongari
116179337Syongari#define	JME_PCI_PE1		0xE4
117179337Syongari
118179337Syongari#define	JME_PCI_PHYTEST		0xF8
119179337Syongari
120179337Syongari#define	JME_PCI_GPR		0xFC
121179337Syongari
122179337Syongari/*
123179337Syongari * JMC Register Map.
124179337Syongari * -----------------------------------------------------------------------
125179337Syongari *   Register               Size           IO space         Memory space
126179337Syongari * -----------------------------------------------------------------------
127179337Syongari * Tx/Rx MAC registers    128 bytes     BAR1 + 0x00 ~       BAR0 + 0x00 ~
128179337Syongari *                                       BAR1 + 0x7F         BAR0 + 0x7F
129179337Syongari * -----------------------------------------------------------------------
130179337Syongari * PHY registers          128 bytes     BAR2 + 0x00 ~       BAR0 + 0x400 ~
131179337Syongari *                                       BAR2 + 0x7F         BAR0 + 0x47F
132179337Syongari * -----------------------------------------------------------------------
133179337Syongari * Misc registers         128 bytes     BAR2 + 0x80 ~       BAR0 + 0x800 ~
134179337Syongari *                                       BAR2 + 0x7F         BAR0 + 0x87F
135179337Syongari * -----------------------------------------------------------------------
136179337Syongari * To simplify register access fuctions and to get better performance
137179337Syongari * this driver doesn't support IO space access. It could be implemented
138179337Syongari * as a function which selects appropriate BARs to access requested
139179337Syongari * register.
140179337Syongari */
141179337Syongari
142179337Syongari/* Tx control and status. */
143179337Syongari#define	JME_TXCSR		0x0000
144179337Syongari#define	TXCSR_QWEIGHT_MASK	0x0F000000
145179337Syongari#define	TXCSR_QWEIGHT_SHIFT	24
146179337Syongari#define	TXCSR_TXQ_SEL_MASK	0x00070000
147179337Syongari#define	TXCSR_TXQ_SEL_SHIFT	16
148179337Syongari#define	TXCSR_TXQ_START		0x00000001
149179337Syongari#define	TXCSR_TXQ_START_SHIFT	8
150179337Syongari#define	TXCSR_FIFO_THRESH_4QW	0x00000000
151179337Syongari#define	TXCSR_FIFO_THRESH_8QW	0x00000040
152179337Syongari#define	TXCSR_FIFO_THRESH_12QW	0x00000080
153179337Syongari#define	TXCSR_FIFO_THRESH_16QW	0x000000C0
154179337Syongari#define	TXCSR_DMA_SIZE_64	0x00000000
155179337Syongari#define	TXCSR_DMA_SIZE_128	0x00000010
156179337Syongari#define	TXCSR_DMA_SIZE_256	0x00000020
157179337Syongari#define	TXCSR_DMA_SIZE_512	0x00000030
158179337Syongari#define	TXCSR_DMA_BURST		0x00000004
159179337Syongari#define	TXCSR_TX_SUSPEND	0x00000002
160179337Syongari#define	TXCSR_TX_ENB		0x00000001
161179337Syongari#define	TXCSR_TXQ0		0
162179337Syongari#define	TXCSR_TXQ1		1
163179337Syongari#define	TXCSR_TXQ2		2
164179337Syongari#define	TXCSR_TXQ3		3
165179337Syongari#define	TXCSR_TXQ4		4
166179337Syongari#define	TXCSR_TXQ5		5
167179337Syongari#define	TXCSR_TXQ6		6
168179337Syongari#define	TXCSR_TXQ7		7
169179337Syongari#define	TXCSR_TXQ_WEIGHT(x)	\
170179337Syongari	(((x) << TXCSR_QWEIGHT_SHIFT) & TXCSR_QWEIGHT_MASK)
171179337Syongari#define	TXCSR_TXQ_WEIGHT_MIN	0
172179337Syongari#define	TXCSR_TXQ_WEIGHT_MAX	15
173179337Syongari#define	TXCSR_TXQ_N_SEL(x)	\
174179337Syongari	(((x) << TXCSR_TXQ_SEL_SHIFT) & TXCSR_TXQ_SEL_MASK)
175179337Syongari#define	TXCSR_TXQ_N_START(x)	\
176179337Syongari	(TXCSR_TXQ_START << (TXCSR_TXQ_START_SHIFT + (x)))
177179337Syongari
178179337Syongari/* Tx queue descriptor base address. 16bytes alignment required. */
179179337Syongari#define	JME_TXDBA_LO		0x0004
180179337Syongari#define	JME_TXDBA_HI		0x0008
181179337Syongari
182179337Syongari/* Tx queue descriptor count. multiple of 16(max = 1024). */
183179337Syongari#define	JME_TXQDC		0x000C
184179337Syongari#define	TXQDC_MASK		0x0000007F0
185179337Syongari
186179337Syongari/* Tx queue next descriptor address. */
187179337Syongari#define	JME_TXNDA		0x0010
188179337Syongari#define	TXNDA_ADDR_MASK		0xFFFFFFF0
189179337Syongari#define	TXNDA_DESC_EMPTY	0x00000008
190179337Syongari#define	TXNDA_DESC_VALID	0x00000004
191179337Syongari#define	TXNDA_DESC_WAIT		0x00000002
192179337Syongari#define	TXNDA_DESC_FETCH	0x00000001
193179337Syongari
194179337Syongari/* Tx MAC control ans status. */
195179337Syongari#define	JME_TXMAC		0x0014
196179337Syongari#define	TXMAC_IFG2_MASK		0xC0000000
197179337Syongari#define	TXMAC_IFG2_DEFAULT	0x40000000
198179337Syongari#define	TXMAC_IFG1_MASK		0x30000000
199179337Syongari#define	TXMAC_IFG1_DEFAULT	0x20000000
200179337Syongari#define	TXMAC_THRESH_1_PKT	0x00000300
201179337Syongari#define	TXMAC_THRESH_1_2_PKT	0x00000200
202179337Syongari#define	TXMAC_THRESH_1_4_PKT	0x00000100
203179337Syongari#define	TXMAC_THRESH_1_8_PKT	0x00000000
204179337Syongari#define	TXMAC_FRAME_BURST	0x00000080
205179337Syongari#define	TXMAC_CARRIER_EXT	0x00000040
206179337Syongari#define	TXMAC_IFG_ENB		0x00000020
207179337Syongari#define	TXMAC_BACKOFF		0x00000010
208179337Syongari#define	TXMAC_CARRIER_SENSE	0x00000008
209179337Syongari#define	TXMAC_COLL_ENB		0x00000004
210179337Syongari#define	TXMAC_CRC_ENB		0x00000002
211179337Syongari#define	TXMAC_PAD_ENB		0x00000001
212179337Syongari
213179337Syongari/* Tx pause frame control. */
214179337Syongari#define	JME_TXPFC		0x0018
215179337Syongari#define	TXPFC_VLAN_TAG_MASK	0xFFFF0000
216179337Syongari#define	TXPFC_VLAN_TAG_SHIFT	16
217179337Syongari#define	TXPFC_VLAN_ENB		0x00008000
218179337Syongari#define	TXPFC_PAUSE_ENB		0x00000001
219179337Syongari
220179337Syongari/* Tx timer/retry at half duplex. */
221179337Syongari#define	JME_TXTRHD		0x001C
222179337Syongari#define	TXTRHD_RT_PERIOD_ENB	0x80000000
223179337Syongari#define	TXTRHD_RT_PERIOD_MASK	0x7FFFFF00
224179337Syongari#define	TXTRHD_RT_PERIOD_SHIFT	8
225179337Syongari#define	TXTRHD_RT_LIMIT_ENB	0x00000080
226179337Syongari#define	TXTRHD_RT_LIMIT_MASK	0x0000007F
227179337Syongari#define	TXTRHD_RT_LIMIT_SHIFT	0
228179337Syongari#define	TXTRHD_RT_PERIOD_DEFAULT	8192
229179337Syongari#define	TXTRHD_RT_LIMIT_DEFAULT	8
230179337Syongari
231179337Syongari/* Rx control & status. */
232179337Syongari#define	JME_RXCSR		0x0020
233179337Syongari#define	RXCSR_FIFO_FTHRESH_16T	0x00000000
234179337Syongari#define	RXCSR_FIFO_FTHRESH_32T	0x10000000
235179337Syongari#define	RXCSR_FIFO_FTHRESH_64T	0x20000000
236179337Syongari#define	RXCSR_FIFO_FTHRESH_128T	0x30000000
237179337Syongari#define	RXCSR_FIFO_FTHRESH_MASK	0x30000000
238179337Syongari#define	RXCSR_FIFO_THRESH_16QW	0x00000000
239179337Syongari#define	RXCSR_FIFO_THRESH_32QW	0x04000000
240179337Syongari#define	RXCSR_FIFO_THRESH_64QW	0x08000000
241179337Syongari#define	RXCSR_FIFO_THRESH_128QW	0x0C000000
242179337Syongari#define	RXCSR_FIFO_THRESH_MASK	0x0C000000
243179337Syongari#define	RXCSR_DMA_SIZE_16	0x00000000
244179337Syongari#define	RXCSR_DMA_SIZE_32	0x01000000
245179337Syongari#define	RXCSR_DMA_SIZE_64	0x02000000
246179337Syongari#define	RXCSR_DMA_SIZE_128	0x03000000
247179337Syongari#define	RXCSR_RXQ_SEL_MASK	0x00030000
248179337Syongari#define	RXCSR_RXQ_SEL_SHIFT	16
249179337Syongari#define	RXCSR_DESC_RT_GAP_MASK	0x0000F000
250179337Syongari#define	RXCSR_DESC_RT_GAP_SHIFT	12
251179337Syongari#define	RXCSR_DESC_RT_GAP_256	0x00000000
252179337Syongari#define	RXCSR_DESC_RT_GAP_512	0x00001000
253179337Syongari#define	RXCSR_DESC_RT_GAP_1024	0x00002000
254179337Syongari#define	RXCSR_DESC_RT_GAP_2048	0x00003000
255179337Syongari#define	RXCSR_DESC_RT_GAP_4096	0x00004000
256179337Syongari#define	RXCSR_DESC_RT_GAP_8192	0x00005000
257179337Syongari#define	RXCSR_DESC_RT_GAP_16384	0x00006000
258179337Syongari#define	RXCSR_DESC_RT_GAP_32768	0x00007000
259179337Syongari#define	RXCSR_DESC_RT_CNT_MASK	0x00000F00
260179337Syongari#define	RXCSR_DESC_RT_CNT_SHIFT	8
261179337Syongari#define	RXCSR_PASS_WAKEUP_PKT	0x00000040
262179337Syongari#define	RXCSR_PASS_MAGIC_PKT	0x00000020
263179337Syongari#define	RXCSR_PASS_RUNT_PKT	0x00000010
264179337Syongari#define	RXCSR_PASS_BAD_PKT	0x00000008
265179337Syongari#define	RXCSR_RXQ_START		0x00000004
266179337Syongari#define	RXCSR_RX_SUSPEND	0x00000002
267179337Syongari#define	RXCSR_RX_ENB		0x00000001
268179337Syongari
269179337Syongari#define	RXCSR_RXQ_N_SEL(x)	((x) << RXCSR_RXQ_SEL_SHIFT)
270179337Syongari#define	RXCSR_RXQ0		0
271179337Syongari#define	RXCSR_RXQ1		1
272179337Syongari#define	RXCSR_RXQ2		2
273179337Syongari#define	RXCSR_RXQ3		3
274179337Syongari#define	RXCSR_DESC_RT_CNT(x)	\
275179337Syongari	((((x) / 4) << RXCSR_DESC_RT_CNT_SHIFT) & RXCSR_DESC_RT_CNT_MASK)
276179337Syongari#define	RXCSR_DESC_RT_CNT_DEFAULT	32
277179337Syongari
278179337Syongari/* Rx queue descriptor base address. 16bytes alignment needed. */
279179337Syongari#define	JME_RXDBA_LO		0x0024
280179337Syongari#define	JME_RXDBA_HI		0x0028
281179337Syongari
282179337Syongari/* Rx queue descriptor count. multiple of 16(max = 1024). */
283179337Syongari#define	JME_RXQDC		0x002C
284179337Syongari#define	RXQDC_MASK		0x0000007F0
285179337Syongari
286179337Syongari/* Rx queue next descriptor address. */
287179337Syongari#define	JME_RXNDA		0x0030
288179337Syongari#define	RXNDA_ADDR_MASK		0xFFFFFFF0
289179337Syongari#define	RXNDA_DESC_EMPTY	0x00000008
290179337Syongari#define	RXNDA_DESC_VALID	0x00000004
291179337Syongari#define	RXNDA_DESC_WAIT		0x00000002
292179337Syongari#define	RXNDA_DESC_FETCH	0x00000001
293179337Syongari
294179337Syongari/* Rx MAC control and status. */
295179337Syongari#define	JME_RXMAC		0x0034
296179337Syongari#define	RXMAC_RSS_UNICAST	0x00000000
297179337Syongari#define	RXMAC_RSS_UNI_MULTICAST	0x00010000
298179337Syongari#define	RXMAC_RSS_UNI_MULTI_BROADCAST	0x00020000
299179337Syongari#define	RXMAC_RSS_ALLFRAME	0x00030000
300179337Syongari#define	RXMAC_PROMISC		0x00000800
301179337Syongari#define	RXMAC_BROADCAST		0x00000400
302179337Syongari#define	RXMAC_MULTICAST		0x00000200
303179337Syongari#define	RXMAC_UNICAST		0x00000100
304179337Syongari#define	RXMAC_ALLMULTI		0x00000080
305179337Syongari#define	RXMAC_MULTICAST_FILTER	0x00000040
306179337Syongari#define	RXMAC_COLL_DET_ENB	0x00000020
307179337Syongari#define	RXMAC_FC_ENB		0x00000008
308179337Syongari#define	RXMAC_VLAN_ENB		0x00000004
309179337Syongari#define	RXMAC_PAD_10BYTES	0x00000002
310179337Syongari#define	RXMAC_CSUM_ENB		0x00000001
311179337Syongari
312179337Syongari/* Rx unicast MAC address. */
313179337Syongari#define	JME_PAR0		0x0038
314179337Syongari#define	JME_PAR1		0x003C
315179337Syongari
316179337Syongari/* Rx multicast address hash table. */
317179337Syongari#define	JME_MAR0		0x0040
318179337Syongari#define	JME_MAR1		0x0044
319179337Syongari
320179337Syongari/* Wakeup frame output data port. */
321179337Syongari#define	JME_WFODP		0x0048
322179337Syongari
323179337Syongari/* Wakeup frame output interface. */
324179337Syongari#define	JME_WFOI		0x004C
325179337Syongari#define	WFOI_MASK_0_31		0x00000000
326179337Syongari#define	WFOI_MASK_31_63		0x00000010
327179337Syongari#define	WFOI_MASK_64_95		0x00000020
328179337Syongari#define	WFOI_MASK_96_127	0x00000030
329179337Syongari#define	WFOI_MASK_SEL		0x00000008
330179337Syongari#define	WFOI_CRC_SEL		0x00000000
331179337Syongari#define	WFOI_WAKEUP_FRAME_MASK	0x00000007
332179337Syongari#define	WFOI_WAKEUP_FRAME_SEL(x)	((x) & WFOI_WAKEUP_FRAME_MASK)
333179337Syongari
334179337Syongari/* Station management interface. */
335179337Syongari#define	JME_SMI			0x0050
336179337Syongari#define	SMI_DATA_MASK		0xFFFF0000
337179337Syongari#define	SMI_DATA_SHIFT		16
338179337Syongari#define	SMI_REG_ADDR_MASK	0x0000F800
339179337Syongari#define	SMI_REG_ADDR_SHIFT	11
340179337Syongari#define	SMI_PHY_ADDR_MASK	0x000007C0
341179337Syongari#define	SMI_PHY_ADDR_SHIFT	6
342179337Syongari#define	SMI_OP_WRITE		0x00000020
343179337Syongari#define	SMI_OP_READ		0x00000000
344179337Syongari#define	SMI_OP_EXECUTE		0x00000010
345179337Syongari#define	SMI_MDIO		0x00000008
346179337Syongari#define	SMI_MDOE		0x00000004
347179337Syongari#define	SMI_MDC			0x00000002
348179337Syongari#define	SMI_MDEN		0x00000001
349179337Syongari#define	SMI_REG_ADDR(x)		\
350179337Syongari	(((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK)
351179337Syongari#define	SMI_PHY_ADDR(x)		\
352179337Syongari	(((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK)
353179337Syongari
354179337Syongari/* Global host control. */
355179337Syongari#define	JME_GHC			0x0054
356179337Syongari#define	GHC_LOOPBACK		0x80000000
357179337Syongari#define	GHC_RESET		0x40000000
358179337Syongari#define	GHC_FULL_DUPLEX		0x00000040
359179337Syongari#define	GHC_SPEED_UNKNOWN	0x00000000
360179337Syongari#define	GHC_SPEED_10		0x00000010
361179337Syongari#define	GHC_SPEED_100		0x00000020
362179337Syongari#define	GHC_SPEED_1000		0x00000030
363179337Syongari#define	GHC_SPEED_MASK		0x00000030
364179337Syongari#define	GHC_LINK_OFF		0x00000004
365179337Syongari#define	GHC_LINK_ON		0x00000002
366179337Syongari#define	GHC_LINK_STAT_POLLING	0x00000001
367179337Syongari
368179337Syongari/* Power management control and status. */
369179337Syongari#define	JME_PMCS		0x0060
370179337Syongari#define	PMCS_WAKEUP_FRAME_7	0x80000000
371179337Syongari#define	PMCS_WAKEUP_FRAME_6	0x40000000
372179337Syongari#define	PMCS_WAKEUP_FRAME_5	0x20000000
373179337Syongari#define	PMCS_WAKEUP_FRAME_4	0x10000000
374179337Syongari#define	PMCS_WAKEUP_FRAME_3	0x08000000
375179337Syongari#define	PMCS_WAKEUP_FRAME_2	0x04000000
376179337Syongari#define	PMCS_WAKEUP_FRAME_1	0x02000000
377179337Syongari#define	PMCS_WAKEUP_FRAME_0	0x01000000
378179337Syongari#define	PMCS_LINK_FAIL		0x00040000
379179337Syongari#define	PMCS_LINK_RISING	0x00020000
380179337Syongari#define	PMCS_MAGIC_FRAME	0x00010000
381179337Syongari#define	PMCS_WAKEUP_FRAME_7_ENB	0x00008000
382179337Syongari#define	PMCS_WAKEUP_FRAME_6_ENB	0x00004000
383179337Syongari#define	PMCS_WAKEUP_FRAME_5_ENB	0x00002000
384179337Syongari#define	PMCS_WAKEUP_FRAME_4_ENB	0x00001000
385179337Syongari#define	PMCS_WAKEUP_FRAME_3_ENB	0x00000800
386179337Syongari#define	PMCS_WAKEUP_FRAME_2_ENB	0x00000400
387179337Syongari#define	PMCS_WAKEUP_FRAME_1_ENB	0x00000200
388179337Syongari#define	PMCS_WAKEUP_FRAME_0_ENB	0x00000100
389179337Syongari#define	PMCS_LINK_FAIL_ENB	0x00000004
390179337Syongari#define	PMCS_LINK_RISING_ENB	0x00000002
391179337Syongari#define	PMCS_MAGIC_FRAME_ENB	0x00000001
392179337Syongari#define	PMCS_WOL_ENB_MASK	0x0000FFFF
393179337Syongari
394179337Syongari/* Giga PHY & EEPROM registers. */
395179337Syongari#define	JME_PHY_EEPROM_BASE_ADDR	0x0400
396179337Syongari
397179337Syongari#define	JME_GIGAR0LO		0x0400
398179337Syongari#define	JME_GIGAR0HI		0x0404
399179337Syongari#define	JME_GIGARALO		0x0408
400179337Syongari#define	JME_GIGARAHI		0x040C
401179337Syongari#define	JME_GIGARBLO		0x0410
402179337Syongari#define	JME_GIGARBHI		0x0414
403179337Syongari#define	JME_GIGARCLO		0x0418
404179337Syongari#define	JME_GIGARCHI		0x041C
405179337Syongari#define	JME_GIGARDLO		0x0420
406179337Syongari#define	JME_GIGARDHI		0x0424
407179337Syongari
408179337Syongari/* BIST status and control. */
409179337Syongari#define	JME_GIGACSR		0x0428
410179337Syongari#define	GIGACSR_STATUS		0x40000000
411179337Syongari#define	GIGACSR_CTRL_MASK	0x30000000
412179337Syongari#define	GIGACSR_CTRL_DEFAULT	0x30000000
413179337Syongari#define	GIGACSR_TX_CLK_MASK	0x0F000000
414179337Syongari#define	GIGACSR_RX_CLK_MASK	0x00F00000
415179337Syongari#define	GIGACSR_TX_CLK_INV	0x00080000
416179337Syongari#define	GIGACSR_RX_CLK_INV	0x00040000
417179337Syongari#define	GIGACSR_PHY_RST		0x00010000
418179337Syongari#define	GIGACSR_IRQ_N_O		0x00001000
419179337Syongari#define	GIGACSR_BIST_OK		0x00000200
420179337Syongari#define	GIGACSR_BIST_DONE	0x00000100
421179337Syongari#define	GIGACSR_BIST_LED_ENB	0x00000010
422179337Syongari#define	GIGACSR_BIST_MASK	0x00000003
423179337Syongari
424179337Syongari/* PHY Link Status. */
425179337Syongari#define	JME_LNKSTS		0x0430
426179337Syongari#define	LINKSTS_SPEED_10	0x00000000
427179337Syongari#define	LINKSTS_SPEED_100	0x00004000
428179337Syongari#define	LINKSTS_SPEED_1000	0x00008000
429179337Syongari#define	LINKSTS_FULL_DUPLEX	0x00002000
430179337Syongari#define	LINKSTS_PAGE_RCVD	0x00001000
431179337Syongari#define	LINKSTS_SPDDPX_RESOLVED	0x00000800
432179337Syongari#define	LINKSTS_UP		0x00000400
433179337Syongari#define	LINKSTS_ANEG_COMP	0x00000200
434179337Syongari#define	LINKSTS_MDI_CROSSOVR	0x00000040
435179337Syongari#define	LINKSTS_LPAR_PAUSE_ASYM	0x00000002
436179337Syongari#define	LINKSTS_LPAR_PAUSE	0x00000001
437179337Syongari
438179337Syongari/* SMB control and status. */
439179337Syongari#define	JME_SMBCSR		0x0440
440179337Syongari#define	SMBCSR_SLAVE_ADDR_MASK	0x7F000000
441179337Syongari#define	SMBCSR_WR_DATA_NACK	0x00040000
442179337Syongari#define	SMBCSR_CMD_NACK		0x00020000
443179337Syongari#define	SMBCSR_RELOAD		0x00010000
444179337Syongari#define	SMBCSR_CMD_ADDR_MASK	0x0000FF00
445179337Syongari#define	SMBCSR_SCL_STAT		0x00000080
446179337Syongari#define	SMBCSR_SDA_STAT		0x00000040
447179337Syongari#define	SMBCSR_EEPROM_PRESENT	0x00000020
448179337Syongari#define	SMBCSR_INIT_LD_DONE	0x00000010
449179337Syongari#define	SMBCSR_HW_BUSY_MASK	0x0000000F
450179337Syongari#define	SMBCSR_HW_IDLE		0x00000000
451179337Syongari
452179337Syongari/* SMB interface. */
453179337Syongari#define	JME_SMBINTF		0x0444
454179337Syongari#define	SMBINTF_RD_DATA_MASK	0xFF000000
455179337Syongari#define	SMBINTF_RD_DATA_SHIFT	24
456179337Syongari#define	SMBINTF_WR_DATA_MASK	0x00FF0000
457179337Syongari#define	SMBINTF_WR_DATA_SHIFT	16
458179337Syongari#define	SMBINTF_ADDR_MASK	0x0000FF00
459179337Syongari#define	SMBINTF_ADDR_SHIFT	8
460179337Syongari#define	SMBINTF_RD		0x00000020
461179337Syongari#define	SMBINTF_WR		0x00000000
462179337Syongari#define	SMBINTF_CMD_TRIGGER	0x00000010
463179337Syongari#define	SMBINTF_BUSY		0x00000010
464179337Syongari#define	SMBINTF_FAST_MODE	0x00000008
465179337Syongari#define	SMBINTF_GPIO_SCL	0x00000004
466179337Syongari#define	SMBINTF_GPIO_SDA	0x00000002
467179337Syongari#define	SMBINTF_GPIO_ENB	0x00000001
468179337Syongari
469179337Syongari#define	JME_EEPROM_SIG0		0x55
470179337Syongari#define	JME_EEPROM_SIG1		0xAA
471179337Syongari#define	JME_EEPROM_DESC_BYTES	3
472179337Syongari#define	JME_EEPROM_DESC_END	0x80
473179337Syongari#define	JME_EEPROM_FUNC_MASK	0x70
474179337Syongari#define	JME_EEPROM_FUNC_SHIFT	4
475179337Syongari#define	JME_EEPROM_PAGE_MASK	0x0F
476179337Syongari#define	JME_EEPROM_PAGE_SHIFT	0
477179337Syongari
478179337Syongari#define	JME_EEPROM_FUNC0	0
479179337Syongari/* PCI configuration space. */
480179337Syongari#define	JME_EEPROM_PAGE_BAR0	0
481179337Syongari/* 128 bytes I/O window. */
482179337Syongari#define	JME_EEPROM_PAGE_BAR1	1
483179337Syongari/* 256 bytes I/O window. */
484179337Syongari#define	JME_EEPROM_PAGE_BAR2	2
485179337Syongari
486179337Syongari#define	JME_EEPROM_END		0xFF
487179337Syongari
488179337Syongari#define	JME_EEPROM_MKDESC(f, p)						\
489179337Syongari	((((f) & JME_EEPROM_FUNC_MASK) << JME_EEPROM_FUNC_SHIFT) |	\
490179337Syongari	(((p) & JME_EEPROM_PAGE_MASK) << JME_EEPROM_PAGE_SHIFT))
491179337Syongari
492179337Syongari/* 3-wire EEPROM interface. Obsolete interface, use SMBCSR. */
493179337Syongari#define	JME_EEPINTF		0x0448
494179337Syongari#define	EEPINTF_DATA_MASK	0xFFFF0000
495179337Syongari#define	EEPINTF_DATA_SHIFT	16
496179337Syongari#define	EEPINTF_ADDR_MASK	0x0000FC00
497179337Syongari#define	EEPINTF_ADDR_SHIFT	10
498179337Syongari#define	EEPRINTF_OP_MASK	0x00000300
499179337Syongari#define	EEPINTF_OP_EXECUTE	0x00000080
500179337Syongari#define	EEPINTF_DATA_OUT	0x00000008
501179337Syongari#define	EEPINTF_DATA_IN		0x00000004
502179337Syongari#define	EEPINTF_CLK		0x00000002
503179337Syongari#define	EEPINTF_SEL		0x00000001
504179337Syongari
505179337Syongari/* 3-wire EEPROM control and status. Obsolete interface, use SMBCSR. */
506179337Syongari#define	JME_EEPCSR		0x044C
507179337Syongari#define	EEPCSR_EEPROM_RELOAD	0x00000002
508179337Syongari#define	EEPCSR_EEPROM_PRESENT	0x00000001
509179337Syongari
510179337Syongari/* Misc registers. */
511179337Syongari#define	JME_MISC_BASE_ADDR	0x800
512179337Syongari
513179337Syongari/* Timer control and status. */
514179337Syongari#define	JME_TMCSR		0x0800
515179337Syongari#define	TMCSR_SW_INTR		0x80000000
516179337Syongari#define	TMCSR_TIMER_INTR	0x10000000
517179337Syongari#define	TMCSR_TIMER_ENB		0x01000000
518179337Syongari#define	TMCSR_TIMER_COUNT_MASK	0x00FFFFFF
519179337Syongari
520179337Syongari/* GPIO control and status. */
521179337Syongari#define	JME_GPIO		0x0804
522179337Syongari#define	GPIO_4_SPI_IN		0x80000000
523179337Syongari#define	GPIO_3_SPI_IN		0x40000000
524179337Syongari#define	GPIO_4_SPI_OUT		0x20000000
525179337Syongari#define	GPIO_4_SPI_OUT_ENB	0x10000000
526179337Syongari#define	GPIO_3_SPI_OUT		0x08000000
527179337Syongari#define	GPIO_3_SPI_OUT_ENB	0x04000000
528179337Syongari#define	GPIO_3_4_LED		0x00000000
529179337Syongari#define	GPIO_3_4_GPIO		0x02000000
530179337Syongari#define	GPIO_2_CLKREQN_IN	0x00100000
531179337Syongari#define	GPIO_2_CLKREQN_OUT	0x00040000
532179337Syongari#define	GPIO_2_CLKREQN_OUT_ENB	0x00020000
533179337Syongari#define	GPIO_1_LED42_IN		0x00001000
534179337Syongari#define	GPIO_1_LED42_OUT	0x00000400
535179337Syongari#define	GPIO_1_LED42_OUT_ENB	0x00000200
536179337Syongari#define	GPIO_1_LED42_ENB	0x00000100
537179337Syongari#define	GPIO_0_SDA_IN		0x00000010
538179337Syongari#define	GPIO_0_SDA_OUT		0x00000004
539179337Syongari#define	GPIO_0_SDA_OUT_ENB	0x00000002
540179337Syongari#define	GPIO_0_SDA_ENB		0x00000001
541179337Syongari
542179337Syongari/* General purpose register 0. */
543179337Syongari#define	JME_GPREG0		0x0808
544179337Syongari#define	GPREG0_SH_POST_DW7_DIS	0x80000000
545179337Syongari#define	GPREG0_SH_POST_DW6_DIS	0x40000000
546179337Syongari#define	GPREG0_SH_POST_DW5_DIS	0x20000000
547179337Syongari#define	GPREG0_SH_POST_DW4_DIS	0x10000000
548179337Syongari#define	GPREG0_SH_POST_DW3_DIS	0x08000000
549179337Syongari#define	GPREG0_SH_POST_DW2_DIS	0x04000000
550179337Syongari#define	GPREG0_SH_POST_DW1_DIS	0x02000000
551179337Syongari#define	GPREG0_SH_POST_DW0_DIS	0x01000000
552179337Syongari#define	GPREG0_DMA_RD_REQ_8	0x00000000
553179337Syongari#define	GPREG0_DMA_RD_REQ_6	0x00100000
554179337Syongari#define	GPREG0_DMA_RD_REQ_5	0x00200000
555179337Syongari#define	GPREG0_DMA_RD_REQ_4	0x00300000
556179337Syongari#define	GPREG0_POST_DW0_ENB	0x00040000
557179337Syongari#define	GPREG0_PCC_CLR_DIS	0x00020000
558179337Syongari#define	GPREG0_FORCE_SCL_OUT	0x00010000
559179337Syongari#define	GPREG0_DL_RSTB_DIS	0x00008000
560179337Syongari#define	GPREG0_STICKY_RESET	0x00004000
561179337Syongari#define	GPREG0_DL_RSTB_CFG_DIS	0x00002000
562179337Syongari#define	GPREG0_LINK_CHG_POLL	0x00001000
563179337Syongari#define	GPREG0_LINK_CHG_DIRECT	0x00000000
564179337Syongari#define	GPREG0_MSI_GEN_SEL	0x00000800
565179337Syongari#define	GPREG0_SMB_PAD_PU_DIS	0x00000400
566179337Syongari#define	GPREG0_PCC_UNIT_16US	0x00000000
567179337Syongari#define	GPREG0_PCC_UNIT_256US	0x00000100
568179337Syongari#define	GPREG0_PCC_UNIT_US	0x00000200
569179337Syongari#define	GPREG0_PCC_UNIT_MS	0x00000300
570179337Syongari#define	GPREG0_PCC_UNIT_MASK	0x00000300
571179337Syongari#define	GPREG0_INTR_EVENT_ENB	0x00000080
572179337Syongari#define	GPREG0_PME_ENB		0x00000020
573179337Syongari#define	GPREG0_PHY_ADDR_MASK	0x0000001F
574179337Syongari#define	GPREG0_PHY_ADDR_SHIFT	0
575179337Syongari#define	GPREG0_PHY_ADDR		1
576179337Syongari
577179337Syongari/* General purpose register 1. reserved for future use. */
578179337Syongari#define	JME_GPREG1		0x080C
579179337Syongari
580179337Syongari/* MSIX entry number of interrupt source. */
581179337Syongari#define	JME_MSINUM_BASE		0x0810
582179337Syongari#define	JME_MSINUM_END		0x081F
583179337Syongari#define	MSINUM_MASK		0x7FFFFFFF
584179337Syongari#define	MSINUM_ENTRY_MASK	7
585179337Syongari#define	MSINUM_REG_INDEX(x)	((x) / 8)
586179337Syongari#define	MSINUM_INTR_SOURCE(x, y)	\
587179337Syongari	(((x) & MSINUM_ENTRY_MASK) << (((y) & 7) * 4))
588179337Syongari#define	MSINUM_NUM_INTR_SOURCE	32
589179337Syongari
590179337Syongari/* Interrupt event status. */
591179337Syongari#define	JME_INTR_STATUS		0x0820
592179337Syongari#define	INTR_SW			0x80000000
593179337Syongari#define	INTR_TIMER		0x40000000
594179337Syongari#define	INTR_LINKCHG		0x20000000
595179337Syongari#define	INTR_PAUSE		0x10000000
596179337Syongari#define	INTR_MAGIC_PKT		0x08000000
597179337Syongari#define	INTR_WAKEUP_PKT		0x04000000
598179337Syongari#define	INTR_RXQ0_COAL_TO	0x02000000
599179337Syongari#define	INTR_RXQ1_COAL_TO	0x01000000
600179337Syongari#define	INTR_RXQ2_COAL_TO	0x00800000
601179337Syongari#define	INTR_RXQ3_COAL_TO	0x00400000
602179337Syongari#define	INTR_TXQ_COAL_TO	0x00200000
603179337Syongari#define	INTR_RXQ0_COAL		0x00100000
604179337Syongari#define	INTR_RXQ1_COAL		0x00080000
605179337Syongari#define	INTR_RXQ2_COAL		0x00040000
606179337Syongari#define	INTR_RXQ3_COAL		0x00020000
607179337Syongari#define	INTR_TXQ_COAL		0x00010000
608179337Syongari#define	INTR_RXQ3_DESC_EMPTY	0x00008000
609179337Syongari#define	INTR_RXQ2_DESC_EMPTY	0x00004000
610179337Syongari#define	INTR_RXQ1_DESC_EMPTY	0x00002000
611179337Syongari#define	INTR_RXQ0_DESC_EMPTY	0x00001000
612179337Syongari#define	INTR_RXQ3_COMP		0x00000800
613179337Syongari#define	INTR_RXQ2_COMP		0x00000400
614179337Syongari#define	INTR_RXQ1_COMP		0x00000200
615179337Syongari#define	INTR_RXQ0_COMP		0x00000100
616179337Syongari#define	INTR_TXQ7_COMP		0x00000080
617179337Syongari#define	INTR_TXQ6_COMP		0x00000040
618179337Syongari#define	INTR_TXQ5_COMP		0x00000020
619179337Syongari#define	INTR_TXQ4_COMP		0x00000010
620179337Syongari#define	INTR_TXQ3_COMP		0x00000008
621179337Syongari#define	INTR_TXQ2_COMP		0x00000004
622179337Syongari#define	INTR_TXQ1_COMP		0x00000002
623179337Syongari#define	INTR_TXQ0_COMP		0x00000001
624179337Syongari
625179337Syongari#define	INTR_RXQ_COAL_TO					\
626179337Syongari	(INTR_RXQ0_COAL_TO | INTR_RXQ1_COAL_TO |		\
627179337Syongari	 INTR_RXQ2_COAL_TO | INTR_RXQ3_COAL_TO)
628179337Syongari
629179337Syongari#define	INTR_RXQ_COAL						\
630179337Syongari	(INTR_RXQ0_COAL | INTR_RXQ1_COAL | INTR_RXQ2_COAL |	\
631179337Syongari	 INTR_RXQ3_COAL)
632179337Syongari
633179337Syongari#define	INTR_RXQ_COMP						\
634179337Syongari	(INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP |	\
635179337Syongari	 INTR_RXQ3_COMP)
636179337Syongari
637179337Syongari#define	INTR_RXQ_DESC_EMPTY					\
638179337Syongari	(INTR_RXQ0_DESC_EMPTY | INTR_RXQ1_DESC_EMPTY |		\
639179337Syongari	INTR_RXQ2_DESC_EMPTY | INTR_RXQ3_DESC_EMPTY)
640179337Syongari
641179337Syongari#define	INTR_RXQ_COMP						\
642179337Syongari	(INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP |	\
643179337Syongari	INTR_RXQ3_COMP)
644179337Syongari
645179337Syongari#define	INTR_TXQ_COMP						\
646179337Syongari	(INTR_TXQ0_COMP | INTR_TXQ1_COMP | INTR_TXQ2_COMP |	\
647179337Syongari	INTR_TXQ3_COMP | INTR_TXQ4_COMP | INTR_TXQ5_COMP | 	\
648179337Syongari	INTR_TXQ6_COMP | INTR_TXQ7_COMP)
649179337Syongari
650179337Syongari#define	JME_INTRS						\
651179337Syongari	(INTR_RXQ_COAL_TO | INTR_TXQ_COAL_TO | INTR_RXQ_COAL |	\
652179337Syongari	 INTR_TXQ_COAL | INTR_RXQ_DESC_EMPTY)
653179337Syongari
654179337Syongari#define	N_INTR_SW		31
655179337Syongari#define	N_INTR_TIMER		30
656179337Syongari#define	N_INTR_LINKCHG		29
657179337Syongari#define	N_INTR_PAUSE		28
658179337Syongari#define	N_INTR_MAGIC_PKT	27
659179337Syongari#define	N_INTR_WAKEUP_PKT	26
660179337Syongari#define	N_INTR_RXQ0_COAL_TO	25
661179337Syongari#define	N_INTR_RXQ1_COAL_TO	24
662179337Syongari#define	N_INTR_RXQ2_COAL_TO	23
663179337Syongari#define	N_INTR_RXQ3_COAL_TO	22
664179337Syongari#define	N_INTR_TXQ_COAL_TO	21
665179337Syongari#define	N_INTR_RXQ0_COAL	20
666179337Syongari#define	N_INTR_RXQ1_COAL	19
667179337Syongari#define	N_INTR_RXQ2_COAL	18
668179337Syongari#define	N_INTR_RXQ3_COAL	17
669179337Syongari#define	N_INTR_TXQ_COAL		16
670179337Syongari#define	N_INTR_RXQ3_DESC_EMPTY	15
671179337Syongari#define	N_INTR_RXQ2_DESC_EMPTY	14
672179337Syongari#define	N_INTR_RXQ1_DESC_EMPTY	13
673179337Syongari#define	N_INTR_RXQ0_DESC_EMPTY	12
674179337Syongari#define	N_INTR_RXQ3_COMP	11
675179337Syongari#define	N_INTR_RXQ2_COMP	10
676179337Syongari#define	N_INTR_RXQ1_COMP	9
677179337Syongari#define	N_INTR_RXQ0_COMP	8
678179337Syongari#define	N_INTR_TXQ7_COMP	7
679179337Syongari#define	N_INTR_TXQ6_COMP	6
680179337Syongari#define	N_INTR_TXQ5_COMP	5
681179337Syongari#define	N_INTR_TXQ4_COMP	4
682179337Syongari#define	N_INTR_TXQ3_COMP	3
683179337Syongari#define	N_INTR_TXQ2_COMP	2
684179337Syongari#define	N_INTR_TXQ1_COMP	1
685179337Syongari#define	N_INTR_TXQ0_COMP	0
686179337Syongari
687179337Syongari/* Interrupt request status. */
688179337Syongari#define	JME_INTR_REQ_STATUS	0x0824
689179337Syongari
690179337Syongari/* Interrupt enable - setting port. */
691179337Syongari#define	JME_INTR_MASK_SET	0x0828
692179337Syongari
693179337Syongari/* Interrupt enable - clearing port. */
694179337Syongari#define	JME_INTR_MASK_CLR	0x082C
695179337Syongari
696179337Syongari/* Packet completion coalescing control of Rx queue 0, 1, 2 and 3. */
697179337Syongari#define	JME_PCCRX0		0x0830
698179337Syongari#define	JME_PCCRX1		0x0834
699179337Syongari#define	JME_PCCRX2		0x0838
700179337Syongari#define	JME_PCCRX3		0x083C
701179337Syongari#define	PCCRX_COAL_TO_MASK	0xFFFF0000
702179337Syongari#define	PCCRX_COAL_TO_SHIFT	16
703179337Syongari#define	PCCRX_COAL_PKT_MASK	0x0000FF00
704179337Syongari#define	PCCRX_COAL_PKT_SHIFT	8
705179337Syongari
706179337Syongari#define	PCCRX_COAL_TO_MIN	1
707179337Syongari#define	PCCRX_COAL_TO_DEFAULT	100
708179337Syongari#define	PCCRX_COAL_TO_MAX	65535
709179337Syongari
710179337Syongari#define	PCCRX_COAL_PKT_MIN	1
711179337Syongari#define	PCCRX_COAL_PKT_DEFAULT	2
712179337Syongari#define	PCCRX_COAL_PKT_MAX	255
713179337Syongari
714179337Syongari/* Packet completion coalescing control of Tx queue. */
715179337Syongari#define	JME_PCCTX		0x0840
716179337Syongari#define	PCCTX_COAL_TO_MASK	0xFFFF0000
717179337Syongari#define	PCCTX_COAL_TO_SHIFT	16
718179337Syongari#define	PCCTX_COAL_PKT_MASK	0x0000FF00
719179337Syongari#define	PCCTX_COAL_PKT_SHIFT	8
720179337Syongari#define	PCCTX_COAL_TXQ7		0x00000080
721179337Syongari#define	PCCTX_COAL_TXQ6		0x00000040
722179337Syongari#define	PCCTX_COAL_TXQ5		0x00000020
723179337Syongari#define	PCCTX_COAL_TXQ4		0x00000010
724179337Syongari#define	PCCTX_COAL_TXQ3		0x00000008
725179337Syongari#define	PCCTX_COAL_TXQ2		0x00000004
726179337Syongari#define	PCCTX_COAL_TXQ1		0x00000002
727179337Syongari#define	PCCTX_COAL_TXQ0		0x00000001
728179337Syongari
729179337Syongari#define	PCCTX_COAL_TO_MIN	1
730179337Syongari#define	PCCTX_COAL_TO_DEFAULT	100
731179337Syongari#define	PCCTX_COAL_TO_MAX	65535
732179337Syongari
733179337Syongari#define	PCCTX_COAL_PKT_MIN	1
734179337Syongari#define	PCCTX_COAL_PKT_DEFAULT	8
735179337Syongari#define	PCCTX_COAL_PKT_MAX	255
736179337Syongari
737179337Syongari/* Chip mode and FPGA version. */
738179337Syongari#define	JME_CHIPMODE		0x0844
739179337Syongari#define	CHIPMODE_FPGA_REV_MASK	0xFFFF0000
740179337Syongari#define	CHIPMODE_FPGA_REV_SHIFT	16
741179337Syongari#define	CHIPMODE_NOT_FPGA	0
742179337Syongari#define	CHIPMODE_REV_MASK	0x0000FF00
743179337Syongari#define	CHIPMODE_REV_SHIFT	8
744179337Syongari#define	CHIPMODE_MODE_48P	0x0000000C
745179337Syongari#define	CHIPMODE_MODE_64P	0x00000004
746179337Syongari#define	CHIPMODE_MODE_128P_MAC	0x00000003
747179337Syongari#define	CHIPMODE_MODE_128P_DBG	0x00000002
748179337Syongari#define	CHIPMODE_MODE_128P_PHY	0x00000000
749179337Syongari
750179337Syongari/* Shadow status base address high/low. */
751179337Syongari#define	JME_SHBASE_ADDR_HI	0x0848
752179337Syongari#define	JME_SHBASE_ADDR_LO	0x084C
753179337Syongari#define	SHBASE_ADDR_LO_MASK	0xFFFFFFE0
754179337Syongari#define	SHBASE_POST_FORCE	0x00000002
755179337Syongari#define	SHBASE_POST_ENB		0x00000001
756179337Syongari
757179337Syongari/* Timer 1 and 2. */
758179337Syongari#define	JME_TIMER1		0x0870
759179337Syongari#define	JME_TIMER2		0x0874
760179337Syongari#define	TIMER_ENB		0x01000000
761179337Syongari#define	TIMER_CNT_MASK		0x00FFFFFF
762179337Syongari#define	TIMER_CNT_SHIFT		0
763179337Syongari#define	TIMER_UNIT		1024	/* 1024us */
764179337Syongari
765179337Syongari/* Aggresive power mode control. */
766179337Syongari#define	JME_APMC		0x087C
767179337Syongari#define	APMC_PCIE_SDOWN_STAT	0x80000000
768179337Syongari#define	APMC_PCIE_SDOWN_ENB	0x40000000
769179337Syongari#define	APMC_PSEUDO_HOT_PLUG	0x20000000
770179337Syongari#define	APMC_EXT_PLUGIN_ENB	0x04000000
771179337Syongari#define	APMC_EXT_PLUGIN_CTL_MSK	0x03000000
772179337Syongari#define	APMC_DIS_SRAM		0x00000004
773179337Syongari#define	APMC_DIS_CLKPM		0x00000002
774179337Syongari#define	APMC_DIS_CLKTX		0x00000001
775179337Syongari
776179337Syongari/* Packet completion coalesing status of Rx queue 0, 1, 2 and 3. */
777179337Syongari#define	JME_PCCSRX_BASE		0x0880
778179337Syongari#define	JME_PCCSRX_END		0x088F
779179337Syongari#define	PCCSRX_REG(x)		(JME_PCCSRX_BASE + ((x) * 4))
780179337Syongari#define	PCCSRX_TO_MASK		0xFFFF0000
781179337Syongari#define	PCCSRX_TO_SHIFT		16
782179337Syongari#define	PCCSRX_PKT_CNT_MASK	0x0000FF00
783179337Syongari#define	PCCSRX_PKT_CNT_SHIFT	8
784179337Syongari
785179337Syongari/* Packet completion coalesing status of Tx queue. */
786179337Syongari#define	JME_PCCSTX		0x0890
787179337Syongari#define	PCCSTX_TO_MASK		0xFFFF0000
788179337Syongari#define	PCCSTX_TO_SHIFT		16
789179337Syongari#define	PCCSTX_PKT_CNT_MASK	0x0000FF00
790179337Syongari#define	PCCSTX_PKT_CNT_SHIFT	8
791179337Syongari
792179337Syongari/* Tx queues empty indicator. */
793179337Syongari#define	JME_TXQEMPTY		0x0894
794179337Syongari#define	TXQEMPTY_TXQ7		0x00000080
795179337Syongari#define	TXQEMPTY_TXQ6		0x00000040
796179337Syongari#define	TXQEMPTY_TXQ5		0x00000020
797179337Syongari#define	TXQEMPTY_TXQ4		0x00000010
798179337Syongari#define	TXQEMPTY_TXQ3		0x00000008
799179337Syongari#define	TXQEMPTY_TXQ2		0x00000004
800179337Syongari#define	TXQEMPTY_TXQ1		0x00000002
801179337Syongari#define	TXQEMPTY_TXQ0		0x00000001
802179337Syongari#define	TXQEMPTY_N_TXQ(x, y)	((x) & (0x01 << (y)))
803179337Syongari
804179337Syongari/* RSS control registers. */
805179337Syongari#define	JME_RSS_BASE		0x0C00
806179337Syongari
807179337Syongari#define	JME_RSSC		0x0C00
808179337Syongari#define	RSSC_HASH_LEN_MASK	0x0000E000
809179337Syongari#define	RSSC_HASH_64_ENTRY	0x0000A000
810179337Syongari#define	RSSC_HASH_128_ENTRY	0x0000E000
811179337Syongari#define	RSSC_HASH_NONE		0x00001000
812179337Syongari#define	RSSC_HASH_IPV6		0x00000800
813179337Syongari#define	RSSC_HASH_IPV4		0x00000400
814179337Syongari#define	RSSC_HASH_IPV6_TCP	0x00000200
815179337Syongari#define	RSSC_HASH_IPV4_TCP	0x00000100
816179337Syongari#define	RSSC_NCPU_MASK		0x000000F8
817179337Syongari#define	RSSC_NCPU_SHIFT		3
818179337Syongari#define	RSSC_DIS_RSS		0x00000000
819179337Syongari#define	RSSC_2RXQ_ENB		0x00000001
820179337Syongari#define	RSSS_4RXQ_ENB		0x00000002
821179337Syongari
822179337Syongari/* CPU vector. */
823179337Syongari#define	JME_RSSCPU		0x0C04
824179337Syongari#define	RSSCPU_N_SEL(x)		((1 << (x))
825179337Syongari
826179337Syongari/* RSS Hash value. */
827179337Syongari#define	JME_RSSHASH		0x0C10
828179337Syongari
829179337Syongari#define	JME_RSSHASH_STAT	0x0C14
830179337Syongari
831179337Syongari#define	JME_RSS_RDATA0		0x0C18
832179337Syongari
833179337Syongari#define	JME_RSS_RDATA1		0x0C1C
834179337Syongari
835179337Syongari/* RSS secret key. */
836179337Syongari#define	JME_RSSKEY_BASE		0x0C40
837179337Syongari#define	JME_RSSKEY_LAST		0x0C64
838179337Syongari#define	JME_RSSKEY_END		0x0C67
839179337Syongari#define	HASHKEY_NBYTES		40
840179337Syongari#define	RSSKEY_REG(x)		(JME_RSSKEY_LAST - (4 * ((x) / 4)))
841179337Syongari#define	RSSKEY_VALUE(x, y)	((x) << (24 - 8 * ((y) % 4)))
842179337Syongari
843179337Syongari/* RSS indirection table entries. */
844179337Syongari#define	JME_RSSTBL_BASE		0x0C80
845179337Syongari#define	JME_RSSTBL_END		0x0CFF
846179337Syongari#define	RSSTBL_NENTRY		128
847179337Syongari#define	RSSTBL_REG(x)		(JME_RSSTBL_BASE + ((x) / 4))
848179337Syongari#define	RSSTBL_VALUE(x, y)	((x) << (8 * ((y) % 4)))
849179337Syongari
850179337Syongari/* MSI-X table. */
851179337Syongari#define	JME_MSIX_BASE_ADDR	0x2000
852179337Syongari
853179337Syongari#define	JME_MSIX_BASE		0x2000
854179337Syongari#define	JME_MSIX_END		0x207F
855179337Syongari#define	JME_MSIX_NENTRY		8
856179337Syongari#define	MSIX_REG(x)		(JME_MSIX_BASE + ((x) * 0x10))
857179337Syongari#define	MSIX_ADDR_HI_OFF	0x00
858179337Syongari#define	MSIX_ADDR_LO_OFF	0x04
859179337Syongari#define	MSIX_ADDR_LO_MASK	0xFFFFFFFC
860179337Syongari#define	MSIX_DATA_OFF		0x08
861179337Syongari#define	MSIX_VECTOR_OFF		0x0C
862179337Syongari#define	MSIX_VECTOR_RSVD	0x80000000
863179337Syongari#define	MSIX_VECTOR_DIS		0x00000001
864179337Syongari
865179337Syongari/* MSI-X PBA. */
866179337Syongari#define	JME_MSIX_PBA_BASE_ADDR	0x3000
867179337Syongari
868179337Syongari#define	JME_MSIX_PBA		0x3000
869179337Syongari#define	MSIX_PBA_RSVD_MASK	0xFFFFFF00
870179337Syongari#define	MSIX_PBA_RSVD_SHIFT	8
871179337Syongari#define	MSIX_PBA_PEND_MASK	0x000000FF
872179337Syongari#define	MSIX_PBA_PEND_SHIFT	0
873179337Syongari#define	MSIX_PBA_PEND_ENTRY7	0x00000080
874179337Syongari#define	MSIX_PBA_PEND_ENTRY6	0x00000040
875179337Syongari#define	MSIX_PBA_PEND_ENTRY5	0x00000020
876179337Syongari#define	MSIX_PBA_PEND_ENTRY4	0x00000010
877179337Syongari#define	MSIX_PBA_PEND_ENTRY3	0x00000008
878179337Syongari#define	MSIX_PBA_PEND_ENTRY2	0x00000004
879179337Syongari#define	MSIX_PBA_PEND_ENTRY1	0x00000002
880179337Syongari#define	MSIX_PBA_PEND_ENTRY0	0x00000001
881179337Syongari
882179337Syongari#define	JME_PHY_OUI		0x001B8C
883179337Syongari#define	JME_PHY_MODEL		0x21
884179337Syongari#define	JME_PHY_REV		0x01
885179337Syongari#define	JME_PHY_ADDR		1
886179337Syongari
887179337Syongari/* JMC250 shadow status block. */
888179337Syongaristruct jme_ssb {
889179337Syongari	uint32_t	dw0;
890179337Syongari	uint32_t	dw1;
891179337Syongari	uint32_t	dw2;
892179337Syongari	uint32_t	dw3;
893179337Syongari	uint32_t	dw4;
894179337Syongari	uint32_t	dw5;
895179337Syongari	uint32_t	dw6;
896179337Syongari	uint32_t	dw7;
897179337Syongari};
898179337Syongari
899179337Syongari/* JMC250 descriptor structures. */
900179337Syongaristruct jme_desc {
901179337Syongari	uint32_t	flags;
902179337Syongari	uint32_t	buflen;
903179337Syongari	uint32_t	addr_hi;
904179337Syongari	uint32_t	addr_lo;
905179337Syongari};
906179337Syongari
907179337Syongari#define	JME_TD_OWN		0x80000000
908179337Syongari#define	JME_TD_INTR		0x40000000
909179337Syongari#define	JME_TD_64BIT		0x20000000
910179337Syongari#define	JME_TD_TCPCSUM		0x10000000
911179337Syongari#define	JME_TD_UDPCSUM		0x08000000
912179337Syongari#define	JME_TD_IPCSUM		0x04000000
913179337Syongari#define	JME_TD_TSO		0x02000000
914179337Syongari#define	JME_TD_VLAN_TAG		0x01000000
915179337Syongari#define	JME_TD_VLAN_MASK	0x0000FFFF
916179337Syongari
917179337Syongari#define	JME_TD_MSS_MASK		0xFFFC0000
918179337Syongari#define	JME_TD_MSS_SHIFT	18
919179337Syongari#define	JME_TD_BUF_LEN_MASK	0x0000FFFF
920179337Syongari#define	JME_TD_BUF_LEN_SHIFT	0
921179337Syongari
922179337Syongari#define	JME_TD_FRAME_LEN_MASK	0x0000FFFF
923179337Syongari#define	JME_TD_FRAME_LEN_SHIFT	0
924179337Syongari
925179337Syongari/*
926179337Syongari * Only the first Tx descriptor of a packet is updated
927179337Syongari * after packet transmission.
928179337Syongari */
929179337Syongari#define	JME_TD_TMOUT		0x20000000
930179337Syongari#define	JME_TD_RETRY_EXP	0x10000000
931179337Syongari#define	JME_TD_COLLISION	0x08000000
932179337Syongari#define	JME_TD_UNDERRUN		0x04000000
933179337Syongari#define	JME_TD_EHDR_SIZE_MASK	0x000000FF
934179337Syongari#define	JME_TD_EHDR_SIZE_SHIFT	0
935179337Syongari
936179337Syongari#define	JME_TD_SEG_CNT_MASK	0xFFFF0000
937179337Syongari#define	JME_TD_SEG_CNT_SHIFT	16
938179337Syongari#define	JME_TD_RETRY_CNT_MASK	0x0000FFFF
939179337Syongari#define	JME_TD_RETRY_CNT_SHIFT	0
940179337Syongari
941179337Syongari#define	JME_RD_OWN		0x80000000
942179337Syongari#define	JME_RD_INTR		0x40000000
943179337Syongari#define	JME_RD_64BIT		0x20000000
944179337Syongari
945179337Syongari#define	JME_RD_BUF_LEN_MASK	0x0000FFFF
946179337Syongari#define	JME_RD_BUF_LEN_SHIFT	0
947179337Syongari
948179337Syongari/*
949179337Syongari * Only the first Rx descriptor of a packet is updated
950179337Syongari * after packet reception.
951179337Syongari */
952179337Syongari#define	JME_RD_MORE_FRAG	0x20000000
953179337Syongari#define	JME_RD_TCP		0x10000000
954179337Syongari#define	JME_RD_UDP		0x08000000
955179337Syongari#define	JME_RD_IPCSUM		0x04000000
956179337Syongari#define	JME_RD_TCPCSUM		0x02000000
957179337Syongari#define	JME_RD_UDPCSUM		0x01000000
958179337Syongari#define	JME_RD_VLAN_TAG		0x00800000
959179337Syongari#define	JME_RD_IPV4		0x00400000
960179337Syongari#define	JME_RD_IPV6		0x00200000
961179337Syongari#define	JME_RD_PAUSE		0x00100000
962179337Syongari#define	JME_RD_MAGIC		0x00080000
963179337Syongari#define	JME_RD_WAKEUP		0x00040000
964179337Syongari#define	JME_RD_BCAST		0x00030000
965179337Syongari#define	JME_RD_MCAST		0x00020000
966179337Syongari#define	JME_RD_UCAST		0x00010000
967179337Syongari#define	JME_RD_VLAN_MASK	0x0000FFFF
968179337Syongari#define	JME_RD_VLAN_SHIFT	0
969179337Syongari
970179337Syongari#define	JME_RD_VALID		0x80000000
971179337Syongari#define	JME_RD_CNT_MASK		0x7F000000
972179337Syongari#define	JME_RD_CNT_SHIFT	24
973179337Syongari#define	JME_RD_GIANT		0x00800000
974179337Syongari#define	JME_RD_GMII_ERR		0x00400000
975179337Syongari#define	JME_RD_NBL_RCVD		0x00200000
976179337Syongari#define	JME_RD_COLL		0x00100000
977179337Syongari#define	JME_RD_ABORT		0x00080000
978179337Syongari#define	JME_RD_RUNT		0x00040000
979179337Syongari#define	JME_RD_FIFO_OVRN	0x00020000
980179337Syongari#define	JME_RD_CRC_ERR		0x00010000
981179337Syongari#define	JME_RD_FRAME_LEN_MASK	0x0000FFFF
982179337Syongari
983179337Syongari#define	JME_RX_ERR_STAT						\
984179337Syongari	(JME_RD_GIANT | JME_RD_GMII_ERR | JME_RD_NBL_RCVD |	\
985179337Syongari	JME_RD_COLL | JME_RD_ABORT | JME_RD_RUNT |		\
986179337Syongari	JME_RD_FIFO_OVRN | JME_RD_CRC_ERR)
987179337Syongari
988179337Syongari#define	JME_RD_ERR_MASK		0x00FF0000
989179337Syongari#define	JME_RD_ERR_SHIFT	16
990179337Syongari#define	JME_RX_ERR(x)		(((x) & JME_RD_ERR_MASK) >> JME_RD_ERR_SHIFT)
991179337Syongari#define	JME_RX_ERR_BITS		"\20"					\
992179337Syongari				"\1CRCERR\2FIFOOVRN\3RUNT\4ABORT"	\
993179337Syongari				"\5COLL\6NBLRCVD\7GMIIERR\10"
994179337Syongari
995179337Syongari#define	JME_RX_NSEGS(x)		(((x) & JME_RD_CNT_MASK) >> JME_RD_CNT_SHIFT)
996179337Syongari#define	JME_RX_BYTES(x)		((x) & JME_RD_FRAME_LEN_MASK)
997179337Syongari#define	JME_RX_PAD_BYTES	10
998179337Syongari
999179337Syongari#define	JME_RD_RSS_HASH_VALUE	0xFFFFFFFF
1000179337Syongari
1001179337Syongari#define	JME_RD_RSS_HASH_MASK	0x00003F00
1002179337Syongari#define	JME_RD_RSS_HASH_SHIFT	8
1003179337Syongari#define	JME_RD_RSS_HASH_NONE	0x00000000
1004179337Syongari#define	JME_RD_RSS_HASH_IPV4	0x00000100
1005179337Syongari#define	JME_RD_RSS_HASH_IPV4TCP	0x00000200
1006179337Syongari#define	JME_RD_RSS_HASH_IPV6	0x00000400
1007179337Syongari#define	JME_RD_RSS_HASH_IPV6TCP	0x00001000
1008179337Syongari#define	JME_RD_HASH_FN_NONE	0x00000000
1009179337Syongari#define	JME_RD_HASH_FN_TOEPLITZ	0x00000001
1010179337Syongari
1011179337Syongari#endif
1012