1179337Syongari/*- 2179337Syongari * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3179337Syongari * All rights reserved. 4179337Syongari * 5179337Syongari * Redistribution and use in source and binary forms, with or without 6179337Syongari * modification, are permitted provided that the following conditions 7179337Syongari * are met: 8179337Syongari * 1. Redistributions of source code must retain the above copyright 9179337Syongari * notice unmodified, this list of conditions, and the following 10179337Syongari * disclaimer. 11179337Syongari * 2. Redistributions in binary form must reproduce the above copyright 12179337Syongari * notice, this list of conditions and the following disclaimer in the 13179337Syongari * documentation and/or other materials provided with the distribution. 14179337Syongari * 15179337Syongari * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16179337Syongari * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17179337Syongari * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18179337Syongari * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19179337Syongari * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20179337Syongari * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21179337Syongari * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22179337Syongari * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23179337Syongari * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24179337Syongari * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25179337Syongari * SUCH DAMAGE. 26179337Syongari * 27179337Syongari * $FreeBSD$ 28179337Syongari */ 29179337Syongari 30179337Syongari#ifndef _IF_JMEREG_H 31179337Syongari#define _IF_JMEREG_H 32179337Syongari 33179337Syongari/* 34179337Syongari * JMicron Inc. PCI vendor ID 35179337Syongari */ 36179337Syongari#define VENDORID_JMICRON 0x197B 37179337Syongari 38179337Syongari/* 39179337Syongari * JMC250 PCI device ID 40179337Syongari */ 41179337Syongari#define DEVICEID_JMC250 0x0250 42182888Syongari#define DEVICEREVID_JMC250_A0 0x00 43182888Syongari#define DEVICEREVID_JMC250_A2 0x11 44179337Syongari 45179337Syongari/* 46179337Syongari * JMC260 PCI device ID 47179337Syongari */ 48179337Syongari#define DEVICEID_JMC260 0x0260 49182888Syongari#define DEVICEREVID_JMC260_A0 0x00 50179337Syongari 51183814Syongari#define DEVICEID_JMC2XX_MASK 0x0FF0 52183814Syongari 53179337Syongari/* JMC250 PCI configuration register. */ 54179337Syongari#define JME_PCI_BAR0 0x10 /* 16KB memory window. */ 55179337Syongari 56179337Syongari#define JME_PCI_BAR1 0x18 /* 128bytes I/O window. */ 57179337Syongari 58179337Syongari#define JME_PCI_BAR2 0x1C /* 256bytes I/O window. */ 59179337Syongari 60179337Syongari#define JME_PCI_BAR3 0x20 /* 64KB memory window. */ 61179337Syongari 62179337Syongari#define JME_PCI_EROM 0x30 63179337Syongari 64179337Syongari#define JME_PCI_DBG 0x9C 65179337Syongari 66216551Syongari#define JME_PCI_PAR0 0xA4 /* JMC25x/JMC26x REVFM >= 5 */ 67216551Syongari 68216551Syongari#define JME_PCI_PAR1 0xA8 /* JMC25x/JMC26x REVFM >= 5 */ 69216551Syongari 70179337Syongari#define JME_PCI_SPI 0xB0 71179337Syongari 72179337Syongari#define SPI_ENB 0x00000010 73179337Syongari#define SPI_SO_STATUS 0x00000008 74179337Syongari#define SPI_SI_CTRL 0x00000004 75179337Syongari#define SPI_SCK_CTRL 0x00000002 76179337Syongari#define SPI_CS_N_CTRL 0x00000001 77179337Syongari 78216551Syongari#define JME_EFUSE_CTL1 0xB8 79216551Syongari#define EFUSE_CTL1_DATA_MASK 0xF0000000 80216551Syongari#define EFUSE_CTL1_EXECUTE 0x08000000 81216551Syongari#define EFUSE_CTL1_CMD_AUTOLOAD 0x02000000 82216551Syongari#define EFUSE_CTL1_CMD_READ 0x04000000 83216551Syongari#define EFUSE_CTL1_CMD_BLOW 0x06000000 84216551Syongari#define EFUSE_CTL1_CMD_MASK 0x06000000 85216551Syongari#define EFUSE_CTL1_AUTOLOAD_ERR 0x00010000 86216551Syongari#define EFUSE_CTL1_BYTE_SEL_MASK 0x0000FF00 87216551Syongari#define EFUSE_CTL1_BIT_SEL_MASK 0x00000070 88216551Syongari#define EFUSE_CTL1_AUTOLAOD_DONE 0x00000001 89216551Syongari 90216551Syongari#define JME_EFUSE_CTL2 0xBC 91216551Syongari#define EFUSE_CTL2_RESET 0x00008000 92216551Syongari 93179337Syongari#define JME_PCI_PHYCFG0 0xC0 94179337Syongari 95179337Syongari#define JME_PCI_PHYCFG1 0xC4 96179337Syongari 97179337Syongari#define JME_PCI_PHYCFG2 0xC8 98179337Syongari 99179337Syongari#define JME_PCI_PHYCFG3 0xCC 100179337Syongari 101179337Syongari#define JME_PCI_PIPECTL1 0xD0 102179337Syongari 103179337Syongari#define JME_PCI_PIPECTL2 0xD4 104179337Syongari 105179337Syongari/* PCIe link error/status. */ 106179337Syongari#define JME_PCI_LES 0xD8 107179337Syongari 108216551Syongari/* Proprietary register 0. */ 109179337Syongari#define JME_PCI_PE0 0xE0 110179337Syongari#define PE0_SPI_EXIST 0x00200000 111179337Syongari#define PE0_PME_D0 0x00100000 112179337Syongari#define PE0_PME_D3H 0x00080000 113179337Syongari#define PE0_PME_SPI_PAD 0x00040000 114179337Syongari#define PE0_MASK_ASPM 0x00020000 115179337Syongari#define PE0_EEPROM_RW_DIS 0x00008000 116179337Syongari#define PE0_PCI_INTA 0x00001000 117179337Syongari#define PE0_PCI_INTB 0x00002000 118179337Syongari#define PE0_PCI_INTC 0x00003000 119179337Syongari#define PE0_PCI_INTD 0x00004000 120179337Syongari#define PE0_PCI_SVSSID_WR_ENB 0x00000800 121179337Syongari#define PE0_MSIX_SIZE_8 0x00000700 122179337Syongari#define PE0_MSIX_SIZE_7 0x00000600 123179337Syongari#define PE0_MSIX_SIZE_6 0x00000500 124179337Syongari#define PE0_MSIX_SIZE_5 0x00000400 125179337Syongari#define PE0_MSIX_SIZE_4 0x00000300 126179337Syongari#define PE0_MSIX_SIZE_3 0x00000200 127179337Syongari#define PE0_MSIX_SIZE_2 0x00000100 128179337Syongari#define PE0_MSIX_SIZE_1 0x00000000 129179337Syongari#define PE0_MSIX_SIZE_DEF 0x00000700 130179337Syongari#define PE0_MSIX_CAP_DIS 0x00000080 131179337Syongari#define PE0_MSI_PVMC_ENB 0x00000040 132179337Syongari#define PE0_LCAP_EXIT_LAT_MASK 0x00000038 133179337Syongari#define PE0_LCAP_EXIT_LAT_DEF 0x00000038 134179337Syongari#define PE0_PM_AUXC_MASK 0x00000007 135179337Syongari#define PE0_PM_AUXC_DEF 0x00000007 136179337Syongari 137216551Syongari/* Proprietary register 1. */ 138179337Syongari#define JME_PCI_PE1 0xE4 139216551Syongari#define PE1_GIGA_PDOWN_MASK 0x0000C000 140216551Syongari#define PE1_GIGA_PDOWN_DIS 0x00000000 141216551Syongari#define PE1_GIGA_PDOWN_D3 0x00004000 142216551Syongari#define PE1_GIGA_PDOWN_PCIE_SHUTDOWN 0x00008000 143216551Syongari#define PE1_GIGA_PDOWN_PCIE_IDDQ 0x0000C000 144179337Syongari 145216551Syongari#define JME_EFUSE_EEPROM 0xE8 146216551Syongari#define JME_EFUSE_EEPROM_WRITE 0x80000000 147216551Syongari#define JME_EFUSE_EEPROM_FUNC_MASK 0x70000000 148216551Syongari#define JME_EFUSE_EEPROM_PAGE_MASK 0x0F000000 149216551Syongari#define JME_EFUSE_EEPROM_ADDR_MASK 0x00FF0000 150216551Syongari#define JME_EFUSE_EEPROM_DATA_MASK 0x0000FF00 151216551Syongari#define JME_EFUSE_EEPROM_SMBSTAT_MASK 0x000000FF 152216551Syongari#define JME_EFUSE_EEPROM_FUNC_SHIFT 28 153216551Syongari#define JME_EFUSE_EEPROM_PAGE_SHIFT 24 154216551Syongari#define JME_EFUSE_EEPROM_ADDR_SHIFT 16 155216551Syongari#define JME_EFUSE_EEPROM_DATA_SHIFT 8 156216551Syongari#define JME_EFUSE_EEPROM_SMBSTAT_SHIFT 0 157216551Syongari 158216551Syongari#define JME_EFUSE_EEPROM_FUNC0 0 159216551Syongari#define JME_EFUSE_EEPROM_PAGE_BAR0 0 160216551Syongari#define JME_EFUSE_EEPROM_PAGE_BAR1 1 161216551Syongari#define JME_EFUSE_EEPROM_PAGE_BAR2 2 162216551Syongari 163179337Syongari#define JME_PCI_PHYTEST 0xF8 164179337Syongari 165179337Syongari#define JME_PCI_GPR 0xFC 166179337Syongari 167179337Syongari/* 168179337Syongari * JMC Register Map. 169179337Syongari * ----------------------------------------------------------------------- 170179337Syongari * Register Size IO space Memory space 171179337Syongari * ----------------------------------------------------------------------- 172179337Syongari * Tx/Rx MAC registers 128 bytes BAR1 + 0x00 ~ BAR0 + 0x00 ~ 173179337Syongari * BAR1 + 0x7F BAR0 + 0x7F 174179337Syongari * ----------------------------------------------------------------------- 175179337Syongari * PHY registers 128 bytes BAR2 + 0x00 ~ BAR0 + 0x400 ~ 176179337Syongari * BAR2 + 0x7F BAR0 + 0x47F 177179337Syongari * ----------------------------------------------------------------------- 178179337Syongari * Misc registers 128 bytes BAR2 + 0x80 ~ BAR0 + 0x800 ~ 179179337Syongari * BAR2 + 0x7F BAR0 + 0x87F 180179337Syongari * ----------------------------------------------------------------------- 181179337Syongari * To simplify register access fuctions and to get better performance 182179337Syongari * this driver doesn't support IO space access. It could be implemented 183179337Syongari * as a function which selects appropriate BARs to access requested 184179337Syongari * register. 185179337Syongari */ 186179337Syongari 187179337Syongari/* Tx control and status. */ 188179337Syongari#define JME_TXCSR 0x0000 189179337Syongari#define TXCSR_QWEIGHT_MASK 0x0F000000 190179337Syongari#define TXCSR_QWEIGHT_SHIFT 24 191179337Syongari#define TXCSR_TXQ_SEL_MASK 0x00070000 192179337Syongari#define TXCSR_TXQ_SEL_SHIFT 16 193179337Syongari#define TXCSR_TXQ_START 0x00000001 194179337Syongari#define TXCSR_TXQ_START_SHIFT 8 195179337Syongari#define TXCSR_FIFO_THRESH_4QW 0x00000000 196179337Syongari#define TXCSR_FIFO_THRESH_8QW 0x00000040 197179337Syongari#define TXCSR_FIFO_THRESH_12QW 0x00000080 198179337Syongari#define TXCSR_FIFO_THRESH_16QW 0x000000C0 199179337Syongari#define TXCSR_DMA_SIZE_64 0x00000000 200179337Syongari#define TXCSR_DMA_SIZE_128 0x00000010 201179337Syongari#define TXCSR_DMA_SIZE_256 0x00000020 202179337Syongari#define TXCSR_DMA_SIZE_512 0x00000030 203179337Syongari#define TXCSR_DMA_BURST 0x00000004 204179337Syongari#define TXCSR_TX_SUSPEND 0x00000002 205179337Syongari#define TXCSR_TX_ENB 0x00000001 206179337Syongari#define TXCSR_TXQ0 0 207179337Syongari#define TXCSR_TXQ1 1 208179337Syongari#define TXCSR_TXQ2 2 209179337Syongari#define TXCSR_TXQ3 3 210179337Syongari#define TXCSR_TXQ4 4 211179337Syongari#define TXCSR_TXQ5 5 212179337Syongari#define TXCSR_TXQ6 6 213179337Syongari#define TXCSR_TXQ7 7 214179337Syongari#define TXCSR_TXQ_WEIGHT(x) \ 215179337Syongari (((x) << TXCSR_QWEIGHT_SHIFT) & TXCSR_QWEIGHT_MASK) 216179337Syongari#define TXCSR_TXQ_WEIGHT_MIN 0 217179337Syongari#define TXCSR_TXQ_WEIGHT_MAX 15 218179337Syongari#define TXCSR_TXQ_N_SEL(x) \ 219179337Syongari (((x) << TXCSR_TXQ_SEL_SHIFT) & TXCSR_TXQ_SEL_MASK) 220179337Syongari#define TXCSR_TXQ_N_START(x) \ 221179337Syongari (TXCSR_TXQ_START << (TXCSR_TXQ_START_SHIFT + (x))) 222179337Syongari 223179337Syongari/* Tx queue descriptor base address. 16bytes alignment required. */ 224179337Syongari#define JME_TXDBA_LO 0x0004 225179337Syongari#define JME_TXDBA_HI 0x0008 226179337Syongari 227179337Syongari/* Tx queue descriptor count. multiple of 16(max = 1024). */ 228179337Syongari#define JME_TXQDC 0x000C 229179337Syongari#define TXQDC_MASK 0x0000007F0 230179337Syongari 231179337Syongari/* Tx queue next descriptor address. */ 232179337Syongari#define JME_TXNDA 0x0010 233179337Syongari#define TXNDA_ADDR_MASK 0xFFFFFFF0 234179337Syongari#define TXNDA_DESC_EMPTY 0x00000008 235179337Syongari#define TXNDA_DESC_VALID 0x00000004 236179337Syongari#define TXNDA_DESC_WAIT 0x00000002 237179337Syongari#define TXNDA_DESC_FETCH 0x00000001 238179337Syongari 239179337Syongari/* Tx MAC control ans status. */ 240179337Syongari#define JME_TXMAC 0x0014 241179337Syongari#define TXMAC_IFG2_MASK 0xC0000000 242179337Syongari#define TXMAC_IFG2_DEFAULT 0x40000000 243179337Syongari#define TXMAC_IFG1_MASK 0x30000000 244179337Syongari#define TXMAC_IFG1_DEFAULT 0x20000000 245185597Syongari#define TXMAC_PAUSE_CNT_MASK 0x00FF0000 246179337Syongari#define TXMAC_THRESH_1_PKT 0x00000300 247179337Syongari#define TXMAC_THRESH_1_2_PKT 0x00000200 248179337Syongari#define TXMAC_THRESH_1_4_PKT 0x00000100 249179337Syongari#define TXMAC_THRESH_1_8_PKT 0x00000000 250179337Syongari#define TXMAC_FRAME_BURST 0x00000080 251179337Syongari#define TXMAC_CARRIER_EXT 0x00000040 252179337Syongari#define TXMAC_IFG_ENB 0x00000020 253179337Syongari#define TXMAC_BACKOFF 0x00000010 254179337Syongari#define TXMAC_CARRIER_SENSE 0x00000008 255179337Syongari#define TXMAC_COLL_ENB 0x00000004 256179337Syongari#define TXMAC_CRC_ENB 0x00000002 257179337Syongari#define TXMAC_PAD_ENB 0x00000001 258179337Syongari 259179337Syongari/* Tx pause frame control. */ 260179337Syongari#define JME_TXPFC 0x0018 261179337Syongari#define TXPFC_VLAN_TAG_MASK 0xFFFF0000 262179337Syongari#define TXPFC_VLAN_TAG_SHIFT 16 263179337Syongari#define TXPFC_VLAN_ENB 0x00008000 264179337Syongari#define TXPFC_PAUSE_ENB 0x00000001 265179337Syongari 266179337Syongari/* Tx timer/retry at half duplex. */ 267179337Syongari#define JME_TXTRHD 0x001C 268179337Syongari#define TXTRHD_RT_PERIOD_ENB 0x80000000 269179337Syongari#define TXTRHD_RT_PERIOD_MASK 0x7FFFFF00 270179337Syongari#define TXTRHD_RT_PERIOD_SHIFT 8 271179337Syongari#define TXTRHD_RT_LIMIT_ENB 0x00000080 272179337Syongari#define TXTRHD_RT_LIMIT_MASK 0x0000007F 273179337Syongari#define TXTRHD_RT_LIMIT_SHIFT 0 274179337Syongari#define TXTRHD_RT_PERIOD_DEFAULT 8192 275179337Syongari#define TXTRHD_RT_LIMIT_DEFAULT 8 276179337Syongari 277179337Syongari/* Rx control & status. */ 278179337Syongari#define JME_RXCSR 0x0020 279179337Syongari#define RXCSR_FIFO_FTHRESH_16T 0x00000000 280179337Syongari#define RXCSR_FIFO_FTHRESH_32T 0x10000000 281179337Syongari#define RXCSR_FIFO_FTHRESH_64T 0x20000000 282179337Syongari#define RXCSR_FIFO_FTHRESH_128T 0x30000000 283179337Syongari#define RXCSR_FIFO_FTHRESH_MASK 0x30000000 284179337Syongari#define RXCSR_FIFO_THRESH_16QW 0x00000000 285179337Syongari#define RXCSR_FIFO_THRESH_32QW 0x04000000 286185596Syongari#define RXCSR_FIFO_THRESH_64QW 0x08000000 /* JMC250/JMC260 REVFM < 2 */ 287185596Syongari#define RXCSR_FIFO_THRESH_128QW 0x0C000000 /* JMC250/JMC260 REVFM < 2 */ 288179337Syongari#define RXCSR_FIFO_THRESH_MASK 0x0C000000 289179337Syongari#define RXCSR_DMA_SIZE_16 0x00000000 290179337Syongari#define RXCSR_DMA_SIZE_32 0x01000000 291179337Syongari#define RXCSR_DMA_SIZE_64 0x02000000 292179337Syongari#define RXCSR_DMA_SIZE_128 0x03000000 293179337Syongari#define RXCSR_RXQ_SEL_MASK 0x00030000 294179337Syongari#define RXCSR_RXQ_SEL_SHIFT 16 295179337Syongari#define RXCSR_DESC_RT_GAP_MASK 0x0000F000 296179337Syongari#define RXCSR_DESC_RT_GAP_SHIFT 12 297179337Syongari#define RXCSR_DESC_RT_GAP_256 0x00000000 298179337Syongari#define RXCSR_DESC_RT_GAP_512 0x00001000 299179337Syongari#define RXCSR_DESC_RT_GAP_1024 0x00002000 300179337Syongari#define RXCSR_DESC_RT_GAP_2048 0x00003000 301179337Syongari#define RXCSR_DESC_RT_GAP_4096 0x00004000 302179337Syongari#define RXCSR_DESC_RT_GAP_8192 0x00005000 303179337Syongari#define RXCSR_DESC_RT_GAP_16384 0x00006000 304179337Syongari#define RXCSR_DESC_RT_GAP_32768 0x00007000 305179337Syongari#define RXCSR_DESC_RT_CNT_MASK 0x00000F00 306179337Syongari#define RXCSR_DESC_RT_CNT_SHIFT 8 307179337Syongari#define RXCSR_PASS_WAKEUP_PKT 0x00000040 308179337Syongari#define RXCSR_PASS_MAGIC_PKT 0x00000020 309179337Syongari#define RXCSR_PASS_RUNT_PKT 0x00000010 310179337Syongari#define RXCSR_PASS_BAD_PKT 0x00000008 311179337Syongari#define RXCSR_RXQ_START 0x00000004 312179337Syongari#define RXCSR_RX_SUSPEND 0x00000002 313179337Syongari#define RXCSR_RX_ENB 0x00000001 314179337Syongari 315179337Syongari#define RXCSR_RXQ_N_SEL(x) ((x) << RXCSR_RXQ_SEL_SHIFT) 316179337Syongari#define RXCSR_RXQ0 0 317179337Syongari#define RXCSR_RXQ1 1 318179337Syongari#define RXCSR_RXQ2 2 319179337Syongari#define RXCSR_RXQ3 3 320179337Syongari#define RXCSR_DESC_RT_CNT(x) \ 321215847Syongari (((x) << RXCSR_DESC_RT_CNT_SHIFT) & RXCSR_DESC_RT_CNT_MASK) 322215847Syongari#define RXCSR_DESC_RT_CNT_DEFAULT 0 323179337Syongari 324179337Syongari/* Rx queue descriptor base address. 16bytes alignment needed. */ 325179337Syongari#define JME_RXDBA_LO 0x0024 326179337Syongari#define JME_RXDBA_HI 0x0028 327179337Syongari 328179337Syongari/* Rx queue descriptor count. multiple of 16(max = 1024). */ 329179337Syongari#define JME_RXQDC 0x002C 330179337Syongari#define RXQDC_MASK 0x0000007F0 331179337Syongari 332179337Syongari/* Rx queue next descriptor address. */ 333179337Syongari#define JME_RXNDA 0x0030 334179337Syongari#define RXNDA_ADDR_MASK 0xFFFFFFF0 335179337Syongari#define RXNDA_DESC_EMPTY 0x00000008 336179337Syongari#define RXNDA_DESC_VALID 0x00000004 337179337Syongari#define RXNDA_DESC_WAIT 0x00000002 338179337Syongari#define RXNDA_DESC_FETCH 0x00000001 339179337Syongari 340179337Syongari/* Rx MAC control and status. */ 341179337Syongari#define JME_RXMAC 0x0034 342179337Syongari#define RXMAC_RSS_UNICAST 0x00000000 343179337Syongari#define RXMAC_RSS_UNI_MULTICAST 0x00010000 344179337Syongari#define RXMAC_RSS_UNI_MULTI_BROADCAST 0x00020000 345179337Syongari#define RXMAC_RSS_ALLFRAME 0x00030000 346179337Syongari#define RXMAC_PROMISC 0x00000800 347179337Syongari#define RXMAC_BROADCAST 0x00000400 348179337Syongari#define RXMAC_MULTICAST 0x00000200 349179337Syongari#define RXMAC_UNICAST 0x00000100 350179337Syongari#define RXMAC_ALLMULTI 0x00000080 351179337Syongari#define RXMAC_MULTICAST_FILTER 0x00000040 352179337Syongari#define RXMAC_COLL_DET_ENB 0x00000020 353179337Syongari#define RXMAC_FC_ENB 0x00000008 354179337Syongari#define RXMAC_VLAN_ENB 0x00000004 355179337Syongari#define RXMAC_PAD_10BYTES 0x00000002 356179337Syongari#define RXMAC_CSUM_ENB 0x00000001 357179337Syongari 358216551Syongari/* Rx unicast MAC address. Read-only on JMC25x/JMC26x REVFM >= 5 */ 359179337Syongari#define JME_PAR0 0x0038 360179337Syongari#define JME_PAR1 0x003C 361179337Syongari 362179337Syongari/* Rx multicast address hash table. */ 363179337Syongari#define JME_MAR0 0x0040 364179337Syongari#define JME_MAR1 0x0044 365179337Syongari 366179337Syongari/* Wakeup frame output data port. */ 367179337Syongari#define JME_WFODP 0x0048 368179337Syongari 369179337Syongari/* Wakeup frame output interface. */ 370179337Syongari#define JME_WFOI 0x004C 371179337Syongari#define WFOI_MASK_0_31 0x00000000 372179337Syongari#define WFOI_MASK_31_63 0x00000010 373179337Syongari#define WFOI_MASK_64_95 0x00000020 374179337Syongari#define WFOI_MASK_96_127 0x00000030 375179337Syongari#define WFOI_MASK_SEL 0x00000008 376179337Syongari#define WFOI_CRC_SEL 0x00000000 377179337Syongari#define WFOI_WAKEUP_FRAME_MASK 0x00000007 378179337Syongari#define WFOI_WAKEUP_FRAME_SEL(x) ((x) & WFOI_WAKEUP_FRAME_MASK) 379179337Syongari 380179337Syongari/* Station management interface. */ 381179337Syongari#define JME_SMI 0x0050 382179337Syongari#define SMI_DATA_MASK 0xFFFF0000 383179337Syongari#define SMI_DATA_SHIFT 16 384179337Syongari#define SMI_REG_ADDR_MASK 0x0000F800 385179337Syongari#define SMI_REG_ADDR_SHIFT 11 386179337Syongari#define SMI_PHY_ADDR_MASK 0x000007C0 387179337Syongari#define SMI_PHY_ADDR_SHIFT 6 388179337Syongari#define SMI_OP_WRITE 0x00000020 389179337Syongari#define SMI_OP_READ 0x00000000 390179337Syongari#define SMI_OP_EXECUTE 0x00000010 391179337Syongari#define SMI_MDIO 0x00000008 392179337Syongari#define SMI_MDOE 0x00000004 393179337Syongari#define SMI_MDC 0x00000002 394179337Syongari#define SMI_MDEN 0x00000001 395179337Syongari#define SMI_REG_ADDR(x) \ 396179337Syongari (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK) 397179337Syongari#define SMI_PHY_ADDR(x) \ 398179337Syongari (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK) 399179337Syongari 400179337Syongari/* Global host control. */ 401179337Syongari#define JME_GHC 0x0054 402179337Syongari#define GHC_LOOPBACK 0x80000000 403179337Syongari#define GHC_RESET 0x40000000 404185596Syongari#define GHC_RX_DMA_PWR_DIS 0x04000000 /* JMC250 REVFM >= 2 */ 405185596Syongari#define GHC_FIFO_RD_PWR_DIS 0x02000000 /* JMC250 REVFM >= 2 */ 406185596Syongari#define GHC_FIFO_WR_PWR_DIS 0x01000000 /* JMC250 REVFM >= 2 */ 407185596Syongari#define GHC_TX_OFFLD_CLK_100 0x00800000 /* JMC250/JMC260 REVFM >= 2 */ 408185596Syongari#define GHC_TX_OFFLD_CLK_1000 0x00400000 /* JMC250/JMC260 REVFM >= 2 */ 409185596Syongari#define GHC_TX_OFFLD_CLK_DIS 0x00000000 /* JMC250/JMC260 REVFM >= 2 */ 410185596Syongari#define GHC_TX_MAC_CLK_100 0x00200000 /* JMC250/JMC260 REVFM >= 2 */ 411185596Syongari#define GHC_TX_MAC_CLK_1000 0x00100000 /* JMC250/JMC260 REVFM >= 2 */ 412185596Syongari#define GHC_TX_MAC_CLK_DIS 0x00000000 /* JMC250/JMC260 REVFM >= 2 */ 413185596Syongari#define GHC_AUTO_PHY_STAT_DIS 0x00000080 /* JMC250/JMC260 REVFM >= 2 */ 414179337Syongari#define GHC_FULL_DUPLEX 0x00000040 415179337Syongari#define GHC_SPEED_UNKNOWN 0x00000000 416179337Syongari#define GHC_SPEED_10 0x00000010 417179337Syongari#define GHC_SPEED_100 0x00000020 418179337Syongari#define GHC_SPEED_1000 0x00000030 419179337Syongari#define GHC_SPEED_MASK 0x00000030 420179337Syongari#define GHC_LINK_OFF 0x00000004 421179337Syongari#define GHC_LINK_ON 0x00000002 422179337Syongari#define GHC_LINK_STAT_POLLING 0x00000001 423179337Syongari 424179337Syongari/* Power management control and status. */ 425179337Syongari#define JME_PMCS 0x0060 426179337Syongari#define PMCS_WAKEUP_FRAME_7 0x80000000 427179337Syongari#define PMCS_WAKEUP_FRAME_6 0x40000000 428179337Syongari#define PMCS_WAKEUP_FRAME_5 0x20000000 429179337Syongari#define PMCS_WAKEUP_FRAME_4 0x10000000 430179337Syongari#define PMCS_WAKEUP_FRAME_3 0x08000000 431179337Syongari#define PMCS_WAKEUP_FRAME_2 0x04000000 432179337Syongari#define PMCS_WAKEUP_FRAME_1 0x02000000 433179337Syongari#define PMCS_WAKEUP_FRAME_0 0x01000000 434179337Syongari#define PMCS_LINK_FAIL 0x00040000 435179337Syongari#define PMCS_LINK_RISING 0x00020000 436179337Syongari#define PMCS_MAGIC_FRAME 0x00010000 437179337Syongari#define PMCS_WAKEUP_FRAME_7_ENB 0x00008000 438179337Syongari#define PMCS_WAKEUP_FRAME_6_ENB 0x00004000 439179337Syongari#define PMCS_WAKEUP_FRAME_5_ENB 0x00002000 440179337Syongari#define PMCS_WAKEUP_FRAME_4_ENB 0x00001000 441179337Syongari#define PMCS_WAKEUP_FRAME_3_ENB 0x00000800 442179337Syongari#define PMCS_WAKEUP_FRAME_2_ENB 0x00000400 443179337Syongari#define PMCS_WAKEUP_FRAME_1_ENB 0x00000200 444179337Syongari#define PMCS_WAKEUP_FRAME_0_ENB 0x00000100 445179337Syongari#define PMCS_LINK_FAIL_ENB 0x00000004 446179337Syongari#define PMCS_LINK_RISING_ENB 0x00000002 447179337Syongari#define PMCS_MAGIC_FRAME_ENB 0x00000001 448179337Syongari#define PMCS_WOL_ENB_MASK 0x0000FFFF 449179337Syongari 450185597Syongari/* 451185597Syongari * Statistic registers control and status. 452185597Syongari * These statistics registers are valid only for JMC250/JMC260 REVFM >= 2. 453185597Syongari */ 454185597Syongari#define JME_STATCSR 0x0064 455185597Syongari#define STATCSR_RXMPT_DIS 0x00000080 456185597Syongari#define STATCSR_OFLOW_DIS 0x00000040 457185597Syongari#define STATCSR_MIIRXER_DIS 0x00000020 458185597Syongari#define STATCSR_CRCERR_DIS 0x00000010 459185597Syongari#define STATCSR_RXBAD_DIS 0x00000008 460185597Syongari#define STATCSR_RXGOOD_DIS 0x00000004 461185597Syongari#define STATCSR_TXBAD_DIS 0x00000002 462185597Syongari#define STATCSR_TXGOOD_DIS 0x00000001 463185597Syongari 464185597Syongari#define JME_STAT_TXGOOD 0x0068 465185597Syongari 466185597Syongari#define JME_STAT_RXGOOD 0x006C 467185597Syongari 468185597Syongari#define JME_STAT_CRCMII 0x0070 469185597Syongari#define STAT_RX_CRC_ERR_MASK 0xFFFF0000 470185597Syongari#define STAT_RX_MII_ERR_MASK 0x0000FFFF 471185597Syongari#define STAT_RX_CRC_ERR_SHIFT 16 472185597Syongari#define STAT_RX_MII_ERR_SHIFT 0 473185597Syongari 474185597Syongari#define JME_STAT_RXERR 0x0074 475185597Syongari#define STAT_RXERR_OFLOW_MASK 0xFFFF0000 476185597Syongari#define STAT_RXERR_MPTY_MASK 0x0000FFFF 477185597Syongari#define STAT_RXERR_OFLOW_SHIFT 16 478185597Syongari#define STAT_RXERR_MPTY_SHIFT 0 479185597Syongari 480185597Syongari#define JME_STAT_RESERVED1 0x0078 481185597Syongari 482185597Syongari#define JME_STAT_FAIL 0x007C 483185597Syongari#define STAT_FAIL_RX_MASK 0xFFFF0000 484185597Syongari#define STAT_FAIL_TX_MASK 0x0000FFFF 485185597Syongari#define STAT_FAIL_RX_SHIFT 16 486185597Syongari#define STAT_FAIL_TX_SHIFT 0 487185597Syongari 488179337Syongari/* Giga PHY & EEPROM registers. */ 489179337Syongari#define JME_PHY_EEPROM_BASE_ADDR 0x0400 490179337Syongari 491179337Syongari#define JME_GIGAR0LO 0x0400 492179337Syongari#define JME_GIGAR0HI 0x0404 493179337Syongari#define JME_GIGARALO 0x0408 494179337Syongari#define JME_GIGARAHI 0x040C 495179337Syongari#define JME_GIGARBLO 0x0410 496179337Syongari#define JME_GIGARBHI 0x0414 497179337Syongari#define JME_GIGARCLO 0x0418 498179337Syongari#define JME_GIGARCHI 0x041C 499179337Syongari#define JME_GIGARDLO 0x0420 500179337Syongari#define JME_GIGARDHI 0x0424 501216551Syongari#define JME_PHYPOWDN 0x0424 /* JMC250/JMC260 REVFM >= 5 */ 502179337Syongari 503179337Syongari/* BIST status and control. */ 504179337Syongari#define JME_GIGACSR 0x0428 505179337Syongari#define GIGACSR_STATUS 0x40000000 506179337Syongari#define GIGACSR_CTRL_MASK 0x30000000 507179337Syongari#define GIGACSR_CTRL_DEFAULT 0x30000000 508179337Syongari#define GIGACSR_TX_CLK_MASK 0x0F000000 509179337Syongari#define GIGACSR_RX_CLK_MASK 0x00F00000 510179337Syongari#define GIGACSR_TX_CLK_INV 0x00080000 511179337Syongari#define GIGACSR_RX_CLK_INV 0x00040000 512179337Syongari#define GIGACSR_PHY_RST 0x00010000 513179337Syongari#define GIGACSR_IRQ_N_O 0x00001000 514179337Syongari#define GIGACSR_BIST_OK 0x00000200 515179337Syongari#define GIGACSR_BIST_DONE 0x00000100 516179337Syongari#define GIGACSR_BIST_LED_ENB 0x00000010 517179337Syongari#define GIGACSR_BIST_MASK 0x00000003 518179337Syongari 519179337Syongari/* PHY Link Status. */ 520179337Syongari#define JME_LNKSTS 0x0430 521179337Syongari#define LINKSTS_SPEED_10 0x00000000 522179337Syongari#define LINKSTS_SPEED_100 0x00004000 523179337Syongari#define LINKSTS_SPEED_1000 0x00008000 524179337Syongari#define LINKSTS_FULL_DUPLEX 0x00002000 525179337Syongari#define LINKSTS_PAGE_RCVD 0x00001000 526179337Syongari#define LINKSTS_SPDDPX_RESOLVED 0x00000800 527179337Syongari#define LINKSTS_UP 0x00000400 528179337Syongari#define LINKSTS_ANEG_COMP 0x00000200 529179337Syongari#define LINKSTS_MDI_CROSSOVR 0x00000040 530179337Syongari#define LINKSTS_LPAR_PAUSE_ASYM 0x00000002 531179337Syongari#define LINKSTS_LPAR_PAUSE 0x00000001 532179337Syongari 533179337Syongari/* SMB control and status. */ 534179337Syongari#define JME_SMBCSR 0x0440 535179337Syongari#define SMBCSR_SLAVE_ADDR_MASK 0x7F000000 536179337Syongari#define SMBCSR_WR_DATA_NACK 0x00040000 537179337Syongari#define SMBCSR_CMD_NACK 0x00020000 538179337Syongari#define SMBCSR_RELOAD 0x00010000 539179337Syongari#define SMBCSR_CMD_ADDR_MASK 0x0000FF00 540179337Syongari#define SMBCSR_SCL_STAT 0x00000080 541179337Syongari#define SMBCSR_SDA_STAT 0x00000040 542179337Syongari#define SMBCSR_EEPROM_PRESENT 0x00000020 543179337Syongari#define SMBCSR_INIT_LD_DONE 0x00000010 544179337Syongari#define SMBCSR_HW_BUSY_MASK 0x0000000F 545179337Syongari#define SMBCSR_HW_IDLE 0x00000000 546179337Syongari 547179337Syongari/* SMB interface. */ 548179337Syongari#define JME_SMBINTF 0x0444 549179337Syongari#define SMBINTF_RD_DATA_MASK 0xFF000000 550179337Syongari#define SMBINTF_RD_DATA_SHIFT 24 551179337Syongari#define SMBINTF_WR_DATA_MASK 0x00FF0000 552179337Syongari#define SMBINTF_WR_DATA_SHIFT 16 553179337Syongari#define SMBINTF_ADDR_MASK 0x0000FF00 554179337Syongari#define SMBINTF_ADDR_SHIFT 8 555179337Syongari#define SMBINTF_RD 0x00000020 556179337Syongari#define SMBINTF_WR 0x00000000 557179337Syongari#define SMBINTF_CMD_TRIGGER 0x00000010 558179337Syongari#define SMBINTF_BUSY 0x00000010 559179337Syongari#define SMBINTF_FAST_MODE 0x00000008 560179337Syongari#define SMBINTF_GPIO_SCL 0x00000004 561179337Syongari#define SMBINTF_GPIO_SDA 0x00000002 562179337Syongari#define SMBINTF_GPIO_ENB 0x00000001 563179337Syongari 564179337Syongari#define JME_EEPROM_SIG0 0x55 565179337Syongari#define JME_EEPROM_SIG1 0xAA 566179337Syongari#define JME_EEPROM_DESC_BYTES 3 567179337Syongari#define JME_EEPROM_DESC_END 0x80 568179337Syongari#define JME_EEPROM_FUNC_MASK 0x70 569179337Syongari#define JME_EEPROM_FUNC_SHIFT 4 570179337Syongari#define JME_EEPROM_PAGE_MASK 0x0F 571179337Syongari#define JME_EEPROM_PAGE_SHIFT 0 572179337Syongari 573179337Syongari#define JME_EEPROM_FUNC0 0 574179337Syongari/* PCI configuration space. */ 575179337Syongari#define JME_EEPROM_PAGE_BAR0 0 576179337Syongari/* 128 bytes I/O window. */ 577179337Syongari#define JME_EEPROM_PAGE_BAR1 1 578179337Syongari/* 256 bytes I/O window. */ 579179337Syongari#define JME_EEPROM_PAGE_BAR2 2 580179337Syongari 581179337Syongari#define JME_EEPROM_END 0xFF 582179337Syongari 583179337Syongari#define JME_EEPROM_MKDESC(f, p) \ 584179337Syongari ((((f) & JME_EEPROM_FUNC_MASK) << JME_EEPROM_FUNC_SHIFT) | \ 585179337Syongari (((p) & JME_EEPROM_PAGE_MASK) << JME_EEPROM_PAGE_SHIFT)) 586179337Syongari 587179337Syongari/* 3-wire EEPROM interface. Obsolete interface, use SMBCSR. */ 588179337Syongari#define JME_EEPINTF 0x0448 589179337Syongari#define EEPINTF_DATA_MASK 0xFFFF0000 590179337Syongari#define EEPINTF_DATA_SHIFT 16 591179337Syongari#define EEPINTF_ADDR_MASK 0x0000FC00 592179337Syongari#define EEPINTF_ADDR_SHIFT 10 593179337Syongari#define EEPRINTF_OP_MASK 0x00000300 594179337Syongari#define EEPINTF_OP_EXECUTE 0x00000080 595179337Syongari#define EEPINTF_DATA_OUT 0x00000008 596179337Syongari#define EEPINTF_DATA_IN 0x00000004 597179337Syongari#define EEPINTF_CLK 0x00000002 598179337Syongari#define EEPINTF_SEL 0x00000001 599179337Syongari 600179337Syongari/* 3-wire EEPROM control and status. Obsolete interface, use SMBCSR. */ 601179337Syongari#define JME_EEPCSR 0x044C 602179337Syongari#define EEPCSR_EEPROM_RELOAD 0x00000002 603179337Syongari#define EEPCSR_EEPROM_PRESENT 0x00000001 604179337Syongari 605179337Syongari/* Misc registers. */ 606179337Syongari#define JME_MISC_BASE_ADDR 0x800 607179337Syongari 608179337Syongari/* Timer control and status. */ 609179337Syongari#define JME_TMCSR 0x0800 610179337Syongari#define TMCSR_SW_INTR 0x80000000 611179337Syongari#define TMCSR_TIMER_INTR 0x10000000 612179337Syongari#define TMCSR_TIMER_ENB 0x01000000 613179337Syongari#define TMCSR_TIMER_COUNT_MASK 0x00FFFFFF 614179337Syongari 615179337Syongari/* GPIO control and status. */ 616179337Syongari#define JME_GPIO 0x0804 617179337Syongari#define GPIO_4_SPI_IN 0x80000000 618179337Syongari#define GPIO_3_SPI_IN 0x40000000 619179337Syongari#define GPIO_4_SPI_OUT 0x20000000 620179337Syongari#define GPIO_4_SPI_OUT_ENB 0x10000000 621179337Syongari#define GPIO_3_SPI_OUT 0x08000000 622179337Syongari#define GPIO_3_SPI_OUT_ENB 0x04000000 623179337Syongari#define GPIO_3_4_LED 0x00000000 624179337Syongari#define GPIO_3_4_GPIO 0x02000000 625179337Syongari#define GPIO_2_CLKREQN_IN 0x00100000 626179337Syongari#define GPIO_2_CLKREQN_OUT 0x00040000 627179337Syongari#define GPIO_2_CLKREQN_OUT_ENB 0x00020000 628179337Syongari#define GPIO_1_LED42_IN 0x00001000 629179337Syongari#define GPIO_1_LED42_OUT 0x00000400 630179337Syongari#define GPIO_1_LED42_OUT_ENB 0x00000200 631179337Syongari#define GPIO_1_LED42_ENB 0x00000100 632179337Syongari#define GPIO_0_SDA_IN 0x00000010 633179337Syongari#define GPIO_0_SDA_OUT 0x00000004 634179337Syongari#define GPIO_0_SDA_OUT_ENB 0x00000002 635179337Syongari#define GPIO_0_SDA_ENB 0x00000001 636179337Syongari 637179337Syongari/* General purpose register 0. */ 638179337Syongari#define JME_GPREG0 0x0808 639179337Syongari#define GPREG0_SH_POST_DW7_DIS 0x80000000 640179337Syongari#define GPREG0_SH_POST_DW6_DIS 0x40000000 641179337Syongari#define GPREG0_SH_POST_DW5_DIS 0x20000000 642179337Syongari#define GPREG0_SH_POST_DW4_DIS 0x10000000 643179337Syongari#define GPREG0_SH_POST_DW3_DIS 0x08000000 644179337Syongari#define GPREG0_SH_POST_DW2_DIS 0x04000000 645179337Syongari#define GPREG0_SH_POST_DW1_DIS 0x02000000 646179337Syongari#define GPREG0_SH_POST_DW0_DIS 0x01000000 647179337Syongari#define GPREG0_DMA_RD_REQ_8 0x00000000 648179337Syongari#define GPREG0_DMA_RD_REQ_6 0x00100000 649179337Syongari#define GPREG0_DMA_RD_REQ_5 0x00200000 650179337Syongari#define GPREG0_DMA_RD_REQ_4 0x00300000 651179337Syongari#define GPREG0_POST_DW0_ENB 0x00040000 652179337Syongari#define GPREG0_PCC_CLR_DIS 0x00020000 653179337Syongari#define GPREG0_FORCE_SCL_OUT 0x00010000 654179337Syongari#define GPREG0_DL_RSTB_DIS 0x00008000 655179337Syongari#define GPREG0_STICKY_RESET 0x00004000 656179337Syongari#define GPREG0_DL_RSTB_CFG_DIS 0x00002000 657179337Syongari#define GPREG0_LINK_CHG_POLL 0x00001000 658179337Syongari#define GPREG0_LINK_CHG_DIRECT 0x00000000 659179337Syongari#define GPREG0_MSI_GEN_SEL 0x00000800 660179337Syongari#define GPREG0_SMB_PAD_PU_DIS 0x00000400 661179337Syongari#define GPREG0_PCC_UNIT_16US 0x00000000 662179337Syongari#define GPREG0_PCC_UNIT_256US 0x00000100 663179337Syongari#define GPREG0_PCC_UNIT_US 0x00000200 664179337Syongari#define GPREG0_PCC_UNIT_MS 0x00000300 665179337Syongari#define GPREG0_PCC_UNIT_MASK 0x00000300 666179337Syongari#define GPREG0_INTR_EVENT_ENB 0x00000080 667179337Syongari#define GPREG0_PME_ENB 0x00000020 668179337Syongari#define GPREG0_PHY_ADDR_MASK 0x0000001F 669179337Syongari#define GPREG0_PHY_ADDR_SHIFT 0 670179337Syongari#define GPREG0_PHY_ADDR 1 671179337Syongari 672183264Syongari/* General purpose register 1. */ 673179337Syongari#define JME_GPREG1 0x080C 674216551Syongari#define GPREG1_RX_MAC_CLK_DIS 0x04000000 /* JMC250/JMC260 REVFM >= 2 */ 675183264Syongari#define GPREG1_RSS_IPV6_10_100 0x00000040 /* JMC250 A2 */ 676183264Syongari#define GPREG1_HDPX_FIX 0x00000020 /* JMC250 A2 */ 677183264Syongari#define GPREG1_INTDLY_UNIT_16US 0x00000018 /* JMC250 A1, A2 */ 678183264Syongari#define GPREG1_INTDLY_UNIT_1US 0x00000010 /* JMC250 A1, A2 */ 679183264Syongari#define GPREG1_INTDLY_UNIT_256NS 0x00000008 /* JMC250 A1, A2 */ 680183264Syongari#define GPREG1_INTDLY_UNIT_16NS 0x00000000 /* JMC250 A1, A2 */ 681183264Syongari#define GPREG1_INTDLY_MASK 0x00000007 682179337Syongari 683179337Syongari/* MSIX entry number of interrupt source. */ 684179337Syongari#define JME_MSINUM_BASE 0x0810 685179337Syongari#define JME_MSINUM_END 0x081F 686179337Syongari#define MSINUM_MASK 0x7FFFFFFF 687179337Syongari#define MSINUM_ENTRY_MASK 7 688179337Syongari#define MSINUM_REG_INDEX(x) ((x) / 8) 689179337Syongari#define MSINUM_INTR_SOURCE(x, y) \ 690179337Syongari (((x) & MSINUM_ENTRY_MASK) << (((y) & 7) * 4)) 691179337Syongari#define MSINUM_NUM_INTR_SOURCE 32 692179337Syongari 693179337Syongari/* Interrupt event status. */ 694179337Syongari#define JME_INTR_STATUS 0x0820 695179337Syongari#define INTR_SW 0x80000000 696179337Syongari#define INTR_TIMER 0x40000000 697179337Syongari#define INTR_LINKCHG 0x20000000 698179337Syongari#define INTR_PAUSE 0x10000000 699179337Syongari#define INTR_MAGIC_PKT 0x08000000 700179337Syongari#define INTR_WAKEUP_PKT 0x04000000 701179337Syongari#define INTR_RXQ0_COAL_TO 0x02000000 702179337Syongari#define INTR_RXQ1_COAL_TO 0x01000000 703179337Syongari#define INTR_RXQ2_COAL_TO 0x00800000 704179337Syongari#define INTR_RXQ3_COAL_TO 0x00400000 705179337Syongari#define INTR_TXQ_COAL_TO 0x00200000 706179337Syongari#define INTR_RXQ0_COAL 0x00100000 707179337Syongari#define INTR_RXQ1_COAL 0x00080000 708179337Syongari#define INTR_RXQ2_COAL 0x00040000 709179337Syongari#define INTR_RXQ3_COAL 0x00020000 710179337Syongari#define INTR_TXQ_COAL 0x00010000 711179337Syongari#define INTR_RXQ3_DESC_EMPTY 0x00008000 712179337Syongari#define INTR_RXQ2_DESC_EMPTY 0x00004000 713179337Syongari#define INTR_RXQ1_DESC_EMPTY 0x00002000 714179337Syongari#define INTR_RXQ0_DESC_EMPTY 0x00001000 715179337Syongari#define INTR_RXQ3_COMP 0x00000800 716179337Syongari#define INTR_RXQ2_COMP 0x00000400 717179337Syongari#define INTR_RXQ1_COMP 0x00000200 718179337Syongari#define INTR_RXQ0_COMP 0x00000100 719179337Syongari#define INTR_TXQ7_COMP 0x00000080 720179337Syongari#define INTR_TXQ6_COMP 0x00000040 721179337Syongari#define INTR_TXQ5_COMP 0x00000020 722179337Syongari#define INTR_TXQ4_COMP 0x00000010 723179337Syongari#define INTR_TXQ3_COMP 0x00000008 724179337Syongari#define INTR_TXQ2_COMP 0x00000004 725179337Syongari#define INTR_TXQ1_COMP 0x00000002 726179337Syongari#define INTR_TXQ0_COMP 0x00000001 727179337Syongari 728179337Syongari#define INTR_RXQ_COAL_TO \ 729179337Syongari (INTR_RXQ0_COAL_TO | INTR_RXQ1_COAL_TO | \ 730179337Syongari INTR_RXQ2_COAL_TO | INTR_RXQ3_COAL_TO) 731179337Syongari 732179337Syongari#define INTR_RXQ_COAL \ 733179337Syongari (INTR_RXQ0_COAL | INTR_RXQ1_COAL | INTR_RXQ2_COAL | \ 734179337Syongari INTR_RXQ3_COAL) 735179337Syongari 736179337Syongari#define INTR_RXQ_COMP \ 737179337Syongari (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 738179337Syongari INTR_RXQ3_COMP) 739179337Syongari 740179337Syongari#define INTR_RXQ_DESC_EMPTY \ 741179337Syongari (INTR_RXQ0_DESC_EMPTY | INTR_RXQ1_DESC_EMPTY | \ 742179337Syongari INTR_RXQ2_DESC_EMPTY | INTR_RXQ3_DESC_EMPTY) 743179337Syongari 744179337Syongari#define INTR_RXQ_COMP \ 745179337Syongari (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 746179337Syongari INTR_RXQ3_COMP) 747179337Syongari 748179337Syongari#define INTR_TXQ_COMP \ 749179337Syongari (INTR_TXQ0_COMP | INTR_TXQ1_COMP | INTR_TXQ2_COMP | \ 750179337Syongari INTR_TXQ3_COMP | INTR_TXQ4_COMP | INTR_TXQ5_COMP | \ 751179337Syongari INTR_TXQ6_COMP | INTR_TXQ7_COMP) 752179337Syongari 753179337Syongari#define JME_INTRS \ 754179337Syongari (INTR_RXQ_COAL_TO | INTR_TXQ_COAL_TO | INTR_RXQ_COAL | \ 755179337Syongari INTR_TXQ_COAL | INTR_RXQ_DESC_EMPTY) 756179337Syongari 757179337Syongari#define N_INTR_SW 31 758179337Syongari#define N_INTR_TIMER 30 759179337Syongari#define N_INTR_LINKCHG 29 760179337Syongari#define N_INTR_PAUSE 28 761179337Syongari#define N_INTR_MAGIC_PKT 27 762179337Syongari#define N_INTR_WAKEUP_PKT 26 763179337Syongari#define N_INTR_RXQ0_COAL_TO 25 764179337Syongari#define N_INTR_RXQ1_COAL_TO 24 765179337Syongari#define N_INTR_RXQ2_COAL_TO 23 766179337Syongari#define N_INTR_RXQ3_COAL_TO 22 767179337Syongari#define N_INTR_TXQ_COAL_TO 21 768179337Syongari#define N_INTR_RXQ0_COAL 20 769179337Syongari#define N_INTR_RXQ1_COAL 19 770179337Syongari#define N_INTR_RXQ2_COAL 18 771179337Syongari#define N_INTR_RXQ3_COAL 17 772179337Syongari#define N_INTR_TXQ_COAL 16 773179337Syongari#define N_INTR_RXQ3_DESC_EMPTY 15 774179337Syongari#define N_INTR_RXQ2_DESC_EMPTY 14 775179337Syongari#define N_INTR_RXQ1_DESC_EMPTY 13 776179337Syongari#define N_INTR_RXQ0_DESC_EMPTY 12 777179337Syongari#define N_INTR_RXQ3_COMP 11 778179337Syongari#define N_INTR_RXQ2_COMP 10 779179337Syongari#define N_INTR_RXQ1_COMP 9 780179337Syongari#define N_INTR_RXQ0_COMP 8 781179337Syongari#define N_INTR_TXQ7_COMP 7 782179337Syongari#define N_INTR_TXQ6_COMP 6 783179337Syongari#define N_INTR_TXQ5_COMP 5 784179337Syongari#define N_INTR_TXQ4_COMP 4 785179337Syongari#define N_INTR_TXQ3_COMP 3 786179337Syongari#define N_INTR_TXQ2_COMP 2 787179337Syongari#define N_INTR_TXQ1_COMP 1 788179337Syongari#define N_INTR_TXQ0_COMP 0 789179337Syongari 790179337Syongari/* Interrupt request status. */ 791179337Syongari#define JME_INTR_REQ_STATUS 0x0824 792179337Syongari 793179337Syongari/* Interrupt enable - setting port. */ 794179337Syongari#define JME_INTR_MASK_SET 0x0828 795179337Syongari 796179337Syongari/* Interrupt enable - clearing port. */ 797179337Syongari#define JME_INTR_MASK_CLR 0x082C 798179337Syongari 799179337Syongari/* Packet completion coalescing control of Rx queue 0, 1, 2 and 3. */ 800179337Syongari#define JME_PCCRX0 0x0830 801179337Syongari#define JME_PCCRX1 0x0834 802179337Syongari#define JME_PCCRX2 0x0838 803179337Syongari#define JME_PCCRX3 0x083C 804179337Syongari#define PCCRX_COAL_TO_MASK 0xFFFF0000 805179337Syongari#define PCCRX_COAL_TO_SHIFT 16 806179337Syongari#define PCCRX_COAL_PKT_MASK 0x0000FF00 807179337Syongari#define PCCRX_COAL_PKT_SHIFT 8 808179337Syongari 809179337Syongari#define PCCRX_COAL_TO_MIN 1 810179337Syongari#define PCCRX_COAL_TO_DEFAULT 100 811179337Syongari#define PCCRX_COAL_TO_MAX 65535 812179337Syongari 813179337Syongari#define PCCRX_COAL_PKT_MIN 1 814179337Syongari#define PCCRX_COAL_PKT_DEFAULT 2 815179337Syongari#define PCCRX_COAL_PKT_MAX 255 816179337Syongari 817179337Syongari/* Packet completion coalescing control of Tx queue. */ 818179337Syongari#define JME_PCCTX 0x0840 819179337Syongari#define PCCTX_COAL_TO_MASK 0xFFFF0000 820179337Syongari#define PCCTX_COAL_TO_SHIFT 16 821179337Syongari#define PCCTX_COAL_PKT_MASK 0x0000FF00 822179337Syongari#define PCCTX_COAL_PKT_SHIFT 8 823179337Syongari#define PCCTX_COAL_TXQ7 0x00000080 824179337Syongari#define PCCTX_COAL_TXQ6 0x00000040 825179337Syongari#define PCCTX_COAL_TXQ5 0x00000020 826179337Syongari#define PCCTX_COAL_TXQ4 0x00000010 827179337Syongari#define PCCTX_COAL_TXQ3 0x00000008 828179337Syongari#define PCCTX_COAL_TXQ2 0x00000004 829179337Syongari#define PCCTX_COAL_TXQ1 0x00000002 830179337Syongari#define PCCTX_COAL_TXQ0 0x00000001 831179337Syongari 832179337Syongari#define PCCTX_COAL_TO_MIN 1 833179337Syongari#define PCCTX_COAL_TO_DEFAULT 100 834179337Syongari#define PCCTX_COAL_TO_MAX 65535 835179337Syongari 836179337Syongari#define PCCTX_COAL_PKT_MIN 1 837179337Syongari#define PCCTX_COAL_PKT_DEFAULT 8 838179337Syongari#define PCCTX_COAL_PKT_MAX 255 839179337Syongari 840179337Syongari/* Chip mode and FPGA version. */ 841179337Syongari#define JME_CHIPMODE 0x0844 842179337Syongari#define CHIPMODE_FPGA_REV_MASK 0xFFFF0000 843179337Syongari#define CHIPMODE_FPGA_REV_SHIFT 16 844179337Syongari#define CHIPMODE_NOT_FPGA 0 845179337Syongari#define CHIPMODE_REV_MASK 0x0000FF00 846179337Syongari#define CHIPMODE_REV_SHIFT 8 847179337Syongari#define CHIPMODE_MODE_48P 0x0000000C 848179337Syongari#define CHIPMODE_MODE_64P 0x00000004 849179337Syongari#define CHIPMODE_MODE_128P_MAC 0x00000003 850179337Syongari#define CHIPMODE_MODE_128P_DBG 0x00000002 851179337Syongari#define CHIPMODE_MODE_128P_PHY 0x00000000 852185596Syongari/* Chip full mask revision. */ 853185596Syongari#define CHIPMODE_REVFM(x) ((x) & 0x0F) 854185596Syongari/* Chip ECO revision. */ 855185596Syongari#define CHIPMODE_REVECO(x) (((x) >> 4) & 0x0F) 856179337Syongari 857179337Syongari/* Shadow status base address high/low. */ 858179337Syongari#define JME_SHBASE_ADDR_HI 0x0848 859179337Syongari#define JME_SHBASE_ADDR_LO 0x084C 860179337Syongari#define SHBASE_ADDR_LO_MASK 0xFFFFFFE0 861179337Syongari#define SHBASE_POST_FORCE 0x00000002 862179337Syongari#define SHBASE_POST_ENB 0x00000001 863179337Syongari 864216551Syongari#define JME_PCDRX_BASE 0x0850 865216551Syongari#define JME_PCDRX_END 0x0857 866216551Syongari#define PCDRX_REG(x) (JME_PCDRX_BASE + (((x) / 2) * 4)) 867216551Syongari#define PCDRX1_TO_THROTTLE_MASK 0xFF000000 868216551Syongari#define PCDRX1_TO_MASK 0x00FF0000 869216551Syongari#define PCDRX0_TO_THROTTLE_MASK 0x0000FF00 870216551Syongari#define PCDRX0_TO_MASK 0x000000FF 871216551Syongari#define PCDRX1_TO_THROTTLE_SHIFT 24 872216551Syongari#define PCDRX1_TO_SHIFT 16 873216551Syongari#define PCDRX0_TO_THROTTLE_SHIFT 8 874216551Syongari#define PCDRX0_TO_SHIFT 0 875216551Syongari#define PCDRX_TO_MIN 1 876216551Syongari#define PCDRX_TO_MAX 255 877216551Syongari 878216551Syongari#define JME_PCDTX 0x0858 879216551Syongari#define PCDTX_TO_THROTTLE_MASK 0x0000FF00 880216551Syongari#define PCDTX_TO_MASK 0x000000FF 881216551Syongari#define PCDTX_TO_THROTTLE_SHIFT 8 882216551Syongari#define PCDTX_TO_SHIFT 0 883216551Syongari#define PCDTX_TO_MIN 1 884216551Syongari#define PCDTX_TO_MAX 255 885216551Syongari 886216551Syongari#define JME_PCCPCD_STAT 0x085C 887216551Syongari#define PCCPCD_STAT_RX3_MASK 0xFF000000 888216551Syongari#define PCCPCD_STAT_RX2_MASK 0x00FF0000 889216551Syongari#define PCCPCD_STAT_RX1_MASK 0x0000FF00 890216551Syongari#define PCCPCD_STAT_RX0_MASK 0x000000FF 891216551Syongari#define PCCPCD_STAT_RX3_SHIFT 24 892216551Syongari#define PCCPCD_STAT_RX2_SHIFT 16 893216551Syongari#define PCCPCD_STAT_RX1_SHIFT 8 894216551Syongari#define PCCPCD_STAT_RX0_SHIFT 0 895216551Syongari 896216551Syongari/* TX data throughput in KB. */ 897216551Syongari#define JME_TX_THROUGHPUT 0x0860 898216551Syongari#define TX_THROUGHPUT_MASK 0x000FFFFF 899216551Syongari 900216551Syongari/* RX data throughput in KB. */ 901216551Syongari#define JME_RX_THROUGHPUT 0x0864 902216551Syongari#define RX_THROUGHPUT_MASK 0x000FFFFF 903216551Syongari 904216551Syongari#define JME_LPI_CTL 0x086C 905216551Syongari#define LPI_STAT_ANC_ANF 0x00000010 906216551Syongari#define LPI_STAT_AN_TIMEOUT 0x00000008 907216551Syongari#define LPI_STAT_RX_LPI 0x00000004 908216551Syongari#define LPI_INT_ENB 0x00000002 909216551Syongari#define LPI_REQ 0x00000001 910216551Syongari 911179337Syongari/* Timer 1 and 2. */ 912179337Syongari#define JME_TIMER1 0x0870 913179337Syongari#define JME_TIMER2 0x0874 914179337Syongari#define TIMER_ENB 0x01000000 915179337Syongari#define TIMER_CNT_MASK 0x00FFFFFF 916179337Syongari#define TIMER_CNT_SHIFT 0 917179337Syongari#define TIMER_UNIT 1024 /* 1024us */ 918179337Syongari 919216551Syongari/* Timer 3. */ 920216551Syongari#define JME_TIMER3 0x0878 921216551Syongari#define TIMER3_TIMEOUT 0x00010000 922216551Syongari#define TIMER3_TIMEOUT_COUNT_MASK 0x0000FF00 /* 130ms unit */ 923216551Syongari#define TIMER3_TIMEOUT_VAL_MASK 0x000000E0 924216551Syongari#define TIMER3_ENB 0x00000001 925216551Syongari#define TIMER3_TIMEOUT_COUNT_SHIFT 8 926216551Syongari#define TIMER3_TIMEOUT_VALUE_SHIFT 1 927216551Syongari 928298955Spfg/* Aggressive power mode control. */ 929179337Syongari#define JME_APMC 0x087C 930179337Syongari#define APMC_PCIE_SDOWN_STAT 0x80000000 931179337Syongari#define APMC_PCIE_SDOWN_ENB 0x40000000 932179337Syongari#define APMC_PSEUDO_HOT_PLUG 0x20000000 933179337Syongari#define APMC_EXT_PLUGIN_ENB 0x04000000 934179337Syongari#define APMC_EXT_PLUGIN_CTL_MSK 0x03000000 935179337Syongari#define APMC_DIS_SRAM 0x00000004 936179337Syongari#define APMC_DIS_CLKPM 0x00000002 937179337Syongari#define APMC_DIS_CLKTX 0x00000001 938179337Syongari 939179337Syongari/* Packet completion coalesing status of Rx queue 0, 1, 2 and 3. */ 940179337Syongari#define JME_PCCSRX_BASE 0x0880 941179337Syongari#define JME_PCCSRX_END 0x088F 942179337Syongari#define PCCSRX_REG(x) (JME_PCCSRX_BASE + ((x) * 4)) 943179337Syongari#define PCCSRX_TO_MASK 0xFFFF0000 944179337Syongari#define PCCSRX_TO_SHIFT 16 945179337Syongari#define PCCSRX_PKT_CNT_MASK 0x0000FF00 946179337Syongari#define PCCSRX_PKT_CNT_SHIFT 8 947179337Syongari 948179337Syongari/* Packet completion coalesing status of Tx queue. */ 949179337Syongari#define JME_PCCSTX 0x0890 950179337Syongari#define PCCSTX_TO_MASK 0xFFFF0000 951179337Syongari#define PCCSTX_TO_SHIFT 16 952179337Syongari#define PCCSTX_PKT_CNT_MASK 0x0000FF00 953179337Syongari#define PCCSTX_PKT_CNT_SHIFT 8 954179337Syongari 955179337Syongari/* Tx queues empty indicator. */ 956179337Syongari#define JME_TXQEMPTY 0x0894 957179337Syongari#define TXQEMPTY_TXQ7 0x00000080 958179337Syongari#define TXQEMPTY_TXQ6 0x00000040 959179337Syongari#define TXQEMPTY_TXQ5 0x00000020 960179337Syongari#define TXQEMPTY_TXQ4 0x00000010 961179337Syongari#define TXQEMPTY_TXQ3 0x00000008 962179337Syongari#define TXQEMPTY_TXQ2 0x00000004 963179337Syongari#define TXQEMPTY_TXQ1 0x00000002 964179337Syongari#define TXQEMPTY_TXQ0 0x00000001 965179337Syongari#define TXQEMPTY_N_TXQ(x, y) ((x) & (0x01 << (y))) 966179337Syongari 967179337Syongari/* RSS control registers. */ 968179337Syongari#define JME_RSS_BASE 0x0C00 969179337Syongari 970179337Syongari#define JME_RSSC 0x0C00 971179337Syongari#define RSSC_HASH_LEN_MASK 0x0000E000 972179337Syongari#define RSSC_HASH_64_ENTRY 0x0000A000 973179337Syongari#define RSSC_HASH_128_ENTRY 0x0000E000 974179337Syongari#define RSSC_HASH_NONE 0x00001000 975179337Syongari#define RSSC_HASH_IPV6 0x00000800 976179337Syongari#define RSSC_HASH_IPV4 0x00000400 977179337Syongari#define RSSC_HASH_IPV6_TCP 0x00000200 978179337Syongari#define RSSC_HASH_IPV4_TCP 0x00000100 979179337Syongari#define RSSC_NCPU_MASK 0x000000F8 980179337Syongari#define RSSC_NCPU_SHIFT 3 981179337Syongari#define RSSC_DIS_RSS 0x00000000 982179337Syongari#define RSSC_2RXQ_ENB 0x00000001 983179337Syongari#define RSSS_4RXQ_ENB 0x00000002 984179337Syongari 985179337Syongari/* CPU vector. */ 986179337Syongari#define JME_RSSCPU 0x0C04 987179337Syongari#define RSSCPU_N_SEL(x) ((1 << (x)) 988179337Syongari 989179337Syongari/* RSS Hash value. */ 990179337Syongari#define JME_RSSHASH 0x0C10 991179337Syongari 992179337Syongari#define JME_RSSHASH_STAT 0x0C14 993179337Syongari 994179337Syongari#define JME_RSS_RDATA0 0x0C18 995179337Syongari 996179337Syongari#define JME_RSS_RDATA1 0x0C1C 997179337Syongari 998179337Syongari/* RSS secret key. */ 999179337Syongari#define JME_RSSKEY_BASE 0x0C40 1000179337Syongari#define JME_RSSKEY_LAST 0x0C64 1001179337Syongari#define JME_RSSKEY_END 0x0C67 1002179337Syongari#define HASHKEY_NBYTES 40 1003179337Syongari#define RSSKEY_REG(x) (JME_RSSKEY_LAST - (4 * ((x) / 4))) 1004179337Syongari#define RSSKEY_VALUE(x, y) ((x) << (24 - 8 * ((y) % 4))) 1005179337Syongari 1006179337Syongari/* RSS indirection table entries. */ 1007179337Syongari#define JME_RSSTBL_BASE 0x0C80 1008179337Syongari#define JME_RSSTBL_END 0x0CFF 1009179337Syongari#define RSSTBL_NENTRY 128 1010179337Syongari#define RSSTBL_REG(x) (JME_RSSTBL_BASE + ((x) / 4)) 1011179337Syongari#define RSSTBL_VALUE(x, y) ((x) << (8 * ((y) % 4))) 1012179337Syongari 1013179337Syongari/* MSI-X table. */ 1014179337Syongari#define JME_MSIX_BASE_ADDR 0x2000 1015179337Syongari 1016179337Syongari#define JME_MSIX_BASE 0x2000 1017179337Syongari#define JME_MSIX_END 0x207F 1018179337Syongari#define JME_MSIX_NENTRY 8 1019179337Syongari#define MSIX_REG(x) (JME_MSIX_BASE + ((x) * 0x10)) 1020179337Syongari#define MSIX_ADDR_HI_OFF 0x00 1021179337Syongari#define MSIX_ADDR_LO_OFF 0x04 1022179337Syongari#define MSIX_ADDR_LO_MASK 0xFFFFFFFC 1023179337Syongari#define MSIX_DATA_OFF 0x08 1024179337Syongari#define MSIX_VECTOR_OFF 0x0C 1025179337Syongari#define MSIX_VECTOR_RSVD 0x80000000 1026179337Syongari#define MSIX_VECTOR_DIS 0x00000001 1027179337Syongari 1028179337Syongari/* MSI-X PBA. */ 1029179337Syongari#define JME_MSIX_PBA_BASE_ADDR 0x3000 1030179337Syongari 1031179337Syongari#define JME_MSIX_PBA 0x3000 1032179337Syongari#define MSIX_PBA_RSVD_MASK 0xFFFFFF00 1033179337Syongari#define MSIX_PBA_RSVD_SHIFT 8 1034179337Syongari#define MSIX_PBA_PEND_MASK 0x000000FF 1035179337Syongari#define MSIX_PBA_PEND_SHIFT 0 1036179337Syongari#define MSIX_PBA_PEND_ENTRY7 0x00000080 1037179337Syongari#define MSIX_PBA_PEND_ENTRY6 0x00000040 1038179337Syongari#define MSIX_PBA_PEND_ENTRY5 0x00000020 1039179337Syongari#define MSIX_PBA_PEND_ENTRY4 0x00000010 1040179337Syongari#define MSIX_PBA_PEND_ENTRY3 0x00000008 1041179337Syongari#define MSIX_PBA_PEND_ENTRY2 0x00000004 1042179337Syongari#define MSIX_PBA_PEND_ENTRY1 0x00000002 1043179337Syongari#define MSIX_PBA_PEND_ENTRY0 0x00000001 1044179337Syongari 1045179337Syongari#define JME_PHY_OUI 0x001B8C 1046179337Syongari#define JME_PHY_MODEL 0x21 1047179337Syongari#define JME_PHY_REV 0x01 1048179337Syongari#define JME_PHY_ADDR 1 1049179337Syongari 1050179337Syongari/* JMC250 shadow status block. */ 1051179337Syongaristruct jme_ssb { 1052179337Syongari uint32_t dw0; 1053179337Syongari uint32_t dw1; 1054179337Syongari uint32_t dw2; 1055179337Syongari uint32_t dw3; 1056179337Syongari uint32_t dw4; 1057179337Syongari uint32_t dw5; 1058179337Syongari uint32_t dw6; 1059179337Syongari uint32_t dw7; 1060179337Syongari}; 1061179337Syongari 1062179337Syongari/* JMC250 descriptor structures. */ 1063179337Syongaristruct jme_desc { 1064179337Syongari uint32_t flags; 1065179337Syongari uint32_t buflen; 1066179337Syongari uint32_t addr_hi; 1067179337Syongari uint32_t addr_lo; 1068179337Syongari}; 1069179337Syongari 1070179337Syongari#define JME_TD_OWN 0x80000000 1071179337Syongari#define JME_TD_INTR 0x40000000 1072179337Syongari#define JME_TD_64BIT 0x20000000 1073179337Syongari#define JME_TD_TCPCSUM 0x10000000 1074179337Syongari#define JME_TD_UDPCSUM 0x08000000 1075179337Syongari#define JME_TD_IPCSUM 0x04000000 1076179337Syongari#define JME_TD_TSO 0x02000000 1077179337Syongari#define JME_TD_VLAN_TAG 0x01000000 1078179337Syongari#define JME_TD_VLAN_MASK 0x0000FFFF 1079179337Syongari 1080179337Syongari#define JME_TD_MSS_MASK 0xFFFC0000 1081179337Syongari#define JME_TD_MSS_SHIFT 18 1082179337Syongari#define JME_TD_BUF_LEN_MASK 0x0000FFFF 1083179337Syongari#define JME_TD_BUF_LEN_SHIFT 0 1084179337Syongari 1085179337Syongari#define JME_TD_FRAME_LEN_MASK 0x0000FFFF 1086179337Syongari#define JME_TD_FRAME_LEN_SHIFT 0 1087179337Syongari 1088179337Syongari/* 1089179337Syongari * Only the first Tx descriptor of a packet is updated 1090179337Syongari * after packet transmission. 1091179337Syongari */ 1092179337Syongari#define JME_TD_TMOUT 0x20000000 1093179337Syongari#define JME_TD_RETRY_EXP 0x10000000 1094179337Syongari#define JME_TD_COLLISION 0x08000000 1095179337Syongari#define JME_TD_UNDERRUN 0x04000000 1096179337Syongari#define JME_TD_EHDR_SIZE_MASK 0x000000FF 1097179337Syongari#define JME_TD_EHDR_SIZE_SHIFT 0 1098179337Syongari 1099179337Syongari#define JME_TD_SEG_CNT_MASK 0xFFFF0000 1100179337Syongari#define JME_TD_SEG_CNT_SHIFT 16 1101179337Syongari#define JME_TD_RETRY_CNT_MASK 0x0000FFFF 1102179337Syongari#define JME_TD_RETRY_CNT_SHIFT 0 1103179337Syongari 1104179337Syongari#define JME_RD_OWN 0x80000000 1105179337Syongari#define JME_RD_INTR 0x40000000 1106179337Syongari#define JME_RD_64BIT 0x20000000 1107179337Syongari 1108179337Syongari#define JME_RD_BUF_LEN_MASK 0x0000FFFF 1109179337Syongari#define JME_RD_BUF_LEN_SHIFT 0 1110179337Syongari 1111179337Syongari/* 1112179337Syongari * Only the first Rx descriptor of a packet is updated 1113179337Syongari * after packet reception. 1114179337Syongari */ 1115179337Syongari#define JME_RD_MORE_FRAG 0x20000000 1116179337Syongari#define JME_RD_TCP 0x10000000 1117179337Syongari#define JME_RD_UDP 0x08000000 1118179337Syongari#define JME_RD_IPCSUM 0x04000000 1119179337Syongari#define JME_RD_TCPCSUM 0x02000000 1120179337Syongari#define JME_RD_UDPCSUM 0x01000000 1121179337Syongari#define JME_RD_VLAN_TAG 0x00800000 1122179337Syongari#define JME_RD_IPV4 0x00400000 1123179337Syongari#define JME_RD_IPV6 0x00200000 1124179337Syongari#define JME_RD_PAUSE 0x00100000 1125179337Syongari#define JME_RD_MAGIC 0x00080000 1126179337Syongari#define JME_RD_WAKEUP 0x00040000 1127179337Syongari#define JME_RD_BCAST 0x00030000 1128179337Syongari#define JME_RD_MCAST 0x00020000 1129179337Syongari#define JME_RD_UCAST 0x00010000 1130179337Syongari#define JME_RD_VLAN_MASK 0x0000FFFF 1131179337Syongari#define JME_RD_VLAN_SHIFT 0 1132179337Syongari 1133179337Syongari#define JME_RD_VALID 0x80000000 1134179337Syongari#define JME_RD_CNT_MASK 0x7F000000 1135179337Syongari#define JME_RD_CNT_SHIFT 24 1136179337Syongari#define JME_RD_GIANT 0x00800000 1137179337Syongari#define JME_RD_GMII_ERR 0x00400000 1138179337Syongari#define JME_RD_NBL_RCVD 0x00200000 1139179337Syongari#define JME_RD_COLL 0x00100000 1140179337Syongari#define JME_RD_ABORT 0x00080000 1141179337Syongari#define JME_RD_RUNT 0x00040000 1142179337Syongari#define JME_RD_FIFO_OVRN 0x00020000 1143179337Syongari#define JME_RD_CRC_ERR 0x00010000 1144179337Syongari#define JME_RD_FRAME_LEN_MASK 0x0000FFFF 1145179337Syongari 1146179337Syongari#define JME_RX_ERR_STAT \ 1147179337Syongari (JME_RD_GIANT | JME_RD_GMII_ERR | JME_RD_NBL_RCVD | \ 1148179337Syongari JME_RD_COLL | JME_RD_ABORT | JME_RD_RUNT | \ 1149179337Syongari JME_RD_FIFO_OVRN | JME_RD_CRC_ERR) 1150179337Syongari 1151179337Syongari#define JME_RD_ERR_MASK 0x00FF0000 1152179337Syongari#define JME_RD_ERR_SHIFT 16 1153179337Syongari#define JME_RX_ERR(x) (((x) & JME_RD_ERR_MASK) >> JME_RD_ERR_SHIFT) 1154179337Syongari#define JME_RX_ERR_BITS "\20" \ 1155179337Syongari "\1CRCERR\2FIFOOVRN\3RUNT\4ABORT" \ 1156179337Syongari "\5COLL\6NBLRCVD\7GMIIERR\10" 1157179337Syongari 1158179337Syongari#define JME_RX_NSEGS(x) (((x) & JME_RD_CNT_MASK) >> JME_RD_CNT_SHIFT) 1159179337Syongari#define JME_RX_BYTES(x) ((x) & JME_RD_FRAME_LEN_MASK) 1160179337Syongari#define JME_RX_PAD_BYTES 10 1161179337Syongari 1162179337Syongari#define JME_RD_RSS_HASH_VALUE 0xFFFFFFFF 1163179337Syongari 1164179337Syongari#define JME_RD_RSS_HASH_MASK 0x00003F00 1165179337Syongari#define JME_RD_RSS_HASH_SHIFT 8 1166179337Syongari#define JME_RD_RSS_HASH_NONE 0x00000000 1167179337Syongari#define JME_RD_RSS_HASH_IPV4 0x00000100 1168179337Syongari#define JME_RD_RSS_HASH_IPV4TCP 0x00000200 1169179337Syongari#define JME_RD_RSS_HASH_IPV6 0x00000400 1170179337Syongari#define JME_RD_RSS_HASH_IPV6TCP 0x00001000 1171179337Syongari#define JME_RD_HASH_FN_NONE 0x00000000 1172179337Syongari#define JME_RD_HASH_FN_TOEPLITZ 0x00000001 1173179337Syongari 1174179337Syongari#endif 1175