if_ixl.c revision 299546
1/****************************************************************************** 2 3 Copyright (c) 2013-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/ixl/if_ixl.c 299546 2016-05-12 18:19:31Z erj $*/ 34 35#ifndef IXL_STANDALONE_BUILD 36#include "opt_inet.h" 37#include "opt_inet6.h" 38#include "opt_rss.h" 39#endif 40 41#include "ixl.h" 42#include "ixl_pf.h" 43 44#ifdef RSS 45#include <net/rss_config.h> 46#endif 47 48/********************************************************************* 49 * Driver version 50 *********************************************************************/ 51char ixl_driver_version[] = "1.4.6-k"; 52 53/********************************************************************* 54 * PCI Device ID Table 55 * 56 * Used by probe to select devices to load on 57 * Last field stores an index into ixl_strings 58 * Last entry must be all 0s 59 * 60 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 61 *********************************************************************/ 62 63static ixl_vendor_info_t ixl_vendor_info_array[] = 64{ 65 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710, 0, 0, 0}, 66 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_A, 0, 0, 0}, 67 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B, 0, 0, 0}, 68 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C, 0, 0, 0}, 69 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A, 0, 0, 0}, 70 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B, 0, 0, 0}, 71 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C, 0, 0, 0}, 72 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T, 0, 0, 0}, 73 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4, 0, 0, 0}, 74 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2, 0, 0, 0}, 75 {I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A, 0, 0, 0}, 76 /* required last entry */ 77 {0, 0, 0, 0, 0} 78}; 79 80/********************************************************************* 81 * Table of branding strings 82 *********************************************************************/ 83 84static char *ixl_strings[] = { 85 "Intel(R) Ethernet Connection XL710 Driver" 86}; 87 88 89/********************************************************************* 90 * Function prototypes 91 *********************************************************************/ 92static int ixl_probe(device_t); 93static int ixl_attach(device_t); 94static int ixl_detach(device_t); 95static int ixl_shutdown(device_t); 96static int ixl_get_hw_capabilities(struct ixl_pf *); 97static void ixl_cap_txcsum_tso(struct ixl_vsi *, struct ifnet *, int); 98static int ixl_ioctl(struct ifnet *, u_long, caddr_t); 99static void ixl_init(void *); 100static void ixl_init_locked(struct ixl_pf *); 101static void ixl_stop(struct ixl_pf *); 102static void ixl_media_status(struct ifnet *, struct ifmediareq *); 103static int ixl_media_change(struct ifnet *); 104static void ixl_update_link_status(struct ixl_pf *); 105static int ixl_allocate_pci_resources(struct ixl_pf *); 106static u16 ixl_get_bus_info(struct i40e_hw *, device_t); 107static int ixl_setup_stations(struct ixl_pf *); 108static int ixl_switch_config(struct ixl_pf *); 109static int ixl_initialize_vsi(struct ixl_vsi *); 110static int ixl_assign_vsi_msix(struct ixl_pf *); 111static int ixl_assign_vsi_legacy(struct ixl_pf *); 112static int ixl_init_msix(struct ixl_pf *); 113static void ixl_configure_msix(struct ixl_pf *); 114static void ixl_configure_itr(struct ixl_pf *); 115static void ixl_configure_legacy(struct ixl_pf *); 116static void ixl_init_taskqueues(struct ixl_pf *); 117static void ixl_free_taskqueues(struct ixl_pf *); 118static void ixl_free_pci_resources(struct ixl_pf *); 119static void ixl_local_timer(void *); 120static int ixl_setup_interface(device_t, struct ixl_vsi *); 121static void ixl_link_event(struct ixl_pf *, struct i40e_arq_event_info *); 122static void ixl_config_rss(struct ixl_vsi *); 123static void ixl_set_queue_rx_itr(struct ixl_queue *); 124static void ixl_set_queue_tx_itr(struct ixl_queue *); 125static int ixl_set_advertised_speeds(struct ixl_pf *, int); 126 127static int ixl_enable_rings(struct ixl_vsi *); 128static int ixl_disable_rings(struct ixl_vsi *); 129static void ixl_enable_intr(struct ixl_vsi *); 130static void ixl_disable_intr(struct ixl_vsi *); 131static void ixl_disable_rings_intr(struct ixl_vsi *); 132 133static void ixl_enable_adminq(struct i40e_hw *); 134static void ixl_disable_adminq(struct i40e_hw *); 135static void ixl_enable_queue(struct i40e_hw *, int); 136static void ixl_disable_queue(struct i40e_hw *, int); 137static void ixl_enable_legacy(struct i40e_hw *); 138static void ixl_disable_legacy(struct i40e_hw *); 139 140static void ixl_set_promisc(struct ixl_vsi *); 141static void ixl_add_multi(struct ixl_vsi *); 142static void ixl_del_multi(struct ixl_vsi *); 143static void ixl_register_vlan(void *, struct ifnet *, u16); 144static void ixl_unregister_vlan(void *, struct ifnet *, u16); 145static void ixl_setup_vlan_filters(struct ixl_vsi *); 146 147static void ixl_init_filters(struct ixl_vsi *); 148static void ixl_reconfigure_filters(struct ixl_vsi *vsi); 149static void ixl_add_filter(struct ixl_vsi *, u8 *, s16 vlan); 150static void ixl_del_filter(struct ixl_vsi *, u8 *, s16 vlan); 151static void ixl_add_hw_filters(struct ixl_vsi *, int, int); 152static void ixl_del_hw_filters(struct ixl_vsi *, int); 153static struct ixl_mac_filter * 154 ixl_find_filter(struct ixl_vsi *, u8 *, s16); 155static void ixl_add_mc_filter(struct ixl_vsi *, u8 *); 156static void ixl_free_mac_filters(struct ixl_vsi *vsi); 157 158 159/* Sysctl debug interface */ 160static int ixl_debug_info(SYSCTL_HANDLER_ARGS); 161static void ixl_print_debug_info(struct ixl_pf *); 162 163/* The MSI/X Interrupt handlers */ 164static void ixl_intr(void *); 165static void ixl_msix_que(void *); 166static void ixl_msix_adminq(void *); 167static void ixl_handle_mdd_event(struct ixl_pf *); 168 169/* Deferred interrupt tasklets */ 170static void ixl_do_adminq(void *, int); 171 172/* Sysctl handlers */ 173static int ixl_set_flowcntl(SYSCTL_HANDLER_ARGS); 174static int ixl_set_advertise(SYSCTL_HANDLER_ARGS); 175static int ixl_current_speed(SYSCTL_HANDLER_ARGS); 176static int ixl_sysctl_show_fw(SYSCTL_HANDLER_ARGS); 177 178/* Statistics */ 179static void ixl_add_hw_stats(struct ixl_pf *); 180static void ixl_add_sysctls_mac_stats(struct sysctl_ctx_list *, 181 struct sysctl_oid_list *, struct i40e_hw_port_stats *); 182static void ixl_add_sysctls_eth_stats(struct sysctl_ctx_list *, 183 struct sysctl_oid_list *, 184 struct i40e_eth_stats *); 185static void ixl_update_stats_counters(struct ixl_pf *); 186static void ixl_update_eth_stats(struct ixl_vsi *); 187static void ixl_update_vsi_stats(struct ixl_vsi *); 188static void ixl_pf_reset_stats(struct ixl_pf *); 189static void ixl_vsi_reset_stats(struct ixl_vsi *); 190static void ixl_stat_update48(struct i40e_hw *, u32, u32, bool, 191 u64 *, u64 *); 192static void ixl_stat_update32(struct i40e_hw *, u32, bool, 193 u64 *, u64 *); 194 195#ifdef IXL_DEBUG_SYSCTL 196static int ixl_sysctl_link_status(SYSCTL_HANDLER_ARGS); 197static int ixl_sysctl_phy_abilities(SYSCTL_HANDLER_ARGS); 198static int ixl_sysctl_sw_filter_list(SYSCTL_HANDLER_ARGS); 199static int ixl_sysctl_hw_res_alloc(SYSCTL_HANDLER_ARGS); 200static int ixl_sysctl_switch_config(SYSCTL_HANDLER_ARGS); 201#endif 202 203#ifdef PCI_IOV 204static int ixl_adminq_err_to_errno(enum i40e_admin_queue_err err); 205 206static int ixl_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t*); 207static void ixl_iov_uninit(device_t dev); 208static int ixl_add_vf(device_t dev, uint16_t vfnum, const nvlist_t*); 209 210static void ixl_handle_vf_msg(struct ixl_pf *, 211 struct i40e_arq_event_info *); 212static void ixl_handle_vflr(void *arg, int pending); 213 214static void ixl_reset_vf(struct ixl_pf *pf, struct ixl_vf *vf); 215static void ixl_reinit_vf(struct ixl_pf *pf, struct ixl_vf *vf); 216#endif 217 218/********************************************************************* 219 * FreeBSD Device Interface Entry Points 220 *********************************************************************/ 221 222static device_method_t ixl_methods[] = { 223 /* Device interface */ 224 DEVMETHOD(device_probe, ixl_probe), 225 DEVMETHOD(device_attach, ixl_attach), 226 DEVMETHOD(device_detach, ixl_detach), 227 DEVMETHOD(device_shutdown, ixl_shutdown), 228#ifdef PCI_IOV 229 DEVMETHOD(pci_iov_init, ixl_iov_init), 230 DEVMETHOD(pci_iov_uninit, ixl_iov_uninit), 231 DEVMETHOD(pci_iov_add_vf, ixl_add_vf), 232#endif 233 {0, 0} 234}; 235 236static driver_t ixl_driver = { 237 "ixl", ixl_methods, sizeof(struct ixl_pf), 238}; 239 240devclass_t ixl_devclass; 241DRIVER_MODULE(ixl, pci, ixl_driver, ixl_devclass, 0, 0); 242 243MODULE_DEPEND(ixl, pci, 1, 1, 1); 244MODULE_DEPEND(ixl, ether, 1, 1, 1); 245#ifdef DEV_NETMAP 246MODULE_DEPEND(ixl, netmap, 1, 1, 1); 247#endif /* DEV_NETMAP */ 248 249/* 250** Global reset mutex 251*/ 252static struct mtx ixl_reset_mtx; 253 254/* 255** TUNEABLE PARAMETERS: 256*/ 257 258static SYSCTL_NODE(_hw, OID_AUTO, ixl, CTLFLAG_RD, 0, 259 "IXL driver parameters"); 260 261/* 262 * MSIX should be the default for best performance, 263 * but this allows it to be forced off for testing. 264 */ 265static int ixl_enable_msix = 1; 266TUNABLE_INT("hw.ixl.enable_msix", &ixl_enable_msix); 267SYSCTL_INT(_hw_ixl, OID_AUTO, enable_msix, CTLFLAG_RDTUN, &ixl_enable_msix, 0, 268 "Enable MSI-X interrupts"); 269 270/* 271** Number of descriptors per ring: 272** - TX and RX are the same size 273*/ 274static int ixl_ringsz = DEFAULT_RING; 275TUNABLE_INT("hw.ixl.ringsz", &ixl_ringsz); 276SYSCTL_INT(_hw_ixl, OID_AUTO, ring_size, CTLFLAG_RDTUN, 277 &ixl_ringsz, 0, "Descriptor Ring Size"); 278 279/* 280** This can be set manually, if left as 0 the 281** number of queues will be calculated based 282** on cpus and msix vectors available. 283*/ 284int ixl_max_queues = 0; 285TUNABLE_INT("hw.ixl.max_queues", &ixl_max_queues); 286SYSCTL_INT(_hw_ixl, OID_AUTO, max_queues, CTLFLAG_RDTUN, 287 &ixl_max_queues, 0, "Number of Queues"); 288 289/* 290** Controls for Interrupt Throttling 291** - true/false for dynamic adjustment 292** - default values for static ITR 293*/ 294int ixl_dynamic_rx_itr = 0; 295TUNABLE_INT("hw.ixl.dynamic_rx_itr", &ixl_dynamic_rx_itr); 296SYSCTL_INT(_hw_ixl, OID_AUTO, dynamic_rx_itr, CTLFLAG_RDTUN, 297 &ixl_dynamic_rx_itr, 0, "Dynamic RX Interrupt Rate"); 298 299int ixl_dynamic_tx_itr = 0; 300TUNABLE_INT("hw.ixl.dynamic_tx_itr", &ixl_dynamic_tx_itr); 301SYSCTL_INT(_hw_ixl, OID_AUTO, dynamic_tx_itr, CTLFLAG_RDTUN, 302 &ixl_dynamic_tx_itr, 0, "Dynamic TX Interrupt Rate"); 303 304int ixl_rx_itr = IXL_ITR_8K; 305TUNABLE_INT("hw.ixl.rx_itr", &ixl_rx_itr); 306SYSCTL_INT(_hw_ixl, OID_AUTO, rx_itr, CTLFLAG_RDTUN, 307 &ixl_rx_itr, 0, "RX Interrupt Rate"); 308 309int ixl_tx_itr = IXL_ITR_4K; 310TUNABLE_INT("hw.ixl.tx_itr", &ixl_tx_itr); 311SYSCTL_INT(_hw_ixl, OID_AUTO, tx_itr, CTLFLAG_RDTUN, 312 &ixl_tx_itr, 0, "TX Interrupt Rate"); 313 314#ifdef IXL_FDIR 315static int ixl_enable_fdir = 1; 316TUNABLE_INT("hw.ixl.enable_fdir", &ixl_enable_fdir); 317/* Rate at which we sample */ 318int ixl_atr_rate = 20; 319TUNABLE_INT("hw.ixl.atr_rate", &ixl_atr_rate); 320#endif 321 322#ifdef DEV_NETMAP 323#define NETMAP_IXL_MAIN /* only bring in one part of the netmap code */ 324#include <dev/netmap/if_ixl_netmap.h> 325#endif /* DEV_NETMAP */ 326 327static char *ixl_fc_string[6] = { 328 "None", 329 "Rx", 330 "Tx", 331 "Full", 332 "Priority", 333 "Default" 334}; 335 336static MALLOC_DEFINE(M_IXL, "ixl", "ixl driver allocations"); 337 338static uint8_t ixl_bcast_addr[ETHER_ADDR_LEN] = 339 {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 340 341/********************************************************************* 342 * Device identification routine 343 * 344 * ixl_probe determines if the driver should be loaded on 345 * the hardware based on PCI vendor/device id of the device. 346 * 347 * return BUS_PROBE_DEFAULT on success, positive on failure 348 *********************************************************************/ 349 350static int 351ixl_probe(device_t dev) 352{ 353 ixl_vendor_info_t *ent; 354 355 u16 pci_vendor_id, pci_device_id; 356 u16 pci_subvendor_id, pci_subdevice_id; 357 char device_name[256]; 358 static bool lock_init = FALSE; 359 360 INIT_DEBUGOUT("ixl_probe: begin"); 361 362 pci_vendor_id = pci_get_vendor(dev); 363 if (pci_vendor_id != I40E_INTEL_VENDOR_ID) 364 return (ENXIO); 365 366 pci_device_id = pci_get_device(dev); 367 pci_subvendor_id = pci_get_subvendor(dev); 368 pci_subdevice_id = pci_get_subdevice(dev); 369 370 ent = ixl_vendor_info_array; 371 while (ent->vendor_id != 0) { 372 if ((pci_vendor_id == ent->vendor_id) && 373 (pci_device_id == ent->device_id) && 374 375 ((pci_subvendor_id == ent->subvendor_id) || 376 (ent->subvendor_id == 0)) && 377 378 ((pci_subdevice_id == ent->subdevice_id) || 379 (ent->subdevice_id == 0))) { 380 sprintf(device_name, "%s, Version - %s", 381 ixl_strings[ent->index], 382 ixl_driver_version); 383 device_set_desc_copy(dev, device_name); 384 /* One shot mutex init */ 385 if (lock_init == FALSE) { 386 lock_init = TRUE; 387 mtx_init(&ixl_reset_mtx, 388 "ixl_reset", 389 "IXL RESET Lock", MTX_DEF); 390 } 391 return (BUS_PROBE_DEFAULT); 392 } 393 ent++; 394 } 395 return (ENXIO); 396} 397 398/********************************************************************* 399 * Device initialization routine 400 * 401 * The attach entry point is called when the driver is being loaded. 402 * This routine identifies the type of hardware, allocates all resources 403 * and initializes the hardware. 404 * 405 * return 0 on success, positive on failure 406 *********************************************************************/ 407 408static int 409ixl_attach(device_t dev) 410{ 411 struct ixl_pf *pf; 412 struct i40e_hw *hw; 413 struct ixl_vsi *vsi; 414 u16 bus; 415 int error = 0; 416#ifdef PCI_IOV 417 nvlist_t *pf_schema, *vf_schema; 418 int iov_error; 419#endif 420 421 INIT_DEBUGOUT("ixl_attach: begin"); 422 423 /* Allocate, clear, and link in our primary soft structure */ 424 pf = device_get_softc(dev); 425 pf->dev = pf->osdep.dev = dev; 426 hw = &pf->hw; 427 428 /* 429 ** Note this assumes we have a single embedded VSI, 430 ** this could be enhanced later to allocate multiple 431 */ 432 vsi = &pf->vsi; 433 vsi->dev = pf->dev; 434 435 /* Core Lock Init*/ 436 IXL_PF_LOCK_INIT(pf, device_get_nameunit(dev)); 437 438 /* Set up the timer callout */ 439 callout_init_mtx(&pf->timer, &pf->pf_mtx, 0); 440 441 /* Set up sysctls */ 442 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 443 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 444 OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW, 445 pf, 0, ixl_set_flowcntl, "I", "Flow Control"); 446 447 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 448 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 449 OID_AUTO, "advertise_speed", CTLTYPE_INT | CTLFLAG_RW, 450 pf, 0, ixl_set_advertise, "I", "Advertised Speed"); 451 452 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 453 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 454 OID_AUTO, "current_speed", CTLTYPE_STRING | CTLFLAG_RD, 455 pf, 0, ixl_current_speed, "A", "Current Port Speed"); 456 457 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 458 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 459 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, 460 pf, 0, ixl_sysctl_show_fw, "A", "Firmware version"); 461 462 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 463 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 464 OID_AUTO, "rx_itr", CTLFLAG_RW, 465 &ixl_rx_itr, IXL_ITR_8K, "RX ITR"); 466 467 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 468 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 469 OID_AUTO, "dynamic_rx_itr", CTLFLAG_RW, 470 &ixl_dynamic_rx_itr, 0, "Dynamic RX ITR"); 471 472 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 473 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 474 OID_AUTO, "tx_itr", CTLFLAG_RW, 475 &ixl_tx_itr, IXL_ITR_4K, "TX ITR"); 476 477 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 478 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 479 OID_AUTO, "dynamic_tx_itr", CTLFLAG_RW, 480 &ixl_dynamic_tx_itr, 0, "Dynamic TX ITR"); 481 482#ifdef IXL_DEBUG_SYSCTL 483 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 484 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 485 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, pf, 0, 486 ixl_debug_info, "I", "Debug Information"); 487 488 /* Debug shared-code message level */ 489 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 490 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 491 OID_AUTO, "debug_mask", CTLFLAG_RW, 492 &pf->hw.debug_mask, 0, "Debug Message Level"); 493 494 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 495 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 496 OID_AUTO, "vc_debug_level", CTLFLAG_RW, &pf->vc_debug_lvl, 497 0, "PF/VF Virtual Channel debug level"); 498 499 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 500 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 501 OID_AUTO, "link_status", CTLTYPE_STRING | CTLFLAG_RD, 502 pf, 0, ixl_sysctl_link_status, "A", "Current Link Status"); 503 504 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 505 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 506 OID_AUTO, "phy_abilities", CTLTYPE_STRING | CTLFLAG_RD, 507 pf, 0, ixl_sysctl_phy_abilities, "A", "PHY Abilities"); 508 509 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 510 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 511 OID_AUTO, "filter_list", CTLTYPE_STRING | CTLFLAG_RD, 512 pf, 0, ixl_sysctl_sw_filter_list, "A", "SW Filter List"); 513 514 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 515 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 516 OID_AUTO, "hw_res_alloc", CTLTYPE_STRING | CTLFLAG_RD, 517 pf, 0, ixl_sysctl_hw_res_alloc, "A", "HW Resource Allocation"); 518 519 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 520 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 521 OID_AUTO, "switch_config", CTLTYPE_STRING | CTLFLAG_RD, 522 pf, 0, ixl_sysctl_switch_config, "A", "HW Switch Configuration"); 523#endif 524 525 /* Save off the PCI information */ 526 hw->vendor_id = pci_get_vendor(dev); 527 hw->device_id = pci_get_device(dev); 528 hw->revision_id = pci_read_config(dev, PCIR_REVID, 1); 529 hw->subsystem_vendor_id = 530 pci_read_config(dev, PCIR_SUBVEND_0, 2); 531 hw->subsystem_device_id = 532 pci_read_config(dev, PCIR_SUBDEV_0, 2); 533 534 hw->bus.device = pci_get_slot(dev); 535 hw->bus.func = pci_get_function(dev); 536 537 pf->vc_debug_lvl = 1; 538 539 /* Do PCI setup - map BAR0, etc */ 540 if (ixl_allocate_pci_resources(pf)) { 541 device_printf(dev, "Allocation of PCI resources failed\n"); 542 error = ENXIO; 543 goto err_out; 544 } 545 546 /* Establish a clean starting point */ 547 i40e_clear_hw(hw); 548 error = i40e_pf_reset(hw); 549 if (error) { 550 device_printf(dev,"PF reset failure %x\n", error); 551 error = EIO; 552 goto err_out; 553 } 554 555 /* Set admin queue parameters */ 556 hw->aq.num_arq_entries = IXL_AQ_LEN; 557 hw->aq.num_asq_entries = IXL_AQ_LEN; 558 hw->aq.arq_buf_size = IXL_AQ_BUFSZ; 559 hw->aq.asq_buf_size = IXL_AQ_BUFSZ; 560 561 /* Initialize the shared code */ 562 error = i40e_init_shared_code(hw); 563 if (error) { 564 device_printf(dev,"Unable to initialize the shared code\n"); 565 error = EIO; 566 goto err_out; 567 } 568 569 /* Set up the admin queue */ 570 error = i40e_init_adminq(hw); 571 if (error) { 572 device_printf(dev, "The driver for the device stopped " 573 "because the NVM image is newer than expected.\n" 574 "You must install the most recent version of " 575 " the network driver.\n"); 576 goto err_out; 577 } 578 device_printf(dev, "%s\n", ixl_fw_version_str(hw)); 579 580 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 581 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR) 582 device_printf(dev, "The driver for the device detected " 583 "a newer version of the NVM image than expected.\n" 584 "Please install the most recent version of the network driver.\n"); 585 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR || 586 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1)) 587 device_printf(dev, "The driver for the device detected " 588 "an older version of the NVM image than expected.\n" 589 "Please update the NVM image.\n"); 590 591 /* Clear PXE mode */ 592 i40e_clear_pxe_mode(hw); 593 594 /* Get capabilities from the device */ 595 error = ixl_get_hw_capabilities(pf); 596 if (error) { 597 device_printf(dev, "HW capabilities failure!\n"); 598 goto err_get_cap; 599 } 600 601 /* Set up host memory cache */ 602 error = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp, 603 hw->func_caps.num_rx_qp, 0, 0); 604 if (error) { 605 device_printf(dev, "init_lan_hmc failed: %d\n", error); 606 goto err_get_cap; 607 } 608 609 error = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY); 610 if (error) { 611 device_printf(dev, "configure_lan_hmc failed: %d\n", error); 612 goto err_mac_hmc; 613 } 614 615 /* Disable LLDP from the firmware */ 616 i40e_aq_stop_lldp(hw, TRUE, NULL); 617 618 i40e_get_mac_addr(hw, hw->mac.addr); 619 error = i40e_validate_mac_addr(hw->mac.addr); 620 if (error) { 621 device_printf(dev, "validate_mac_addr failed: %d\n", error); 622 goto err_mac_hmc; 623 } 624 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHER_ADDR_LEN); 625 i40e_get_port_mac_addr(hw, hw->mac.port_addr); 626 627 /* Set up VSI and queues */ 628 if (ixl_setup_stations(pf) != 0) { 629 device_printf(dev, "setup stations failed!\n"); 630 error = ENOMEM; 631 goto err_mac_hmc; 632 } 633 634 /* Initialize mac filter list for VSI */ 635 SLIST_INIT(&vsi->ftl); 636 637 /* Set up interrupt routing here */ 638 if (pf->msix > 1) 639 error = ixl_assign_vsi_msix(pf); 640 else 641 error = ixl_assign_vsi_legacy(pf); 642 if (error) 643 goto err_mac_hmc; 644 645 if (((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver < 33)) || 646 (hw->aq.fw_maj_ver < 4)) { 647 i40e_msec_delay(75); 648 error = i40e_aq_set_link_restart_an(hw, TRUE, NULL); 649 if (error) 650 device_printf(dev, "link restart failed, aq_err=%d\n", 651 pf->hw.aq.asq_last_status); 652 } 653 654 /* Determine link state */ 655 i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 656 i40e_get_link_status(hw, &pf->link_up); 657 658 /* Setup OS specific network interface */ 659 if (ixl_setup_interface(dev, vsi) != 0) { 660 device_printf(dev, "interface setup failed!\n"); 661 error = EIO; 662 goto err_late; 663 } 664 665 error = ixl_switch_config(pf); 666 if (error) { 667 device_printf(dev, "Initial switch config failed: %d\n", error); 668 goto err_late; 669 } 670 671 /* Limit phy interrupts to link and modules failure */ 672 error = i40e_aq_set_phy_int_mask(hw, 673 I40E_AQ_EVENT_LINK_UPDOWN | I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL); 674 if (error) 675 device_printf(dev, "set phy mask failed: %d\n", error); 676 677 /* Get the bus configuration and set the shared code */ 678 bus = ixl_get_bus_info(hw, dev); 679 i40e_set_pci_config_data(hw, bus); 680 681 /* Initialize taskqueues */ 682 ixl_init_taskqueues(pf); 683 684 /* Initialize statistics */ 685 ixl_pf_reset_stats(pf); 686 ixl_update_stats_counters(pf); 687 ixl_add_hw_stats(pf); 688 689 /* Register for VLAN events */ 690 vsi->vlan_attach = EVENTHANDLER_REGISTER(vlan_config, 691 ixl_register_vlan, vsi, EVENTHANDLER_PRI_FIRST); 692 vsi->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig, 693 ixl_unregister_vlan, vsi, EVENTHANDLER_PRI_FIRST); 694 695#ifdef PCI_IOV 696 /* SR-IOV is only supported when MSI-X is in use. */ 697 if (pf->msix > 1) { 698 pf_schema = pci_iov_schema_alloc_node(); 699 vf_schema = pci_iov_schema_alloc_node(); 700 pci_iov_schema_add_unicast_mac(vf_schema, "mac-addr", 0, NULL); 701 pci_iov_schema_add_bool(vf_schema, "mac-anti-spoof", 702 IOV_SCHEMA_HASDEFAULT, TRUE); 703 pci_iov_schema_add_bool(vf_schema, "allow-set-mac", 704 IOV_SCHEMA_HASDEFAULT, FALSE); 705 pci_iov_schema_add_bool(vf_schema, "allow-promisc", 706 IOV_SCHEMA_HASDEFAULT, FALSE); 707 708 iov_error = pci_iov_attach(dev, pf_schema, vf_schema); 709 if (iov_error != 0) 710 device_printf(dev, 711 "Failed to initialize SR-IOV (error=%d)\n", 712 iov_error); 713 } 714#endif 715 716#ifdef DEV_NETMAP 717 ixl_netmap_attach(vsi); 718#endif /* DEV_NETMAP */ 719 INIT_DEBUGOUT("ixl_attach: end"); 720 return (0); 721 722err_late: 723 if (vsi->ifp != NULL) 724 if_free(vsi->ifp); 725err_mac_hmc: 726 i40e_shutdown_lan_hmc(hw); 727err_get_cap: 728 i40e_shutdown_adminq(hw); 729err_out: 730 ixl_free_pci_resources(pf); 731 ixl_free_vsi(vsi); 732 IXL_PF_LOCK_DESTROY(pf); 733 return (error); 734} 735 736/********************************************************************* 737 * Device removal routine 738 * 739 * The detach entry point is called when the driver is being removed. 740 * This routine stops the adapter and deallocates all the resources 741 * that were allocated for driver operation. 742 * 743 * return 0 on success, positive on failure 744 *********************************************************************/ 745 746static int 747ixl_detach(device_t dev) 748{ 749 struct ixl_pf *pf = device_get_softc(dev); 750 struct i40e_hw *hw = &pf->hw; 751 struct ixl_vsi *vsi = &pf->vsi; 752 i40e_status status; 753#ifdef PCI_IOV 754 int error; 755#endif 756 757 INIT_DEBUGOUT("ixl_detach: begin"); 758 759 /* Make sure VLANS are not using driver */ 760 if (vsi->ifp->if_vlantrunk != NULL) { 761 device_printf(dev,"Vlan in use, detach first\n"); 762 return (EBUSY); 763 } 764 765#ifdef PCI_IOV 766 error = pci_iov_detach(dev); 767 if (error != 0) { 768 device_printf(dev, "SR-IOV in use; detach first.\n"); 769 return (error); 770 } 771#endif 772 773 ether_ifdetach(vsi->ifp); 774 if (vsi->ifp->if_drv_flags & IFF_DRV_RUNNING) { 775 IXL_PF_LOCK(pf); 776 ixl_stop(pf); 777 IXL_PF_UNLOCK(pf); 778 } 779 780 ixl_free_taskqueues(pf); 781 782 /* Shutdown LAN HMC */ 783 status = i40e_shutdown_lan_hmc(hw); 784 if (status) 785 device_printf(dev, 786 "Shutdown LAN HMC failed with code %d\n", status); 787 788 /* Shutdown admin queue */ 789 status = i40e_shutdown_adminq(hw); 790 if (status) 791 device_printf(dev, 792 "Shutdown Admin queue failed with code %d\n", status); 793 794 /* Unregister VLAN events */ 795 if (vsi->vlan_attach != NULL) 796 EVENTHANDLER_DEREGISTER(vlan_config, vsi->vlan_attach); 797 if (vsi->vlan_detach != NULL) 798 EVENTHANDLER_DEREGISTER(vlan_unconfig, vsi->vlan_detach); 799 800 callout_drain(&pf->timer); 801#ifdef DEV_NETMAP 802 netmap_detach(vsi->ifp); 803#endif /* DEV_NETMAP */ 804 ixl_free_pci_resources(pf); 805 bus_generic_detach(dev); 806 if_free(vsi->ifp); 807 ixl_free_vsi(vsi); 808 IXL_PF_LOCK_DESTROY(pf); 809 return (0); 810} 811 812/********************************************************************* 813 * 814 * Shutdown entry point 815 * 816 **********************************************************************/ 817 818static int 819ixl_shutdown(device_t dev) 820{ 821 struct ixl_pf *pf = device_get_softc(dev); 822 IXL_PF_LOCK(pf); 823 ixl_stop(pf); 824 IXL_PF_UNLOCK(pf); 825 return (0); 826} 827 828 829/********************************************************************* 830 * 831 * Get the hardware capabilities 832 * 833 **********************************************************************/ 834 835static int 836ixl_get_hw_capabilities(struct ixl_pf *pf) 837{ 838 struct i40e_aqc_list_capabilities_element_resp *buf; 839 struct i40e_hw *hw = &pf->hw; 840 device_t dev = pf->dev; 841 int error, len; 842 u16 needed; 843 bool again = TRUE; 844 845 len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp); 846retry: 847 if (!(buf = (struct i40e_aqc_list_capabilities_element_resp *) 848 malloc(len, M_DEVBUF, M_NOWAIT | M_ZERO))) { 849 device_printf(dev, "Unable to allocate cap memory\n"); 850 return (ENOMEM); 851 } 852 853 /* This populates the hw struct */ 854 error = i40e_aq_discover_capabilities(hw, buf, len, 855 &needed, i40e_aqc_opc_list_func_capabilities, NULL); 856 free(buf, M_DEVBUF); 857 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) && 858 (again == TRUE)) { 859 /* retry once with a larger buffer */ 860 again = FALSE; 861 len = needed; 862 goto retry; 863 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) { 864 device_printf(dev, "capability discovery failed: %d\n", 865 pf->hw.aq.asq_last_status); 866 return (ENODEV); 867 } 868 869 /* Capture this PF's starting queue pair */ 870 pf->qbase = hw->func_caps.base_queue; 871 872#ifdef IXL_DEBUG 873 device_printf(dev,"pf_id=%d, num_vfs=%d, msix_pf=%d, " 874 "msix_vf=%d, fd_g=%d, fd_b=%d, tx_qp=%d rx_qp=%d qbase=%d\n", 875 hw->pf_id, hw->func_caps.num_vfs, 876 hw->func_caps.num_msix_vectors, 877 hw->func_caps.num_msix_vectors_vf, 878 hw->func_caps.fd_filters_guaranteed, 879 hw->func_caps.fd_filters_best_effort, 880 hw->func_caps.num_tx_qp, 881 hw->func_caps.num_rx_qp, 882 hw->func_caps.base_queue); 883#endif 884 return (error); 885} 886 887static void 888ixl_cap_txcsum_tso(struct ixl_vsi *vsi, struct ifnet *ifp, int mask) 889{ 890 device_t dev = vsi->dev; 891 892 /* Enable/disable TXCSUM/TSO4 */ 893 if (!(ifp->if_capenable & IFCAP_TXCSUM) 894 && !(ifp->if_capenable & IFCAP_TSO4)) { 895 if (mask & IFCAP_TXCSUM) { 896 ifp->if_capenable |= IFCAP_TXCSUM; 897 /* enable TXCSUM, restore TSO if previously enabled */ 898 if (vsi->flags & IXL_FLAGS_KEEP_TSO4) { 899 vsi->flags &= ~IXL_FLAGS_KEEP_TSO4; 900 ifp->if_capenable |= IFCAP_TSO4; 901 } 902 } 903 else if (mask & IFCAP_TSO4) { 904 ifp->if_capenable |= (IFCAP_TXCSUM | IFCAP_TSO4); 905 vsi->flags &= ~IXL_FLAGS_KEEP_TSO4; 906 device_printf(dev, 907 "TSO4 requires txcsum, enabling both...\n"); 908 } 909 } else if((ifp->if_capenable & IFCAP_TXCSUM) 910 && !(ifp->if_capenable & IFCAP_TSO4)) { 911 if (mask & IFCAP_TXCSUM) 912 ifp->if_capenable &= ~IFCAP_TXCSUM; 913 else if (mask & IFCAP_TSO4) 914 ifp->if_capenable |= IFCAP_TSO4; 915 } else if((ifp->if_capenable & IFCAP_TXCSUM) 916 && (ifp->if_capenable & IFCAP_TSO4)) { 917 if (mask & IFCAP_TXCSUM) { 918 vsi->flags |= IXL_FLAGS_KEEP_TSO4; 919 ifp->if_capenable &= ~(IFCAP_TXCSUM | IFCAP_TSO4); 920 device_printf(dev, 921 "TSO4 requires txcsum, disabling both...\n"); 922 } else if (mask & IFCAP_TSO4) 923 ifp->if_capenable &= ~IFCAP_TSO4; 924 } 925 926 /* Enable/disable TXCSUM_IPV6/TSO6 */ 927 if (!(ifp->if_capenable & IFCAP_TXCSUM_IPV6) 928 && !(ifp->if_capenable & IFCAP_TSO6)) { 929 if (mask & IFCAP_TXCSUM_IPV6) { 930 ifp->if_capenable |= IFCAP_TXCSUM_IPV6; 931 if (vsi->flags & IXL_FLAGS_KEEP_TSO6) { 932 vsi->flags &= ~IXL_FLAGS_KEEP_TSO6; 933 ifp->if_capenable |= IFCAP_TSO6; 934 } 935 } else if (mask & IFCAP_TSO6) { 936 ifp->if_capenable |= (IFCAP_TXCSUM_IPV6 | IFCAP_TSO6); 937 vsi->flags &= ~IXL_FLAGS_KEEP_TSO6; 938 device_printf(dev, 939 "TSO6 requires txcsum6, enabling both...\n"); 940 } 941 } else if((ifp->if_capenable & IFCAP_TXCSUM_IPV6) 942 && !(ifp->if_capenable & IFCAP_TSO6)) { 943 if (mask & IFCAP_TXCSUM_IPV6) 944 ifp->if_capenable &= ~IFCAP_TXCSUM_IPV6; 945 else if (mask & IFCAP_TSO6) 946 ifp->if_capenable |= IFCAP_TSO6; 947 } else if ((ifp->if_capenable & IFCAP_TXCSUM_IPV6) 948 && (ifp->if_capenable & IFCAP_TSO6)) { 949 if (mask & IFCAP_TXCSUM_IPV6) { 950 vsi->flags |= IXL_FLAGS_KEEP_TSO6; 951 ifp->if_capenable &= ~(IFCAP_TXCSUM_IPV6 | IFCAP_TSO6); 952 device_printf(dev, 953 "TSO6 requires txcsum6, disabling both...\n"); 954 } else if (mask & IFCAP_TSO6) 955 ifp->if_capenable &= ~IFCAP_TSO6; 956 } 957} 958 959/********************************************************************* 960 * Ioctl entry point 961 * 962 * ixl_ioctl is called when the user wants to configure the 963 * interface. 964 * 965 * return 0 on success, positive on failure 966 **********************************************************************/ 967 968static int 969ixl_ioctl(struct ifnet * ifp, u_long command, caddr_t data) 970{ 971 struct ixl_vsi *vsi = ifp->if_softc; 972 struct ixl_pf *pf = vsi->back; 973 struct ifreq *ifr = (struct ifreq *) data; 974#if defined(INET) || defined(INET6) 975 struct ifaddr *ifa = (struct ifaddr *)data; 976 bool avoid_reset = FALSE; 977#endif 978 int error = 0; 979 980 switch (command) { 981 982 case SIOCSIFADDR: 983#ifdef INET 984 if (ifa->ifa_addr->sa_family == AF_INET) 985 avoid_reset = TRUE; 986#endif 987#ifdef INET6 988 if (ifa->ifa_addr->sa_family == AF_INET6) 989 avoid_reset = TRUE; 990#endif 991#if defined(INET) || defined(INET6) 992 /* 993 ** Calling init results in link renegotiation, 994 ** so we avoid doing it when possible. 995 */ 996 if (avoid_reset) { 997 ifp->if_flags |= IFF_UP; 998 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 999 ixl_init(pf); 1000#ifdef INET 1001 if (!(ifp->if_flags & IFF_NOARP)) 1002 arp_ifinit(ifp, ifa); 1003#endif 1004 } else 1005 error = ether_ioctl(ifp, command, data); 1006 break; 1007#endif 1008 case SIOCSIFMTU: 1009 IOCTL_DEBUGOUT("ioctl: SIOCSIFMTU (Set Interface MTU)"); 1010 if (ifr->ifr_mtu > IXL_MAX_FRAME - 1011 ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) { 1012 error = EINVAL; 1013 } else { 1014 IXL_PF_LOCK(pf); 1015 ifp->if_mtu = ifr->ifr_mtu; 1016 vsi->max_frame_size = 1017 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN 1018 + ETHER_VLAN_ENCAP_LEN; 1019 ixl_init_locked(pf); 1020 IXL_PF_UNLOCK(pf); 1021 } 1022 break; 1023 case SIOCSIFFLAGS: 1024 IOCTL_DEBUGOUT("ioctl: SIOCSIFFLAGS (Set Interface Flags)"); 1025 IXL_PF_LOCK(pf); 1026 if (ifp->if_flags & IFF_UP) { 1027 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1028 if ((ifp->if_flags ^ pf->if_flags) & 1029 (IFF_PROMISC | IFF_ALLMULTI)) { 1030 ixl_set_promisc(vsi); 1031 } 1032 } else 1033 ixl_init_locked(pf); 1034 } else 1035 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1036 ixl_stop(pf); 1037 pf->if_flags = ifp->if_flags; 1038 IXL_PF_UNLOCK(pf); 1039 break; 1040 case SIOCADDMULTI: 1041 IOCTL_DEBUGOUT("ioctl: SIOCADDMULTI"); 1042 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1043 IXL_PF_LOCK(pf); 1044 ixl_disable_intr(vsi); 1045 ixl_add_multi(vsi); 1046 ixl_enable_intr(vsi); 1047 IXL_PF_UNLOCK(pf); 1048 } 1049 break; 1050 case SIOCDELMULTI: 1051 IOCTL_DEBUGOUT("ioctl: SIOCDELMULTI"); 1052 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1053 IXL_PF_LOCK(pf); 1054 ixl_disable_intr(vsi); 1055 ixl_del_multi(vsi); 1056 ixl_enable_intr(vsi); 1057 IXL_PF_UNLOCK(pf); 1058 } 1059 break; 1060 case SIOCSIFMEDIA: 1061 case SIOCGIFMEDIA: 1062#ifdef IFM_ETH_XTYPE 1063 case SIOCGIFXMEDIA: 1064#endif 1065 IOCTL_DEBUGOUT("ioctl: SIOCxIFMEDIA (Get/Set Interface Media)"); 1066 error = ifmedia_ioctl(ifp, ifr, &vsi->media, command); 1067 break; 1068 case SIOCSIFCAP: 1069 { 1070 int mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1071 IOCTL_DEBUGOUT("ioctl: SIOCSIFCAP (Set Capabilities)"); 1072 1073 ixl_cap_txcsum_tso(vsi, ifp, mask); 1074 1075 if (mask & IFCAP_RXCSUM) 1076 ifp->if_capenable ^= IFCAP_RXCSUM; 1077 if (mask & IFCAP_RXCSUM_IPV6) 1078 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1079 if (mask & IFCAP_LRO) 1080 ifp->if_capenable ^= IFCAP_LRO; 1081 if (mask & IFCAP_VLAN_HWTAGGING) 1082 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1083 if (mask & IFCAP_VLAN_HWFILTER) 1084 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER; 1085 if (mask & IFCAP_VLAN_HWTSO) 1086 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1087 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1088 IXL_PF_LOCK(pf); 1089 ixl_init_locked(pf); 1090 IXL_PF_UNLOCK(pf); 1091 } 1092 VLAN_CAPABILITIES(ifp); 1093 1094 break; 1095 } 1096 1097 default: 1098 IOCTL_DEBUGOUT("ioctl: UNKNOWN (0x%X)\n", (int)command); 1099 error = ether_ioctl(ifp, command, data); 1100 break; 1101 } 1102 1103 return (error); 1104} 1105 1106 1107/********************************************************************* 1108 * Init entry point 1109 * 1110 * This routine is used in two ways. It is used by the stack as 1111 * init entry point in network interface structure. It is also used 1112 * by the driver as a hw/sw initialization routine to get to a 1113 * consistent state. 1114 * 1115 * return 0 on success, positive on failure 1116 **********************************************************************/ 1117 1118static void 1119ixl_init_locked(struct ixl_pf *pf) 1120{ 1121 struct i40e_hw *hw = &pf->hw; 1122 struct ixl_vsi *vsi = &pf->vsi; 1123 struct ifnet *ifp = vsi->ifp; 1124 device_t dev = pf->dev; 1125 struct i40e_filter_control_settings filter; 1126 u8 tmpaddr[ETHER_ADDR_LEN]; 1127 int ret; 1128 1129 mtx_assert(&pf->pf_mtx, MA_OWNED); 1130 INIT_DEBUGOUT("ixl_init: begin"); 1131 ixl_stop(pf); 1132 1133 /* Get the latest mac address... User might use a LAA */ 1134 bcopy(IF_LLADDR(vsi->ifp), tmpaddr, 1135 I40E_ETH_LENGTH_OF_ADDRESS); 1136 if (!cmp_etheraddr(hw->mac.addr, tmpaddr) && 1137 (i40e_validate_mac_addr(tmpaddr) == I40E_SUCCESS)) { 1138 ixl_del_filter(vsi, hw->mac.addr, IXL_VLAN_ANY); 1139 bcopy(tmpaddr, hw->mac.addr, 1140 I40E_ETH_LENGTH_OF_ADDRESS); 1141 ret = i40e_aq_mac_address_write(hw, 1142 I40E_AQC_WRITE_TYPE_LAA_ONLY, 1143 hw->mac.addr, NULL); 1144 if (ret) { 1145 device_printf(dev, "LLA address" 1146 "change failed!!\n"); 1147 return; 1148 } else { 1149 ixl_add_filter(vsi, hw->mac.addr, IXL_VLAN_ANY); 1150 } 1151 } 1152 1153 /* Set the various hardware offload abilities */ 1154 ifp->if_hwassist = 0; 1155 if (ifp->if_capenable & IFCAP_TSO) 1156 ifp->if_hwassist |= CSUM_TSO; 1157 if (ifp->if_capenable & IFCAP_TXCSUM) 1158 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP); 1159 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6) 1160 ifp->if_hwassist |= (CSUM_TCP_IPV6 | CSUM_UDP_IPV6); 1161 1162 /* Set up the device filtering */ 1163 bzero(&filter, sizeof(filter)); 1164 filter.enable_ethtype = TRUE; 1165 filter.enable_macvlan = TRUE; 1166#ifdef IXL_FDIR 1167 filter.enable_fdir = TRUE; 1168#endif 1169 if (i40e_set_filter_control(hw, &filter)) 1170 device_printf(dev, "set_filter_control() failed\n"); 1171 1172 /* Set up RSS */ 1173 ixl_config_rss(vsi); 1174 1175 /* 1176 ** Prepare the VSI: rings, hmc contexts, etc... 1177 */ 1178 if (ixl_initialize_vsi(vsi)) { 1179 device_printf(dev, "initialize vsi failed!!\n"); 1180 return; 1181 } 1182 1183 /* Add protocol filters to list */ 1184 ixl_init_filters(vsi); 1185 1186 /* Setup vlan's if needed */ 1187 ixl_setup_vlan_filters(vsi); 1188 1189 /* Start the local timer */ 1190 callout_reset(&pf->timer, hz, ixl_local_timer, pf); 1191 1192 /* Set up MSI/X routing and the ITR settings */ 1193 if (ixl_enable_msix) { 1194 ixl_configure_msix(pf); 1195 ixl_configure_itr(pf); 1196 } else 1197 ixl_configure_legacy(pf); 1198 1199 ixl_enable_rings(vsi); 1200 1201 i40e_aq_set_default_vsi(hw, vsi->seid, NULL); 1202 1203 ixl_reconfigure_filters(vsi); 1204 1205 /* Set MTU in hardware*/ 1206 int aq_error = i40e_aq_set_mac_config(hw, vsi->max_frame_size, 1207 TRUE, 0, NULL); 1208 if (aq_error) 1209 device_printf(vsi->dev, 1210 "aq_set_mac_config in init error, code %d\n", 1211 aq_error); 1212 1213 /* And now turn on interrupts */ 1214 ixl_enable_intr(vsi); 1215 1216 /* Now inform the stack we're ready */ 1217 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1218 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1219 1220 return; 1221} 1222 1223static void 1224ixl_init(void *arg) 1225{ 1226 struct ixl_pf *pf = arg; 1227 1228 IXL_PF_LOCK(pf); 1229 ixl_init_locked(pf); 1230 IXL_PF_UNLOCK(pf); 1231 return; 1232} 1233 1234/* 1235** 1236** MSIX Interrupt Handlers and Tasklets 1237** 1238*/ 1239static void 1240ixl_handle_que(void *context, int pending) 1241{ 1242 struct ixl_queue *que = context; 1243 struct ixl_vsi *vsi = que->vsi; 1244 struct i40e_hw *hw = vsi->hw; 1245 struct tx_ring *txr = &que->txr; 1246 struct ifnet *ifp = vsi->ifp; 1247 bool more; 1248 1249 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1250 more = ixl_rxeof(que, IXL_RX_LIMIT); 1251 IXL_TX_LOCK(txr); 1252 ixl_txeof(que); 1253 if (!drbr_empty(ifp, txr->br)) 1254 ixl_mq_start_locked(ifp, txr); 1255 IXL_TX_UNLOCK(txr); 1256 if (more) { 1257 taskqueue_enqueue(que->tq, &que->task); 1258 return; 1259 } 1260 } 1261 1262 /* Reenable this interrupt - hmmm */ 1263 ixl_enable_queue(hw, que->me); 1264 return; 1265} 1266 1267 1268/********************************************************************* 1269 * 1270 * Legacy Interrupt Service routine 1271 * 1272 **********************************************************************/ 1273void 1274ixl_intr(void *arg) 1275{ 1276 struct ixl_pf *pf = arg; 1277 struct i40e_hw *hw = &pf->hw; 1278 struct ixl_vsi *vsi = &pf->vsi; 1279 struct ixl_queue *que = vsi->queues; 1280 struct ifnet *ifp = vsi->ifp; 1281 struct tx_ring *txr = &que->txr; 1282 u32 reg, icr0, mask; 1283 bool more_tx, more_rx; 1284 1285 ++que->irqs; 1286 1287 /* Protect against spurious interrupts */ 1288 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1289 return; 1290 1291 icr0 = rd32(hw, I40E_PFINT_ICR0); 1292 1293 reg = rd32(hw, I40E_PFINT_DYN_CTL0); 1294 reg = reg | I40E_PFINT_DYN_CTL0_CLEARPBA_MASK; 1295 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 1296 1297 mask = rd32(hw, I40E_PFINT_ICR0_ENA); 1298 1299#ifdef PCI_IOV 1300 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) 1301 taskqueue_enqueue(pf->tq, &pf->vflr_task); 1302#endif 1303 1304 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) { 1305 taskqueue_enqueue(pf->tq, &pf->adminq); 1306 return; 1307 } 1308 1309 more_rx = ixl_rxeof(que, IXL_RX_LIMIT); 1310 1311 IXL_TX_LOCK(txr); 1312 more_tx = ixl_txeof(que); 1313 if (!drbr_empty(vsi->ifp, txr->br)) 1314 more_tx = 1; 1315 IXL_TX_UNLOCK(txr); 1316 1317 /* re-enable other interrupt causes */ 1318 wr32(hw, I40E_PFINT_ICR0_ENA, mask); 1319 1320 /* And now the queues */ 1321 reg = rd32(hw, I40E_QINT_RQCTL(0)); 1322 reg |= I40E_QINT_RQCTL_CAUSE_ENA_MASK; 1323 wr32(hw, I40E_QINT_RQCTL(0), reg); 1324 1325 reg = rd32(hw, I40E_QINT_TQCTL(0)); 1326 reg |= I40E_QINT_TQCTL_CAUSE_ENA_MASK; 1327 reg &= ~I40E_PFINT_ICR0_INTEVENT_MASK; 1328 wr32(hw, I40E_QINT_TQCTL(0), reg); 1329 1330 ixl_enable_legacy(hw); 1331 1332 return; 1333} 1334 1335 1336/********************************************************************* 1337 * 1338 * MSIX VSI Interrupt Service routine 1339 * 1340 **********************************************************************/ 1341void 1342ixl_msix_que(void *arg) 1343{ 1344 struct ixl_queue *que = arg; 1345 struct ixl_vsi *vsi = que->vsi; 1346 struct i40e_hw *hw = vsi->hw; 1347 struct tx_ring *txr = &que->txr; 1348 bool more_tx, more_rx; 1349 1350 /* Protect against spurious interrupts */ 1351 if (!(vsi->ifp->if_drv_flags & IFF_DRV_RUNNING)) 1352 return; 1353 1354 ++que->irqs; 1355 1356 more_rx = ixl_rxeof(que, IXL_RX_LIMIT); 1357 1358 IXL_TX_LOCK(txr); 1359 more_tx = ixl_txeof(que); 1360 /* 1361 ** Make certain that if the stack 1362 ** has anything queued the task gets 1363 ** scheduled to handle it. 1364 */ 1365 if (!drbr_empty(vsi->ifp, txr->br)) 1366 more_tx = 1; 1367 IXL_TX_UNLOCK(txr); 1368 1369 ixl_set_queue_rx_itr(que); 1370 ixl_set_queue_tx_itr(que); 1371 1372 if (more_tx || more_rx) 1373 taskqueue_enqueue(que->tq, &que->task); 1374 else 1375 ixl_enable_queue(hw, que->me); 1376 1377 return; 1378} 1379 1380 1381/********************************************************************* 1382 * 1383 * MSIX Admin Queue Interrupt Service routine 1384 * 1385 **********************************************************************/ 1386static void 1387ixl_msix_adminq(void *arg) 1388{ 1389 struct ixl_pf *pf = arg; 1390 struct i40e_hw *hw = &pf->hw; 1391 u32 reg, mask; 1392 1393 ++pf->admin_irq; 1394 1395 reg = rd32(hw, I40E_PFINT_ICR0); 1396 mask = rd32(hw, I40E_PFINT_ICR0_ENA); 1397 1398 /* Check on the cause */ 1399 if (reg & I40E_PFINT_ICR0_ADMINQ_MASK) 1400 mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK; 1401 1402 if (reg & I40E_PFINT_ICR0_MAL_DETECT_MASK) { 1403 ixl_handle_mdd_event(pf); 1404 mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK; 1405 } 1406 1407#ifdef PCI_IOV 1408 if (reg & I40E_PFINT_ICR0_VFLR_MASK) { 1409 mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK; 1410 taskqueue_enqueue(pf->tq, &pf->vflr_task); 1411 } 1412#endif 1413 1414 reg = rd32(hw, I40E_PFINT_DYN_CTL0); 1415 reg = reg | I40E_PFINT_DYN_CTL0_CLEARPBA_MASK; 1416 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 1417 1418 taskqueue_enqueue(pf->tq, &pf->adminq); 1419 return; 1420} 1421 1422/********************************************************************* 1423 * 1424 * Media Ioctl callback 1425 * 1426 * This routine is called whenever the user queries the status of 1427 * the interface using ifconfig. 1428 * 1429 **********************************************************************/ 1430static void 1431ixl_media_status(struct ifnet * ifp, struct ifmediareq * ifmr) 1432{ 1433 struct ixl_vsi *vsi = ifp->if_softc; 1434 struct ixl_pf *pf = vsi->back; 1435 struct i40e_hw *hw = &pf->hw; 1436 1437 INIT_DEBUGOUT("ixl_media_status: begin"); 1438 IXL_PF_LOCK(pf); 1439 1440 hw->phy.get_link_info = TRUE; 1441 i40e_get_link_status(hw, &pf->link_up); 1442 ixl_update_link_status(pf); 1443 1444 ifmr->ifm_status = IFM_AVALID; 1445 ifmr->ifm_active = IFM_ETHER; 1446 1447 if (!pf->link_up) { 1448 IXL_PF_UNLOCK(pf); 1449 return; 1450 } 1451 1452 ifmr->ifm_status |= IFM_ACTIVE; 1453 1454 /* Hardware always does full-duplex */ 1455 ifmr->ifm_active |= IFM_FDX; 1456 1457 switch (hw->phy.link_info.phy_type) { 1458 /* 100 M */ 1459 case I40E_PHY_TYPE_100BASE_TX: 1460 ifmr->ifm_active |= IFM_100_TX; 1461 break; 1462 /* 1 G */ 1463 case I40E_PHY_TYPE_1000BASE_T: 1464 ifmr->ifm_active |= IFM_1000_T; 1465 break; 1466 case I40E_PHY_TYPE_1000BASE_SX: 1467 ifmr->ifm_active |= IFM_1000_SX; 1468 break; 1469 case I40E_PHY_TYPE_1000BASE_LX: 1470 ifmr->ifm_active |= IFM_1000_LX; 1471 break; 1472 /* 10 G */ 1473 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1474 ifmr->ifm_active |= IFM_10G_TWINAX; 1475 break; 1476 case I40E_PHY_TYPE_10GBASE_SR: 1477 ifmr->ifm_active |= IFM_10G_SR; 1478 break; 1479 case I40E_PHY_TYPE_10GBASE_LR: 1480 ifmr->ifm_active |= IFM_10G_LR; 1481 break; 1482 case I40E_PHY_TYPE_10GBASE_T: 1483 ifmr->ifm_active |= IFM_10G_T; 1484 break; 1485 /* 40 G */ 1486 case I40E_PHY_TYPE_40GBASE_CR4: 1487 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1488 ifmr->ifm_active |= IFM_40G_CR4; 1489 break; 1490 case I40E_PHY_TYPE_40GBASE_SR4: 1491 ifmr->ifm_active |= IFM_40G_SR4; 1492 break; 1493 case I40E_PHY_TYPE_40GBASE_LR4: 1494 ifmr->ifm_active |= IFM_40G_LR4; 1495 break; 1496#ifndef IFM_ETH_XTYPE 1497 case I40E_PHY_TYPE_1000BASE_KX: 1498 ifmr->ifm_active |= IFM_1000_CX; 1499 break; 1500 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1501 case I40E_PHY_TYPE_10GBASE_CR1: 1502 ifmr->ifm_active |= IFM_10G_TWINAX; 1503 break; 1504 case I40E_PHY_TYPE_10GBASE_KX4: 1505 ifmr->ifm_active |= IFM_10G_CX4; 1506 break; 1507 case I40E_PHY_TYPE_10GBASE_KR: 1508 ifmr->ifm_active |= IFM_10G_SR; 1509 break; 1510 case I40E_PHY_TYPE_40GBASE_KR4: 1511 case I40E_PHY_TYPE_XLPPI: 1512 ifmr->ifm_active |= IFM_40G_SR4; 1513 break; 1514#else 1515 case I40E_PHY_TYPE_1000BASE_KX: 1516 ifmr->ifm_active |= IFM_1000_KX; 1517 break; 1518 /* ERJ: What's the difference between these? */ 1519 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1520 case I40E_PHY_TYPE_10GBASE_CR1: 1521 ifmr->ifm_active |= IFM_10G_CR1; 1522 break; 1523 case I40E_PHY_TYPE_10GBASE_KX4: 1524 ifmr->ifm_active |= IFM_10G_KX4; 1525 break; 1526 case I40E_PHY_TYPE_10GBASE_KR: 1527 ifmr->ifm_active |= IFM_10G_KR; 1528 break; 1529 /* Our single 20G media type */ 1530 case I40E_PHY_TYPE_20GBASE_KR2: 1531 ifmr->ifm_active |= IFM_20G_KR2; 1532 break; 1533 case I40E_PHY_TYPE_40GBASE_KR4: 1534 ifmr->ifm_active |= IFM_40G_KR4; 1535 break; 1536 case I40E_PHY_TYPE_XLPPI: 1537 ifmr->ifm_active |= IFM_40G_XLPPI; 1538 break; 1539#endif 1540 default: 1541 ifmr->ifm_active |= IFM_UNKNOWN; 1542 break; 1543 } 1544 /* Report flow control status as well */ 1545 if (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) 1546 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 1547 if (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX) 1548 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 1549 1550 IXL_PF_UNLOCK(pf); 1551 1552 return; 1553} 1554 1555/* 1556 * NOTE: Fortville does not support forcing media speeds. Instead, 1557 * use the set_advertise sysctl to set the speeds Fortville 1558 * will advertise or be allowed to operate at. 1559 */ 1560static int 1561ixl_media_change(struct ifnet * ifp) 1562{ 1563 struct ixl_vsi *vsi = ifp->if_softc; 1564 struct ifmedia *ifm = &vsi->media; 1565 1566 INIT_DEBUGOUT("ixl_media_change: begin"); 1567 1568 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1569 return (EINVAL); 1570 1571 if_printf(ifp, "Media change is not supported.\n"); 1572 1573 return (ENODEV); 1574} 1575 1576 1577#ifdef IXL_FDIR 1578/* 1579** ATR: Application Targetted Receive - creates a filter 1580** based on TX flow info that will keep the receive 1581** portion of the flow on the same queue. Based on the 1582** implementation this is only available for TCP connections 1583*/ 1584void 1585ixl_atr(struct ixl_queue *que, struct tcphdr *th, int etype) 1586{ 1587 struct ixl_vsi *vsi = que->vsi; 1588 struct tx_ring *txr = &que->txr; 1589 struct i40e_filter_program_desc *FDIR; 1590 u32 ptype, dtype; 1591 int idx; 1592 1593 /* check if ATR is enabled and sample rate */ 1594 if ((!ixl_enable_fdir) || (!txr->atr_rate)) 1595 return; 1596 /* 1597 ** We sample all TCP SYN/FIN packets, 1598 ** or at the selected sample rate 1599 */ 1600 txr->atr_count++; 1601 if (((th->th_flags & (TH_FIN | TH_SYN)) == 0) && 1602 (txr->atr_count < txr->atr_rate)) 1603 return; 1604 txr->atr_count = 0; 1605 1606 /* Get a descriptor to use */ 1607 idx = txr->next_avail; 1608 FDIR = (struct i40e_filter_program_desc *) &txr->base[idx]; 1609 if (++idx == que->num_desc) 1610 idx = 0; 1611 txr->avail--; 1612 txr->next_avail = idx; 1613 1614 ptype = (que->me << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) & 1615 I40E_TXD_FLTR_QW0_QINDEX_MASK; 1616 1617 ptype |= (etype == ETHERTYPE_IP) ? 1618 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP << 1619 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) : 1620 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP << 1621 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); 1622 1623 ptype |= vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; 1624 1625 dtype = I40E_TX_DESC_DTYPE_FILTER_PROG; 1626 1627 /* 1628 ** We use the TCP TH_FIN as a trigger to remove 1629 ** the filter, otherwise its an update. 1630 */ 1631 dtype |= (th->th_flags & TH_FIN) ? 1632 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << 1633 I40E_TXD_FLTR_QW1_PCMD_SHIFT) : 1634 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << 1635 I40E_TXD_FLTR_QW1_PCMD_SHIFT); 1636 1637 dtype |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX << 1638 I40E_TXD_FLTR_QW1_DEST_SHIFT; 1639 1640 dtype |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID << 1641 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT; 1642 1643 FDIR->qindex_flex_ptype_vsi = htole32(ptype); 1644 FDIR->dtype_cmd_cntindex = htole32(dtype); 1645 return; 1646} 1647#endif 1648 1649 1650static void 1651ixl_set_promisc(struct ixl_vsi *vsi) 1652{ 1653 struct ifnet *ifp = vsi->ifp; 1654 struct i40e_hw *hw = vsi->hw; 1655 int err, mcnt = 0; 1656 bool uni = FALSE, multi = FALSE; 1657 1658 if (ifp->if_flags & IFF_ALLMULTI) 1659 multi = TRUE; 1660 else { /* Need to count the multicast addresses */ 1661 struct ifmultiaddr *ifma; 1662 if_maddr_rlock(ifp); 1663 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1664 if (ifma->ifma_addr->sa_family != AF_LINK) 1665 continue; 1666 if (mcnt == MAX_MULTICAST_ADDR) 1667 break; 1668 mcnt++; 1669 } 1670 if_maddr_runlock(ifp); 1671 } 1672 1673 if (mcnt >= MAX_MULTICAST_ADDR) 1674 multi = TRUE; 1675 if (ifp->if_flags & IFF_PROMISC) 1676 uni = TRUE; 1677 1678 err = i40e_aq_set_vsi_unicast_promiscuous(hw, 1679 vsi->seid, uni, NULL); 1680 err = i40e_aq_set_vsi_multicast_promiscuous(hw, 1681 vsi->seid, multi, NULL); 1682 return; 1683} 1684 1685/********************************************************************* 1686 * Filter Routines 1687 * 1688 * Routines for multicast and vlan filter management. 1689 * 1690 *********************************************************************/ 1691static void 1692ixl_add_multi(struct ixl_vsi *vsi) 1693{ 1694 struct ifmultiaddr *ifma; 1695 struct ifnet *ifp = vsi->ifp; 1696 struct i40e_hw *hw = vsi->hw; 1697 int mcnt = 0, flags; 1698 1699 IOCTL_DEBUGOUT("ixl_add_multi: begin"); 1700 1701 if_maddr_rlock(ifp); 1702 /* 1703 ** First just get a count, to decide if we 1704 ** we simply use multicast promiscuous. 1705 */ 1706 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1707 if (ifma->ifma_addr->sa_family != AF_LINK) 1708 continue; 1709 mcnt++; 1710 } 1711 if_maddr_runlock(ifp); 1712 1713 if (__predict_false(mcnt >= MAX_MULTICAST_ADDR)) { 1714 /* delete existing MC filters */ 1715 ixl_del_hw_filters(vsi, mcnt); 1716 i40e_aq_set_vsi_multicast_promiscuous(hw, 1717 vsi->seid, TRUE, NULL); 1718 return; 1719 } 1720 1721 mcnt = 0; 1722 if_maddr_rlock(ifp); 1723 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1724 if (ifma->ifma_addr->sa_family != AF_LINK) 1725 continue; 1726 ixl_add_mc_filter(vsi, 1727 (u8*)LLADDR((struct sockaddr_dl *) ifma->ifma_addr)); 1728 mcnt++; 1729 } 1730 if_maddr_runlock(ifp); 1731 if (mcnt > 0) { 1732 flags = (IXL_FILTER_ADD | IXL_FILTER_USED | IXL_FILTER_MC); 1733 ixl_add_hw_filters(vsi, flags, mcnt); 1734 } 1735 1736 IOCTL_DEBUGOUT("ixl_add_multi: end"); 1737 return; 1738} 1739 1740static void 1741ixl_del_multi(struct ixl_vsi *vsi) 1742{ 1743 struct ifnet *ifp = vsi->ifp; 1744 struct ifmultiaddr *ifma; 1745 struct ixl_mac_filter *f; 1746 int mcnt = 0; 1747 bool match = FALSE; 1748 1749 IOCTL_DEBUGOUT("ixl_del_multi: begin"); 1750 1751 /* Search for removed multicast addresses */ 1752 if_maddr_rlock(ifp); 1753 SLIST_FOREACH(f, &vsi->ftl, next) { 1754 if ((f->flags & IXL_FILTER_USED) && (f->flags & IXL_FILTER_MC)) { 1755 match = FALSE; 1756 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1757 if (ifma->ifma_addr->sa_family != AF_LINK) 1758 continue; 1759 u8 *mc_addr = (u8 *)LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1760 if (cmp_etheraddr(f->macaddr, mc_addr)) { 1761 match = TRUE; 1762 break; 1763 } 1764 } 1765 if (match == FALSE) { 1766 f->flags |= IXL_FILTER_DEL; 1767 mcnt++; 1768 } 1769 } 1770 } 1771 if_maddr_runlock(ifp); 1772 1773 if (mcnt > 0) 1774 ixl_del_hw_filters(vsi, mcnt); 1775} 1776 1777 1778/********************************************************************* 1779 * Timer routine 1780 * 1781 * This routine checks for link status,updates statistics, 1782 * and runs the watchdog check. 1783 * 1784 **********************************************************************/ 1785 1786static void 1787ixl_local_timer(void *arg) 1788{ 1789 struct ixl_pf *pf = arg; 1790 struct i40e_hw *hw = &pf->hw; 1791 struct ixl_vsi *vsi = &pf->vsi; 1792 struct ixl_queue *que = vsi->queues; 1793 device_t dev = pf->dev; 1794 int hung = 0; 1795 u32 mask; 1796 1797 mtx_assert(&pf->pf_mtx, MA_OWNED); 1798 1799 /* Fire off the adminq task */ 1800 taskqueue_enqueue(pf->tq, &pf->adminq); 1801 1802 /* Update stats */ 1803 ixl_update_stats_counters(pf); 1804 1805 /* 1806 ** Check status of the queues 1807 */ 1808 mask = (I40E_PFINT_DYN_CTLN_INTENA_MASK | 1809 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK); 1810 1811 for (int i = 0; i < vsi->num_queues; i++,que++) { 1812 /* Any queues with outstanding work get a sw irq */ 1813 if (que->busy) 1814 wr32(hw, I40E_PFINT_DYN_CTLN(que->me), mask); 1815 /* 1816 ** Each time txeof runs without cleaning, but there 1817 ** are uncleaned descriptors it increments busy. If 1818 ** we get to 5 we declare it hung. 1819 */ 1820 if (que->busy == IXL_QUEUE_HUNG) { 1821 ++hung; 1822 /* Mark the queue as inactive */ 1823 vsi->active_queues &= ~((u64)1 << que->me); 1824 continue; 1825 } else { 1826 /* Check if we've come back from hung */ 1827 if ((vsi->active_queues & ((u64)1 << que->me)) == 0) 1828 vsi->active_queues |= ((u64)1 << que->me); 1829 } 1830 if (que->busy >= IXL_MAX_TX_BUSY) { 1831#ifdef IXL_DEBUG 1832 device_printf(dev,"Warning queue %d " 1833 "appears to be hung!\n", i); 1834#endif 1835 que->busy = IXL_QUEUE_HUNG; 1836 ++hung; 1837 } 1838 } 1839 /* Only reinit if all queues show hung */ 1840 if (hung == vsi->num_queues) 1841 goto hung; 1842 1843 callout_reset(&pf->timer, hz, ixl_local_timer, pf); 1844 return; 1845 1846hung: 1847 device_printf(dev, "Local Timer: HANG DETECT - Resetting!!\n"); 1848 ixl_init_locked(pf); 1849} 1850 1851/* 1852** Note: this routine updates the OS on the link state 1853** the real check of the hardware only happens with 1854** a link interrupt. 1855*/ 1856static void 1857ixl_update_link_status(struct ixl_pf *pf) 1858{ 1859 struct ixl_vsi *vsi = &pf->vsi; 1860 struct i40e_hw *hw = &pf->hw; 1861 struct ifnet *ifp = vsi->ifp; 1862 device_t dev = pf->dev; 1863 1864 if (pf->link_up){ 1865 if (vsi->link_active == FALSE) { 1866 pf->fc = hw->fc.current_mode; 1867 if (bootverbose) { 1868 device_printf(dev,"Link is up %d Gbps %s," 1869 " Flow Control: %s\n", 1870 ((pf->link_speed == 1871 I40E_LINK_SPEED_40GB)? 40:10), 1872 "Full Duplex", ixl_fc_string[pf->fc]); 1873 } 1874 vsi->link_active = TRUE; 1875 /* 1876 ** Warn user if link speed on NPAR enabled 1877 ** partition is not at least 10GB 1878 */ 1879 if (hw->func_caps.npar_enable && 1880 (hw->phy.link_info.link_speed == 1881 I40E_LINK_SPEED_1GB || 1882 hw->phy.link_info.link_speed == 1883 I40E_LINK_SPEED_100MB)) 1884 device_printf(dev, "The partition detected" 1885 "link speed that is less than 10Gbps\n"); 1886 if_link_state_change(ifp, LINK_STATE_UP); 1887 } 1888 } else { /* Link down */ 1889 if (vsi->link_active == TRUE) { 1890 if (bootverbose) 1891 device_printf(dev,"Link is Down\n"); 1892 if_link_state_change(ifp, LINK_STATE_DOWN); 1893 vsi->link_active = FALSE; 1894 } 1895 } 1896 1897 return; 1898} 1899 1900/********************************************************************* 1901 * 1902 * This routine disables all traffic on the adapter by issuing a 1903 * global reset on the MAC and deallocates TX/RX buffers. 1904 * 1905 **********************************************************************/ 1906 1907static void 1908ixl_stop(struct ixl_pf *pf) 1909{ 1910 struct ixl_vsi *vsi = &pf->vsi; 1911 struct ifnet *ifp = vsi->ifp; 1912 1913 mtx_assert(&pf->pf_mtx, MA_OWNED); 1914 1915 INIT_DEBUGOUT("ixl_stop: begin\n"); 1916 if (pf->num_vfs == 0) 1917 ixl_disable_intr(vsi); 1918 else 1919 ixl_disable_rings_intr(vsi); 1920 ixl_disable_rings(vsi); 1921 1922 /* Tell the stack that the interface is no longer active */ 1923 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1924 1925 /* Stop the local timer */ 1926 callout_stop(&pf->timer); 1927 1928 return; 1929} 1930 1931 1932/********************************************************************* 1933 * 1934 * Setup MSIX Interrupt resources and handlers for the VSI 1935 * 1936 **********************************************************************/ 1937static int 1938ixl_assign_vsi_legacy(struct ixl_pf *pf) 1939{ 1940 device_t dev = pf->dev; 1941 struct ixl_vsi *vsi = &pf->vsi; 1942 struct ixl_queue *que = vsi->queues; 1943 int error, rid = 0; 1944 1945 if (pf->msix == 1) 1946 rid = 1; 1947 pf->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1948 &rid, RF_SHAREABLE | RF_ACTIVE); 1949 if (pf->res == NULL) { 1950 device_printf(dev,"Unable to allocate" 1951 " bus resource: vsi legacy/msi interrupt\n"); 1952 return (ENXIO); 1953 } 1954 1955 /* Set the handler function */ 1956 error = bus_setup_intr(dev, pf->res, 1957 INTR_TYPE_NET | INTR_MPSAFE, NULL, 1958 ixl_intr, pf, &pf->tag); 1959 if (error) { 1960 pf->res = NULL; 1961 device_printf(dev, "Failed to register legacy/msi handler"); 1962 return (error); 1963 } 1964 bus_describe_intr(dev, pf->res, pf->tag, "irq0"); 1965 TASK_INIT(&que->tx_task, 0, ixl_deferred_mq_start, que); 1966 TASK_INIT(&que->task, 0, ixl_handle_que, que); 1967 que->tq = taskqueue_create_fast("ixl_que", M_NOWAIT, 1968 taskqueue_thread_enqueue, &que->tq); 1969 taskqueue_start_threads(&que->tq, 1, PI_NET, "%s que", 1970 device_get_nameunit(dev)); 1971 TASK_INIT(&pf->adminq, 0, ixl_do_adminq, pf); 1972 1973#ifdef PCI_IOV 1974 TASK_INIT(&pf->vflr_task, 0, ixl_handle_vflr, pf); 1975#endif 1976 1977 pf->tq = taskqueue_create_fast("ixl_adm", M_NOWAIT, 1978 taskqueue_thread_enqueue, &pf->tq); 1979 taskqueue_start_threads(&pf->tq, 1, PI_NET, "%s adminq", 1980 device_get_nameunit(dev)); 1981 1982 return (0); 1983} 1984 1985static void 1986ixl_init_taskqueues(struct ixl_pf *pf) 1987{ 1988 struct ixl_vsi *vsi = &pf->vsi; 1989 struct ixl_queue *que = vsi->queues; 1990 device_t dev = pf->dev; 1991 1992 /* Tasklet for Admin Queue */ 1993 TASK_INIT(&pf->adminq, 0, ixl_do_adminq, pf); 1994#ifdef PCI_IOV 1995 /* VFLR Tasklet */ 1996 TASK_INIT(&pf->vflr_task, 0, ixl_handle_vflr, pf); 1997#endif 1998 1999 /* Create and start PF taskqueue */ 2000 pf->tq = taskqueue_create_fast("ixl_adm", M_NOWAIT, 2001 taskqueue_thread_enqueue, &pf->tq); 2002 taskqueue_start_threads(&pf->tq, 1, PI_NET, "%s adminq", 2003 device_get_nameunit(dev)); 2004 2005 /* Create queue tasks and start queue taskqueues */ 2006 for (int i = 0; i < vsi->num_queues; i++, que++) { 2007 TASK_INIT(&que->tx_task, 0, ixl_deferred_mq_start, que); 2008 TASK_INIT(&que->task, 0, ixl_handle_que, que); 2009 que->tq = taskqueue_create_fast("ixl_que", M_NOWAIT, 2010 taskqueue_thread_enqueue, &que->tq); 2011#ifdef RSS 2012 CPU_SETOF(cpu_id, &cpu_mask); 2013 taskqueue_start_threads_cpuset(&que->tq, 1, PI_NET, 2014 &cpu_mask, "%s (bucket %d)", 2015 device_get_nameunit(dev), cpu_id); 2016#else 2017 taskqueue_start_threads(&que->tq, 1, PI_NET, 2018 "%s (que %d)", device_get_nameunit(dev), que->me); 2019#endif 2020 } 2021 2022} 2023 2024static void 2025ixl_free_taskqueues(struct ixl_pf *pf) 2026{ 2027 struct ixl_vsi *vsi = &pf->vsi; 2028 struct ixl_queue *que = vsi->queues; 2029 2030 if (pf->tq) 2031 taskqueue_free(pf->tq); 2032 for (int i = 0; i < vsi->num_queues; i++, que++) { 2033 if (que->tq) 2034 taskqueue_free(que->tq); 2035 } 2036} 2037 2038/********************************************************************* 2039 * 2040 * Setup MSIX Interrupt resources and handlers for the VSI 2041 * 2042 **********************************************************************/ 2043static int 2044ixl_assign_vsi_msix(struct ixl_pf *pf) 2045{ 2046 device_t dev = pf->dev; 2047 struct ixl_vsi *vsi = &pf->vsi; 2048 struct ixl_queue *que = vsi->queues; 2049 struct tx_ring *txr; 2050 int error, rid, vector = 0; 2051#ifdef RSS 2052 cpuset_t cpu_mask; 2053#endif 2054 2055 /* Admin Queue interrupt vector is 0 */ 2056 rid = vector + 1; 2057 pf->res = bus_alloc_resource_any(dev, 2058 SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); 2059 if (!pf->res) { 2060 device_printf(dev, "Unable to allocate" 2061 " bus resource: Adminq interrupt [rid=%d]\n", rid); 2062 return (ENXIO); 2063 } 2064 /* Set the adminq vector and handler */ 2065 error = bus_setup_intr(dev, pf->res, 2066 INTR_TYPE_NET | INTR_MPSAFE, NULL, 2067 ixl_msix_adminq, pf, &pf->tag); 2068 if (error) { 2069 pf->res = NULL; 2070 device_printf(dev, "Failed to register Admin que handler"); 2071 return (error); 2072 } 2073 bus_describe_intr(dev, pf->res, pf->tag, "aq"); 2074 pf->admvec = vector; 2075 ++vector; 2076 2077 /* Now set up the stations */ 2078 for (int i = 0; i < vsi->num_queues; i++, vector++, que++) { 2079 int cpu_id = i; 2080 rid = vector + 1; 2081 txr = &que->txr; 2082 que->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2083 RF_SHAREABLE | RF_ACTIVE); 2084 if (que->res == NULL) { 2085 device_printf(dev, "Unable to allocate" 2086 " bus resource: que interrupt [rid=%d]\n", rid); 2087 return (ENXIO); 2088 } 2089 /* Set the handler function */ 2090 error = bus_setup_intr(dev, que->res, 2091 INTR_TYPE_NET | INTR_MPSAFE, NULL, 2092 ixl_msix_que, que, &que->tag); 2093 if (error) { 2094 que->res = NULL; 2095 device_printf(dev, "Failed to register que handler"); 2096 return (error); 2097 } 2098 bus_describe_intr(dev, que->res, que->tag, "que%d", i); 2099 /* Bind the vector to a CPU */ 2100#ifdef RSS 2101 cpu_id = rss_getcpu(i % rss_getnumbuckets()); 2102#endif 2103 bus_bind_intr(dev, que->res, cpu_id); 2104 que->msix = vector; 2105 } 2106 2107 return (0); 2108} 2109 2110 2111/* 2112 * Allocate MSI/X vectors 2113 */ 2114static int 2115ixl_init_msix(struct ixl_pf *pf) 2116{ 2117 device_t dev = pf->dev; 2118 int rid, want, vectors, queues, available; 2119 2120 /* Override by tuneable */ 2121 if (ixl_enable_msix == 0) 2122 goto msi; 2123 2124 /* 2125 ** When used in a virtualized environment 2126 ** PCI BUSMASTER capability may not be set 2127 ** so explicity set it here and rewrite 2128 ** the ENABLE in the MSIX control register 2129 ** at this point to cause the host to 2130 ** successfully initialize us. 2131 */ 2132 { 2133 u16 pci_cmd_word; 2134 int msix_ctrl; 2135 pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2136 pci_cmd_word |= PCIM_CMD_BUSMASTEREN; 2137 pci_write_config(dev, PCIR_COMMAND, pci_cmd_word, 2); 2138 pci_find_cap(dev, PCIY_MSIX, &rid); 2139 rid += PCIR_MSIX_CTRL; 2140 msix_ctrl = pci_read_config(dev, rid, 2); 2141 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 2142 pci_write_config(dev, rid, msix_ctrl, 2); 2143 } 2144 2145 /* First try MSI/X */ 2146 rid = PCIR_BAR(IXL_BAR); 2147 pf->msix_mem = bus_alloc_resource_any(dev, 2148 SYS_RES_MEMORY, &rid, RF_ACTIVE); 2149 if (!pf->msix_mem) { 2150 /* May not be enabled */ 2151 device_printf(pf->dev, 2152 "Unable to map MSIX table \n"); 2153 goto msi; 2154 } 2155 2156 available = pci_msix_count(dev); 2157 if (available == 0) { /* system has msix disabled */ 2158 bus_release_resource(dev, SYS_RES_MEMORY, 2159 rid, pf->msix_mem); 2160 pf->msix_mem = NULL; 2161 goto msi; 2162 } 2163 2164 /* Figure out a reasonable auto config value */ 2165 queues = (mp_ncpus > (available - 1)) ? (available - 1) : mp_ncpus; 2166 2167 /* Override with hardcoded value if it's less than autoconfig count */ 2168 if ((ixl_max_queues != 0) && (ixl_max_queues <= queues)) 2169 queues = ixl_max_queues; 2170 else if ((ixl_max_queues != 0) && (ixl_max_queues > queues)) 2171 device_printf(dev, "ixl_max_queues > # of cpus, using " 2172 "autoconfig amount...\n"); 2173 /* Or limit maximum auto-configured queues to 8 */ 2174 else if ((ixl_max_queues == 0) && (queues > 8)) 2175 queues = 8; 2176 2177#ifdef RSS 2178 /* If we're doing RSS, clamp at the number of RSS buckets */ 2179 if (queues > rss_getnumbuckets()) 2180 queues = rss_getnumbuckets(); 2181#endif 2182 2183 /* 2184 ** Want one vector (RX/TX pair) per queue 2185 ** plus an additional for the admin queue. 2186 */ 2187 want = queues + 1; 2188 if (want <= available) /* Have enough */ 2189 vectors = want; 2190 else { 2191 device_printf(pf->dev, 2192 "MSIX Configuration Problem, " 2193 "%d vectors available but %d wanted!\n", 2194 available, want); 2195 return (0); /* Will go to Legacy setup */ 2196 } 2197 2198 if (pci_alloc_msix(dev, &vectors) == 0) { 2199 device_printf(pf->dev, 2200 "Using MSIX interrupts with %d vectors\n", vectors); 2201 pf->msix = vectors; 2202 pf->vsi.num_queues = queues; 2203#ifdef RSS 2204 /* 2205 * If we're doing RSS, the number of queues needs to 2206 * match the number of RSS buckets that are configured. 2207 * 2208 * + If there's more queues than RSS buckets, we'll end 2209 * up with queues that get no traffic. 2210 * 2211 * + If there's more RSS buckets than queues, we'll end 2212 * up having multiple RSS buckets map to the same queue, 2213 * so there'll be some contention. 2214 */ 2215 if (queues != rss_getnumbuckets()) { 2216 device_printf(dev, 2217 "%s: queues (%d) != RSS buckets (%d)" 2218 "; performance will be impacted.\n", 2219 __func__, queues, rss_getnumbuckets()); 2220 } 2221#endif 2222 return (vectors); 2223 } 2224msi: 2225 vectors = pci_msi_count(dev); 2226 pf->vsi.num_queues = 1; 2227 pf->msix = 1; 2228 ixl_max_queues = 1; 2229 ixl_enable_msix = 0; 2230 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) 2231 device_printf(pf->dev,"Using an MSI interrupt\n"); 2232 else { 2233 pf->msix = 0; 2234 device_printf(pf->dev,"Using a Legacy interrupt\n"); 2235 } 2236 return (vectors); 2237} 2238 2239 2240/* 2241 * Plumb MSI/X vectors 2242 */ 2243static void 2244ixl_configure_msix(struct ixl_pf *pf) 2245{ 2246 struct i40e_hw *hw = &pf->hw; 2247 struct ixl_vsi *vsi = &pf->vsi; 2248 u32 reg; 2249 u16 vector = 1; 2250 2251 /* First set up the adminq - vector 0 */ 2252 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */ 2253 rd32(hw, I40E_PFINT_ICR0); /* read to clear */ 2254 2255 reg = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | 2256 I40E_PFINT_ICR0_ENA_GRST_MASK | 2257 I40E_PFINT_ICR0_HMC_ERR_MASK | 2258 I40E_PFINT_ICR0_ENA_ADMINQ_MASK | 2259 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | 2260 I40E_PFINT_ICR0_ENA_VFLR_MASK | 2261 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK; 2262 wr32(hw, I40E_PFINT_ICR0_ENA, reg); 2263 2264 wr32(hw, I40E_PFINT_LNKLST0, 0x7FF); 2265 wr32(hw, I40E_PFINT_ITR0(IXL_RX_ITR), 0x003E); 2266 2267 wr32(hw, I40E_PFINT_DYN_CTL0, 2268 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK | 2269 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK); 2270 2271 wr32(hw, I40E_PFINT_STAT_CTL0, 0); 2272 2273 /* Next configure the queues */ 2274 for (int i = 0; i < vsi->num_queues; i++, vector++) { 2275 wr32(hw, I40E_PFINT_DYN_CTLN(i), i); 2276 wr32(hw, I40E_PFINT_LNKLSTN(i), i); 2277 2278 reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK | 2279 (IXL_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | 2280 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | 2281 (i << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | 2282 (I40E_QUEUE_TYPE_TX << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT); 2283 wr32(hw, I40E_QINT_RQCTL(i), reg); 2284 2285 reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK | 2286 (IXL_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | 2287 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | 2288 ((i+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | 2289 (I40E_QUEUE_TYPE_RX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); 2290 if (i == (vsi->num_queues - 1)) 2291 reg |= (IXL_QUEUE_EOL 2292 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT); 2293 wr32(hw, I40E_QINT_TQCTL(i), reg); 2294 } 2295} 2296 2297/* 2298 * Configure for MSI single vector operation 2299 */ 2300static void 2301ixl_configure_legacy(struct ixl_pf *pf) 2302{ 2303 struct i40e_hw *hw = &pf->hw; 2304 u32 reg; 2305 2306 2307 wr32(hw, I40E_PFINT_ITR0(0), 0); 2308 wr32(hw, I40E_PFINT_ITR0(1), 0); 2309 2310 2311 /* Setup "other" causes */ 2312 reg = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK 2313 | I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK 2314 | I40E_PFINT_ICR0_ENA_GRST_MASK 2315 | I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK 2316 | I40E_PFINT_ICR0_ENA_GPIO_MASK 2317 | I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK 2318 | I40E_PFINT_ICR0_ENA_HMC_ERR_MASK 2319 | I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK 2320 | I40E_PFINT_ICR0_ENA_VFLR_MASK 2321 | I40E_PFINT_ICR0_ENA_ADMINQ_MASK 2322 ; 2323 wr32(hw, I40E_PFINT_ICR0_ENA, reg); 2324 2325 /* SW_ITR_IDX = 0, but don't change INTENA */ 2326 wr32(hw, I40E_PFINT_DYN_CTL0, 2327 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK | 2328 I40E_PFINT_DYN_CTLN_INTENA_MSK_MASK); 2329 /* SW_ITR_IDX = 0, OTHER_ITR_IDX = 0 */ 2330 wr32(hw, I40E_PFINT_STAT_CTL0, 0); 2331 2332 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */ 2333 wr32(hw, I40E_PFINT_LNKLST0, 0); 2334 2335 /* Associate the queue pair to the vector and enable the q int */ 2336 reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK 2337 | (IXL_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) 2338 | (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); 2339 wr32(hw, I40E_QINT_RQCTL(0), reg); 2340 2341 reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK 2342 | (IXL_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) 2343 | (IXL_QUEUE_EOL << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT); 2344 wr32(hw, I40E_QINT_TQCTL(0), reg); 2345 2346 /* Next enable the queue pair */ 2347 reg = rd32(hw, I40E_QTX_ENA(0)); 2348 reg |= I40E_QTX_ENA_QENA_REQ_MASK; 2349 wr32(hw, I40E_QTX_ENA(0), reg); 2350 2351 reg = rd32(hw, I40E_QRX_ENA(0)); 2352 reg |= I40E_QRX_ENA_QENA_REQ_MASK; 2353 wr32(hw, I40E_QRX_ENA(0), reg); 2354} 2355 2356 2357/* 2358 * Set the Initial ITR state 2359 */ 2360static void 2361ixl_configure_itr(struct ixl_pf *pf) 2362{ 2363 struct i40e_hw *hw = &pf->hw; 2364 struct ixl_vsi *vsi = &pf->vsi; 2365 struct ixl_queue *que = vsi->queues; 2366 2367 vsi->rx_itr_setting = ixl_rx_itr; 2368 if (ixl_dynamic_rx_itr) 2369 vsi->rx_itr_setting |= IXL_ITR_DYNAMIC; 2370 vsi->tx_itr_setting = ixl_tx_itr; 2371 if (ixl_dynamic_tx_itr) 2372 vsi->tx_itr_setting |= IXL_ITR_DYNAMIC; 2373 2374 for (int i = 0; i < vsi->num_queues; i++, que++) { 2375 struct tx_ring *txr = &que->txr; 2376 struct rx_ring *rxr = &que->rxr; 2377 2378 wr32(hw, I40E_PFINT_ITRN(IXL_RX_ITR, i), 2379 vsi->rx_itr_setting); 2380 rxr->itr = vsi->rx_itr_setting; 2381 rxr->latency = IXL_AVE_LATENCY; 2382 wr32(hw, I40E_PFINT_ITRN(IXL_TX_ITR, i), 2383 vsi->tx_itr_setting); 2384 txr->itr = vsi->tx_itr_setting; 2385 txr->latency = IXL_AVE_LATENCY; 2386 } 2387} 2388 2389 2390static int 2391ixl_allocate_pci_resources(struct ixl_pf *pf) 2392{ 2393 int rid; 2394 device_t dev = pf->dev; 2395 2396 rid = PCIR_BAR(0); 2397 pf->pci_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2398 &rid, RF_ACTIVE); 2399 2400 if (!(pf->pci_mem)) { 2401 device_printf(dev,"Unable to allocate bus resource: memory\n"); 2402 return (ENXIO); 2403 } 2404 2405 pf->osdep.mem_bus_space_tag = 2406 rman_get_bustag(pf->pci_mem); 2407 pf->osdep.mem_bus_space_handle = 2408 rman_get_bushandle(pf->pci_mem); 2409 pf->osdep.mem_bus_space_size = rman_get_size(pf->pci_mem); 2410 pf->osdep.flush_reg = I40E_GLGEN_STAT; 2411 pf->hw.hw_addr = (u8 *) &pf->osdep.mem_bus_space_handle; 2412 2413 pf->hw.back = &pf->osdep; 2414 2415 /* 2416 ** Now setup MSI or MSI/X, should 2417 ** return us the number of supported 2418 ** vectors. (Will be 1 for MSI) 2419 */ 2420 pf->msix = ixl_init_msix(pf); 2421 return (0); 2422} 2423 2424static void 2425ixl_free_pci_resources(struct ixl_pf * pf) 2426{ 2427 struct ixl_vsi *vsi = &pf->vsi; 2428 struct ixl_queue *que = vsi->queues; 2429 device_t dev = pf->dev; 2430 int rid, memrid; 2431 2432 memrid = PCIR_BAR(IXL_BAR); 2433 2434 /* We may get here before stations are setup */ 2435 if ((!ixl_enable_msix) || (que == NULL)) 2436 goto early; 2437 2438 /* 2439 ** Release all msix VSI resources: 2440 */ 2441 for (int i = 0; i < vsi->num_queues; i++, que++) { 2442 rid = que->msix + 1; 2443 if (que->tag != NULL) { 2444 bus_teardown_intr(dev, que->res, que->tag); 2445 que->tag = NULL; 2446 } 2447 if (que->res != NULL) 2448 bus_release_resource(dev, SYS_RES_IRQ, rid, que->res); 2449 } 2450 2451early: 2452 /* Clean the AdminQ interrupt last */ 2453 if (pf->admvec) /* we are doing MSIX */ 2454 rid = pf->admvec + 1; 2455 else 2456 (pf->msix != 0) ? (rid = 1):(rid = 0); 2457 2458 if (pf->tag != NULL) { 2459 bus_teardown_intr(dev, pf->res, pf->tag); 2460 pf->tag = NULL; 2461 } 2462 if (pf->res != NULL) 2463 bus_release_resource(dev, SYS_RES_IRQ, rid, pf->res); 2464 2465 if (pf->msix) 2466 pci_release_msi(dev); 2467 2468 if (pf->msix_mem != NULL) 2469 bus_release_resource(dev, SYS_RES_MEMORY, 2470 memrid, pf->msix_mem); 2471 2472 if (pf->pci_mem != NULL) 2473 bus_release_resource(dev, SYS_RES_MEMORY, 2474 PCIR_BAR(0), pf->pci_mem); 2475 2476 return; 2477} 2478 2479static void 2480ixl_add_ifmedia(struct ixl_vsi *vsi, u32 phy_type) 2481{ 2482 /* Display supported media types */ 2483 if (phy_type & (1 << I40E_PHY_TYPE_100BASE_TX)) 2484 ifmedia_add(&vsi->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2485 2486 if (phy_type & (1 << I40E_PHY_TYPE_1000BASE_T)) 2487 ifmedia_add(&vsi->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2488 if (phy_type & (1 << I40E_PHY_TYPE_1000BASE_SX)) 2489 ifmedia_add(&vsi->media, IFM_ETHER | IFM_1000_SX, 0, NULL); 2490 if (phy_type & (1 << I40E_PHY_TYPE_1000BASE_LX)) 2491 ifmedia_add(&vsi->media, IFM_ETHER | IFM_1000_LX, 0, NULL); 2492 2493 if (phy_type & (1 << I40E_PHY_TYPE_XAUI) || 2494 phy_type & (1 << I40E_PHY_TYPE_XFI) || 2495 phy_type & (1 << I40E_PHY_TYPE_10GBASE_SFPP_CU)) 2496 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_TWINAX, 0, NULL); 2497 2498 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_SR)) 2499 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_SR, 0, NULL); 2500 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_LR)) 2501 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_LR, 0, NULL); 2502 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_T)) 2503 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_T, 0, NULL); 2504 2505 if (phy_type & (1 << I40E_PHY_TYPE_40GBASE_CR4) || 2506 phy_type & (1 << I40E_PHY_TYPE_40GBASE_CR4_CU) || 2507 phy_type & (1 << I40E_PHY_TYPE_40GBASE_AOC) || 2508 phy_type & (1 << I40E_PHY_TYPE_XLAUI) || 2509 phy_type & (1 << I40E_PHY_TYPE_40GBASE_KR4)) 2510 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_CR4, 0, NULL); 2511 if (phy_type & (1 << I40E_PHY_TYPE_40GBASE_SR4)) 2512 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_SR4, 0, NULL); 2513 if (phy_type & (1 << I40E_PHY_TYPE_40GBASE_LR4)) 2514 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_LR4, 0, NULL); 2515 2516#ifndef IFM_ETH_XTYPE 2517 if (phy_type & (1 << I40E_PHY_TYPE_1000BASE_KX)) 2518 ifmedia_add(&vsi->media, IFM_ETHER | IFM_1000_CX, 0, NULL); 2519 2520 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_CR1_CU) || 2521 phy_type & (1 << I40E_PHY_TYPE_10GBASE_CR1) || 2522 phy_type & (1 << I40E_PHY_TYPE_10GBASE_AOC) || 2523 phy_type & (1 << I40E_PHY_TYPE_SFI)) 2524 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_TWINAX, 0, NULL); 2525 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_KX4)) 2526 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_CX4, 0, NULL); 2527 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_KR)) 2528 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_SR, 0, NULL); 2529 2530 if (phy_type & (1 << I40E_PHY_TYPE_40GBASE_KR4)) 2531 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_SR4, 0, NULL); 2532 if (phy_type & (1 << I40E_PHY_TYPE_XLPPI)) 2533 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_CR4, 0, NULL); 2534#else 2535 if (phy_type & (1 << I40E_PHY_TYPE_1000BASE_KX)) 2536 ifmedia_add(&vsi->media, IFM_ETHER | IFM_1000_KX, 0, NULL); 2537 2538 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_CR1_CU) 2539 || phy_type & (1 << I40E_PHY_TYPE_10GBASE_CR1)) 2540 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_CR1, 0, NULL); 2541 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_AOC)) 2542 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_TWINAX_LONG, 0, NULL); 2543 if (phy_type & (1 << I40E_PHY_TYPE_SFI)) 2544 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_SFI, 0, NULL); 2545 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_KX4)) 2546 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_KX4, 0, NULL); 2547 if (phy_type & (1 << I40E_PHY_TYPE_10GBASE_KR)) 2548 ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_KR, 0, NULL); 2549 2550 if (phy_type & (1 << I40E_PHY_TYPE_20GBASE_KR2)) 2551 ifmedia_add(&vsi->media, IFM_ETHER | IFM_20G_KR2, 0, NULL); 2552 2553 if (phy_type & (1 << I40E_PHY_TYPE_40GBASE_KR4)) 2554 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_KR4, 0, NULL); 2555 if (phy_type & (1 << I40E_PHY_TYPE_XLPPI)) 2556 ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_XLPPI, 0, NULL); 2557#endif 2558} 2559 2560/********************************************************************* 2561 * 2562 * Setup networking device structure and register an interface. 2563 * 2564 **********************************************************************/ 2565static int 2566ixl_setup_interface(device_t dev, struct ixl_vsi *vsi) 2567{ 2568 struct ifnet *ifp; 2569 struct i40e_hw *hw = vsi->hw; 2570 struct ixl_queue *que = vsi->queues; 2571 struct i40e_aq_get_phy_abilities_resp abilities; 2572 enum i40e_status_code aq_error = 0; 2573 2574 INIT_DEBUGOUT("ixl_setup_interface: begin"); 2575 2576 ifp = vsi->ifp = if_alloc(IFT_ETHER); 2577 if (ifp == NULL) { 2578 device_printf(dev, "can not allocate ifnet structure\n"); 2579 return (-1); 2580 } 2581 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2582 ifp->if_mtu = ETHERMTU; 2583 ifp->if_baudrate = IF_Gbps(40); 2584 ifp->if_init = ixl_init; 2585 ifp->if_softc = vsi; 2586 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2587 ifp->if_ioctl = ixl_ioctl; 2588 2589#if __FreeBSD_version >= 1100036 2590 if_setgetcounterfn(ifp, ixl_get_counter); 2591#endif 2592 2593 ifp->if_transmit = ixl_mq_start; 2594 2595 ifp->if_qflush = ixl_qflush; 2596 2597 ifp->if_snd.ifq_maxlen = que->num_desc - 2; 2598 2599 vsi->max_frame_size = 2600 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN 2601 + ETHER_VLAN_ENCAP_LEN; 2602 2603 /* 2604 * Tell the upper layer(s) we support long frames. 2605 */ 2606 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 2607 2608 ifp->if_capabilities |= IFCAP_HWCSUM; 2609 ifp->if_capabilities |= IFCAP_HWCSUM_IPV6; 2610 ifp->if_capabilities |= IFCAP_TSO; 2611 ifp->if_capabilities |= IFCAP_JUMBO_MTU; 2612 ifp->if_capabilities |= IFCAP_LRO; 2613 2614 /* VLAN capabilties */ 2615 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING 2616 | IFCAP_VLAN_HWTSO 2617 | IFCAP_VLAN_MTU 2618 | IFCAP_VLAN_HWCSUM; 2619 ifp->if_capenable = ifp->if_capabilities; 2620 2621 /* 2622 ** Don't turn this on by default, if vlans are 2623 ** created on another pseudo device (eg. lagg) 2624 ** then vlan events are not passed thru, breaking 2625 ** operation, but with HW FILTER off it works. If 2626 ** using vlans directly on the ixl driver you can 2627 ** enable this and get full hardware tag filtering. 2628 */ 2629 ifp->if_capabilities |= IFCAP_VLAN_HWFILTER; 2630 2631 /* 2632 * Specify the media types supported by this adapter and register 2633 * callbacks to update media and link information 2634 */ 2635 ifmedia_init(&vsi->media, IFM_IMASK, ixl_media_change, 2636 ixl_media_status); 2637 2638 aq_error = i40e_aq_get_phy_capabilities(hw, 2639 FALSE, TRUE, &abilities, NULL); 2640 /* May need delay to detect fiber correctly */ 2641 if (aq_error == I40E_ERR_UNKNOWN_PHY) { 2642 i40e_msec_delay(200); 2643 aq_error = i40e_aq_get_phy_capabilities(hw, FALSE, 2644 TRUE, &abilities, NULL); 2645 } 2646 if (aq_error) { 2647 if (aq_error == I40E_ERR_UNKNOWN_PHY) 2648 device_printf(dev, "Unknown PHY type detected!\n"); 2649 else 2650 device_printf(dev, 2651 "Error getting supported media types, err %d," 2652 " AQ error %d\n", aq_error, hw->aq.asq_last_status); 2653 return (0); 2654 } 2655 2656 ixl_add_ifmedia(vsi, abilities.phy_type); 2657 2658 /* Use autoselect media by default */ 2659 ifmedia_add(&vsi->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2660 ifmedia_set(&vsi->media, IFM_ETHER | IFM_AUTO); 2661 2662 ether_ifattach(ifp, hw->mac.addr); 2663 2664 return (0); 2665} 2666 2667/* 2668** Run when the Admin Queue gets a 2669** link transition interrupt. 2670*/ 2671static void 2672ixl_link_event(struct ixl_pf *pf, struct i40e_arq_event_info *e) 2673{ 2674 struct i40e_hw *hw = &pf->hw; 2675 struct i40e_aqc_get_link_status *status = 2676 (struct i40e_aqc_get_link_status *)&e->desc.params.raw; 2677 bool check; 2678 2679 hw->phy.get_link_info = TRUE; 2680 i40e_get_link_status(hw, &check); 2681 pf->link_up = check; 2682#ifdef IXL_DEBUG 2683 printf("Link is %s\n", check ? "up":"down"); 2684#endif 2685 /* Report if Unqualified modules are found */ 2686 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) && 2687 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) && 2688 (!(status->link_info & I40E_AQ_LINK_UP))) 2689 device_printf(pf->dev, "Link failed because " 2690 "an unqualified module was detected\n"); 2691 2692 return; 2693} 2694 2695/********************************************************************* 2696 * 2697 * Get Firmware Switch configuration 2698 * - this will need to be more robust when more complex 2699 * switch configurations are enabled. 2700 * 2701 **********************************************************************/ 2702static int 2703ixl_switch_config(struct ixl_pf *pf) 2704{ 2705 struct i40e_hw *hw = &pf->hw; 2706 struct ixl_vsi *vsi = &pf->vsi; 2707 device_t dev = vsi->dev; 2708 struct i40e_aqc_get_switch_config_resp *sw_config; 2709 u8 aq_buf[I40E_AQ_LARGE_BUF]; 2710 int ret; 2711 u16 next = 0; 2712 2713 memset(&aq_buf, 0, sizeof(aq_buf)); 2714 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf; 2715 ret = i40e_aq_get_switch_config(hw, sw_config, 2716 sizeof(aq_buf), &next, NULL); 2717 if (ret) { 2718 device_printf(dev,"aq_get_switch_config failed (ret=%d)!!\n", 2719 ret); 2720 return (ret); 2721 } 2722#ifdef IXL_DEBUG 2723 device_printf(dev, 2724 "Switch config: header reported: %d in structure, %d total\n", 2725 sw_config->header.num_reported, sw_config->header.num_total); 2726 for (int i = 0; i < sw_config->header.num_reported; i++) { 2727 device_printf(dev, 2728 "%d: type=%d seid=%d uplink=%d downlink=%d\n", i, 2729 sw_config->element[i].element_type, 2730 sw_config->element[i].seid, 2731 sw_config->element[i].uplink_seid, 2732 sw_config->element[i].downlink_seid); 2733 } 2734#endif 2735 /* Simplified due to a single VSI at the moment */ 2736 vsi->uplink_seid = sw_config->element[0].uplink_seid; 2737 vsi->downlink_seid = sw_config->element[0].downlink_seid; 2738 vsi->seid = sw_config->element[0].seid; 2739 return (ret); 2740} 2741 2742/********************************************************************* 2743 * 2744 * Initialize the VSI: this handles contexts, which means things 2745 * like the number of descriptors, buffer size, 2746 * plus we init the rings thru this function. 2747 * 2748 **********************************************************************/ 2749static int 2750ixl_initialize_vsi(struct ixl_vsi *vsi) 2751{ 2752 struct ixl_pf *pf = vsi->back; 2753 struct ixl_queue *que = vsi->queues; 2754 device_t dev = vsi->dev; 2755 struct i40e_hw *hw = vsi->hw; 2756 struct i40e_vsi_context ctxt; 2757 int err = 0; 2758 2759 memset(&ctxt, 0, sizeof(ctxt)); 2760 ctxt.seid = vsi->seid; 2761 if (pf->veb_seid != 0) 2762 ctxt.uplink_seid = pf->veb_seid; 2763 ctxt.pf_num = hw->pf_id; 2764 err = i40e_aq_get_vsi_params(hw, &ctxt, NULL); 2765 if (err) { 2766 device_printf(dev,"get vsi params failed %x!!\n", err); 2767 return (err); 2768 } 2769#ifdef IXL_DEBUG 2770 printf("get_vsi_params: seid: %d, uplinkseid: %d, vsi_number: %d, " 2771 "vsis_allocated: %d, vsis_unallocated: %d, flags: 0x%x, " 2772 "pfnum: %d, vfnum: %d, stat idx: %d, enabled: %d\n", ctxt.seid, 2773 ctxt.uplink_seid, ctxt.vsi_number, 2774 ctxt.vsis_allocated, ctxt.vsis_unallocated, 2775 ctxt.flags, ctxt.pf_num, ctxt.vf_num, 2776 ctxt.info.stat_counter_idx, ctxt.info.up_enable_bits); 2777#endif 2778 /* 2779 ** Set the queue and traffic class bits 2780 ** - when multiple traffic classes are supported 2781 ** this will need to be more robust. 2782 */ 2783 ctxt.info.valid_sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID; 2784 ctxt.info.mapping_flags |= I40E_AQ_VSI_QUE_MAP_CONTIG; 2785 ctxt.info.queue_mapping[0] = 0; 2786 ctxt.info.tc_mapping[0] = 0x0800; 2787 2788 /* Set VLAN receive stripping mode */ 2789 ctxt.info.valid_sections |= I40E_AQ_VSI_PROP_VLAN_VALID; 2790 ctxt.info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL; 2791 if (vsi->ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 2792 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH; 2793 else 2794 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_EMOD_NOTHING; 2795 2796 /* Keep copy of VSI info in VSI for statistic counters */ 2797 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info)); 2798 2799 /* Reset VSI statistics */ 2800 ixl_vsi_reset_stats(vsi); 2801 vsi->hw_filters_add = 0; 2802 vsi->hw_filters_del = 0; 2803 2804 ctxt.flags = htole16(I40E_AQ_VSI_TYPE_PF); 2805 2806 err = i40e_aq_update_vsi_params(hw, &ctxt, NULL); 2807 if (err) { 2808 device_printf(dev,"update vsi params failed %x!!\n", 2809 hw->aq.asq_last_status); 2810 return (err); 2811 } 2812 2813 for (int i = 0; i < vsi->num_queues; i++, que++) { 2814 struct tx_ring *txr = &que->txr; 2815 struct rx_ring *rxr = &que->rxr; 2816 struct i40e_hmc_obj_txq tctx; 2817 struct i40e_hmc_obj_rxq rctx; 2818 u32 txctl; 2819 u16 size; 2820 2821 2822 /* Setup the HMC TX Context */ 2823 size = que->num_desc * sizeof(struct i40e_tx_desc); 2824 memset(&tctx, 0, sizeof(struct i40e_hmc_obj_txq)); 2825 tctx.new_context = 1; 2826 tctx.base = (txr->dma.pa/IXL_TX_CTX_BASE_UNITS); 2827 tctx.qlen = que->num_desc; 2828 tctx.fc_ena = 0; 2829 tctx.rdylist = vsi->info.qs_handle[0]; /* index is TC */ 2830 /* Enable HEAD writeback */ 2831 tctx.head_wb_ena = 1; 2832 tctx.head_wb_addr = txr->dma.pa + 2833 (que->num_desc * sizeof(struct i40e_tx_desc)); 2834 tctx.rdylist_act = 0; 2835 err = i40e_clear_lan_tx_queue_context(hw, i); 2836 if (err) { 2837 device_printf(dev, "Unable to clear TX context\n"); 2838 break; 2839 } 2840 err = i40e_set_lan_tx_queue_context(hw, i, &tctx); 2841 if (err) { 2842 device_printf(dev, "Unable to set TX context\n"); 2843 break; 2844 } 2845 /* Associate the ring with this PF */ 2846 txctl = I40E_QTX_CTL_PF_QUEUE; 2847 txctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) & 2848 I40E_QTX_CTL_PF_INDX_MASK); 2849 wr32(hw, I40E_QTX_CTL(i), txctl); 2850 ixl_flush(hw); 2851 2852 /* Do ring (re)init */ 2853 ixl_init_tx_ring(que); 2854 2855 /* Next setup the HMC RX Context */ 2856 if (vsi->max_frame_size <= MCLBYTES) 2857 rxr->mbuf_sz = MCLBYTES; 2858 else 2859 rxr->mbuf_sz = MJUMPAGESIZE; 2860 2861 u16 max_rxmax = rxr->mbuf_sz * hw->func_caps.rx_buf_chain_len; 2862 2863 /* Set up an RX context for the HMC */ 2864 memset(&rctx, 0, sizeof(struct i40e_hmc_obj_rxq)); 2865 rctx.dbuff = rxr->mbuf_sz >> I40E_RXQ_CTX_DBUFF_SHIFT; 2866 /* ignore header split for now */ 2867 rctx.hbuff = 0 >> I40E_RXQ_CTX_HBUFF_SHIFT; 2868 rctx.rxmax = (vsi->max_frame_size < max_rxmax) ? 2869 vsi->max_frame_size : max_rxmax; 2870 rctx.dtype = 0; 2871 rctx.dsize = 1; /* do 32byte descriptors */ 2872 rctx.hsplit_0 = 0; /* no HDR split initially */ 2873 rctx.base = (rxr->dma.pa/IXL_RX_CTX_BASE_UNITS); 2874 rctx.qlen = que->num_desc; 2875 rctx.tphrdesc_ena = 1; 2876 rctx.tphwdesc_ena = 1; 2877 rctx.tphdata_ena = 0; 2878 rctx.tphhead_ena = 0; 2879 rctx.lrxqthresh = 2; 2880 rctx.crcstrip = 1; 2881 rctx.l2tsel = 1; 2882 rctx.showiv = 1; 2883 rctx.fc_ena = 0; 2884 rctx.prefena = 1; 2885 2886 err = i40e_clear_lan_rx_queue_context(hw, i); 2887 if (err) { 2888 device_printf(dev, 2889 "Unable to clear RX context %d\n", i); 2890 break; 2891 } 2892 err = i40e_set_lan_rx_queue_context(hw, i, &rctx); 2893 if (err) { 2894 device_printf(dev, "Unable to set RX context %d\n", i); 2895 break; 2896 } 2897 err = ixl_init_rx_ring(que); 2898 if (err) { 2899 device_printf(dev, "Fail in init_rx_ring %d\n", i); 2900 break; 2901 } 2902 wr32(vsi->hw, I40E_QRX_TAIL(que->me), 0); 2903#ifdef DEV_NETMAP 2904 /* preserve queue */ 2905 if (vsi->ifp->if_capenable & IFCAP_NETMAP) { 2906 struct netmap_adapter *na = NA(vsi->ifp); 2907 struct netmap_kring *kring = &na->rx_rings[i]; 2908 int t = na->num_rx_desc - 1 - nm_kr_rxspace(kring); 2909 wr32(vsi->hw, I40E_QRX_TAIL(que->me), t); 2910 } else 2911#endif /* DEV_NETMAP */ 2912 wr32(vsi->hw, I40E_QRX_TAIL(que->me), que->num_desc - 1); 2913 } 2914 return (err); 2915} 2916 2917 2918/********************************************************************* 2919 * 2920 * Free all VSI structs. 2921 * 2922 **********************************************************************/ 2923void 2924ixl_free_vsi(struct ixl_vsi *vsi) 2925{ 2926 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 2927 struct ixl_queue *que = vsi->queues; 2928 2929 /* Free station queues */ 2930 for (int i = 0; i < vsi->num_queues; i++, que++) { 2931 struct tx_ring *txr = &que->txr; 2932 struct rx_ring *rxr = &que->rxr; 2933 2934 if (!mtx_initialized(&txr->mtx)) /* uninitialized */ 2935 continue; 2936 IXL_TX_LOCK(txr); 2937 ixl_free_que_tx(que); 2938 if (txr->base) 2939 i40e_free_dma_mem(&pf->hw, &txr->dma); 2940 IXL_TX_UNLOCK(txr); 2941 IXL_TX_LOCK_DESTROY(txr); 2942 2943 if (!mtx_initialized(&rxr->mtx)) /* uninitialized */ 2944 continue; 2945 IXL_RX_LOCK(rxr); 2946 ixl_free_que_rx(que); 2947 if (rxr->base) 2948 i40e_free_dma_mem(&pf->hw, &rxr->dma); 2949 IXL_RX_UNLOCK(rxr); 2950 IXL_RX_LOCK_DESTROY(rxr); 2951 2952 } 2953 free(vsi->queues, M_DEVBUF); 2954 2955 /* Free VSI filter list */ 2956 ixl_free_mac_filters(vsi); 2957} 2958 2959static void 2960ixl_free_mac_filters(struct ixl_vsi *vsi) 2961{ 2962 struct ixl_mac_filter *f; 2963 2964 while (!SLIST_EMPTY(&vsi->ftl)) { 2965 f = SLIST_FIRST(&vsi->ftl); 2966 SLIST_REMOVE_HEAD(&vsi->ftl, next); 2967 free(f, M_DEVBUF); 2968 } 2969} 2970 2971 2972/********************************************************************* 2973 * 2974 * Allocate memory for the VSI (virtual station interface) and their 2975 * associated queues, rings and the descriptors associated with each, 2976 * called only once at attach. 2977 * 2978 **********************************************************************/ 2979static int 2980ixl_setup_stations(struct ixl_pf *pf) 2981{ 2982 device_t dev = pf->dev; 2983 struct ixl_vsi *vsi; 2984 struct ixl_queue *que; 2985 struct tx_ring *txr; 2986 struct rx_ring *rxr; 2987 int rsize, tsize; 2988 int error = I40E_SUCCESS; 2989 2990 vsi = &pf->vsi; 2991 vsi->back = (void *)pf; 2992 vsi->hw = &pf->hw; 2993 vsi->id = 0; 2994 vsi->num_vlans = 0; 2995 vsi->back = pf; 2996 2997 /* Get memory for the station queues */ 2998 if (!(vsi->queues = 2999 (struct ixl_queue *) malloc(sizeof(struct ixl_queue) * 3000 vsi->num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3001 device_printf(dev, "Unable to allocate queue memory\n"); 3002 error = ENOMEM; 3003 goto early; 3004 } 3005 3006 for (int i = 0; i < vsi->num_queues; i++) { 3007 que = &vsi->queues[i]; 3008 que->num_desc = ixl_ringsz; 3009 que->me = i; 3010 que->vsi = vsi; 3011 /* mark the queue as active */ 3012 vsi->active_queues |= (u64)1 << que->me; 3013 txr = &que->txr; 3014 txr->que = que; 3015 txr->tail = I40E_QTX_TAIL(que->me); 3016 3017 /* Initialize the TX lock */ 3018 snprintf(txr->mtx_name, sizeof(txr->mtx_name), "%s:tx(%d)", 3019 device_get_nameunit(dev), que->me); 3020 mtx_init(&txr->mtx, txr->mtx_name, NULL, MTX_DEF); 3021 /* Create the TX descriptor ring */ 3022 tsize = roundup2((que->num_desc * 3023 sizeof(struct i40e_tx_desc)) + 3024 sizeof(u32), DBA_ALIGN); 3025 if (i40e_allocate_dma_mem(&pf->hw, 3026 &txr->dma, i40e_mem_reserved, tsize, DBA_ALIGN)) { 3027 device_printf(dev, 3028 "Unable to allocate TX Descriptor memory\n"); 3029 error = ENOMEM; 3030 goto fail; 3031 } 3032 txr->base = (struct i40e_tx_desc *)txr->dma.va; 3033 bzero((void *)txr->base, tsize); 3034 /* Now allocate transmit soft structs for the ring */ 3035 if (ixl_allocate_tx_data(que)) { 3036 device_printf(dev, 3037 "Critical Failure setting up TX structures\n"); 3038 error = ENOMEM; 3039 goto fail; 3040 } 3041 /* Allocate a buf ring */ 3042 txr->br = buf_ring_alloc(4096, M_DEVBUF, 3043 M_WAITOK, &txr->mtx); 3044 if (txr->br == NULL) { 3045 device_printf(dev, 3046 "Critical Failure setting up TX buf ring\n"); 3047 error = ENOMEM; 3048 goto fail; 3049 } 3050 3051 /* 3052 * Next the RX queues... 3053 */ 3054 rsize = roundup2(que->num_desc * 3055 sizeof(union i40e_rx_desc), DBA_ALIGN); 3056 rxr = &que->rxr; 3057 rxr->que = que; 3058 rxr->tail = I40E_QRX_TAIL(que->me); 3059 3060 /* Initialize the RX side lock */ 3061 snprintf(rxr->mtx_name, sizeof(rxr->mtx_name), "%s:rx(%d)", 3062 device_get_nameunit(dev), que->me); 3063 mtx_init(&rxr->mtx, rxr->mtx_name, NULL, MTX_DEF); 3064 3065 if (i40e_allocate_dma_mem(&pf->hw, 3066 &rxr->dma, i40e_mem_reserved, rsize, 4096)) { 3067 device_printf(dev, 3068 "Unable to allocate RX Descriptor memory\n"); 3069 error = ENOMEM; 3070 goto fail; 3071 } 3072 rxr->base = (union i40e_rx_desc *)rxr->dma.va; 3073 bzero((void *)rxr->base, rsize); 3074 3075 /* Allocate receive soft structs for the ring*/ 3076 if (ixl_allocate_rx_data(que)) { 3077 device_printf(dev, 3078 "Critical Failure setting up receive structs\n"); 3079 error = ENOMEM; 3080 goto fail; 3081 } 3082 } 3083 3084 return (0); 3085 3086fail: 3087 for (int i = 0; i < vsi->num_queues; i++) { 3088 que = &vsi->queues[i]; 3089 rxr = &que->rxr; 3090 txr = &que->txr; 3091 if (rxr->base) 3092 i40e_free_dma_mem(&pf->hw, &rxr->dma); 3093 if (txr->base) 3094 i40e_free_dma_mem(&pf->hw, &txr->dma); 3095 } 3096 3097early: 3098 return (error); 3099} 3100 3101/* 3102** Provide a update to the queue RX 3103** interrupt moderation value. 3104*/ 3105static void 3106ixl_set_queue_rx_itr(struct ixl_queue *que) 3107{ 3108 struct ixl_vsi *vsi = que->vsi; 3109 struct i40e_hw *hw = vsi->hw; 3110 struct rx_ring *rxr = &que->rxr; 3111 u16 rx_itr; 3112 u16 rx_latency = 0; 3113 int rx_bytes; 3114 3115 3116 /* Idle, do nothing */ 3117 if (rxr->bytes == 0) 3118 return; 3119 3120 if (ixl_dynamic_rx_itr) { 3121 rx_bytes = rxr->bytes/rxr->itr; 3122 rx_itr = rxr->itr; 3123 3124 /* Adjust latency range */ 3125 switch (rxr->latency) { 3126 case IXL_LOW_LATENCY: 3127 if (rx_bytes > 10) { 3128 rx_latency = IXL_AVE_LATENCY; 3129 rx_itr = IXL_ITR_20K; 3130 } 3131 break; 3132 case IXL_AVE_LATENCY: 3133 if (rx_bytes > 20) { 3134 rx_latency = IXL_BULK_LATENCY; 3135 rx_itr = IXL_ITR_8K; 3136 } else if (rx_bytes <= 10) { 3137 rx_latency = IXL_LOW_LATENCY; 3138 rx_itr = IXL_ITR_100K; 3139 } 3140 break; 3141 case IXL_BULK_LATENCY: 3142 if (rx_bytes <= 20) { 3143 rx_latency = IXL_AVE_LATENCY; 3144 rx_itr = IXL_ITR_20K; 3145 } 3146 break; 3147 } 3148 3149 rxr->latency = rx_latency; 3150 3151 if (rx_itr != rxr->itr) { 3152 /* do an exponential smoothing */ 3153 rx_itr = (10 * rx_itr * rxr->itr) / 3154 ((9 * rx_itr) + rxr->itr); 3155 rxr->itr = rx_itr & IXL_MAX_ITR; 3156 wr32(hw, I40E_PFINT_ITRN(IXL_RX_ITR, 3157 que->me), rxr->itr); 3158 } 3159 } else { /* We may have have toggled to non-dynamic */ 3160 if (vsi->rx_itr_setting & IXL_ITR_DYNAMIC) 3161 vsi->rx_itr_setting = ixl_rx_itr; 3162 /* Update the hardware if needed */ 3163 if (rxr->itr != vsi->rx_itr_setting) { 3164 rxr->itr = vsi->rx_itr_setting; 3165 wr32(hw, I40E_PFINT_ITRN(IXL_RX_ITR, 3166 que->me), rxr->itr); 3167 } 3168 } 3169 rxr->bytes = 0; 3170 rxr->packets = 0; 3171 return; 3172} 3173 3174 3175/* 3176** Provide a update to the queue TX 3177** interrupt moderation value. 3178*/ 3179static void 3180ixl_set_queue_tx_itr(struct ixl_queue *que) 3181{ 3182 struct ixl_vsi *vsi = que->vsi; 3183 struct i40e_hw *hw = vsi->hw; 3184 struct tx_ring *txr = &que->txr; 3185 u16 tx_itr; 3186 u16 tx_latency = 0; 3187 int tx_bytes; 3188 3189 3190 /* Idle, do nothing */ 3191 if (txr->bytes == 0) 3192 return; 3193 3194 if (ixl_dynamic_tx_itr) { 3195 tx_bytes = txr->bytes/txr->itr; 3196 tx_itr = txr->itr; 3197 3198 switch (txr->latency) { 3199 case IXL_LOW_LATENCY: 3200 if (tx_bytes > 10) { 3201 tx_latency = IXL_AVE_LATENCY; 3202 tx_itr = IXL_ITR_20K; 3203 } 3204 break; 3205 case IXL_AVE_LATENCY: 3206 if (tx_bytes > 20) { 3207 tx_latency = IXL_BULK_LATENCY; 3208 tx_itr = IXL_ITR_8K; 3209 } else if (tx_bytes <= 10) { 3210 tx_latency = IXL_LOW_LATENCY; 3211 tx_itr = IXL_ITR_100K; 3212 } 3213 break; 3214 case IXL_BULK_LATENCY: 3215 if (tx_bytes <= 20) { 3216 tx_latency = IXL_AVE_LATENCY; 3217 tx_itr = IXL_ITR_20K; 3218 } 3219 break; 3220 } 3221 3222 txr->latency = tx_latency; 3223 3224 if (tx_itr != txr->itr) { 3225 /* do an exponential smoothing */ 3226 tx_itr = (10 * tx_itr * txr->itr) / 3227 ((9 * tx_itr) + txr->itr); 3228 txr->itr = tx_itr & IXL_MAX_ITR; 3229 wr32(hw, I40E_PFINT_ITRN(IXL_TX_ITR, 3230 que->me), txr->itr); 3231 } 3232 3233 } else { /* We may have have toggled to non-dynamic */ 3234 if (vsi->tx_itr_setting & IXL_ITR_DYNAMIC) 3235 vsi->tx_itr_setting = ixl_tx_itr; 3236 /* Update the hardware if needed */ 3237 if (txr->itr != vsi->tx_itr_setting) { 3238 txr->itr = vsi->tx_itr_setting; 3239 wr32(hw, I40E_PFINT_ITRN(IXL_TX_ITR, 3240 que->me), txr->itr); 3241 } 3242 } 3243 txr->bytes = 0; 3244 txr->packets = 0; 3245 return; 3246} 3247 3248#define QUEUE_NAME_LEN 32 3249 3250static void 3251ixl_add_vsi_sysctls(struct ixl_pf *pf, struct ixl_vsi *vsi, 3252 struct sysctl_ctx_list *ctx, const char *sysctl_name) 3253{ 3254 struct sysctl_oid *tree; 3255 struct sysctl_oid_list *child; 3256 struct sysctl_oid_list *vsi_list; 3257 3258 tree = device_get_sysctl_tree(pf->dev); 3259 child = SYSCTL_CHILDREN(tree); 3260 vsi->vsi_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, sysctl_name, 3261 CTLFLAG_RD, NULL, "VSI Number"); 3262 vsi_list = SYSCTL_CHILDREN(vsi->vsi_node); 3263 3264 ixl_add_sysctls_eth_stats(ctx, vsi_list, &vsi->eth_stats); 3265} 3266 3267static void 3268ixl_add_hw_stats(struct ixl_pf *pf) 3269{ 3270 device_t dev = pf->dev; 3271 struct ixl_vsi *vsi = &pf->vsi; 3272 struct ixl_queue *queues = vsi->queues; 3273 struct i40e_hw_port_stats *pf_stats = &pf->stats; 3274 3275 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 3276 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 3277 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 3278 struct sysctl_oid_list *vsi_list; 3279 3280 struct sysctl_oid *queue_node; 3281 struct sysctl_oid_list *queue_list; 3282 3283 struct tx_ring *txr; 3284 struct rx_ring *rxr; 3285 char queue_namebuf[QUEUE_NAME_LEN]; 3286 3287 /* Driver statistics */ 3288 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_events", 3289 CTLFLAG_RD, &pf->watchdog_events, 3290 "Watchdog timeouts"); 3291 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "admin_irq", 3292 CTLFLAG_RD, &pf->admin_irq, 3293 "Admin Queue IRQ Handled"); 3294 3295 ixl_add_vsi_sysctls(pf, &pf->vsi, ctx, "pf"); 3296 vsi_list = SYSCTL_CHILDREN(pf->vsi.vsi_node); 3297 3298 /* Queue statistics */ 3299 for (int q = 0; q < vsi->num_queues; q++) { 3300 snprintf(queue_namebuf, QUEUE_NAME_LEN, "que%d", q); 3301 queue_node = SYSCTL_ADD_NODE(ctx, vsi_list, 3302 OID_AUTO, queue_namebuf, CTLFLAG_RD, NULL, "Queue #"); 3303 queue_list = SYSCTL_CHILDREN(queue_node); 3304 3305 txr = &(queues[q].txr); 3306 rxr = &(queues[q].rxr); 3307 3308 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "mbuf_defrag_failed", 3309 CTLFLAG_RD, &(queues[q].mbuf_defrag_failed), 3310 "m_defrag() failed"); 3311 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "dropped", 3312 CTLFLAG_RD, &(queues[q].dropped_pkts), 3313 "Driver dropped packets"); 3314 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "irqs", 3315 CTLFLAG_RD, &(queues[q].irqs), 3316 "irqs on this queue"); 3317 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tso_tx", 3318 CTLFLAG_RD, &(queues[q].tso), 3319 "TSO"); 3320 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_dma_setup", 3321 CTLFLAG_RD, &(queues[q].tx_dma_setup), 3322 "Driver tx dma failure in xmit"); 3323 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "no_desc_avail", 3324 CTLFLAG_RD, &(txr->no_desc), 3325 "Queue No Descriptor Available"); 3326 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_packets", 3327 CTLFLAG_RD, &(txr->total_packets), 3328 "Queue Packets Transmitted"); 3329 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_bytes", 3330 CTLFLAG_RD, &(txr->tx_bytes), 3331 "Queue Bytes Transmitted"); 3332 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_packets", 3333 CTLFLAG_RD, &(rxr->rx_packets), 3334 "Queue Packets Received"); 3335 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_bytes", 3336 CTLFLAG_RD, &(rxr->rx_bytes), 3337 "Queue Bytes Received"); 3338 } 3339 3340 /* MAC stats */ 3341 ixl_add_sysctls_mac_stats(ctx, child, pf_stats); 3342} 3343 3344static void 3345ixl_add_sysctls_eth_stats(struct sysctl_ctx_list *ctx, 3346 struct sysctl_oid_list *child, 3347 struct i40e_eth_stats *eth_stats) 3348{ 3349 struct ixl_sysctl_info ctls[] = 3350 { 3351 {ð_stats->rx_bytes, "good_octets_rcvd", "Good Octets Received"}, 3352 {ð_stats->rx_unicast, "ucast_pkts_rcvd", 3353 "Unicast Packets Received"}, 3354 {ð_stats->rx_multicast, "mcast_pkts_rcvd", 3355 "Multicast Packets Received"}, 3356 {ð_stats->rx_broadcast, "bcast_pkts_rcvd", 3357 "Broadcast Packets Received"}, 3358 {ð_stats->rx_discards, "rx_discards", "Discarded RX packets"}, 3359 {ð_stats->tx_bytes, "good_octets_txd", "Good Octets Transmitted"}, 3360 {ð_stats->tx_unicast, "ucast_pkts_txd", "Unicast Packets Transmitted"}, 3361 {ð_stats->tx_multicast, "mcast_pkts_txd", 3362 "Multicast Packets Transmitted"}, 3363 {ð_stats->tx_broadcast, "bcast_pkts_txd", 3364 "Broadcast Packets Transmitted"}, 3365 // end 3366 {0,0,0} 3367 }; 3368 3369 struct ixl_sysctl_info *entry = ctls; 3370 while (entry->stat != NULL) 3371 { 3372 SYSCTL_ADD_UQUAD(ctx, child, OID_AUTO, entry->name, 3373 CTLFLAG_RD, entry->stat, 3374 entry->description); 3375 entry++; 3376 } 3377} 3378 3379static void 3380ixl_add_sysctls_mac_stats(struct sysctl_ctx_list *ctx, 3381 struct sysctl_oid_list *child, 3382 struct i40e_hw_port_stats *stats) 3383{ 3384 struct sysctl_oid *stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac", 3385 CTLFLAG_RD, NULL, "Mac Statistics"); 3386 struct sysctl_oid_list *stat_list = SYSCTL_CHILDREN(stat_node); 3387 3388 struct i40e_eth_stats *eth_stats = &stats->eth; 3389 ixl_add_sysctls_eth_stats(ctx, stat_list, eth_stats); 3390 3391 struct ixl_sysctl_info ctls[] = 3392 { 3393 {&stats->crc_errors, "crc_errors", "CRC Errors"}, 3394 {&stats->illegal_bytes, "illegal_bytes", "Illegal Byte Errors"}, 3395 {&stats->mac_local_faults, "local_faults", "MAC Local Faults"}, 3396 {&stats->mac_remote_faults, "remote_faults", "MAC Remote Faults"}, 3397 {&stats->rx_length_errors, "rx_length_errors", "Receive Length Errors"}, 3398 /* Packet Reception Stats */ 3399 {&stats->rx_size_64, "rx_frames_64", "64 byte frames received"}, 3400 {&stats->rx_size_127, "rx_frames_65_127", "65-127 byte frames received"}, 3401 {&stats->rx_size_255, "rx_frames_128_255", "128-255 byte frames received"}, 3402 {&stats->rx_size_511, "rx_frames_256_511", "256-511 byte frames received"}, 3403 {&stats->rx_size_1023, "rx_frames_512_1023", "512-1023 byte frames received"}, 3404 {&stats->rx_size_1522, "rx_frames_1024_1522", "1024-1522 byte frames received"}, 3405 {&stats->rx_size_big, "rx_frames_big", "1523-9522 byte frames received"}, 3406 {&stats->rx_undersize, "rx_undersize", "Undersized packets received"}, 3407 {&stats->rx_fragments, "rx_fragmented", "Fragmented packets received"}, 3408 {&stats->rx_oversize, "rx_oversized", "Oversized packets received"}, 3409 {&stats->rx_jabber, "rx_jabber", "Received Jabber"}, 3410 {&stats->checksum_error, "checksum_errors", "Checksum Errors"}, 3411 /* Packet Transmission Stats */ 3412 {&stats->tx_size_64, "tx_frames_64", "64 byte frames transmitted"}, 3413 {&stats->tx_size_127, "tx_frames_65_127", "65-127 byte frames transmitted"}, 3414 {&stats->tx_size_255, "tx_frames_128_255", "128-255 byte frames transmitted"}, 3415 {&stats->tx_size_511, "tx_frames_256_511", "256-511 byte frames transmitted"}, 3416 {&stats->tx_size_1023, "tx_frames_512_1023", "512-1023 byte frames transmitted"}, 3417 {&stats->tx_size_1522, "tx_frames_1024_1522", "1024-1522 byte frames transmitted"}, 3418 {&stats->tx_size_big, "tx_frames_big", "1523-9522 byte frames transmitted"}, 3419 /* Flow control */ 3420 {&stats->link_xon_tx, "xon_txd", "Link XON transmitted"}, 3421 {&stats->link_xon_rx, "xon_recvd", "Link XON received"}, 3422 {&stats->link_xoff_tx, "xoff_txd", "Link XOFF transmitted"}, 3423 {&stats->link_xoff_rx, "xoff_recvd", "Link XOFF received"}, 3424 /* End */ 3425 {0,0,0} 3426 }; 3427 3428 struct ixl_sysctl_info *entry = ctls; 3429 while (entry->stat != NULL) 3430 { 3431 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, entry->name, 3432 CTLFLAG_RD, entry->stat, 3433 entry->description); 3434 entry++; 3435 } 3436} 3437 3438 3439/* 3440** ixl_config_rss - setup RSS 3441** - note this is done for the single vsi 3442*/ 3443static void ixl_config_rss(struct ixl_vsi *vsi) 3444{ 3445 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 3446 struct i40e_hw *hw = vsi->hw; 3447 u32 lut = 0; 3448 u64 set_hena = 0, hena; 3449 int i, j, que_id; 3450#ifdef RSS 3451 u32 rss_hash_config; 3452 u32 rss_seed[IXL_KEYSZ]; 3453#else 3454 u32 rss_seed[IXL_KEYSZ] = {0x41b01687, 3455 0x183cfd8c, 0xce880440, 0x580cbc3c, 3456 0x35897377, 0x328b25e1, 0x4fa98922, 3457 0xb7d90c14, 0xd5bad70d, 0xcd15a2c1}; 3458#endif 3459 3460#ifdef RSS 3461 /* Fetch the configured RSS key */ 3462 rss_getkey((uint8_t *) &rss_seed); 3463#endif 3464 3465 /* Fill out hash function seed */ 3466 for (i = 0; i < IXL_KEYSZ; i++) 3467 wr32(hw, I40E_PFQF_HKEY(i), rss_seed[i]); 3468 3469 /* Enable PCTYPES for RSS: */ 3470#ifdef RSS 3471 rss_hash_config = rss_gethashconfig(); 3472 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV4) 3473 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER); 3474 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV4) 3475 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP); 3476 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV4) 3477 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP); 3478 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6) 3479 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER); 3480 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6_EX) 3481 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6); 3482 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV6) 3483 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP); 3484 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV6) 3485 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP); 3486#else 3487 set_hena = 3488 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | 3489 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | 3490 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | 3491 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | 3492 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4) | 3493 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | 3494 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | 3495 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | 3496 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | 3497 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6) | 3498 ((u64)1 << I40E_FILTER_PCTYPE_L2_PAYLOAD); 3499#endif 3500 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) | 3501 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32); 3502 hena |= set_hena; 3503 wr32(hw, I40E_PFQF_HENA(0), (u32)hena); 3504 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32)); 3505 3506 /* Populate the LUT with max no. of queues in round robin fashion */ 3507 for (i = j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) { 3508 if (j == vsi->num_queues) 3509 j = 0; 3510#ifdef RSS 3511 /* 3512 * Fetch the RSS bucket id for the given indirection entry. 3513 * Cap it at the number of configured buckets (which is 3514 * num_queues.) 3515 */ 3516 que_id = rss_get_indirection_to_bucket(i); 3517 que_id = que_id % vsi->num_queues; 3518#else 3519 que_id = j; 3520#endif 3521 /* lut = 4-byte sliding window of 4 lut entries */ 3522 lut = (lut << 8) | (que_id & 3523 ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1)); 3524 /* On i = 3, we have 4 entries in lut; write to the register */ 3525 if ((i & 3) == 3) 3526 wr32(hw, I40E_PFQF_HLUT(i >> 2), lut); 3527 } 3528 ixl_flush(hw); 3529} 3530 3531 3532/* 3533** This routine is run via an vlan config EVENT, 3534** it enables us to use the HW Filter table since 3535** we can get the vlan id. This just creates the 3536** entry in the soft version of the VFTA, init will 3537** repopulate the real table. 3538*/ 3539static void 3540ixl_register_vlan(void *arg, struct ifnet *ifp, u16 vtag) 3541{ 3542 struct ixl_vsi *vsi = ifp->if_softc; 3543 struct i40e_hw *hw = vsi->hw; 3544 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 3545 3546 if (ifp->if_softc != arg) /* Not our event */ 3547 return; 3548 3549 if ((vtag == 0) || (vtag > 4095)) /* Invalid */ 3550 return; 3551 3552 IXL_PF_LOCK(pf); 3553 ++vsi->num_vlans; 3554 ixl_add_filter(vsi, hw->mac.addr, vtag); 3555 IXL_PF_UNLOCK(pf); 3556} 3557 3558/* 3559** This routine is run via an vlan 3560** unconfig EVENT, remove our entry 3561** in the soft vfta. 3562*/ 3563static void 3564ixl_unregister_vlan(void *arg, struct ifnet *ifp, u16 vtag) 3565{ 3566 struct ixl_vsi *vsi = ifp->if_softc; 3567 struct i40e_hw *hw = vsi->hw; 3568 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 3569 3570 if (ifp->if_softc != arg) 3571 return; 3572 3573 if ((vtag == 0) || (vtag > 4095)) /* Invalid */ 3574 return; 3575 3576 IXL_PF_LOCK(pf); 3577 --vsi->num_vlans; 3578 ixl_del_filter(vsi, hw->mac.addr, vtag); 3579 IXL_PF_UNLOCK(pf); 3580} 3581 3582/* 3583** This routine updates vlan filters, called by init 3584** it scans the filter table and then updates the hw 3585** after a soft reset. 3586*/ 3587static void 3588ixl_setup_vlan_filters(struct ixl_vsi *vsi) 3589{ 3590 struct ixl_mac_filter *f; 3591 int cnt = 0, flags; 3592 3593 if (vsi->num_vlans == 0) 3594 return; 3595 /* 3596 ** Scan the filter list for vlan entries, 3597 ** mark them for addition and then call 3598 ** for the AQ update. 3599 */ 3600 SLIST_FOREACH(f, &vsi->ftl, next) { 3601 if (f->flags & IXL_FILTER_VLAN) { 3602 f->flags |= 3603 (IXL_FILTER_ADD | 3604 IXL_FILTER_USED); 3605 cnt++; 3606 } 3607 } 3608 if (cnt == 0) { 3609 printf("setup vlan: no filters found!\n"); 3610 return; 3611 } 3612 flags = IXL_FILTER_VLAN; 3613 flags |= (IXL_FILTER_ADD | IXL_FILTER_USED); 3614 ixl_add_hw_filters(vsi, flags, cnt); 3615 return; 3616} 3617 3618/* 3619** Initialize filter list and add filters that the hardware 3620** needs to know about. 3621*/ 3622static void 3623ixl_init_filters(struct ixl_vsi *vsi) 3624{ 3625 /* Add broadcast address */ 3626 ixl_add_filter(vsi, ixl_bcast_addr, IXL_VLAN_ANY); 3627} 3628 3629/* 3630** This routine adds mulicast filters 3631*/ 3632static void 3633ixl_add_mc_filter(struct ixl_vsi *vsi, u8 *macaddr) 3634{ 3635 struct ixl_mac_filter *f; 3636 3637 /* Does one already exist */ 3638 f = ixl_find_filter(vsi, macaddr, IXL_VLAN_ANY); 3639 if (f != NULL) 3640 return; 3641 3642 f = ixl_get_filter(vsi); 3643 if (f == NULL) { 3644 printf("WARNING: no filter available!!\n"); 3645 return; 3646 } 3647 bcopy(macaddr, f->macaddr, ETHER_ADDR_LEN); 3648 f->vlan = IXL_VLAN_ANY; 3649 f->flags |= (IXL_FILTER_ADD | IXL_FILTER_USED 3650 | IXL_FILTER_MC); 3651 3652 return; 3653} 3654 3655static void 3656ixl_reconfigure_filters(struct ixl_vsi *vsi) 3657{ 3658 3659 ixl_add_hw_filters(vsi, IXL_FILTER_USED, vsi->num_macs); 3660} 3661 3662/* 3663** This routine adds macvlan filters 3664*/ 3665static void 3666ixl_add_filter(struct ixl_vsi *vsi, u8 *macaddr, s16 vlan) 3667{ 3668 struct ixl_mac_filter *f, *tmp; 3669 struct ixl_pf *pf; 3670 device_t dev; 3671 3672 DEBUGOUT("ixl_add_filter: begin"); 3673 3674 pf = vsi->back; 3675 dev = pf->dev; 3676 3677 /* Does one already exist */ 3678 f = ixl_find_filter(vsi, macaddr, vlan); 3679 if (f != NULL) 3680 return; 3681 /* 3682 ** Is this the first vlan being registered, if so we 3683 ** need to remove the ANY filter that indicates we are 3684 ** not in a vlan, and replace that with a 0 filter. 3685 */ 3686 if ((vlan != IXL_VLAN_ANY) && (vsi->num_vlans == 1)) { 3687 tmp = ixl_find_filter(vsi, macaddr, IXL_VLAN_ANY); 3688 if (tmp != NULL) { 3689 ixl_del_filter(vsi, macaddr, IXL_VLAN_ANY); 3690 ixl_add_filter(vsi, macaddr, 0); 3691 } 3692 } 3693 3694 f = ixl_get_filter(vsi); 3695 if (f == NULL) { 3696 device_printf(dev, "WARNING: no filter available!!\n"); 3697 return; 3698 } 3699 bcopy(macaddr, f->macaddr, ETHER_ADDR_LEN); 3700 f->vlan = vlan; 3701 f->flags |= (IXL_FILTER_ADD | IXL_FILTER_USED); 3702 if (f->vlan != IXL_VLAN_ANY) 3703 f->flags |= IXL_FILTER_VLAN; 3704 else 3705 vsi->num_macs++; 3706 3707 ixl_add_hw_filters(vsi, f->flags, 1); 3708 return; 3709} 3710 3711static void 3712ixl_del_filter(struct ixl_vsi *vsi, u8 *macaddr, s16 vlan) 3713{ 3714 struct ixl_mac_filter *f; 3715 3716 f = ixl_find_filter(vsi, macaddr, vlan); 3717 if (f == NULL) 3718 return; 3719 3720 f->flags |= IXL_FILTER_DEL; 3721 ixl_del_hw_filters(vsi, 1); 3722 vsi->num_macs--; 3723 3724 /* Check if this is the last vlan removal */ 3725 if (vlan != IXL_VLAN_ANY && vsi->num_vlans == 0) { 3726 /* Switch back to a non-vlan filter */ 3727 ixl_del_filter(vsi, macaddr, 0); 3728 ixl_add_filter(vsi, macaddr, IXL_VLAN_ANY); 3729 } 3730 return; 3731} 3732 3733/* 3734** Find the filter with both matching mac addr and vlan id 3735*/ 3736static struct ixl_mac_filter * 3737ixl_find_filter(struct ixl_vsi *vsi, u8 *macaddr, s16 vlan) 3738{ 3739 struct ixl_mac_filter *f; 3740 bool match = FALSE; 3741 3742 SLIST_FOREACH(f, &vsi->ftl, next) { 3743 if (!cmp_etheraddr(f->macaddr, macaddr)) 3744 continue; 3745 if (f->vlan == vlan) { 3746 match = TRUE; 3747 break; 3748 } 3749 } 3750 3751 if (!match) 3752 f = NULL; 3753 return (f); 3754} 3755 3756/* 3757** This routine takes additions to the vsi filter 3758** table and creates an Admin Queue call to create 3759** the filters in the hardware. 3760*/ 3761static void 3762ixl_add_hw_filters(struct ixl_vsi *vsi, int flags, int cnt) 3763{ 3764 struct i40e_aqc_add_macvlan_element_data *a, *b; 3765 struct ixl_mac_filter *f; 3766 struct ixl_pf *pf; 3767 struct i40e_hw *hw; 3768 device_t dev; 3769 int err, j = 0; 3770 3771 pf = vsi->back; 3772 dev = pf->dev; 3773 hw = &pf->hw; 3774 IXL_PF_LOCK_ASSERT(pf); 3775 3776 a = malloc(sizeof(struct i40e_aqc_add_macvlan_element_data) * cnt, 3777 M_DEVBUF, M_NOWAIT | M_ZERO); 3778 if (a == NULL) { 3779 device_printf(dev, "add_hw_filters failed to get memory\n"); 3780 return; 3781 } 3782 3783 /* 3784 ** Scan the filter list, each time we find one 3785 ** we add it to the admin queue array and turn off 3786 ** the add bit. 3787 */ 3788 SLIST_FOREACH(f, &vsi->ftl, next) { 3789 if (f->flags == flags) { 3790 b = &a[j]; // a pox on fvl long names :) 3791 bcopy(f->macaddr, b->mac_addr, ETHER_ADDR_LEN); 3792 if (f->vlan == IXL_VLAN_ANY) { 3793 b->vlan_tag = 0; 3794 b->flags = I40E_AQC_MACVLAN_ADD_IGNORE_VLAN; 3795 } else { 3796 b->vlan_tag = f->vlan; 3797 b->flags = 0; 3798 } 3799 b->flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH; 3800 f->flags &= ~IXL_FILTER_ADD; 3801 j++; 3802 } 3803 if (j == cnt) 3804 break; 3805 } 3806 if (j > 0) { 3807 err = i40e_aq_add_macvlan(hw, vsi->seid, a, j, NULL); 3808 if (err) 3809 device_printf(dev, "aq_add_macvlan err %d, " 3810 "aq_error %d\n", err, hw->aq.asq_last_status); 3811 else 3812 vsi->hw_filters_add += j; 3813 } 3814 free(a, M_DEVBUF); 3815 return; 3816} 3817 3818/* 3819** This routine takes removals in the vsi filter 3820** table and creates an Admin Queue call to delete 3821** the filters in the hardware. 3822*/ 3823static void 3824ixl_del_hw_filters(struct ixl_vsi *vsi, int cnt) 3825{ 3826 struct i40e_aqc_remove_macvlan_element_data *d, *e; 3827 struct ixl_pf *pf; 3828 struct i40e_hw *hw; 3829 device_t dev; 3830 struct ixl_mac_filter *f, *f_temp; 3831 int err, j = 0; 3832 3833 DEBUGOUT("ixl_del_hw_filters: begin\n"); 3834 3835 pf = vsi->back; 3836 hw = &pf->hw; 3837 dev = pf->dev; 3838 3839 d = malloc(sizeof(struct i40e_aqc_remove_macvlan_element_data) * cnt, 3840 M_DEVBUF, M_NOWAIT | M_ZERO); 3841 if (d == NULL) { 3842 printf("del hw filter failed to get memory\n"); 3843 return; 3844 } 3845 3846 SLIST_FOREACH_SAFE(f, &vsi->ftl, next, f_temp) { 3847 if (f->flags & IXL_FILTER_DEL) { 3848 e = &d[j]; // a pox on fvl long names :) 3849 bcopy(f->macaddr, e->mac_addr, ETHER_ADDR_LEN); 3850 e->vlan_tag = (f->vlan == IXL_VLAN_ANY ? 0 : f->vlan); 3851 e->flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH; 3852 /* delete entry from vsi list */ 3853 SLIST_REMOVE(&vsi->ftl, f, ixl_mac_filter, next); 3854 free(f, M_DEVBUF); 3855 j++; 3856 } 3857 if (j == cnt) 3858 break; 3859 } 3860 if (j > 0) { 3861 err = i40e_aq_remove_macvlan(hw, vsi->seid, d, j, NULL); 3862 /* NOTE: returns ENOENT every time but seems to work fine, 3863 so we'll ignore that specific error. */ 3864 // TODO: Does this still occur on current firmwares? 3865 if (err && hw->aq.asq_last_status != I40E_AQ_RC_ENOENT) { 3866 int sc = 0; 3867 for (int i = 0; i < j; i++) 3868 sc += (!d[i].error_code); 3869 vsi->hw_filters_del += sc; 3870 device_printf(dev, 3871 "Failed to remove %d/%d filters, aq error %d\n", 3872 j - sc, j, hw->aq.asq_last_status); 3873 } else 3874 vsi->hw_filters_del += j; 3875 } 3876 free(d, M_DEVBUF); 3877 3878 DEBUGOUT("ixl_del_hw_filters: end\n"); 3879 return; 3880} 3881 3882static int 3883ixl_enable_rings(struct ixl_vsi *vsi) 3884{ 3885 struct ixl_pf *pf = vsi->back; 3886 struct i40e_hw *hw = &pf->hw; 3887 int index, error; 3888 u32 reg; 3889 3890 error = 0; 3891 for (int i = 0; i < vsi->num_queues; i++) { 3892 index = vsi->first_queue + i; 3893 i40e_pre_tx_queue_cfg(hw, index, TRUE); 3894 3895 reg = rd32(hw, I40E_QTX_ENA(index)); 3896 reg |= I40E_QTX_ENA_QENA_REQ_MASK | 3897 I40E_QTX_ENA_QENA_STAT_MASK; 3898 wr32(hw, I40E_QTX_ENA(index), reg); 3899 /* Verify the enable took */ 3900 for (int j = 0; j < 10; j++) { 3901 reg = rd32(hw, I40E_QTX_ENA(index)); 3902 if (reg & I40E_QTX_ENA_QENA_STAT_MASK) 3903 break; 3904 i40e_msec_delay(10); 3905 } 3906 if ((reg & I40E_QTX_ENA_QENA_STAT_MASK) == 0) { 3907 device_printf(pf->dev, "TX queue %d disabled!\n", 3908 index); 3909 error = ETIMEDOUT; 3910 } 3911 3912 reg = rd32(hw, I40E_QRX_ENA(index)); 3913 reg |= I40E_QRX_ENA_QENA_REQ_MASK | 3914 I40E_QRX_ENA_QENA_STAT_MASK; 3915 wr32(hw, I40E_QRX_ENA(index), reg); 3916 /* Verify the enable took */ 3917 for (int j = 0; j < 10; j++) { 3918 reg = rd32(hw, I40E_QRX_ENA(index)); 3919 if (reg & I40E_QRX_ENA_QENA_STAT_MASK) 3920 break; 3921 i40e_msec_delay(10); 3922 } 3923 if ((reg & I40E_QRX_ENA_QENA_STAT_MASK) == 0) { 3924 device_printf(pf->dev, "RX queue %d disabled!\n", 3925 index); 3926 error = ETIMEDOUT; 3927 } 3928 } 3929 3930 return (error); 3931} 3932 3933static int 3934ixl_disable_rings(struct ixl_vsi *vsi) 3935{ 3936 struct ixl_pf *pf = vsi->back; 3937 struct i40e_hw *hw = &pf->hw; 3938 int index, error; 3939 u32 reg; 3940 3941 error = 0; 3942 for (int i = 0; i < vsi->num_queues; i++) { 3943 index = vsi->first_queue + i; 3944 3945 i40e_pre_tx_queue_cfg(hw, index, FALSE); 3946 i40e_usec_delay(500); 3947 3948 reg = rd32(hw, I40E_QTX_ENA(index)); 3949 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK; 3950 wr32(hw, I40E_QTX_ENA(index), reg); 3951 /* Verify the disable took */ 3952 for (int j = 0; j < 10; j++) { 3953 reg = rd32(hw, I40E_QTX_ENA(index)); 3954 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK)) 3955 break; 3956 i40e_msec_delay(10); 3957 } 3958 if (reg & I40E_QTX_ENA_QENA_STAT_MASK) { 3959 device_printf(pf->dev, "TX queue %d still enabled!\n", 3960 index); 3961 error = ETIMEDOUT; 3962 } 3963 3964 reg = rd32(hw, I40E_QRX_ENA(index)); 3965 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK; 3966 wr32(hw, I40E_QRX_ENA(index), reg); 3967 /* Verify the disable took */ 3968 for (int j = 0; j < 10; j++) { 3969 reg = rd32(hw, I40E_QRX_ENA(index)); 3970 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK)) 3971 break; 3972 i40e_msec_delay(10); 3973 } 3974 if (reg & I40E_QRX_ENA_QENA_STAT_MASK) { 3975 device_printf(pf->dev, "RX queue %d still enabled!\n", 3976 index); 3977 error = ETIMEDOUT; 3978 } 3979 } 3980 3981 return (error); 3982} 3983 3984/** 3985 * ixl_handle_mdd_event 3986 * 3987 * Called from interrupt handler to identify possibly malicious vfs 3988 * (But also detects events from the PF, as well) 3989 **/ 3990static void ixl_handle_mdd_event(struct ixl_pf *pf) 3991{ 3992 struct i40e_hw *hw = &pf->hw; 3993 device_t dev = pf->dev; 3994 bool mdd_detected = false; 3995 bool pf_mdd_detected = false; 3996 u32 reg; 3997 3998 /* find what triggered the MDD event */ 3999 reg = rd32(hw, I40E_GL_MDET_TX); 4000 if (reg & I40E_GL_MDET_TX_VALID_MASK) { 4001 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >> 4002 I40E_GL_MDET_TX_PF_NUM_SHIFT; 4003 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >> 4004 I40E_GL_MDET_TX_EVENT_SHIFT; 4005 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK) >> 4006 I40E_GL_MDET_TX_QUEUE_SHIFT; 4007 device_printf(dev, 4008 "Malicious Driver Detection event 0x%02x" 4009 " on TX queue %d pf number 0x%02x\n", 4010 event, queue, pf_num); 4011 wr32(hw, I40E_GL_MDET_TX, 0xffffffff); 4012 mdd_detected = true; 4013 } 4014 reg = rd32(hw, I40E_GL_MDET_RX); 4015 if (reg & I40E_GL_MDET_RX_VALID_MASK) { 4016 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >> 4017 I40E_GL_MDET_RX_FUNCTION_SHIFT; 4018 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >> 4019 I40E_GL_MDET_RX_EVENT_SHIFT; 4020 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK) >> 4021 I40E_GL_MDET_RX_QUEUE_SHIFT; 4022 device_printf(dev, 4023 "Malicious Driver Detection event 0x%02x" 4024 " on RX queue %d of function 0x%02x\n", 4025 event, queue, func); 4026 wr32(hw, I40E_GL_MDET_RX, 0xffffffff); 4027 mdd_detected = true; 4028 } 4029 4030 if (mdd_detected) { 4031 reg = rd32(hw, I40E_PF_MDET_TX); 4032 if (reg & I40E_PF_MDET_TX_VALID_MASK) { 4033 wr32(hw, I40E_PF_MDET_TX, 0xFFFF); 4034 device_printf(dev, 4035 "MDD TX event is for this function 0x%08x", 4036 reg); 4037 pf_mdd_detected = true; 4038 } 4039 reg = rd32(hw, I40E_PF_MDET_RX); 4040 if (reg & I40E_PF_MDET_RX_VALID_MASK) { 4041 wr32(hw, I40E_PF_MDET_RX, 0xFFFF); 4042 device_printf(dev, 4043 "MDD RX event is for this function 0x%08x", 4044 reg); 4045 pf_mdd_detected = true; 4046 } 4047 } 4048 4049 /* re-enable mdd interrupt cause */ 4050 reg = rd32(hw, I40E_PFINT_ICR0_ENA); 4051 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK; 4052 wr32(hw, I40E_PFINT_ICR0_ENA, reg); 4053 ixl_flush(hw); 4054} 4055 4056static void 4057ixl_enable_intr(struct ixl_vsi *vsi) 4058{ 4059 struct i40e_hw *hw = vsi->hw; 4060 struct ixl_queue *que = vsi->queues; 4061 4062 if (ixl_enable_msix) { 4063 ixl_enable_adminq(hw); 4064 for (int i = 0; i < vsi->num_queues; i++, que++) 4065 ixl_enable_queue(hw, que->me); 4066 } else 4067 ixl_enable_legacy(hw); 4068} 4069 4070static void 4071ixl_disable_rings_intr(struct ixl_vsi *vsi) 4072{ 4073 struct i40e_hw *hw = vsi->hw; 4074 struct ixl_queue *que = vsi->queues; 4075 4076 for (int i = 0; i < vsi->num_queues; i++, que++) 4077 ixl_disable_queue(hw, que->me); 4078} 4079 4080static void 4081ixl_disable_intr(struct ixl_vsi *vsi) 4082{ 4083 struct i40e_hw *hw = vsi->hw; 4084 4085 if (ixl_enable_msix) 4086 ixl_disable_adminq(hw); 4087 else 4088 ixl_disable_legacy(hw); 4089} 4090 4091static void 4092ixl_enable_adminq(struct i40e_hw *hw) 4093{ 4094 u32 reg; 4095 4096 reg = I40E_PFINT_DYN_CTL0_INTENA_MASK | 4097 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | 4098 (IXL_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT); 4099 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 4100 ixl_flush(hw); 4101 return; 4102} 4103 4104static void 4105ixl_disable_adminq(struct i40e_hw *hw) 4106{ 4107 u32 reg; 4108 4109 reg = IXL_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT; 4110 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 4111 4112 return; 4113} 4114 4115static void 4116ixl_enable_queue(struct i40e_hw *hw, int id) 4117{ 4118 u32 reg; 4119 4120 reg = I40E_PFINT_DYN_CTLN_INTENA_MASK | 4121 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 4122 (IXL_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); 4123 wr32(hw, I40E_PFINT_DYN_CTLN(id), reg); 4124} 4125 4126static void 4127ixl_disable_queue(struct i40e_hw *hw, int id) 4128{ 4129 u32 reg; 4130 4131 reg = IXL_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 4132 wr32(hw, I40E_PFINT_DYN_CTLN(id), reg); 4133 4134 return; 4135} 4136 4137static void 4138ixl_enable_legacy(struct i40e_hw *hw) 4139{ 4140 u32 reg; 4141 reg = I40E_PFINT_DYN_CTL0_INTENA_MASK | 4142 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | 4143 (IXL_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT); 4144 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 4145} 4146 4147static void 4148ixl_disable_legacy(struct i40e_hw *hw) 4149{ 4150 u32 reg; 4151 4152 reg = IXL_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT; 4153 wr32(hw, I40E_PFINT_DYN_CTL0, reg); 4154 4155 return; 4156} 4157 4158static void 4159ixl_update_stats_counters(struct ixl_pf *pf) 4160{ 4161 struct i40e_hw *hw = &pf->hw; 4162 struct ixl_vsi *vsi = &pf->vsi; 4163 struct ixl_vf *vf; 4164 4165 struct i40e_hw_port_stats *nsd = &pf->stats; 4166 struct i40e_hw_port_stats *osd = &pf->stats_offsets; 4167 4168 /* Update hw stats */ 4169 ixl_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port), 4170 pf->stat_offsets_loaded, 4171 &osd->crc_errors, &nsd->crc_errors); 4172 ixl_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port), 4173 pf->stat_offsets_loaded, 4174 &osd->illegal_bytes, &nsd->illegal_bytes); 4175 ixl_stat_update48(hw, I40E_GLPRT_GORCH(hw->port), 4176 I40E_GLPRT_GORCL(hw->port), 4177 pf->stat_offsets_loaded, 4178 &osd->eth.rx_bytes, &nsd->eth.rx_bytes); 4179 ixl_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port), 4180 I40E_GLPRT_GOTCL(hw->port), 4181 pf->stat_offsets_loaded, 4182 &osd->eth.tx_bytes, &nsd->eth.tx_bytes); 4183 ixl_stat_update32(hw, I40E_GLPRT_RDPC(hw->port), 4184 pf->stat_offsets_loaded, 4185 &osd->eth.rx_discards, 4186 &nsd->eth.rx_discards); 4187 ixl_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port), 4188 I40E_GLPRT_UPRCL(hw->port), 4189 pf->stat_offsets_loaded, 4190 &osd->eth.rx_unicast, 4191 &nsd->eth.rx_unicast); 4192 ixl_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port), 4193 I40E_GLPRT_UPTCL(hw->port), 4194 pf->stat_offsets_loaded, 4195 &osd->eth.tx_unicast, 4196 &nsd->eth.tx_unicast); 4197 ixl_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port), 4198 I40E_GLPRT_MPRCL(hw->port), 4199 pf->stat_offsets_loaded, 4200 &osd->eth.rx_multicast, 4201 &nsd->eth.rx_multicast); 4202 ixl_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port), 4203 I40E_GLPRT_MPTCL(hw->port), 4204 pf->stat_offsets_loaded, 4205 &osd->eth.tx_multicast, 4206 &nsd->eth.tx_multicast); 4207 ixl_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port), 4208 I40E_GLPRT_BPRCL(hw->port), 4209 pf->stat_offsets_loaded, 4210 &osd->eth.rx_broadcast, 4211 &nsd->eth.rx_broadcast); 4212 ixl_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port), 4213 I40E_GLPRT_BPTCL(hw->port), 4214 pf->stat_offsets_loaded, 4215 &osd->eth.tx_broadcast, 4216 &nsd->eth.tx_broadcast); 4217 4218 ixl_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port), 4219 pf->stat_offsets_loaded, 4220 &osd->tx_dropped_link_down, 4221 &nsd->tx_dropped_link_down); 4222 ixl_stat_update32(hw, I40E_GLPRT_MLFC(hw->port), 4223 pf->stat_offsets_loaded, 4224 &osd->mac_local_faults, 4225 &nsd->mac_local_faults); 4226 ixl_stat_update32(hw, I40E_GLPRT_MRFC(hw->port), 4227 pf->stat_offsets_loaded, 4228 &osd->mac_remote_faults, 4229 &nsd->mac_remote_faults); 4230 ixl_stat_update32(hw, I40E_GLPRT_RLEC(hw->port), 4231 pf->stat_offsets_loaded, 4232 &osd->rx_length_errors, 4233 &nsd->rx_length_errors); 4234 4235 /* Flow control (LFC) stats */ 4236 ixl_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port), 4237 pf->stat_offsets_loaded, 4238 &osd->link_xon_rx, &nsd->link_xon_rx); 4239 ixl_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port), 4240 pf->stat_offsets_loaded, 4241 &osd->link_xon_tx, &nsd->link_xon_tx); 4242 ixl_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port), 4243 pf->stat_offsets_loaded, 4244 &osd->link_xoff_rx, &nsd->link_xoff_rx); 4245 ixl_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port), 4246 pf->stat_offsets_loaded, 4247 &osd->link_xoff_tx, &nsd->link_xoff_tx); 4248 4249 /* Packet size stats rx */ 4250 ixl_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port), 4251 I40E_GLPRT_PRC64L(hw->port), 4252 pf->stat_offsets_loaded, 4253 &osd->rx_size_64, &nsd->rx_size_64); 4254 ixl_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port), 4255 I40E_GLPRT_PRC127L(hw->port), 4256 pf->stat_offsets_loaded, 4257 &osd->rx_size_127, &nsd->rx_size_127); 4258 ixl_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port), 4259 I40E_GLPRT_PRC255L(hw->port), 4260 pf->stat_offsets_loaded, 4261 &osd->rx_size_255, &nsd->rx_size_255); 4262 ixl_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port), 4263 I40E_GLPRT_PRC511L(hw->port), 4264 pf->stat_offsets_loaded, 4265 &osd->rx_size_511, &nsd->rx_size_511); 4266 ixl_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port), 4267 I40E_GLPRT_PRC1023L(hw->port), 4268 pf->stat_offsets_loaded, 4269 &osd->rx_size_1023, &nsd->rx_size_1023); 4270 ixl_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port), 4271 I40E_GLPRT_PRC1522L(hw->port), 4272 pf->stat_offsets_loaded, 4273 &osd->rx_size_1522, &nsd->rx_size_1522); 4274 ixl_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port), 4275 I40E_GLPRT_PRC9522L(hw->port), 4276 pf->stat_offsets_loaded, 4277 &osd->rx_size_big, &nsd->rx_size_big); 4278 4279 /* Packet size stats tx */ 4280 ixl_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port), 4281 I40E_GLPRT_PTC64L(hw->port), 4282 pf->stat_offsets_loaded, 4283 &osd->tx_size_64, &nsd->tx_size_64); 4284 ixl_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port), 4285 I40E_GLPRT_PTC127L(hw->port), 4286 pf->stat_offsets_loaded, 4287 &osd->tx_size_127, &nsd->tx_size_127); 4288 ixl_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port), 4289 I40E_GLPRT_PTC255L(hw->port), 4290 pf->stat_offsets_loaded, 4291 &osd->tx_size_255, &nsd->tx_size_255); 4292 ixl_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port), 4293 I40E_GLPRT_PTC511L(hw->port), 4294 pf->stat_offsets_loaded, 4295 &osd->tx_size_511, &nsd->tx_size_511); 4296 ixl_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port), 4297 I40E_GLPRT_PTC1023L(hw->port), 4298 pf->stat_offsets_loaded, 4299 &osd->tx_size_1023, &nsd->tx_size_1023); 4300 ixl_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port), 4301 I40E_GLPRT_PTC1522L(hw->port), 4302 pf->stat_offsets_loaded, 4303 &osd->tx_size_1522, &nsd->tx_size_1522); 4304 ixl_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port), 4305 I40E_GLPRT_PTC9522L(hw->port), 4306 pf->stat_offsets_loaded, 4307 &osd->tx_size_big, &nsd->tx_size_big); 4308 4309 ixl_stat_update32(hw, I40E_GLPRT_RUC(hw->port), 4310 pf->stat_offsets_loaded, 4311 &osd->rx_undersize, &nsd->rx_undersize); 4312 ixl_stat_update32(hw, I40E_GLPRT_RFC(hw->port), 4313 pf->stat_offsets_loaded, 4314 &osd->rx_fragments, &nsd->rx_fragments); 4315 ixl_stat_update32(hw, I40E_GLPRT_ROC(hw->port), 4316 pf->stat_offsets_loaded, 4317 &osd->rx_oversize, &nsd->rx_oversize); 4318 ixl_stat_update32(hw, I40E_GLPRT_RJC(hw->port), 4319 pf->stat_offsets_loaded, 4320 &osd->rx_jabber, &nsd->rx_jabber); 4321 pf->stat_offsets_loaded = true; 4322 /* End hw stats */ 4323 4324 /* Update vsi stats */ 4325 ixl_update_vsi_stats(vsi); 4326 4327 for (int i = 0; i < pf->num_vfs; i++) { 4328 vf = &pf->vfs[i]; 4329 if (vf->vf_flags & VF_FLAG_ENABLED) 4330 ixl_update_eth_stats(&pf->vfs[i].vsi); 4331 } 4332} 4333 4334/* 4335** Tasklet handler for MSIX Adminq interrupts 4336** - do outside interrupt since it might sleep 4337*/ 4338static void 4339ixl_do_adminq(void *context, int pending) 4340{ 4341 struct ixl_pf *pf = context; 4342 struct i40e_hw *hw = &pf->hw; 4343 struct ixl_vsi *vsi = &pf->vsi; 4344 struct i40e_arq_event_info event; 4345 i40e_status ret; 4346 u32 reg, loop = 0; 4347 u16 opcode, result; 4348 4349 event.buf_len = IXL_AQ_BUF_SZ; 4350 event.msg_buf = malloc(event.buf_len, 4351 M_DEVBUF, M_NOWAIT | M_ZERO); 4352 if (!event.msg_buf) { 4353 printf("Unable to allocate adminq memory\n"); 4354 return; 4355 } 4356 4357 IXL_PF_LOCK(pf); 4358 /* clean and process any events */ 4359 do { 4360 ret = i40e_clean_arq_element(hw, &event, &result); 4361 if (ret) 4362 break; 4363 opcode = LE16_TO_CPU(event.desc.opcode); 4364 switch (opcode) { 4365 case i40e_aqc_opc_get_link_status: 4366 ixl_link_event(pf, &event); 4367 ixl_update_link_status(pf); 4368 break; 4369 case i40e_aqc_opc_send_msg_to_pf: 4370#ifdef PCI_IOV 4371 ixl_handle_vf_msg(pf, &event); 4372#endif 4373 break; 4374 case i40e_aqc_opc_event_lan_overflow: 4375 break; 4376 default: 4377#ifdef IXL_DEBUG 4378 printf("AdminQ unknown event %x\n", opcode); 4379#endif 4380 break; 4381 } 4382 4383 } while (result && (loop++ < IXL_ADM_LIMIT)); 4384 4385 reg = rd32(hw, I40E_PFINT_ICR0_ENA); 4386 reg |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK; 4387 wr32(hw, I40E_PFINT_ICR0_ENA, reg); 4388 free(event.msg_buf, M_DEVBUF); 4389 4390 /* 4391 * If there are still messages to process, reschedule ourselves. 4392 * Otherwise, re-enable our interrupt and go to sleep. 4393 */ 4394 if (result > 0) 4395 taskqueue_enqueue(pf->tq, &pf->adminq); 4396 else 4397 ixl_enable_intr(vsi); 4398 4399 IXL_PF_UNLOCK(pf); 4400} 4401 4402static int 4403ixl_debug_info(SYSCTL_HANDLER_ARGS) 4404{ 4405 struct ixl_pf *pf; 4406 int error, input = 0; 4407 4408 error = sysctl_handle_int(oidp, &input, 0, req); 4409 4410 if (error || !req->newptr) 4411 return (error); 4412 4413 if (input == 1) { 4414 pf = (struct ixl_pf *)arg1; 4415 ixl_print_debug_info(pf); 4416 } 4417 4418 return (error); 4419} 4420 4421static void 4422ixl_print_debug_info(struct ixl_pf *pf) 4423{ 4424 struct i40e_hw *hw = &pf->hw; 4425 struct ixl_vsi *vsi = &pf->vsi; 4426 struct ixl_queue *que = vsi->queues; 4427 struct rx_ring *rxr = &que->rxr; 4428 struct tx_ring *txr = &que->txr; 4429 u32 reg; 4430 4431 4432 printf("Queue irqs = %jx\n", (uintmax_t)que->irqs); 4433 printf("AdminQ irqs = %jx\n", (uintmax_t)pf->admin_irq); 4434 printf("RX next check = %x\n", rxr->next_check); 4435 printf("RX not ready = %jx\n", (uintmax_t)rxr->not_done); 4436 printf("RX packets = %jx\n", (uintmax_t)rxr->rx_packets); 4437 printf("TX desc avail = %x\n", txr->avail); 4438 4439 reg = rd32(hw, I40E_GLV_GORCL(0xc)); 4440 printf("RX Bytes = %x\n", reg); 4441 reg = rd32(hw, I40E_GLPRT_GORCL(hw->port)); 4442 printf("Port RX Bytes = %x\n", reg); 4443 reg = rd32(hw, I40E_GLV_RDPC(0xc)); 4444 printf("RX discard = %x\n", reg); 4445 reg = rd32(hw, I40E_GLPRT_RDPC(hw->port)); 4446 printf("Port RX discard = %x\n", reg); 4447 4448 reg = rd32(hw, I40E_GLV_TEPC(0xc)); 4449 printf("TX errors = %x\n", reg); 4450 reg = rd32(hw, I40E_GLV_GOTCL(0xc)); 4451 printf("TX Bytes = %x\n", reg); 4452 4453 reg = rd32(hw, I40E_GLPRT_RUC(hw->port)); 4454 printf("RX undersize = %x\n", reg); 4455 reg = rd32(hw, I40E_GLPRT_RFC(hw->port)); 4456 printf("RX fragments = %x\n", reg); 4457 reg = rd32(hw, I40E_GLPRT_ROC(hw->port)); 4458 printf("RX oversize = %x\n", reg); 4459 reg = rd32(hw, I40E_GLPRT_RLEC(hw->port)); 4460 printf("RX length error = %x\n", reg); 4461 reg = rd32(hw, I40E_GLPRT_MRFC(hw->port)); 4462 printf("mac remote fault = %x\n", reg); 4463 reg = rd32(hw, I40E_GLPRT_MLFC(hw->port)); 4464 printf("mac local fault = %x\n", reg); 4465} 4466 4467/** 4468 * Update VSI-specific ethernet statistics counters. 4469 **/ 4470void ixl_update_eth_stats(struct ixl_vsi *vsi) 4471{ 4472 struct ixl_pf *pf = (struct ixl_pf *)vsi->back; 4473 struct i40e_hw *hw = &pf->hw; 4474 struct i40e_eth_stats *es; 4475 struct i40e_eth_stats *oes; 4476 struct i40e_hw_port_stats *nsd; 4477 u16 stat_idx = vsi->info.stat_counter_idx; 4478 4479 es = &vsi->eth_stats; 4480 oes = &vsi->eth_stats_offsets; 4481 nsd = &pf->stats; 4482 4483 /* Gather up the stats that the hw collects */ 4484 ixl_stat_update32(hw, I40E_GLV_TEPC(stat_idx), 4485 vsi->stat_offsets_loaded, 4486 &oes->tx_errors, &es->tx_errors); 4487 ixl_stat_update32(hw, I40E_GLV_RDPC(stat_idx), 4488 vsi->stat_offsets_loaded, 4489 &oes->rx_discards, &es->rx_discards); 4490 4491 ixl_stat_update48(hw, I40E_GLV_GORCH(stat_idx), 4492 I40E_GLV_GORCL(stat_idx), 4493 vsi->stat_offsets_loaded, 4494 &oes->rx_bytes, &es->rx_bytes); 4495 ixl_stat_update48(hw, I40E_GLV_UPRCH(stat_idx), 4496 I40E_GLV_UPRCL(stat_idx), 4497 vsi->stat_offsets_loaded, 4498 &oes->rx_unicast, &es->rx_unicast); 4499 ixl_stat_update48(hw, I40E_GLV_MPRCH(stat_idx), 4500 I40E_GLV_MPRCL(stat_idx), 4501 vsi->stat_offsets_loaded, 4502 &oes->rx_multicast, &es->rx_multicast); 4503 ixl_stat_update48(hw, I40E_GLV_BPRCH(stat_idx), 4504 I40E_GLV_BPRCL(stat_idx), 4505 vsi->stat_offsets_loaded, 4506 &oes->rx_broadcast, &es->rx_broadcast); 4507 4508 ixl_stat_update48(hw, I40E_GLV_GOTCH(stat_idx), 4509 I40E_GLV_GOTCL(stat_idx), 4510 vsi->stat_offsets_loaded, 4511 &oes->tx_bytes, &es->tx_bytes); 4512 ixl_stat_update48(hw, I40E_GLV_UPTCH(stat_idx), 4513 I40E_GLV_UPTCL(stat_idx), 4514 vsi->stat_offsets_loaded, 4515 &oes->tx_unicast, &es->tx_unicast); 4516 ixl_stat_update48(hw, I40E_GLV_MPTCH(stat_idx), 4517 I40E_GLV_MPTCL(stat_idx), 4518 vsi->stat_offsets_loaded, 4519 &oes->tx_multicast, &es->tx_multicast); 4520 ixl_stat_update48(hw, I40E_GLV_BPTCH(stat_idx), 4521 I40E_GLV_BPTCL(stat_idx), 4522 vsi->stat_offsets_loaded, 4523 &oes->tx_broadcast, &es->tx_broadcast); 4524 vsi->stat_offsets_loaded = true; 4525} 4526 4527static void 4528ixl_update_vsi_stats(struct ixl_vsi *vsi) 4529{ 4530 struct ixl_pf *pf; 4531 struct ifnet *ifp; 4532 struct i40e_eth_stats *es; 4533 u64 tx_discards; 4534 4535 struct i40e_hw_port_stats *nsd; 4536 4537 pf = vsi->back; 4538 ifp = vsi->ifp; 4539 es = &vsi->eth_stats; 4540 nsd = &pf->stats; 4541 4542 ixl_update_eth_stats(vsi); 4543 4544 tx_discards = es->tx_discards + nsd->tx_dropped_link_down; 4545 for (int i = 0; i < vsi->num_queues; i++) 4546 tx_discards += vsi->queues[i].txr.br->br_drops; 4547 4548 /* Update ifnet stats */ 4549 IXL_SET_IPACKETS(vsi, es->rx_unicast + 4550 es->rx_multicast + 4551 es->rx_broadcast); 4552 IXL_SET_OPACKETS(vsi, es->tx_unicast + 4553 es->tx_multicast + 4554 es->tx_broadcast); 4555 IXL_SET_IBYTES(vsi, es->rx_bytes); 4556 IXL_SET_OBYTES(vsi, es->tx_bytes); 4557 IXL_SET_IMCASTS(vsi, es->rx_multicast); 4558 IXL_SET_OMCASTS(vsi, es->tx_multicast); 4559 4560 IXL_SET_IERRORS(vsi, nsd->crc_errors + nsd->illegal_bytes + 4561 nsd->rx_undersize + nsd->rx_oversize + nsd->rx_fragments + 4562 nsd->rx_jabber); 4563 IXL_SET_OERRORS(vsi, es->tx_errors); 4564 IXL_SET_IQDROPS(vsi, es->rx_discards + nsd->eth.rx_discards); 4565 IXL_SET_OQDROPS(vsi, tx_discards); 4566 IXL_SET_NOPROTO(vsi, es->rx_unknown_protocol); 4567 IXL_SET_COLLISIONS(vsi, 0); 4568} 4569 4570/** 4571 * Reset all of the stats for the given pf 4572 **/ 4573void ixl_pf_reset_stats(struct ixl_pf *pf) 4574{ 4575 bzero(&pf->stats, sizeof(struct i40e_hw_port_stats)); 4576 bzero(&pf->stats_offsets, sizeof(struct i40e_hw_port_stats)); 4577 pf->stat_offsets_loaded = false; 4578} 4579 4580/** 4581 * Resets all stats of the given vsi 4582 **/ 4583void ixl_vsi_reset_stats(struct ixl_vsi *vsi) 4584{ 4585 bzero(&vsi->eth_stats, sizeof(struct i40e_eth_stats)); 4586 bzero(&vsi->eth_stats_offsets, sizeof(struct i40e_eth_stats)); 4587 vsi->stat_offsets_loaded = false; 4588} 4589 4590/** 4591 * Read and update a 48 bit stat from the hw 4592 * 4593 * Since the device stats are not reset at PFReset, they likely will not 4594 * be zeroed when the driver starts. We'll save the first values read 4595 * and use them as offsets to be subtracted from the raw values in order 4596 * to report stats that count from zero. 4597 **/ 4598static void 4599ixl_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg, 4600 bool offset_loaded, u64 *offset, u64 *stat) 4601{ 4602 u64 new_data; 4603 4604#if defined(__FreeBSD__) && (__FreeBSD_version >= 1000000) && defined(__amd64__) 4605 new_data = rd64(hw, loreg); 4606#else 4607 /* 4608 * Use two rd32's instead of one rd64; FreeBSD versions before 4609 * 10 don't support 8 byte bus reads/writes. 4610 */ 4611 new_data = rd32(hw, loreg); 4612 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32; 4613#endif 4614 4615 if (!offset_loaded) 4616 *offset = new_data; 4617 if (new_data >= *offset) 4618 *stat = new_data - *offset; 4619 else 4620 *stat = (new_data + ((u64)1 << 48)) - *offset; 4621 *stat &= 0xFFFFFFFFFFFFULL; 4622} 4623 4624/** 4625 * Read and update a 32 bit stat from the hw 4626 **/ 4627static void 4628ixl_stat_update32(struct i40e_hw *hw, u32 reg, 4629 bool offset_loaded, u64 *offset, u64 *stat) 4630{ 4631 u32 new_data; 4632 4633 new_data = rd32(hw, reg); 4634 if (!offset_loaded) 4635 *offset = new_data; 4636 if (new_data >= *offset) 4637 *stat = (u32)(new_data - *offset); 4638 else 4639 *stat = (u32)((new_data + ((u64)1 << 32)) - *offset); 4640} 4641 4642/* 4643** Set flow control using sysctl: 4644** 0 - off 4645** 1 - rx pause 4646** 2 - tx pause 4647** 3 - full 4648*/ 4649static int 4650ixl_set_flowcntl(SYSCTL_HANDLER_ARGS) 4651{ 4652 /* 4653 * TODO: ensure flow control is disabled if 4654 * priority flow control is enabled 4655 * 4656 * TODO: ensure tx CRC by hardware should be enabled 4657 * if tx flow control is enabled. 4658 */ 4659 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4660 struct i40e_hw *hw = &pf->hw; 4661 device_t dev = pf->dev; 4662 int error = 0; 4663 enum i40e_status_code aq_error = 0; 4664 u8 fc_aq_err = 0; 4665 4666 /* Get request */ 4667 error = sysctl_handle_int(oidp, &pf->fc, 0, req); 4668 if ((error) || (req->newptr == NULL)) 4669 return (error); 4670 if (pf->fc < 0 || pf->fc > 3) { 4671 device_printf(dev, 4672 "Invalid fc mode; valid modes are 0 through 3\n"); 4673 return (EINVAL); 4674 } 4675 4676 /* 4677 ** Changing flow control mode currently does not work on 4678 ** 40GBASE-CR4 PHYs 4679 */ 4680 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_40GBASE_CR4 4681 || hw->phy.link_info.phy_type == I40E_PHY_TYPE_40GBASE_CR4_CU) { 4682 device_printf(dev, "Changing flow control mode unsupported" 4683 " on 40GBase-CR4 media.\n"); 4684 return (ENODEV); 4685 } 4686 4687 /* Set fc ability for port */ 4688 hw->fc.requested_mode = pf->fc; 4689 aq_error = i40e_set_fc(hw, &fc_aq_err, TRUE); 4690 if (aq_error) { 4691 device_printf(dev, 4692 "%s: Error setting new fc mode %d; fc_err %#x\n", 4693 __func__, aq_error, fc_aq_err); 4694 return (EAGAIN); 4695 } 4696 4697 return (0); 4698} 4699 4700static int 4701ixl_current_speed(SYSCTL_HANDLER_ARGS) 4702{ 4703 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4704 struct i40e_hw *hw = &pf->hw; 4705 int error = 0, index = 0; 4706 4707 char *speeds[] = { 4708 "Unknown", 4709 "100M", 4710 "1G", 4711 "10G", 4712 "40G", 4713 "20G" 4714 }; 4715 4716 ixl_update_link_status(pf); 4717 4718 switch (hw->phy.link_info.link_speed) { 4719 case I40E_LINK_SPEED_100MB: 4720 index = 1; 4721 break; 4722 case I40E_LINK_SPEED_1GB: 4723 index = 2; 4724 break; 4725 case I40E_LINK_SPEED_10GB: 4726 index = 3; 4727 break; 4728 case I40E_LINK_SPEED_40GB: 4729 index = 4; 4730 break; 4731 case I40E_LINK_SPEED_20GB: 4732 index = 5; 4733 break; 4734 case I40E_LINK_SPEED_UNKNOWN: 4735 default: 4736 index = 0; 4737 break; 4738 } 4739 4740 error = sysctl_handle_string(oidp, speeds[index], 4741 strlen(speeds[index]), req); 4742 return (error); 4743} 4744 4745static int 4746ixl_set_advertised_speeds(struct ixl_pf *pf, int speeds) 4747{ 4748 struct i40e_hw *hw = &pf->hw; 4749 device_t dev = pf->dev; 4750 struct i40e_aq_get_phy_abilities_resp abilities; 4751 struct i40e_aq_set_phy_config config; 4752 enum i40e_status_code aq_error = 0; 4753 4754 /* Get current capability information */ 4755 aq_error = i40e_aq_get_phy_capabilities(hw, 4756 FALSE, FALSE, &abilities, NULL); 4757 if (aq_error) { 4758 device_printf(dev, 4759 "%s: Error getting phy capabilities %d," 4760 " aq error: %d\n", __func__, aq_error, 4761 hw->aq.asq_last_status); 4762 return (EAGAIN); 4763 } 4764 4765 /* Prepare new config */ 4766 bzero(&config, sizeof(config)); 4767 config.phy_type = abilities.phy_type; 4768 config.abilities = abilities.abilities 4769 | I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 4770 config.eee_capability = abilities.eee_capability; 4771 config.eeer = abilities.eeer_val; 4772 config.low_power_ctrl = abilities.d3_lpan; 4773 /* Translate into aq cmd link_speed */ 4774 if (speeds & 0x8) 4775 config.link_speed |= I40E_LINK_SPEED_20GB; 4776 if (speeds & 0x4) 4777 config.link_speed |= I40E_LINK_SPEED_10GB; 4778 if (speeds & 0x2) 4779 config.link_speed |= I40E_LINK_SPEED_1GB; 4780 if (speeds & 0x1) 4781 config.link_speed |= I40E_LINK_SPEED_100MB; 4782 4783 /* Do aq command & restart link */ 4784 aq_error = i40e_aq_set_phy_config(hw, &config, NULL); 4785 if (aq_error) { 4786 device_printf(dev, 4787 "%s: Error setting new phy config %d," 4788 " aq error: %d\n", __func__, aq_error, 4789 hw->aq.asq_last_status); 4790 return (EAGAIN); 4791 } 4792 4793 /* 4794 ** This seems a bit heavy handed, but we 4795 ** need to get a reinit on some devices 4796 */ 4797 IXL_PF_LOCK(pf); 4798 ixl_stop(pf); 4799 ixl_init_locked(pf); 4800 IXL_PF_UNLOCK(pf); 4801 4802 return (0); 4803} 4804 4805/* 4806** Control link advertise speed: 4807** Flags: 4808** 0x1 - advertise 100 Mb 4809** 0x2 - advertise 1G 4810** 0x4 - advertise 10G 4811** 0x8 - advertise 20G 4812** 4813** Does not work on 40G devices. 4814*/ 4815static int 4816ixl_set_advertise(SYSCTL_HANDLER_ARGS) 4817{ 4818 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4819 struct i40e_hw *hw = &pf->hw; 4820 device_t dev = pf->dev; 4821 int requested_ls = 0; 4822 int error = 0; 4823 4824 /* 4825 ** FW doesn't support changing advertised speed 4826 ** for 40G devices; speed is always 40G. 4827 */ 4828 if (i40e_is_40G_device(hw->device_id)) 4829 return (ENODEV); 4830 4831 /* Read in new mode */ 4832 requested_ls = pf->advertised_speed; 4833 error = sysctl_handle_int(oidp, &requested_ls, 0, req); 4834 if ((error) || (req->newptr == NULL)) 4835 return (error); 4836 /* Check for sane value */ 4837 if (requested_ls < 0x1 || requested_ls > 0xE) { 4838 device_printf(dev, "Invalid advertised speed; " 4839 "valid modes are 0x1 through 0xE\n"); 4840 return (EINVAL); 4841 } 4842 /* Then check for validity based on adapter type */ 4843 switch (hw->device_id) { 4844 case I40E_DEV_ID_10G_BASE_T: 4845 case I40E_DEV_ID_10G_BASE_T4: 4846 if (requested_ls & 0x8) { 4847 device_printf(dev, 4848 "20Gbs speed not supported on this device.\n"); 4849 return (EINVAL); 4850 } 4851 break; 4852 case I40E_DEV_ID_20G_KR2: 4853 case I40E_DEV_ID_20G_KR2_A: 4854 if (requested_ls & 0x1) { 4855 device_printf(dev, 4856 "100Mbs speed not supported on this device.\n"); 4857 return (EINVAL); 4858 } 4859 break; 4860 default: 4861 if (requested_ls & ~0x6) { 4862 device_printf(dev, 4863 "Only 1/10Gbs speeds are supported on this device.\n"); 4864 return (EINVAL); 4865 } 4866 break; 4867 } 4868 4869 /* Exit if no change */ 4870 if (pf->advertised_speed == requested_ls) 4871 return (0); 4872 4873 error = ixl_set_advertised_speeds(pf, requested_ls); 4874 if (error) 4875 return (error); 4876 4877 pf->advertised_speed = requested_ls; 4878 ixl_update_link_status(pf); 4879 return (0); 4880} 4881 4882/* 4883** Get the width and transaction speed of 4884** the bus this adapter is plugged into. 4885*/ 4886static u16 4887ixl_get_bus_info(struct i40e_hw *hw, device_t dev) 4888{ 4889 u16 link; 4890 u32 offset; 4891 4892 /* Get the PCI Express Capabilities offset */ 4893 pci_find_cap(dev, PCIY_EXPRESS, &offset); 4894 4895 /* ...and read the Link Status Register */ 4896 link = pci_read_config(dev, offset + PCIER_LINK_STA, 2); 4897 4898 switch (link & I40E_PCI_LINK_WIDTH) { 4899 case I40E_PCI_LINK_WIDTH_1: 4900 hw->bus.width = i40e_bus_width_pcie_x1; 4901 break; 4902 case I40E_PCI_LINK_WIDTH_2: 4903 hw->bus.width = i40e_bus_width_pcie_x2; 4904 break; 4905 case I40E_PCI_LINK_WIDTH_4: 4906 hw->bus.width = i40e_bus_width_pcie_x4; 4907 break; 4908 case I40E_PCI_LINK_WIDTH_8: 4909 hw->bus.width = i40e_bus_width_pcie_x8; 4910 break; 4911 default: 4912 hw->bus.width = i40e_bus_width_unknown; 4913 break; 4914 } 4915 4916 switch (link & I40E_PCI_LINK_SPEED) { 4917 case I40E_PCI_LINK_SPEED_2500: 4918 hw->bus.speed = i40e_bus_speed_2500; 4919 break; 4920 case I40E_PCI_LINK_SPEED_5000: 4921 hw->bus.speed = i40e_bus_speed_5000; 4922 break; 4923 case I40E_PCI_LINK_SPEED_8000: 4924 hw->bus.speed = i40e_bus_speed_8000; 4925 break; 4926 default: 4927 hw->bus.speed = i40e_bus_speed_unknown; 4928 break; 4929 } 4930 4931 4932 device_printf(dev,"PCI Express Bus: Speed %s %s\n", 4933 ((hw->bus.speed == i40e_bus_speed_8000) ? "8.0GT/s": 4934 (hw->bus.speed == i40e_bus_speed_5000) ? "5.0GT/s": 4935 (hw->bus.speed == i40e_bus_speed_2500) ? "2.5GT/s":"Unknown"), 4936 (hw->bus.width == i40e_bus_width_pcie_x8) ? "Width x8" : 4937 (hw->bus.width == i40e_bus_width_pcie_x4) ? "Width x4" : 4938 (hw->bus.width == i40e_bus_width_pcie_x1) ? "Width x1" : 4939 ("Unknown")); 4940 4941 if ((hw->bus.width <= i40e_bus_width_pcie_x8) && 4942 (hw->bus.speed < i40e_bus_speed_8000)) { 4943 device_printf(dev, "PCI-Express bandwidth available" 4944 " for this device\n may be insufficient for" 4945 " optimal performance.\n"); 4946 device_printf(dev, "For expected performance a x8 " 4947 "PCIE Gen3 slot is required.\n"); 4948 } 4949 4950 return (link); 4951} 4952 4953static int 4954ixl_sysctl_show_fw(SYSCTL_HANDLER_ARGS) 4955{ 4956 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4957 struct i40e_hw *hw = &pf->hw; 4958 char buf[32]; 4959 4960 snprintf(buf, sizeof(buf), 4961 "f%d.%d a%d.%d n%02x.%02x e%08x", 4962 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, 4963 hw->aq.api_maj_ver, hw->aq.api_min_ver, 4964 (hw->nvm.version & IXL_NVM_VERSION_HI_MASK) >> 4965 IXL_NVM_VERSION_HI_SHIFT, 4966 (hw->nvm.version & IXL_NVM_VERSION_LO_MASK) >> 4967 IXL_NVM_VERSION_LO_SHIFT, 4968 hw->nvm.eetrack); 4969 return (sysctl_handle_string(oidp, buf, strlen(buf), req)); 4970} 4971 4972 4973#ifdef IXL_DEBUG_SYSCTL 4974static int 4975ixl_sysctl_link_status(SYSCTL_HANDLER_ARGS) 4976{ 4977 struct ixl_pf *pf = (struct ixl_pf *)arg1; 4978 struct i40e_hw *hw = &pf->hw; 4979 struct i40e_link_status link_status; 4980 char buf[512]; 4981 4982 enum i40e_status_code aq_error = 0; 4983 4984 aq_error = i40e_aq_get_link_info(hw, TRUE, &link_status, NULL); 4985 if (aq_error) { 4986 printf("i40e_aq_get_link_info() error %d\n", aq_error); 4987 return (EPERM); 4988 } 4989 4990 sprintf(buf, "\n" 4991 "PHY Type : %#04x\n" 4992 "Speed : %#04x\n" 4993 "Link info: %#04x\n" 4994 "AN info : %#04x\n" 4995 "Ext info : %#04x", 4996 link_status.phy_type, link_status.link_speed, 4997 link_status.link_info, link_status.an_info, 4998 link_status.ext_info); 4999 5000 return (sysctl_handle_string(oidp, buf, strlen(buf), req)); 5001} 5002 5003static int 5004ixl_sysctl_phy_abilities(SYSCTL_HANDLER_ARGS) 5005{ 5006 struct ixl_pf *pf = (struct ixl_pf *)arg1; 5007 struct i40e_hw *hw = &pf->hw; 5008 char buf[512]; 5009 enum i40e_status_code aq_error = 0; 5010 5011 struct i40e_aq_get_phy_abilities_resp abilities; 5012 5013 aq_error = i40e_aq_get_phy_capabilities(hw, 5014 TRUE, FALSE, &abilities, NULL); 5015 if (aq_error) { 5016 printf("i40e_aq_get_phy_capabilities() error %d\n", aq_error); 5017 return (EPERM); 5018 } 5019 5020 sprintf(buf, "\n" 5021 "PHY Type : %#010x\n" 5022 "Speed : %#04x\n" 5023 "Abilities: %#04x\n" 5024 "EEE cap : %#06x\n" 5025 "EEER reg : %#010x\n" 5026 "D3 Lpan : %#04x", 5027 abilities.phy_type, abilities.link_speed, 5028 abilities.abilities, abilities.eee_capability, 5029 abilities.eeer_val, abilities.d3_lpan); 5030 5031 return (sysctl_handle_string(oidp, buf, strlen(buf), req)); 5032} 5033 5034static int 5035ixl_sysctl_sw_filter_list(SYSCTL_HANDLER_ARGS) 5036{ 5037 struct ixl_pf *pf = (struct ixl_pf *)arg1; 5038 struct ixl_vsi *vsi = &pf->vsi; 5039 struct ixl_mac_filter *f; 5040 char *buf, *buf_i; 5041 5042 int error = 0; 5043 int ftl_len = 0; 5044 int ftl_counter = 0; 5045 int buf_len = 0; 5046 int entry_len = 42; 5047 5048 SLIST_FOREACH(f, &vsi->ftl, next) { 5049 ftl_len++; 5050 } 5051 5052 if (ftl_len < 1) { 5053 sysctl_handle_string(oidp, "(none)", 6, req); 5054 return (0); 5055 } 5056 5057 buf_len = sizeof(char) * (entry_len + 1) * ftl_len + 2; 5058 buf = buf_i = malloc(buf_len, M_DEVBUF, M_NOWAIT); 5059 5060 sprintf(buf_i++, "\n"); 5061 SLIST_FOREACH(f, &vsi->ftl, next) { 5062 sprintf(buf_i, 5063 MAC_FORMAT ", vlan %4d, flags %#06x", 5064 MAC_FORMAT_ARGS(f->macaddr), f->vlan, f->flags); 5065 buf_i += entry_len; 5066 /* don't print '\n' for last entry */ 5067 if (++ftl_counter != ftl_len) { 5068 sprintf(buf_i, "\n"); 5069 buf_i++; 5070 } 5071 } 5072 5073 error = sysctl_handle_string(oidp, buf, strlen(buf), req); 5074 if (error) 5075 printf("sysctl error: %d\n", error); 5076 free(buf, M_DEVBUF); 5077 return error; 5078} 5079 5080#define IXL_SW_RES_SIZE 0x14 5081static int 5082ixl_res_alloc_cmp(const void *a, const void *b) 5083{ 5084 const struct i40e_aqc_switch_resource_alloc_element_resp *one, *two; 5085 one = (const struct i40e_aqc_switch_resource_alloc_element_resp *)a; 5086 two = (const struct i40e_aqc_switch_resource_alloc_element_resp *)b; 5087 5088 return ((int)one->resource_type - (int)two->resource_type); 5089} 5090 5091static int 5092ixl_sysctl_hw_res_alloc(SYSCTL_HANDLER_ARGS) 5093{ 5094 struct ixl_pf *pf = (struct ixl_pf *)arg1; 5095 struct i40e_hw *hw = &pf->hw; 5096 device_t dev = pf->dev; 5097 struct sbuf *buf; 5098 int error = 0; 5099 5100 u8 num_entries; 5101 struct i40e_aqc_switch_resource_alloc_element_resp resp[IXL_SW_RES_SIZE]; 5102 5103 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 5104 if (!buf) { 5105 device_printf(dev, "Could not allocate sbuf for output.\n"); 5106 return (ENOMEM); 5107 } 5108 5109 bzero(resp, sizeof(resp)); 5110 error = i40e_aq_get_switch_resource_alloc(hw, &num_entries, 5111 resp, 5112 IXL_SW_RES_SIZE, 5113 NULL); 5114 if (error) { 5115 device_printf(dev, 5116 "%s: get_switch_resource_alloc() error %d, aq error %d\n", 5117 __func__, error, hw->aq.asq_last_status); 5118 sbuf_delete(buf); 5119 return error; 5120 } 5121 5122 /* Sort entries by type for display */ 5123 qsort(resp, num_entries, 5124 sizeof(struct i40e_aqc_switch_resource_alloc_element_resp), 5125 &ixl_res_alloc_cmp); 5126 5127 sbuf_cat(buf, "\n"); 5128 sbuf_printf(buf, "# of entries: %d\n", num_entries); 5129 sbuf_printf(buf, 5130 "Type | Guaranteed | Total | Used | Un-allocated\n" 5131 " | (this) | (all) | (this) | (all) \n"); 5132 for (int i = 0; i < num_entries; i++) { 5133 sbuf_printf(buf, 5134 "%#4x | %10d %5d %6d %12d", 5135 resp[i].resource_type, 5136 resp[i].guaranteed, 5137 resp[i].total, 5138 resp[i].used, 5139 resp[i].total_unalloced); 5140 if (i < num_entries - 1) 5141 sbuf_cat(buf, "\n"); 5142 } 5143 5144 error = sbuf_finish(buf); 5145 if (error) 5146 device_printf(dev, "Error finishing sbuf: %d\n", error); 5147 5148 sbuf_delete(buf); 5149 return error; 5150} 5151 5152/* 5153** Caller must init and delete sbuf; this function will clear and 5154** finish it for caller. 5155*/ 5156static char * 5157ixl_switch_element_string(struct sbuf *s, u16 seid, bool uplink) 5158{ 5159 sbuf_clear(s); 5160 5161 if (seid == 0 && uplink) 5162 sbuf_cat(s, "Network"); 5163 else if (seid == 0) 5164 sbuf_cat(s, "Host"); 5165 else if (seid == 1) 5166 sbuf_cat(s, "EMP"); 5167 else if (seid <= 5) 5168 sbuf_printf(s, "MAC %d", seid - 2); 5169 else if (seid <= 15) 5170 sbuf_cat(s, "Reserved"); 5171 else if (seid <= 31) 5172 sbuf_printf(s, "PF %d", seid - 16); 5173 else if (seid <= 159) 5174 sbuf_printf(s, "VF %d", seid - 32); 5175 else if (seid <= 287) 5176 sbuf_cat(s, "Reserved"); 5177 else if (seid <= 511) 5178 sbuf_cat(s, "Other"); // for other structures 5179 else if (seid <= 895) 5180 sbuf_printf(s, "VSI %d", seid - 512); 5181 else if (seid <= 1023) 5182 sbuf_printf(s, "Reserved"); 5183 else 5184 sbuf_cat(s, "Invalid"); 5185 5186 sbuf_finish(s); 5187 return sbuf_data(s); 5188} 5189 5190static int 5191ixl_sysctl_switch_config(SYSCTL_HANDLER_ARGS) 5192{ 5193 struct ixl_pf *pf = (struct ixl_pf *)arg1; 5194 struct i40e_hw *hw = &pf->hw; 5195 device_t dev = pf->dev; 5196 struct sbuf *buf; 5197 struct sbuf *nmbuf; 5198 int error = 0; 5199 u8 aq_buf[I40E_AQ_LARGE_BUF]; 5200 5201 u16 next = 0; 5202 struct i40e_aqc_get_switch_config_resp *sw_config; 5203 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf; 5204 5205 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 5206 if (!buf) { 5207 device_printf(dev, "Could not allocate sbuf for sysctl output.\n"); 5208 return (ENOMEM); 5209 } 5210 5211 error = i40e_aq_get_switch_config(hw, sw_config, 5212 sizeof(aq_buf), &next, NULL); 5213 if (error) { 5214 device_printf(dev, 5215 "%s: aq_get_switch_config() error %d, aq error %d\n", 5216 __func__, error, hw->aq.asq_last_status); 5217 sbuf_delete(buf); 5218 return error; 5219 } 5220 5221 nmbuf = sbuf_new_auto(); 5222 if (!nmbuf) { 5223 device_printf(dev, "Could not allocate sbuf for name output.\n"); 5224 sbuf_delete(buf); 5225 return (ENOMEM); 5226 } 5227 5228 sbuf_cat(buf, "\n"); 5229 // Assuming <= 255 elements in switch 5230 sbuf_printf(buf, "# of elements: %d\n", sw_config->header.num_reported); 5231 /* Exclude: 5232 ** Revision -- all elements are revision 1 for now 5233 */ 5234 sbuf_printf(buf, 5235 "SEID ( Name ) | Uplink | Downlink | Conn Type\n" 5236 " | | | (uplink)\n"); 5237 for (int i = 0; i < sw_config->header.num_reported; i++) { 5238 // "%4d (%8s) | %8s %8s %#8x", 5239 sbuf_printf(buf, "%4d", sw_config->element[i].seid); 5240 sbuf_cat(buf, " "); 5241 sbuf_printf(buf, "(%8s)", ixl_switch_element_string(nmbuf, 5242 sw_config->element[i].seid, false)); 5243 sbuf_cat(buf, " | "); 5244 sbuf_printf(buf, "%8s", ixl_switch_element_string(nmbuf, 5245 sw_config->element[i].uplink_seid, true)); 5246 sbuf_cat(buf, " "); 5247 sbuf_printf(buf, "%8s", ixl_switch_element_string(nmbuf, 5248 sw_config->element[i].downlink_seid, false)); 5249 sbuf_cat(buf, " "); 5250 sbuf_printf(buf, "%#8x", sw_config->element[i].connection_type); 5251 if (i < sw_config->header.num_reported - 1) 5252 sbuf_cat(buf, "\n"); 5253 } 5254 sbuf_delete(nmbuf); 5255 5256 error = sbuf_finish(buf); 5257 if (error) 5258 device_printf(dev, "Error finishing sbuf: %d\n", error); 5259 5260 sbuf_delete(buf); 5261 5262 return (error); 5263} 5264#endif /* IXL_DEBUG_SYSCTL */ 5265 5266 5267#ifdef PCI_IOV 5268static int 5269ixl_vf_alloc_vsi(struct ixl_pf *pf, struct ixl_vf *vf) 5270{ 5271 struct i40e_hw *hw; 5272 struct ixl_vsi *vsi; 5273 struct i40e_vsi_context vsi_ctx; 5274 int i; 5275 uint16_t first_queue; 5276 enum i40e_status_code code; 5277 5278 hw = &pf->hw; 5279 vsi = &pf->vsi; 5280 5281 vsi_ctx.pf_num = hw->pf_id; 5282 vsi_ctx.uplink_seid = pf->veb_seid; 5283 vsi_ctx.connection_type = IXL_VSI_DATA_PORT; 5284 vsi_ctx.vf_num = hw->func_caps.vf_base_id + vf->vf_num; 5285 vsi_ctx.flags = I40E_AQ_VSI_TYPE_VF; 5286 5287 bzero(&vsi_ctx.info, sizeof(vsi_ctx.info)); 5288 5289 vsi_ctx.info.valid_sections = htole16(I40E_AQ_VSI_PROP_SWITCH_VALID); 5290 vsi_ctx.info.switch_id = htole16(0); 5291 5292 vsi_ctx.info.valid_sections |= htole16(I40E_AQ_VSI_PROP_SECURITY_VALID); 5293 vsi_ctx.info.sec_flags = 0; 5294 if (vf->vf_flags & VF_FLAG_MAC_ANTI_SPOOF) 5295 vsi_ctx.info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK; 5296 5297 vsi_ctx.info.valid_sections |= htole16(I40E_AQ_VSI_PROP_VLAN_VALID); 5298 vsi_ctx.info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL | 5299 I40E_AQ_VSI_PVLAN_EMOD_NOTHING; 5300 5301 vsi_ctx.info.valid_sections |= 5302 htole16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID); 5303 vsi_ctx.info.mapping_flags = htole16(I40E_AQ_VSI_QUE_MAP_NONCONTIG); 5304 first_queue = vsi->num_queues + vf->vf_num * IXLV_MAX_QUEUES; 5305 for (i = 0; i < IXLV_MAX_QUEUES; i++) 5306 vsi_ctx.info.queue_mapping[i] = htole16(first_queue + i); 5307 for (; i < nitems(vsi_ctx.info.queue_mapping); i++) 5308 vsi_ctx.info.queue_mapping[i] = htole16(I40E_AQ_VSI_QUEUE_MASK); 5309 5310 vsi_ctx.info.tc_mapping[0] = htole16( 5311 (0 << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | 5312 (1 << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)); 5313 5314 code = i40e_aq_add_vsi(hw, &vsi_ctx, NULL); 5315 if (code != I40E_SUCCESS) 5316 return (ixl_adminq_err_to_errno(hw->aq.asq_last_status)); 5317 vf->vsi.seid = vsi_ctx.seid; 5318 vf->vsi.vsi_num = vsi_ctx.vsi_number; 5319 vf->vsi.first_queue = first_queue; 5320 vf->vsi.num_queues = IXLV_MAX_QUEUES; 5321 5322 code = i40e_aq_get_vsi_params(hw, &vsi_ctx, NULL); 5323 if (code != I40E_SUCCESS) 5324 return (ixl_adminq_err_to_errno(hw->aq.asq_last_status)); 5325 5326 code = i40e_aq_config_vsi_bw_limit(hw, vf->vsi.seid, 0, 0, NULL); 5327 if (code != I40E_SUCCESS) { 5328 device_printf(pf->dev, "Failed to disable BW limit: %d\n", 5329 ixl_adminq_err_to_errno(hw->aq.asq_last_status)); 5330 return (ixl_adminq_err_to_errno(hw->aq.asq_last_status)); 5331 } 5332 5333 memcpy(&vf->vsi.info, &vsi_ctx.info, sizeof(vf->vsi.info)); 5334 return (0); 5335} 5336 5337static int 5338ixl_vf_setup_vsi(struct ixl_pf *pf, struct ixl_vf *vf) 5339{ 5340 struct i40e_hw *hw; 5341 int error; 5342 5343 hw = &pf->hw; 5344 5345 error = ixl_vf_alloc_vsi(pf, vf); 5346 if (error != 0) 5347 return (error); 5348 5349 vf->vsi.hw_filters_add = 0; 5350 vf->vsi.hw_filters_del = 0; 5351 ixl_add_filter(&vf->vsi, ixl_bcast_addr, IXL_VLAN_ANY); 5352 ixl_reconfigure_filters(&vf->vsi); 5353 5354 return (0); 5355} 5356 5357static void 5358ixl_vf_map_vsi_queue(struct i40e_hw *hw, struct ixl_vf *vf, int qnum, 5359 uint32_t val) 5360{ 5361 uint32_t qtable; 5362 int index, shift; 5363 5364 /* 5365 * Two queues are mapped in a single register, so we have to do some 5366 * gymnastics to convert the queue number into a register index and 5367 * shift. 5368 */ 5369 index = qnum / 2; 5370 shift = (qnum % 2) * I40E_VSILAN_QTABLE_QINDEX_1_SHIFT; 5371 5372 qtable = rd32(hw, I40E_VSILAN_QTABLE(index, vf->vsi.vsi_num)); 5373 qtable &= ~(I40E_VSILAN_QTABLE_QINDEX_0_MASK << shift); 5374 qtable |= val << shift; 5375 wr32(hw, I40E_VSILAN_QTABLE(index, vf->vsi.vsi_num), qtable); 5376} 5377 5378static void 5379ixl_vf_map_queues(struct ixl_pf *pf, struct ixl_vf *vf) 5380{ 5381 struct i40e_hw *hw; 5382 uint32_t qtable; 5383 int i; 5384 5385 hw = &pf->hw; 5386 5387 /* 5388 * Contiguous mappings aren't actually supported by the hardware, 5389 * so we have to use non-contiguous mappings. 5390 */ 5391 wr32(hw, I40E_VSILAN_QBASE(vf->vsi.vsi_num), 5392 I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK); 5393 5394 wr32(hw, I40E_VPLAN_MAPENA(vf->vf_num), 5395 I40E_VPLAN_MAPENA_TXRX_ENA_MASK); 5396 5397 for (i = 0; i < vf->vsi.num_queues; i++) { 5398 qtable = (vf->vsi.first_queue + i) << 5399 I40E_VPLAN_QTABLE_QINDEX_SHIFT; 5400 5401 wr32(hw, I40E_VPLAN_QTABLE(i, vf->vf_num), qtable); 5402 } 5403 5404 /* Map queues allocated to VF to its VSI. */ 5405 for (i = 0; i < vf->vsi.num_queues; i++) 5406 ixl_vf_map_vsi_queue(hw, vf, i, vf->vsi.first_queue + i); 5407 5408 /* Set rest of VSI queues as unused. */ 5409 for (; i < IXL_MAX_VSI_QUEUES; i++) 5410 ixl_vf_map_vsi_queue(hw, vf, i, 5411 I40E_VSILAN_QTABLE_QINDEX_0_MASK); 5412 5413 ixl_flush(hw); 5414} 5415 5416static void 5417ixl_vf_vsi_release(struct ixl_pf *pf, struct ixl_vsi *vsi) 5418{ 5419 struct i40e_hw *hw; 5420 5421 hw = &pf->hw; 5422 5423 if (vsi->seid == 0) 5424 return; 5425 5426 i40e_aq_delete_element(hw, vsi->seid, NULL); 5427} 5428 5429static void 5430ixl_vf_disable_queue_intr(struct i40e_hw *hw, uint32_t vfint_reg) 5431{ 5432 5433 wr32(hw, vfint_reg, I40E_VFINT_DYN_CTLN_CLEARPBA_MASK); 5434 ixl_flush(hw); 5435} 5436 5437static void 5438ixl_vf_unregister_intr(struct i40e_hw *hw, uint32_t vpint_reg) 5439{ 5440 5441 wr32(hw, vpint_reg, I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK | 5442 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK); 5443 ixl_flush(hw); 5444} 5445 5446static void 5447ixl_vf_release_resources(struct ixl_pf *pf, struct ixl_vf *vf) 5448{ 5449 struct i40e_hw *hw; 5450 uint32_t vfint_reg, vpint_reg; 5451 int i; 5452 5453 hw = &pf->hw; 5454 5455 ixl_vf_vsi_release(pf, &vf->vsi); 5456 5457 /* Index 0 has a special register. */ 5458 ixl_vf_disable_queue_intr(hw, I40E_VFINT_DYN_CTL0(vf->vf_num)); 5459 5460 for (i = 1; i < hw->func_caps.num_msix_vectors_vf; i++) { 5461 vfint_reg = IXL_VFINT_DYN_CTLN_REG(hw, i , vf->vf_num); 5462 ixl_vf_disable_queue_intr(hw, vfint_reg); 5463 } 5464 5465 /* Index 0 has a special register. */ 5466 ixl_vf_unregister_intr(hw, I40E_VPINT_LNKLST0(vf->vf_num)); 5467 5468 for (i = 1; i < hw->func_caps.num_msix_vectors_vf; i++) { 5469 vpint_reg = IXL_VPINT_LNKLSTN_REG(hw, i, vf->vf_num); 5470 ixl_vf_unregister_intr(hw, vpint_reg); 5471 } 5472 5473 vf->vsi.num_queues = 0; 5474} 5475 5476static int 5477ixl_flush_pcie(struct ixl_pf *pf, struct ixl_vf *vf) 5478{ 5479 struct i40e_hw *hw; 5480 int i; 5481 uint16_t global_vf_num; 5482 uint32_t ciad; 5483 5484 hw = &pf->hw; 5485 global_vf_num = hw->func_caps.vf_base_id + vf->vf_num; 5486 5487 wr32(hw, I40E_PF_PCI_CIAA, IXL_PF_PCI_CIAA_VF_DEVICE_STATUS | 5488 (global_vf_num << I40E_PF_PCI_CIAA_VF_NUM_SHIFT)); 5489 for (i = 0; i < IXL_VF_RESET_TIMEOUT; i++) { 5490 ciad = rd32(hw, I40E_PF_PCI_CIAD); 5491 if ((ciad & IXL_PF_PCI_CIAD_VF_TRANS_PENDING_MASK) == 0) 5492 return (0); 5493 DELAY(1); 5494 } 5495 5496 return (ETIMEDOUT); 5497} 5498 5499static void 5500ixl_reset_vf(struct ixl_pf *pf, struct ixl_vf *vf) 5501{ 5502 struct i40e_hw *hw; 5503 uint32_t vfrtrig; 5504 5505 hw = &pf->hw; 5506 5507 vfrtrig = rd32(hw, I40E_VPGEN_VFRTRIG(vf->vf_num)); 5508 vfrtrig |= I40E_VPGEN_VFRTRIG_VFSWR_MASK; 5509 wr32(hw, I40E_VPGEN_VFRTRIG(vf->vf_num), vfrtrig); 5510 ixl_flush(hw); 5511 5512 ixl_reinit_vf(pf, vf); 5513} 5514 5515static void 5516ixl_reinit_vf(struct ixl_pf *pf, struct ixl_vf *vf) 5517{ 5518 struct i40e_hw *hw; 5519 uint32_t vfrstat, vfrtrig; 5520 int i, error; 5521 5522 hw = &pf->hw; 5523 5524 error = ixl_flush_pcie(pf, vf); 5525 if (error != 0) 5526 device_printf(pf->dev, 5527 "Timed out waiting for PCIe activity to stop on VF-%d\n", 5528 vf->vf_num); 5529 5530 for (i = 0; i < IXL_VF_RESET_TIMEOUT; i++) { 5531 DELAY(10); 5532 5533 vfrstat = rd32(hw, I40E_VPGEN_VFRSTAT(vf->vf_num)); 5534 if (vfrstat & I40E_VPGEN_VFRSTAT_VFRD_MASK) 5535 break; 5536 } 5537 5538 if (i == IXL_VF_RESET_TIMEOUT) 5539 device_printf(pf->dev, "VF %d failed to reset\n", vf->vf_num); 5540 5541 wr32(hw, I40E_VFGEN_RSTAT1(vf->vf_num), I40E_VFR_COMPLETED); 5542 5543 vfrtrig = rd32(hw, I40E_VPGEN_VFRTRIG(vf->vf_num)); 5544 vfrtrig &= ~I40E_VPGEN_VFRTRIG_VFSWR_MASK; 5545 wr32(hw, I40E_VPGEN_VFRTRIG(vf->vf_num), vfrtrig); 5546 5547 if (vf->vsi.seid != 0) 5548 ixl_disable_rings(&vf->vsi); 5549 5550 ixl_vf_release_resources(pf, vf); 5551 ixl_vf_setup_vsi(pf, vf); 5552 ixl_vf_map_queues(pf, vf); 5553 5554 wr32(hw, I40E_VFGEN_RSTAT1(vf->vf_num), I40E_VFR_VFACTIVE); 5555 ixl_flush(hw); 5556} 5557 5558static const char * 5559ixl_vc_opcode_str(uint16_t op) 5560{ 5561 5562 switch (op) { 5563 case I40E_VIRTCHNL_OP_VERSION: 5564 return ("VERSION"); 5565 case I40E_VIRTCHNL_OP_RESET_VF: 5566 return ("RESET_VF"); 5567 case I40E_VIRTCHNL_OP_GET_VF_RESOURCES: 5568 return ("GET_VF_RESOURCES"); 5569 case I40E_VIRTCHNL_OP_CONFIG_TX_QUEUE: 5570 return ("CONFIG_TX_QUEUE"); 5571 case I40E_VIRTCHNL_OP_CONFIG_RX_QUEUE: 5572 return ("CONFIG_RX_QUEUE"); 5573 case I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES: 5574 return ("CONFIG_VSI_QUEUES"); 5575 case I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP: 5576 return ("CONFIG_IRQ_MAP"); 5577 case I40E_VIRTCHNL_OP_ENABLE_QUEUES: 5578 return ("ENABLE_QUEUES"); 5579 case I40E_VIRTCHNL_OP_DISABLE_QUEUES: 5580 return ("DISABLE_QUEUES"); 5581 case I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS: 5582 return ("ADD_ETHER_ADDRESS"); 5583 case I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS: 5584 return ("DEL_ETHER_ADDRESS"); 5585 case I40E_VIRTCHNL_OP_ADD_VLAN: 5586 return ("ADD_VLAN"); 5587 case I40E_VIRTCHNL_OP_DEL_VLAN: 5588 return ("DEL_VLAN"); 5589 case I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE: 5590 return ("CONFIG_PROMISCUOUS_MODE"); 5591 case I40E_VIRTCHNL_OP_GET_STATS: 5592 return ("GET_STATS"); 5593 case I40E_VIRTCHNL_OP_FCOE: 5594 return ("FCOE"); 5595 case I40E_VIRTCHNL_OP_EVENT: 5596 return ("EVENT"); 5597 default: 5598 return ("UNKNOWN"); 5599 } 5600} 5601 5602static int 5603ixl_vc_opcode_level(uint16_t opcode) 5604{ 5605 5606 switch (opcode) { 5607 case I40E_VIRTCHNL_OP_GET_STATS: 5608 return (10); 5609 default: 5610 return (5); 5611 } 5612} 5613 5614static void 5615ixl_send_vf_msg(struct ixl_pf *pf, struct ixl_vf *vf, uint16_t op, 5616 enum i40e_status_code status, void *msg, uint16_t len) 5617{ 5618 struct i40e_hw *hw; 5619 int global_vf_id; 5620 5621 hw = &pf->hw; 5622 global_vf_id = hw->func_caps.vf_base_id + vf->vf_num; 5623 5624 I40E_VC_DEBUG(pf, ixl_vc_opcode_level(op), 5625 "Sending msg (op=%s[%d], status=%d) to VF-%d\n", 5626 ixl_vc_opcode_str(op), op, status, vf->vf_num); 5627 5628 i40e_aq_send_msg_to_vf(hw, global_vf_id, op, status, msg, len, NULL); 5629} 5630 5631static void 5632ixl_send_vf_ack(struct ixl_pf *pf, struct ixl_vf *vf, uint16_t op) 5633{ 5634 5635 ixl_send_vf_msg(pf, vf, op, I40E_SUCCESS, NULL, 0); 5636} 5637 5638static void 5639ixl_send_vf_nack_msg(struct ixl_pf *pf, struct ixl_vf *vf, uint16_t op, 5640 enum i40e_status_code status, const char *file, int line) 5641{ 5642 5643 I40E_VC_DEBUG(pf, 1, 5644 "Sending NACK (op=%s[%d], err=%d) to VF-%d from %s:%d\n", 5645 ixl_vc_opcode_str(op), op, status, vf->vf_num, file, line); 5646 ixl_send_vf_msg(pf, vf, op, status, NULL, 0); 5647} 5648 5649static void 5650ixl_vf_version_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 5651 uint16_t msg_size) 5652{ 5653 struct i40e_virtchnl_version_info reply; 5654 5655 if (msg_size != sizeof(struct i40e_virtchnl_version_info)) { 5656 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_VERSION, 5657 I40E_ERR_PARAM); 5658 return; 5659 } 5660 5661 reply.major = I40E_VIRTCHNL_VERSION_MAJOR; 5662 reply.minor = I40E_VIRTCHNL_VERSION_MINOR; 5663 ixl_send_vf_msg(pf, vf, I40E_VIRTCHNL_OP_VERSION, I40E_SUCCESS, &reply, 5664 sizeof(reply)); 5665} 5666 5667static void 5668ixl_vf_reset_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 5669 uint16_t msg_size) 5670{ 5671 5672 if (msg_size != 0) { 5673 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_RESET_VF, 5674 I40E_ERR_PARAM); 5675 return; 5676 } 5677 5678 ixl_reset_vf(pf, vf); 5679 5680 /* No response to a reset message. */ 5681} 5682 5683static void 5684ixl_vf_get_resources_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 5685 uint16_t msg_size) 5686{ 5687 struct i40e_virtchnl_vf_resource reply; 5688 5689 if (msg_size != 0) { 5690 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_GET_VF_RESOURCES, 5691 I40E_ERR_PARAM); 5692 return; 5693 } 5694 5695 bzero(&reply, sizeof(reply)); 5696 5697 reply.vf_offload_flags = I40E_VIRTCHNL_VF_OFFLOAD_L2; 5698 5699 reply.num_vsis = 1; 5700 reply.num_queue_pairs = vf->vsi.num_queues; 5701 reply.max_vectors = pf->hw.func_caps.num_msix_vectors_vf; 5702 reply.vsi_res[0].vsi_id = vf->vsi.vsi_num; 5703 reply.vsi_res[0].vsi_type = I40E_VSI_SRIOV; 5704 reply.vsi_res[0].num_queue_pairs = vf->vsi.num_queues; 5705 memcpy(reply.vsi_res[0].default_mac_addr, vf->mac, ETHER_ADDR_LEN); 5706 5707 ixl_send_vf_msg(pf, vf, I40E_VIRTCHNL_OP_GET_VF_RESOURCES, 5708 I40E_SUCCESS, &reply, sizeof(reply)); 5709} 5710 5711static int 5712ixl_vf_config_tx_queue(struct ixl_pf *pf, struct ixl_vf *vf, 5713 struct i40e_virtchnl_txq_info *info) 5714{ 5715 struct i40e_hw *hw; 5716 struct i40e_hmc_obj_txq txq; 5717 uint16_t global_queue_num, global_vf_num; 5718 enum i40e_status_code status; 5719 uint32_t qtx_ctl; 5720 5721 hw = &pf->hw; 5722 global_queue_num = vf->vsi.first_queue + info->queue_id; 5723 global_vf_num = hw->func_caps.vf_base_id + vf->vf_num; 5724 bzero(&txq, sizeof(txq)); 5725 5726 status = i40e_clear_lan_tx_queue_context(hw, global_queue_num); 5727 if (status != I40E_SUCCESS) 5728 return (EINVAL); 5729 5730 txq.base = info->dma_ring_addr / IXL_TX_CTX_BASE_UNITS; 5731 5732 txq.head_wb_ena = info->headwb_enabled; 5733 txq.head_wb_addr = info->dma_headwb_addr; 5734 txq.qlen = info->ring_len; 5735 txq.rdylist = le16_to_cpu(vf->vsi.info.qs_handle[0]); 5736 txq.rdylist_act = 0; 5737 5738 status = i40e_set_lan_tx_queue_context(hw, global_queue_num, &txq); 5739 if (status != I40E_SUCCESS) 5740 return (EINVAL); 5741 5742 qtx_ctl = I40E_QTX_CTL_VF_QUEUE | 5743 (hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) | 5744 (global_vf_num << I40E_QTX_CTL_VFVM_INDX_SHIFT); 5745 wr32(hw, I40E_QTX_CTL(global_queue_num), qtx_ctl); 5746 ixl_flush(hw); 5747 5748 return (0); 5749} 5750 5751static int 5752ixl_vf_config_rx_queue(struct ixl_pf *pf, struct ixl_vf *vf, 5753 struct i40e_virtchnl_rxq_info *info) 5754{ 5755 struct i40e_hw *hw; 5756 struct i40e_hmc_obj_rxq rxq; 5757 uint16_t global_queue_num; 5758 enum i40e_status_code status; 5759 5760 hw = &pf->hw; 5761 global_queue_num = vf->vsi.first_queue + info->queue_id; 5762 bzero(&rxq, sizeof(rxq)); 5763 5764 if (info->databuffer_size > IXL_VF_MAX_BUFFER) 5765 return (EINVAL); 5766 5767 if (info->max_pkt_size > IXL_VF_MAX_FRAME || 5768 info->max_pkt_size < ETHER_MIN_LEN) 5769 return (EINVAL); 5770 5771 if (info->splithdr_enabled) { 5772 if (info->hdr_size > IXL_VF_MAX_HDR_BUFFER) 5773 return (EINVAL); 5774 5775 rxq.hsplit_0 = info->rx_split_pos & 5776 (I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_L2 | 5777 I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_IP | 5778 I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_TCP_UDP | 5779 I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_SCTP); 5780 rxq.hbuff = info->hdr_size >> I40E_RXQ_CTX_HBUFF_SHIFT; 5781 5782 rxq.dtype = 2; 5783 } 5784 5785 status = i40e_clear_lan_rx_queue_context(hw, global_queue_num); 5786 if (status != I40E_SUCCESS) 5787 return (EINVAL); 5788 5789 rxq.base = info->dma_ring_addr / IXL_RX_CTX_BASE_UNITS; 5790 rxq.qlen = info->ring_len; 5791 5792 rxq.dbuff = info->databuffer_size >> I40E_RXQ_CTX_DBUFF_SHIFT; 5793 5794 rxq.dsize = 1; 5795 rxq.crcstrip = 1; 5796 rxq.l2tsel = 1; 5797 5798 rxq.rxmax = info->max_pkt_size; 5799 rxq.tphrdesc_ena = 1; 5800 rxq.tphwdesc_ena = 1; 5801 rxq.tphdata_ena = 1; 5802 rxq.tphhead_ena = 1; 5803 rxq.lrxqthresh = 2; 5804 rxq.prefena = 1; 5805 5806 status = i40e_set_lan_rx_queue_context(hw, global_queue_num, &rxq); 5807 if (status != I40E_SUCCESS) 5808 return (EINVAL); 5809 5810 return (0); 5811} 5812 5813static void 5814ixl_vf_config_vsi_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 5815 uint16_t msg_size) 5816{ 5817 struct i40e_virtchnl_vsi_queue_config_info *info; 5818 struct i40e_virtchnl_queue_pair_info *pair; 5819 int i; 5820 5821 if (msg_size < sizeof(*info)) { 5822 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES, 5823 I40E_ERR_PARAM); 5824 return; 5825 } 5826 5827 info = msg; 5828 if (info->num_queue_pairs == 0) { 5829 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES, 5830 I40E_ERR_PARAM); 5831 return; 5832 } 5833 5834 if (msg_size != sizeof(*info) + info->num_queue_pairs * sizeof(*pair)) { 5835 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES, 5836 I40E_ERR_PARAM); 5837 return; 5838 } 5839 5840 if (info->vsi_id != vf->vsi.vsi_num) { 5841 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES, 5842 I40E_ERR_PARAM); 5843 return; 5844 } 5845 5846 for (i = 0; i < info->num_queue_pairs; i++) { 5847 pair = &info->qpair[i]; 5848 5849 if (pair->txq.vsi_id != vf->vsi.vsi_num || 5850 pair->rxq.vsi_id != vf->vsi.vsi_num || 5851 pair->txq.queue_id != pair->rxq.queue_id || 5852 pair->txq.queue_id >= vf->vsi.num_queues) { 5853 5854 i40e_send_vf_nack(pf, vf, 5855 I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES, I40E_ERR_PARAM); 5856 return; 5857 } 5858 5859 if (ixl_vf_config_tx_queue(pf, vf, &pair->txq) != 0) { 5860 i40e_send_vf_nack(pf, vf, 5861 I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES, I40E_ERR_PARAM); 5862 return; 5863 } 5864 5865 if (ixl_vf_config_rx_queue(pf, vf, &pair->rxq) != 0) { 5866 i40e_send_vf_nack(pf, vf, 5867 I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES, I40E_ERR_PARAM); 5868 return; 5869 } 5870 } 5871 5872 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES); 5873} 5874 5875static void 5876ixl_vf_set_qctl(struct ixl_pf *pf, 5877 const struct i40e_virtchnl_vector_map *vector, 5878 enum i40e_queue_type cur_type, uint16_t cur_queue, 5879 enum i40e_queue_type *last_type, uint16_t *last_queue) 5880{ 5881 uint32_t offset, qctl; 5882 uint16_t itr_indx; 5883 5884 if (cur_type == I40E_QUEUE_TYPE_RX) { 5885 offset = I40E_QINT_RQCTL(cur_queue); 5886 itr_indx = vector->rxitr_idx; 5887 } else { 5888 offset = I40E_QINT_TQCTL(cur_queue); 5889 itr_indx = vector->txitr_idx; 5890 } 5891 5892 qctl = htole32((vector->vector_id << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | 5893 (*last_type << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) | 5894 (*last_queue << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | 5895 I40E_QINT_RQCTL_CAUSE_ENA_MASK | 5896 (itr_indx << I40E_QINT_RQCTL_ITR_INDX_SHIFT)); 5897 5898 wr32(&pf->hw, offset, qctl); 5899 5900 *last_type = cur_type; 5901 *last_queue = cur_queue; 5902} 5903 5904static void 5905ixl_vf_config_vector(struct ixl_pf *pf, struct ixl_vf *vf, 5906 const struct i40e_virtchnl_vector_map *vector) 5907{ 5908 struct i40e_hw *hw; 5909 u_int qindex; 5910 enum i40e_queue_type type, last_type; 5911 uint32_t lnklst_reg; 5912 uint16_t rxq_map, txq_map, cur_queue, last_queue; 5913 5914 hw = &pf->hw; 5915 5916 rxq_map = vector->rxq_map; 5917 txq_map = vector->txq_map; 5918 5919 last_queue = IXL_END_OF_INTR_LNKLST; 5920 last_type = I40E_QUEUE_TYPE_RX; 5921 5922 /* 5923 * The datasheet says to optimize performance, RX queues and TX queues 5924 * should be interleaved in the interrupt linked list, so we process 5925 * both at once here. 5926 */ 5927 while ((rxq_map != 0) || (txq_map != 0)) { 5928 if (txq_map != 0) { 5929 qindex = ffs(txq_map) - 1; 5930 type = I40E_QUEUE_TYPE_TX; 5931 cur_queue = vf->vsi.first_queue + qindex; 5932 ixl_vf_set_qctl(pf, vector, type, cur_queue, 5933 &last_type, &last_queue); 5934 txq_map &= ~(1 << qindex); 5935 } 5936 5937 if (rxq_map != 0) { 5938 qindex = ffs(rxq_map) - 1; 5939 type = I40E_QUEUE_TYPE_RX; 5940 cur_queue = vf->vsi.first_queue + qindex; 5941 ixl_vf_set_qctl(pf, vector, type, cur_queue, 5942 &last_type, &last_queue); 5943 rxq_map &= ~(1 << qindex); 5944 } 5945 } 5946 5947 if (vector->vector_id == 0) 5948 lnklst_reg = I40E_VPINT_LNKLST0(vf->vf_num); 5949 else 5950 lnklst_reg = IXL_VPINT_LNKLSTN_REG(hw, vector->vector_id, 5951 vf->vf_num); 5952 wr32(hw, lnklst_reg, 5953 (last_queue << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) | 5954 (last_type << I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT)); 5955 5956 ixl_flush(hw); 5957} 5958 5959static void 5960ixl_vf_config_irq_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 5961 uint16_t msg_size) 5962{ 5963 struct i40e_virtchnl_irq_map_info *map; 5964 struct i40e_virtchnl_vector_map *vector; 5965 struct i40e_hw *hw; 5966 int i, largest_txq, largest_rxq; 5967 5968 hw = &pf->hw; 5969 5970 if (msg_size < sizeof(*map)) { 5971 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP, 5972 I40E_ERR_PARAM); 5973 return; 5974 } 5975 5976 map = msg; 5977 if (map->num_vectors == 0) { 5978 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP, 5979 I40E_ERR_PARAM); 5980 return; 5981 } 5982 5983 if (msg_size != sizeof(*map) + map->num_vectors * sizeof(*vector)) { 5984 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP, 5985 I40E_ERR_PARAM); 5986 return; 5987 } 5988 5989 for (i = 0; i < map->num_vectors; i++) { 5990 vector = &map->vecmap[i]; 5991 5992 if ((vector->vector_id >= hw->func_caps.num_msix_vectors_vf) || 5993 vector->vsi_id != vf->vsi.vsi_num) { 5994 i40e_send_vf_nack(pf, vf, 5995 I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP, I40E_ERR_PARAM); 5996 return; 5997 } 5998 5999 if (vector->rxq_map != 0) { 6000 largest_rxq = fls(vector->rxq_map) - 1; 6001 if (largest_rxq >= vf->vsi.num_queues) { 6002 i40e_send_vf_nack(pf, vf, 6003 I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP, 6004 I40E_ERR_PARAM); 6005 return; 6006 } 6007 } 6008 6009 if (vector->txq_map != 0) { 6010 largest_txq = fls(vector->txq_map) - 1; 6011 if (largest_txq >= vf->vsi.num_queues) { 6012 i40e_send_vf_nack(pf, vf, 6013 I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP, 6014 I40E_ERR_PARAM); 6015 return; 6016 } 6017 } 6018 6019 if (vector->rxitr_idx > IXL_MAX_ITR_IDX || 6020 vector->txitr_idx > IXL_MAX_ITR_IDX) { 6021 i40e_send_vf_nack(pf, vf, 6022 I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP, 6023 I40E_ERR_PARAM); 6024 return; 6025 } 6026 6027 ixl_vf_config_vector(pf, vf, vector); 6028 } 6029 6030 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP); 6031} 6032 6033static void 6034ixl_vf_enable_queues_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 6035 uint16_t msg_size) 6036{ 6037 struct i40e_virtchnl_queue_select *select; 6038 int error; 6039 6040 if (msg_size != sizeof(*select)) { 6041 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ENABLE_QUEUES, 6042 I40E_ERR_PARAM); 6043 return; 6044 } 6045 6046 select = msg; 6047 if (select->vsi_id != vf->vsi.vsi_num || 6048 select->rx_queues == 0 || select->tx_queues == 0) { 6049 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ENABLE_QUEUES, 6050 I40E_ERR_PARAM); 6051 return; 6052 } 6053 6054 error = ixl_enable_rings(&vf->vsi); 6055 if (error) { 6056 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ENABLE_QUEUES, 6057 I40E_ERR_TIMEOUT); 6058 return; 6059 } 6060 6061 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_ENABLE_QUEUES); 6062} 6063 6064static void 6065ixl_vf_disable_queues_msg(struct ixl_pf *pf, struct ixl_vf *vf, 6066 void *msg, uint16_t msg_size) 6067{ 6068 struct i40e_virtchnl_queue_select *select; 6069 int error; 6070 6071 if (msg_size != sizeof(*select)) { 6072 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_DISABLE_QUEUES, 6073 I40E_ERR_PARAM); 6074 return; 6075 } 6076 6077 select = msg; 6078 if (select->vsi_id != vf->vsi.vsi_num || 6079 select->rx_queues == 0 || select->tx_queues == 0) { 6080 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_DISABLE_QUEUES, 6081 I40E_ERR_PARAM); 6082 return; 6083 } 6084 6085 error = ixl_disable_rings(&vf->vsi); 6086 if (error) { 6087 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_DISABLE_QUEUES, 6088 I40E_ERR_TIMEOUT); 6089 return; 6090 } 6091 6092 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_DISABLE_QUEUES); 6093} 6094 6095static boolean_t 6096ixl_zero_mac(const uint8_t *addr) 6097{ 6098 uint8_t zero[ETHER_ADDR_LEN] = {0, 0, 0, 0, 0, 0}; 6099 6100 return (cmp_etheraddr(addr, zero)); 6101} 6102 6103static boolean_t 6104ixl_bcast_mac(const uint8_t *addr) 6105{ 6106 6107 return (cmp_etheraddr(addr, ixl_bcast_addr)); 6108} 6109 6110static int 6111ixl_vf_mac_valid(struct ixl_vf *vf, const uint8_t *addr) 6112{ 6113 6114 if (ixl_zero_mac(addr) || ixl_bcast_mac(addr)) 6115 return (EINVAL); 6116 6117 /* 6118 * If the VF is not allowed to change its MAC address, don't let it 6119 * set a MAC filter for an address that is not a multicast address and 6120 * is not its assigned MAC. 6121 */ 6122 if (!(vf->vf_flags & VF_FLAG_SET_MAC_CAP) && 6123 !(ETHER_IS_MULTICAST(addr) || cmp_etheraddr(addr, vf->mac))) 6124 return (EPERM); 6125 6126 return (0); 6127} 6128 6129static void 6130ixl_vf_add_mac_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 6131 uint16_t msg_size) 6132{ 6133 struct i40e_virtchnl_ether_addr_list *addr_list; 6134 struct i40e_virtchnl_ether_addr *addr; 6135 struct ixl_vsi *vsi; 6136 int i; 6137 size_t expected_size; 6138 6139 vsi = &vf->vsi; 6140 6141 if (msg_size < sizeof(*addr_list)) { 6142 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS, 6143 I40E_ERR_PARAM); 6144 return; 6145 } 6146 6147 addr_list = msg; 6148 expected_size = sizeof(*addr_list) + 6149 addr_list->num_elements * sizeof(*addr); 6150 6151 if (addr_list->num_elements == 0 || 6152 addr_list->vsi_id != vsi->vsi_num || 6153 msg_size != expected_size) { 6154 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS, 6155 I40E_ERR_PARAM); 6156 return; 6157 } 6158 6159 for (i = 0; i < addr_list->num_elements; i++) { 6160 if (ixl_vf_mac_valid(vf, addr_list->list[i].addr) != 0) { 6161 i40e_send_vf_nack(pf, vf, 6162 I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS, I40E_ERR_PARAM); 6163 return; 6164 } 6165 } 6166 6167 for (i = 0; i < addr_list->num_elements; i++) { 6168 addr = &addr_list->list[i]; 6169 ixl_add_filter(vsi, addr->addr, IXL_VLAN_ANY); 6170 } 6171 6172 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS); 6173} 6174 6175static void 6176ixl_vf_del_mac_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 6177 uint16_t msg_size) 6178{ 6179 struct i40e_virtchnl_ether_addr_list *addr_list; 6180 struct i40e_virtchnl_ether_addr *addr; 6181 size_t expected_size; 6182 int i; 6183 6184 if (msg_size < sizeof(*addr_list)) { 6185 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS, 6186 I40E_ERR_PARAM); 6187 return; 6188 } 6189 6190 addr_list = msg; 6191 expected_size = sizeof(*addr_list) + 6192 addr_list->num_elements * sizeof(*addr); 6193 6194 if (addr_list->num_elements == 0 || 6195 addr_list->vsi_id != vf->vsi.vsi_num || 6196 msg_size != expected_size) { 6197 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS, 6198 I40E_ERR_PARAM); 6199 return; 6200 } 6201 6202 for (i = 0; i < addr_list->num_elements; i++) { 6203 addr = &addr_list->list[i]; 6204 if (ixl_zero_mac(addr->addr) || ixl_bcast_mac(addr->addr)) { 6205 i40e_send_vf_nack(pf, vf, 6206 I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS, I40E_ERR_PARAM); 6207 return; 6208 } 6209 } 6210 6211 for (i = 0; i < addr_list->num_elements; i++) { 6212 addr = &addr_list->list[i]; 6213 ixl_del_filter(&vf->vsi, addr->addr, IXL_VLAN_ANY); 6214 } 6215 6216 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS); 6217} 6218 6219static enum i40e_status_code 6220ixl_vf_enable_vlan_strip(struct ixl_pf *pf, struct ixl_vf *vf) 6221{ 6222 struct i40e_vsi_context vsi_ctx; 6223 6224 vsi_ctx.seid = vf->vsi.seid; 6225 6226 bzero(&vsi_ctx.info, sizeof(vsi_ctx.info)); 6227 vsi_ctx.info.valid_sections = htole16(I40E_AQ_VSI_PROP_VLAN_VALID); 6228 vsi_ctx.info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL | 6229 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH; 6230 return (i40e_aq_update_vsi_params(&pf->hw, &vsi_ctx, NULL)); 6231} 6232 6233static void 6234ixl_vf_add_vlan_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 6235 uint16_t msg_size) 6236{ 6237 struct i40e_virtchnl_vlan_filter_list *filter_list; 6238 enum i40e_status_code code; 6239 size_t expected_size; 6240 int i; 6241 6242 if (msg_size < sizeof(*filter_list)) { 6243 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_VLAN, 6244 I40E_ERR_PARAM); 6245 return; 6246 } 6247 6248 filter_list = msg; 6249 expected_size = sizeof(*filter_list) + 6250 filter_list->num_elements * sizeof(uint16_t); 6251 if (filter_list->num_elements == 0 || 6252 filter_list->vsi_id != vf->vsi.vsi_num || 6253 msg_size != expected_size) { 6254 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_VLAN, 6255 I40E_ERR_PARAM); 6256 return; 6257 } 6258 6259 if (!(vf->vf_flags & VF_FLAG_VLAN_CAP)) { 6260 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_VLAN, 6261 I40E_ERR_PARAM); 6262 return; 6263 } 6264 6265 for (i = 0; i < filter_list->num_elements; i++) { 6266 if (filter_list->vlan_id[i] > EVL_VLID_MASK) { 6267 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_VLAN, 6268 I40E_ERR_PARAM); 6269 return; 6270 } 6271 } 6272 6273 code = ixl_vf_enable_vlan_strip(pf, vf); 6274 if (code != I40E_SUCCESS) { 6275 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_VLAN, 6276 I40E_ERR_PARAM); 6277 } 6278 6279 for (i = 0; i < filter_list->num_elements; i++) 6280 ixl_add_filter(&vf->vsi, vf->mac, filter_list->vlan_id[i]); 6281 6282 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_ADD_VLAN); 6283} 6284 6285static void 6286ixl_vf_del_vlan_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 6287 uint16_t msg_size) 6288{ 6289 struct i40e_virtchnl_vlan_filter_list *filter_list; 6290 int i; 6291 size_t expected_size; 6292 6293 if (msg_size < sizeof(*filter_list)) { 6294 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_DEL_VLAN, 6295 I40E_ERR_PARAM); 6296 return; 6297 } 6298 6299 filter_list = msg; 6300 expected_size = sizeof(*filter_list) + 6301 filter_list->num_elements * sizeof(uint16_t); 6302 if (filter_list->num_elements == 0 || 6303 filter_list->vsi_id != vf->vsi.vsi_num || 6304 msg_size != expected_size) { 6305 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_DEL_VLAN, 6306 I40E_ERR_PARAM); 6307 return; 6308 } 6309 6310 for (i = 0; i < filter_list->num_elements; i++) { 6311 if (filter_list->vlan_id[i] > EVL_VLID_MASK) { 6312 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_VLAN, 6313 I40E_ERR_PARAM); 6314 return; 6315 } 6316 } 6317 6318 if (!(vf->vf_flags & VF_FLAG_VLAN_CAP)) { 6319 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_ADD_VLAN, 6320 I40E_ERR_PARAM); 6321 return; 6322 } 6323 6324 for (i = 0; i < filter_list->num_elements; i++) 6325 ixl_del_filter(&vf->vsi, vf->mac, filter_list->vlan_id[i]); 6326 6327 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_DEL_VLAN); 6328} 6329 6330static void 6331ixl_vf_config_promisc_msg(struct ixl_pf *pf, struct ixl_vf *vf, 6332 void *msg, uint16_t msg_size) 6333{ 6334 struct i40e_virtchnl_promisc_info *info; 6335 enum i40e_status_code code; 6336 6337 if (msg_size != sizeof(*info)) { 6338 i40e_send_vf_nack(pf, vf, 6339 I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE, I40E_ERR_PARAM); 6340 return; 6341 } 6342 6343 if (!(vf->vf_flags & VF_FLAG_PROMISC_CAP)) { 6344 i40e_send_vf_nack(pf, vf, 6345 I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE, I40E_ERR_PARAM); 6346 return; 6347 } 6348 6349 info = msg; 6350 if (info->vsi_id != vf->vsi.vsi_num) { 6351 i40e_send_vf_nack(pf, vf, 6352 I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE, I40E_ERR_PARAM); 6353 return; 6354 } 6355 6356 code = i40e_aq_set_vsi_unicast_promiscuous(&pf->hw, info->vsi_id, 6357 info->flags & I40E_FLAG_VF_UNICAST_PROMISC, NULL); 6358 if (code != I40E_SUCCESS) { 6359 i40e_send_vf_nack(pf, vf, 6360 I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE, code); 6361 return; 6362 } 6363 6364 code = i40e_aq_set_vsi_multicast_promiscuous(&pf->hw, info->vsi_id, 6365 info->flags & I40E_FLAG_VF_MULTICAST_PROMISC, NULL); 6366 if (code != I40E_SUCCESS) { 6367 i40e_send_vf_nack(pf, vf, 6368 I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE, code); 6369 return; 6370 } 6371 6372 ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE); 6373} 6374 6375static void 6376ixl_vf_get_stats_msg(struct ixl_pf *pf, struct ixl_vf *vf, void *msg, 6377 uint16_t msg_size) 6378{ 6379 struct i40e_virtchnl_queue_select *queue; 6380 6381 if (msg_size != sizeof(*queue)) { 6382 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_GET_STATS, 6383 I40E_ERR_PARAM); 6384 return; 6385 } 6386 6387 queue = msg; 6388 if (queue->vsi_id != vf->vsi.vsi_num) { 6389 i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_GET_STATS, 6390 I40E_ERR_PARAM); 6391 return; 6392 } 6393 6394 ixl_update_eth_stats(&vf->vsi); 6395 6396 ixl_send_vf_msg(pf, vf, I40E_VIRTCHNL_OP_GET_STATS, 6397 I40E_SUCCESS, &vf->vsi.eth_stats, sizeof(vf->vsi.eth_stats)); 6398} 6399 6400static void 6401ixl_handle_vf_msg(struct ixl_pf *pf, struct i40e_arq_event_info *event) 6402{ 6403 struct ixl_vf *vf; 6404 void *msg; 6405 uint16_t vf_num, msg_size; 6406 uint32_t opcode; 6407 6408 vf_num = le16toh(event->desc.retval) - pf->hw.func_caps.vf_base_id; 6409 opcode = le32toh(event->desc.cookie_high); 6410 6411 if (vf_num >= pf->num_vfs) { 6412 device_printf(pf->dev, "Got msg from illegal VF: %d\n", vf_num); 6413 return; 6414 } 6415 6416 vf = &pf->vfs[vf_num]; 6417 msg = event->msg_buf; 6418 msg_size = event->msg_len; 6419 6420 I40E_VC_DEBUG(pf, ixl_vc_opcode_level(opcode), 6421 "Got msg %s(%d) from VF-%d of size %d\n", 6422 ixl_vc_opcode_str(opcode), opcode, vf_num, msg_size); 6423 6424 switch (opcode) { 6425 case I40E_VIRTCHNL_OP_VERSION: 6426 ixl_vf_version_msg(pf, vf, msg, msg_size); 6427 break; 6428 case I40E_VIRTCHNL_OP_RESET_VF: 6429 ixl_vf_reset_msg(pf, vf, msg, msg_size); 6430 break; 6431 case I40E_VIRTCHNL_OP_GET_VF_RESOURCES: 6432 ixl_vf_get_resources_msg(pf, vf, msg, msg_size); 6433 break; 6434 case I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES: 6435 ixl_vf_config_vsi_msg(pf, vf, msg, msg_size); 6436 break; 6437 case I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP: 6438 ixl_vf_config_irq_msg(pf, vf, msg, msg_size); 6439 break; 6440 case I40E_VIRTCHNL_OP_ENABLE_QUEUES: 6441 ixl_vf_enable_queues_msg(pf, vf, msg, msg_size); 6442 break; 6443 case I40E_VIRTCHNL_OP_DISABLE_QUEUES: 6444 ixl_vf_disable_queues_msg(pf, vf, msg, msg_size); 6445 break; 6446 case I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS: 6447 ixl_vf_add_mac_msg(pf, vf, msg, msg_size); 6448 break; 6449 case I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS: 6450 ixl_vf_del_mac_msg(pf, vf, msg, msg_size); 6451 break; 6452 case I40E_VIRTCHNL_OP_ADD_VLAN: 6453 ixl_vf_add_vlan_msg(pf, vf, msg, msg_size); 6454 break; 6455 case I40E_VIRTCHNL_OP_DEL_VLAN: 6456 ixl_vf_del_vlan_msg(pf, vf, msg, msg_size); 6457 break; 6458 case I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE: 6459 ixl_vf_config_promisc_msg(pf, vf, msg, msg_size); 6460 break; 6461 case I40E_VIRTCHNL_OP_GET_STATS: 6462 ixl_vf_get_stats_msg(pf, vf, msg, msg_size); 6463 break; 6464 6465 /* These two opcodes have been superseded by CONFIG_VSI_QUEUES. */ 6466 case I40E_VIRTCHNL_OP_CONFIG_TX_QUEUE: 6467 case I40E_VIRTCHNL_OP_CONFIG_RX_QUEUE: 6468 default: 6469 i40e_send_vf_nack(pf, vf, opcode, I40E_ERR_NOT_IMPLEMENTED); 6470 break; 6471 } 6472} 6473 6474/* Handle any VFs that have reset themselves via a Function Level Reset(FLR). */ 6475static void 6476ixl_handle_vflr(void *arg, int pending) 6477{ 6478 struct ixl_pf *pf; 6479 struct i40e_hw *hw; 6480 uint16_t global_vf_num; 6481 uint32_t vflrstat_index, vflrstat_mask, vflrstat, icr0; 6482 int i; 6483 6484 pf = arg; 6485 hw = &pf->hw; 6486 6487 IXL_PF_LOCK(pf); 6488 for (i = 0; i < pf->num_vfs; i++) { 6489 global_vf_num = hw->func_caps.vf_base_id + i; 6490 6491 vflrstat_index = IXL_GLGEN_VFLRSTAT_INDEX(global_vf_num); 6492 vflrstat_mask = IXL_GLGEN_VFLRSTAT_MASK(global_vf_num); 6493 vflrstat = rd32(hw, I40E_GLGEN_VFLRSTAT(vflrstat_index)); 6494 if (vflrstat & vflrstat_mask) { 6495 wr32(hw, I40E_GLGEN_VFLRSTAT(vflrstat_index), 6496 vflrstat_mask); 6497 6498 ixl_reinit_vf(pf, &pf->vfs[i]); 6499 } 6500 } 6501 6502 icr0 = rd32(hw, I40E_PFINT_ICR0_ENA); 6503 icr0 |= I40E_PFINT_ICR0_ENA_VFLR_MASK; 6504 wr32(hw, I40E_PFINT_ICR0_ENA, icr0); 6505 ixl_flush(hw); 6506 6507 IXL_PF_UNLOCK(pf); 6508} 6509 6510static int 6511ixl_adminq_err_to_errno(enum i40e_admin_queue_err err) 6512{ 6513 6514 switch (err) { 6515 case I40E_AQ_RC_EPERM: 6516 return (EPERM); 6517 case I40E_AQ_RC_ENOENT: 6518 return (ENOENT); 6519 case I40E_AQ_RC_ESRCH: 6520 return (ESRCH); 6521 case I40E_AQ_RC_EINTR: 6522 return (EINTR); 6523 case I40E_AQ_RC_EIO: 6524 return (EIO); 6525 case I40E_AQ_RC_ENXIO: 6526 return (ENXIO); 6527 case I40E_AQ_RC_E2BIG: 6528 return (E2BIG); 6529 case I40E_AQ_RC_EAGAIN: 6530 return (EAGAIN); 6531 case I40E_AQ_RC_ENOMEM: 6532 return (ENOMEM); 6533 case I40E_AQ_RC_EACCES: 6534 return (EACCES); 6535 case I40E_AQ_RC_EFAULT: 6536 return (EFAULT); 6537 case I40E_AQ_RC_EBUSY: 6538 return (EBUSY); 6539 case I40E_AQ_RC_EEXIST: 6540 return (EEXIST); 6541 case I40E_AQ_RC_EINVAL: 6542 return (EINVAL); 6543 case I40E_AQ_RC_ENOTTY: 6544 return (ENOTTY); 6545 case I40E_AQ_RC_ENOSPC: 6546 return (ENOSPC); 6547 case I40E_AQ_RC_ENOSYS: 6548 return (ENOSYS); 6549 case I40E_AQ_RC_ERANGE: 6550 return (ERANGE); 6551 case I40E_AQ_RC_EFLUSHED: 6552 return (EINVAL); /* No exact equivalent in errno.h */ 6553 case I40E_AQ_RC_BAD_ADDR: 6554 return (EFAULT); 6555 case I40E_AQ_RC_EMODE: 6556 return (EPERM); 6557 case I40E_AQ_RC_EFBIG: 6558 return (EFBIG); 6559 default: 6560 return (EINVAL); 6561 } 6562} 6563 6564static int 6565ixl_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 6566{ 6567 struct ixl_pf *pf; 6568 struct i40e_hw *hw; 6569 struct ixl_vsi *pf_vsi; 6570 enum i40e_status_code ret; 6571 int i, error; 6572 6573 pf = device_get_softc(dev); 6574 hw = &pf->hw; 6575 pf_vsi = &pf->vsi; 6576 6577 IXL_PF_LOCK(pf); 6578 pf->vfs = malloc(sizeof(struct ixl_vf) * num_vfs, M_IXL, M_NOWAIT | 6579 M_ZERO); 6580 6581 if (pf->vfs == NULL) { 6582 error = ENOMEM; 6583 goto fail; 6584 } 6585 6586 for (i = 0; i < num_vfs; i++) 6587 sysctl_ctx_init(&pf->vfs[i].ctx); 6588 6589 ret = i40e_aq_add_veb(hw, pf_vsi->uplink_seid, pf_vsi->seid, 6590 1, FALSE, FALSE, &pf->veb_seid, NULL); 6591 if (ret != I40E_SUCCESS) { 6592 error = ixl_adminq_err_to_errno(hw->aq.asq_last_status); 6593 device_printf(dev, "add_veb failed; code=%d error=%d", ret, 6594 error); 6595 goto fail; 6596 } 6597 6598 ixl_configure_msix(pf); 6599 ixl_enable_adminq(hw); 6600 6601 pf->num_vfs = num_vfs; 6602 IXL_PF_UNLOCK(pf); 6603 return (0); 6604 6605fail: 6606 free(pf->vfs, M_IXL); 6607 pf->vfs = NULL; 6608 IXL_PF_UNLOCK(pf); 6609 return (error); 6610} 6611 6612static void 6613ixl_iov_uninit(device_t dev) 6614{ 6615 struct ixl_pf *pf; 6616 struct i40e_hw *hw; 6617 struct ixl_vsi *vsi; 6618 struct ifnet *ifp; 6619 struct ixl_vf *vfs; 6620 int i, num_vfs; 6621 6622 pf = device_get_softc(dev); 6623 hw = &pf->hw; 6624 vsi = &pf->vsi; 6625 ifp = vsi->ifp; 6626 6627 IXL_PF_LOCK(pf); 6628 for (i = 0; i < pf->num_vfs; i++) { 6629 if (pf->vfs[i].vsi.seid != 0) 6630 i40e_aq_delete_element(hw, pf->vfs[i].vsi.seid, NULL); 6631 } 6632 6633 if (pf->veb_seid != 0) { 6634 i40e_aq_delete_element(hw, pf->veb_seid, NULL); 6635 pf->veb_seid = 0; 6636 } 6637 6638 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 6639 ixl_disable_intr(vsi); 6640 6641 vfs = pf->vfs; 6642 num_vfs = pf->num_vfs; 6643 6644 pf->vfs = NULL; 6645 pf->num_vfs = 0; 6646 IXL_PF_UNLOCK(pf); 6647 6648 /* Do this after the unlock as sysctl_ctx_free might sleep. */ 6649 for (i = 0; i < num_vfs; i++) 6650 sysctl_ctx_free(&vfs[i].ctx); 6651 free(vfs, M_IXL); 6652} 6653 6654static int 6655ixl_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 6656{ 6657 char sysctl_name[QUEUE_NAME_LEN]; 6658 struct ixl_pf *pf; 6659 struct ixl_vf *vf; 6660 const void *mac; 6661 size_t size; 6662 int error; 6663 6664 pf = device_get_softc(dev); 6665 vf = &pf->vfs[vfnum]; 6666 6667 IXL_PF_LOCK(pf); 6668 vf->vf_num = vfnum; 6669 6670 vf->vsi.back = pf; 6671 vf->vf_flags = VF_FLAG_ENABLED; 6672 SLIST_INIT(&vf->vsi.ftl); 6673 6674 error = ixl_vf_setup_vsi(pf, vf); 6675 if (error != 0) 6676 goto out; 6677 6678 if (nvlist_exists_binary(params, "mac-addr")) { 6679 mac = nvlist_get_binary(params, "mac-addr", &size); 6680 bcopy(mac, vf->mac, ETHER_ADDR_LEN); 6681 6682 if (nvlist_get_bool(params, "allow-set-mac")) 6683 vf->vf_flags |= VF_FLAG_SET_MAC_CAP; 6684 } else 6685 /* 6686 * If the administrator has not specified a MAC address then 6687 * we must allow the VF to choose one. 6688 */ 6689 vf->vf_flags |= VF_FLAG_SET_MAC_CAP; 6690 6691 if (nvlist_get_bool(params, "mac-anti-spoof")) 6692 vf->vf_flags |= VF_FLAG_MAC_ANTI_SPOOF; 6693 6694 if (nvlist_get_bool(params, "allow-promisc")) 6695 vf->vf_flags |= VF_FLAG_PROMISC_CAP; 6696 6697 vf->vf_flags |= VF_FLAG_VLAN_CAP; 6698 6699 ixl_reset_vf(pf, vf); 6700out: 6701 IXL_PF_UNLOCK(pf); 6702 if (error == 0) { 6703 snprintf(sysctl_name, sizeof(sysctl_name), "vf%d", vfnum); 6704 ixl_add_vsi_sysctls(pf, &vf->vsi, &vf->ctx, sysctl_name); 6705 } 6706 6707 return (error); 6708} 6709#endif /* PCI_IOV */ 6710