i40e_type.h revision 299546
1/****************************************************************************** 2 3 Copyright (c) 2013-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/ixl/i40e_type.h 299546 2016-05-12 18:19:31Z erj $*/ 34 35#ifndef _I40E_TYPE_H_ 36#define _I40E_TYPE_H_ 37 38#include "i40e_status.h" 39#include "i40e_osdep.h" 40#include "i40e_register.h" 41#include "i40e_adminq.h" 42#include "i40e_hmc.h" 43#include "i40e_lan_hmc.h" 44#include "i40e_devids.h" 45 46#define UNREFERENCED_XPARAMETER 47 48#define BIT(a) (1UL << (a)) 49#define BIT_ULL(a) (1ULL << (a)) 50 51#ifndef I40E_MASK 52/* I40E_MASK is a macro used on 32 bit registers */ 53#define I40E_MASK(mask, shift) (mask << shift) 54#endif 55 56#define I40E_MAX_PF 16 57#define I40E_MAX_PF_VSI 64 58#define I40E_MAX_PF_QP 128 59#define I40E_MAX_VSI_QP 16 60#define I40E_MAX_VF_VSI 3 61#define I40E_MAX_CHAINED_RX_BUFFERS 5 62#define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16 63 64/* something less than 1 minute */ 65#define I40E_HEARTBEAT_TIMEOUT (HZ * 50) 66 67/* Max default timeout in ms, */ 68#define I40E_MAX_NVM_TIMEOUT 18000 69 70/* Check whether address is multicast. */ 71#define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01)) 72 73/* Check whether an address is broadcast. */ 74#define I40E_IS_BROADCAST(address) \ 75 ((((u8 *)(address))[0] == ((u8)0xff)) && \ 76 (((u8 *)(address))[1] == ((u8)0xff))) 77 78/* Switch from ms to the 1usec global time (this is the GTIME resolution) */ 79#define I40E_MS_TO_GTIME(time) ((time) * 1000) 80 81/* forward declaration */ 82struct i40e_hw; 83typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *); 84 85#define I40E_ETH_LENGTH_OF_ADDRESS 6 86/* Data type manipulation macros. */ 87#define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF)) 88#define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF)) 89 90#define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF)) 91#define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF)) 92 93#define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF)) 94#define I40E_LO_BYTE(x) ((u8)((x) & 0xFF)) 95 96/* Number of Transmit Descriptors must be a multiple of 8. */ 97#define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8 98/* Number of Receive Descriptors must be a multiple of 32 if 99 * the number of descriptors is greater than 32. 100 */ 101#define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32 102 103#define I40E_DESC_UNUSED(R) \ 104 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 105 (R)->next_to_clean - (R)->next_to_use - 1) 106 107/* bitfields for Tx queue mapping in QTX_CTL */ 108#define I40E_QTX_CTL_VF_QUEUE 0x0 109#define I40E_QTX_CTL_VM_QUEUE 0x1 110#define I40E_QTX_CTL_PF_QUEUE 0x2 111 112/* debug masks - set these bits in hw->debug_mask to control output */ 113enum i40e_debug_mask { 114 I40E_DEBUG_INIT = 0x00000001, 115 I40E_DEBUG_RELEASE = 0x00000002, 116 117 I40E_DEBUG_LINK = 0x00000010, 118 I40E_DEBUG_PHY = 0x00000020, 119 I40E_DEBUG_HMC = 0x00000040, 120 I40E_DEBUG_NVM = 0x00000080, 121 I40E_DEBUG_LAN = 0x00000100, 122 I40E_DEBUG_FLOW = 0x00000200, 123 I40E_DEBUG_DCB = 0x00000400, 124 I40E_DEBUG_DIAG = 0x00000800, 125 I40E_DEBUG_FD = 0x00001000, 126 127 I40E_DEBUG_AQ_MESSAGE = 0x01000000, 128 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000, 129 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000, 130 I40E_DEBUG_AQ_COMMAND = 0x06000000, 131 I40E_DEBUG_AQ = 0x0F000000, 132 133 I40E_DEBUG_USER = 0xF0000000, 134 135 I40E_DEBUG_ALL = 0xFFFFFFFF 136}; 137 138/* PCI Bus Info */ 139#define I40E_PCI_LINK_STATUS 0xB2 140#define I40E_PCI_LINK_WIDTH 0x3F0 141#define I40E_PCI_LINK_WIDTH_1 0x10 142#define I40E_PCI_LINK_WIDTH_2 0x20 143#define I40E_PCI_LINK_WIDTH_4 0x40 144#define I40E_PCI_LINK_WIDTH_8 0x80 145#define I40E_PCI_LINK_SPEED 0xF 146#define I40E_PCI_LINK_SPEED_2500 0x1 147#define I40E_PCI_LINK_SPEED_5000 0x2 148#define I40E_PCI_LINK_SPEED_8000 0x3 149 150/* Memory types */ 151enum i40e_memset_type { 152 I40E_NONDMA_MEM = 0, 153 I40E_DMA_MEM 154}; 155 156/* Memcpy types */ 157enum i40e_memcpy_type { 158 I40E_NONDMA_TO_NONDMA = 0, 159 I40E_NONDMA_TO_DMA, 160 I40E_DMA_TO_DMA, 161 I40E_DMA_TO_NONDMA 162}; 163 164 165#define I40E_FW_API_VERSION_MINOR_X710 0x0004 166 167 168/* These are structs for managing the hardware information and the operations. 169 * The structures of function pointers are filled out at init time when we 170 * know for sure exactly which hardware we're working with. This gives us the 171 * flexibility of using the same main driver code but adapting to slightly 172 * different hardware needs as new parts are developed. For this architecture, 173 * the Firmware and AdminQ are intended to insulate the driver from most of the 174 * future changes, but these structures will also do part of the job. 175 */ 176enum i40e_mac_type { 177 I40E_MAC_UNKNOWN = 0, 178 I40E_MAC_X710, 179 I40E_MAC_XL710, 180 I40E_MAC_VF, 181 I40E_MAC_GENERIC, 182}; 183 184enum i40e_media_type { 185 I40E_MEDIA_TYPE_UNKNOWN = 0, 186 I40E_MEDIA_TYPE_FIBER, 187 I40E_MEDIA_TYPE_BASET, 188 I40E_MEDIA_TYPE_BACKPLANE, 189 I40E_MEDIA_TYPE_CX4, 190 I40E_MEDIA_TYPE_DA, 191 I40E_MEDIA_TYPE_VIRTUAL 192}; 193 194enum i40e_fc_mode { 195 I40E_FC_NONE = 0, 196 I40E_FC_RX_PAUSE, 197 I40E_FC_TX_PAUSE, 198 I40E_FC_FULL, 199 I40E_FC_PFC, 200 I40E_FC_DEFAULT 201}; 202 203enum i40e_set_fc_aq_failures { 204 I40E_SET_FC_AQ_FAIL_NONE = 0, 205 I40E_SET_FC_AQ_FAIL_GET = 1, 206 I40E_SET_FC_AQ_FAIL_SET = 2, 207 I40E_SET_FC_AQ_FAIL_UPDATE = 4, 208 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6 209}; 210 211enum i40e_vsi_type { 212 I40E_VSI_MAIN = 0, 213 I40E_VSI_VMDQ1 = 1, 214 I40E_VSI_VMDQ2 = 2, 215 I40E_VSI_CTRL = 3, 216 I40E_VSI_FCOE = 4, 217 I40E_VSI_MIRROR = 5, 218 I40E_VSI_SRIOV = 6, 219 I40E_VSI_FDIR = 7, 220 I40E_VSI_TYPE_UNKNOWN 221}; 222 223enum i40e_queue_type { 224 I40E_QUEUE_TYPE_RX = 0, 225 I40E_QUEUE_TYPE_TX, 226 I40E_QUEUE_TYPE_PE_CEQ, 227 I40E_QUEUE_TYPE_UNKNOWN 228}; 229 230struct i40e_link_status { 231 enum i40e_aq_phy_type phy_type; 232 enum i40e_aq_link_speed link_speed; 233 u8 link_info; 234 u8 an_info; 235 u8 ext_info; 236 u8 loopback; 237 /* is Link Status Event notification to SW enabled */ 238 bool lse_enable; 239 u16 max_frame_size; 240 bool crc_enable; 241 u8 pacing; 242 u8 requested_speeds; 243 u8 module_type[3]; 244 /* 1st byte: module identifier */ 245#define I40E_MODULE_TYPE_SFP 0x03 246#define I40E_MODULE_TYPE_QSFP 0x0D 247 /* 2nd byte: ethernet compliance codes for 10/40G */ 248#define I40E_MODULE_TYPE_40G_ACTIVE 0x01 249#define I40E_MODULE_TYPE_40G_LR4 0x02 250#define I40E_MODULE_TYPE_40G_SR4 0x04 251#define I40E_MODULE_TYPE_40G_CR4 0x08 252#define I40E_MODULE_TYPE_10G_BASE_SR 0x10 253#define I40E_MODULE_TYPE_10G_BASE_LR 0x20 254#define I40E_MODULE_TYPE_10G_BASE_LRM 0x40 255#define I40E_MODULE_TYPE_10G_BASE_ER 0x80 256 /* 3rd byte: ethernet compliance codes for 1G */ 257#define I40E_MODULE_TYPE_1000BASE_SX 0x01 258#define I40E_MODULE_TYPE_1000BASE_LX 0x02 259#define I40E_MODULE_TYPE_1000BASE_CX 0x04 260#define I40E_MODULE_TYPE_1000BASE_T 0x08 261}; 262 263enum i40e_aq_capabilities_phy_type { 264 I40E_CAP_PHY_TYPE_SGMII = BIT(I40E_PHY_TYPE_SGMII), 265 I40E_CAP_PHY_TYPE_1000BASE_KX = BIT(I40E_PHY_TYPE_1000BASE_KX), 266 I40E_CAP_PHY_TYPE_10GBASE_KX4 = BIT(I40E_PHY_TYPE_10GBASE_KX4), 267 I40E_CAP_PHY_TYPE_10GBASE_KR = BIT(I40E_PHY_TYPE_10GBASE_KR), 268 I40E_CAP_PHY_TYPE_40GBASE_KR4 = BIT(I40E_PHY_TYPE_40GBASE_KR4), 269 I40E_CAP_PHY_TYPE_XAUI = BIT(I40E_PHY_TYPE_XAUI), 270 I40E_CAP_PHY_TYPE_XFI = BIT(I40E_PHY_TYPE_XFI), 271 I40E_CAP_PHY_TYPE_SFI = BIT(I40E_PHY_TYPE_SFI), 272 I40E_CAP_PHY_TYPE_XLAUI = BIT(I40E_PHY_TYPE_XLAUI), 273 I40E_CAP_PHY_TYPE_XLPPI = BIT(I40E_PHY_TYPE_XLPPI), 274 I40E_CAP_PHY_TYPE_40GBASE_CR4_CU = BIT(I40E_PHY_TYPE_40GBASE_CR4_CU), 275 I40E_CAP_PHY_TYPE_10GBASE_CR1_CU = BIT(I40E_PHY_TYPE_10GBASE_CR1_CU), 276 I40E_CAP_PHY_TYPE_10GBASE_AOC = BIT(I40E_PHY_TYPE_10GBASE_AOC), 277 I40E_CAP_PHY_TYPE_40GBASE_AOC = BIT(I40E_PHY_TYPE_40GBASE_AOC), 278 I40E_CAP_PHY_TYPE_100BASE_TX = BIT(I40E_PHY_TYPE_100BASE_TX), 279 I40E_CAP_PHY_TYPE_1000BASE_T = BIT(I40E_PHY_TYPE_1000BASE_T), 280 I40E_CAP_PHY_TYPE_10GBASE_T = BIT(I40E_PHY_TYPE_10GBASE_T), 281 I40E_CAP_PHY_TYPE_10GBASE_SR = BIT(I40E_PHY_TYPE_10GBASE_SR), 282 I40E_CAP_PHY_TYPE_10GBASE_LR = BIT(I40E_PHY_TYPE_10GBASE_LR), 283 I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU = BIT(I40E_PHY_TYPE_10GBASE_SFPP_CU), 284 I40E_CAP_PHY_TYPE_10GBASE_CR1 = BIT(I40E_PHY_TYPE_10GBASE_CR1), 285 I40E_CAP_PHY_TYPE_40GBASE_CR4 = BIT(I40E_PHY_TYPE_40GBASE_CR4), 286 I40E_CAP_PHY_TYPE_40GBASE_SR4 = BIT(I40E_PHY_TYPE_40GBASE_SR4), 287 I40E_CAP_PHY_TYPE_40GBASE_LR4 = BIT(I40E_PHY_TYPE_40GBASE_LR4), 288 I40E_CAP_PHY_TYPE_1000BASE_SX = BIT(I40E_PHY_TYPE_1000BASE_SX), 289 I40E_CAP_PHY_TYPE_1000BASE_LX = BIT(I40E_PHY_TYPE_1000BASE_LX), 290 I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL = BIT(I40E_PHY_TYPE_1000BASE_T_OPTICAL), 291 I40E_CAP_PHY_TYPE_20GBASE_KR2 = BIT(I40E_PHY_TYPE_20GBASE_KR2) 292}; 293 294struct i40e_phy_info { 295 struct i40e_link_status link_info; 296 struct i40e_link_status link_info_old; 297 bool get_link_info; 298 enum i40e_media_type media_type; 299 /* all the phy types the NVM is capable of */ 300 u32 phy_types; 301}; 302 303#define I40E_HW_CAP_MAX_GPIO 30 304#define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0 305#define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1 306 307/* Capabilities of a PF or a VF or the whole device */ 308struct i40e_hw_capabilities { 309 u32 switch_mode; 310#define I40E_NVM_IMAGE_TYPE_EVB 0x0 311#define I40E_NVM_IMAGE_TYPE_CLOUD 0x2 312#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3 313 314 u32 management_mode; 315 u32 npar_enable; 316 u32 os2bmc; 317 u32 valid_functions; 318 bool sr_iov_1_1; 319 bool vmdq; 320 bool evb_802_1_qbg; /* Edge Virtual Bridging */ 321 bool evb_802_1_qbh; /* Bridge Port Extension */ 322 bool dcb; 323 bool fcoe; 324 bool iscsi; /* Indicates iSCSI enabled */ 325 bool flex10_enable; 326 bool flex10_capable; 327 u32 flex10_mode; 328#define I40E_FLEX10_MODE_UNKNOWN 0x0 329#define I40E_FLEX10_MODE_DCC 0x1 330#define I40E_FLEX10_MODE_DCI 0x2 331 332 u32 flex10_status; 333#define I40E_FLEX10_STATUS_DCC_ERROR 0x1 334#define I40E_FLEX10_STATUS_VC_MODE 0x2 335 336 bool mgmt_cem; 337 bool ieee_1588; 338 bool iwarp; 339 bool fd; 340 u32 fd_filters_guaranteed; 341 u32 fd_filters_best_effort; 342 bool rss; 343 u32 rss_table_size; 344 u32 rss_table_entry_width; 345 bool led[I40E_HW_CAP_MAX_GPIO]; 346 bool sdp[I40E_HW_CAP_MAX_GPIO]; 347 u32 nvm_image_type; 348 u32 num_flow_director_filters; 349 u32 num_vfs; 350 u32 vf_base_id; 351 u32 num_vsis; 352 u32 num_rx_qp; 353 u32 num_tx_qp; 354 u32 base_queue; 355 u32 num_msix_vectors; 356 u32 num_msix_vectors_vf; 357 u32 led_pin_num; 358 u32 sdp_pin_num; 359 u32 mdio_port_num; 360 u32 mdio_port_mode; 361 u8 rx_buf_chain_len; 362 u32 enabled_tcmap; 363 u32 maxtc; 364 u64 wr_csr_prot; 365}; 366 367struct i40e_mac_info { 368 enum i40e_mac_type type; 369 u8 addr[I40E_ETH_LENGTH_OF_ADDRESS]; 370 u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS]; 371 u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS]; 372 u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS]; 373 u16 max_fcoeq; 374}; 375 376enum i40e_aq_resources_ids { 377 I40E_NVM_RESOURCE_ID = 1 378}; 379 380enum i40e_aq_resource_access_type { 381 I40E_RESOURCE_READ = 1, 382 I40E_RESOURCE_WRITE 383}; 384 385struct i40e_nvm_info { 386 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */ 387 u32 timeout; /* [ms] */ 388 u16 sr_size; /* Shadow RAM size in words */ 389 bool blank_nvm_mode; /* is NVM empty (no FW present)*/ 390 u16 version; /* NVM package version */ 391 u32 eetrack; /* NVM data version */ 392 u32 oem_ver; /* OEM version info */ 393}; 394 395/* definitions used in NVM update support */ 396 397enum i40e_nvmupd_cmd { 398 I40E_NVMUPD_INVALID, 399 I40E_NVMUPD_READ_CON, 400 I40E_NVMUPD_READ_SNT, 401 I40E_NVMUPD_READ_LCB, 402 I40E_NVMUPD_READ_SA, 403 I40E_NVMUPD_WRITE_ERA, 404 I40E_NVMUPD_WRITE_CON, 405 I40E_NVMUPD_WRITE_SNT, 406 I40E_NVMUPD_WRITE_LCB, 407 I40E_NVMUPD_WRITE_SA, 408 I40E_NVMUPD_CSUM_CON, 409 I40E_NVMUPD_CSUM_SA, 410 I40E_NVMUPD_CSUM_LCB, 411 I40E_NVMUPD_STATUS, 412 I40E_NVMUPD_EXEC_AQ, 413 I40E_NVMUPD_GET_AQ_RESULT, 414}; 415 416enum i40e_nvmupd_state { 417 I40E_NVMUPD_STATE_INIT, 418 I40E_NVMUPD_STATE_READING, 419 I40E_NVMUPD_STATE_WRITING, 420 I40E_NVMUPD_STATE_INIT_WAIT, 421 I40E_NVMUPD_STATE_WRITE_WAIT, 422}; 423 424/* nvm_access definition and its masks/shifts need to be accessible to 425 * application, core driver, and shared code. Where is the right file? 426 */ 427#define I40E_NVM_READ 0xB 428#define I40E_NVM_WRITE 0xC 429 430#define I40E_NVM_MOD_PNT_MASK 0xFF 431 432#define I40E_NVM_TRANS_SHIFT 8 433#define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT) 434#define I40E_NVM_CON 0x0 435#define I40E_NVM_SNT 0x1 436#define I40E_NVM_LCB 0x2 437#define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB) 438#define I40E_NVM_ERA 0x4 439#define I40E_NVM_CSUM 0x8 440#define I40E_NVM_EXEC 0xf 441 442#define I40E_NVM_ADAPT_SHIFT 16 443#define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT) 444 445#define I40E_NVMUPD_MAX_DATA 4096 446#define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */ 447 448struct i40e_nvm_access { 449 u32 command; 450 u32 config; 451 u32 offset; /* in bytes */ 452 u32 data_size; /* in bytes */ 453 u8 data[1]; 454}; 455 456/* PCI bus types */ 457enum i40e_bus_type { 458 i40e_bus_type_unknown = 0, 459 i40e_bus_type_pci, 460 i40e_bus_type_pcix, 461 i40e_bus_type_pci_express, 462 i40e_bus_type_reserved 463}; 464 465/* PCI bus speeds */ 466enum i40e_bus_speed { 467 i40e_bus_speed_unknown = 0, 468 i40e_bus_speed_33 = 33, 469 i40e_bus_speed_66 = 66, 470 i40e_bus_speed_100 = 100, 471 i40e_bus_speed_120 = 120, 472 i40e_bus_speed_133 = 133, 473 i40e_bus_speed_2500 = 2500, 474 i40e_bus_speed_5000 = 5000, 475 i40e_bus_speed_8000 = 8000, 476 i40e_bus_speed_reserved 477}; 478 479/* PCI bus widths */ 480enum i40e_bus_width { 481 i40e_bus_width_unknown = 0, 482 i40e_bus_width_pcie_x1 = 1, 483 i40e_bus_width_pcie_x2 = 2, 484 i40e_bus_width_pcie_x4 = 4, 485 i40e_bus_width_pcie_x8 = 8, 486 i40e_bus_width_32 = 32, 487 i40e_bus_width_64 = 64, 488 i40e_bus_width_reserved 489}; 490 491/* Bus parameters */ 492struct i40e_bus_info { 493 enum i40e_bus_speed speed; 494 enum i40e_bus_width width; 495 enum i40e_bus_type type; 496 497 u16 func; 498 u16 device; 499 u16 lan_id; 500}; 501 502/* Flow control (FC) parameters */ 503struct i40e_fc_info { 504 enum i40e_fc_mode current_mode; /* FC mode in effect */ 505 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */ 506}; 507 508#define I40E_MAX_TRAFFIC_CLASS 8 509#define I40E_MAX_USER_PRIORITY 8 510#define I40E_DCBX_MAX_APPS 32 511#define I40E_LLDPDU_SIZE 1500 512#define I40E_TLV_STATUS_OPER 0x1 513#define I40E_TLV_STATUS_SYNC 0x2 514#define I40E_TLV_STATUS_ERR 0x4 515#define I40E_CEE_OPER_MAX_APPS 3 516#define I40E_APP_PROTOID_FCOE 0x8906 517#define I40E_APP_PROTOID_ISCSI 0x0cbc 518#define I40E_APP_PROTOID_FIP 0x8914 519#define I40E_APP_SEL_ETHTYPE 0x1 520#define I40E_APP_SEL_TCPIP 0x2 521#define I40E_CEE_APP_SEL_ETHTYPE 0x0 522#define I40E_CEE_APP_SEL_TCPIP 0x1 523 524/* CEE or IEEE 802.1Qaz ETS Configuration data */ 525struct i40e_dcb_ets_config { 526 u8 willing; 527 u8 cbs; 528 u8 maxtcs; 529 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS]; 530 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS]; 531 u8 tsatable[I40E_MAX_TRAFFIC_CLASS]; 532}; 533 534/* CEE or IEEE 802.1Qaz PFC Configuration data */ 535struct i40e_dcb_pfc_config { 536 u8 willing; 537 u8 mbc; 538 u8 pfccap; 539 u8 pfcenable; 540}; 541 542/* CEE or IEEE 802.1Qaz Application Priority data */ 543struct i40e_dcb_app_priority_table { 544 u8 priority; 545 u8 selector; 546 u16 protocolid; 547}; 548 549struct i40e_dcbx_config { 550 u8 dcbx_mode; 551#define I40E_DCBX_MODE_CEE 0x1 552#define I40E_DCBX_MODE_IEEE 0x2 553 u8 app_mode; 554#define I40E_DCBX_APPS_NON_WILLING 0x1 555 u32 numapps; 556 u32 tlv_status; /* CEE mode TLV status */ 557 struct i40e_dcb_ets_config etscfg; 558 struct i40e_dcb_ets_config etsrec; 559 struct i40e_dcb_pfc_config pfc; 560 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS]; 561}; 562 563/* Port hardware description */ 564struct i40e_hw { 565 u8 *hw_addr; 566 void *back; 567 568 /* subsystem structs */ 569 struct i40e_phy_info phy; 570 struct i40e_mac_info mac; 571 struct i40e_bus_info bus; 572 struct i40e_nvm_info nvm; 573 struct i40e_fc_info fc; 574 575 /* pci info */ 576 u16 device_id; 577 u16 vendor_id; 578 u16 subsystem_device_id; 579 u16 subsystem_vendor_id; 580 u8 revision_id; 581 u8 port; 582 bool adapter_stopped; 583 584 /* capabilities for entire device and PCI func */ 585 struct i40e_hw_capabilities dev_caps; 586 struct i40e_hw_capabilities func_caps; 587 588 /* Flow Director shared filter space */ 589 u16 fdir_shared_filter_count; 590 591 /* device profile info */ 592 u8 pf_id; 593 u16 main_vsi_seid; 594 595 /* for multi-function MACs */ 596 u16 partition_id; 597 u16 num_partitions; 598 u16 num_ports; 599 600 /* Closest numa node to the device */ 601 u16 numa_node; 602 603 /* Admin Queue info */ 604 struct i40e_adminq_info aq; 605 606 /* state of nvm update process */ 607 enum i40e_nvmupd_state nvmupd_state; 608 struct i40e_aq_desc nvm_wb_desc; 609 struct i40e_virt_mem nvm_buff; 610 611 /* HMC info */ 612 struct i40e_hmc_info hmc; /* HMC info struct */ 613 614 /* LLDP/DCBX Status */ 615 u16 dcbx_status; 616 617 /* DCBX info */ 618 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */ 619 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */ 620 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */ 621 622 /* debug mask */ 623 u32 debug_mask; 624 char err_str[16]; 625}; 626 627static INLINE bool i40e_is_vf(struct i40e_hw *hw) 628{ 629 return hw->mac.type == I40E_MAC_VF; 630} 631 632struct i40e_driver_version { 633 u8 major_version; 634 u8 minor_version; 635 u8 build_version; 636 u8 subbuild_version; 637 u8 driver_string[32]; 638}; 639 640/* RX Descriptors */ 641union i40e_16byte_rx_desc { 642 struct { 643 __le64 pkt_addr; /* Packet buffer address */ 644 __le64 hdr_addr; /* Header buffer address */ 645 } read; 646 struct { 647 struct { 648 struct { 649 union { 650 __le16 mirroring_status; 651 __le16 fcoe_ctx_id; 652 } mirr_fcoe; 653 __le16 l2tag1; 654 } lo_dword; 655 union { 656 __le32 rss; /* RSS Hash */ 657 __le32 fd_id; /* Flow director filter id */ 658 __le32 fcoe_param; /* FCoE DDP Context id */ 659 } hi_dword; 660 } qword0; 661 struct { 662 /* ext status/error/pktype/length */ 663 __le64 status_error_len; 664 } qword1; 665 } wb; /* writeback */ 666}; 667 668union i40e_32byte_rx_desc { 669 struct { 670 __le64 pkt_addr; /* Packet buffer address */ 671 __le64 hdr_addr; /* Header buffer address */ 672 /* bit 0 of hdr_buffer_addr is DD bit */ 673 __le64 rsvd1; 674 __le64 rsvd2; 675 } read; 676 struct { 677 struct { 678 struct { 679 union { 680 __le16 mirroring_status; 681 __le16 fcoe_ctx_id; 682 } mirr_fcoe; 683 __le16 l2tag1; 684 } lo_dword; 685 union { 686 __le32 rss; /* RSS Hash */ 687 __le32 fcoe_param; /* FCoE DDP Context id */ 688 /* Flow director filter id in case of 689 * Programming status desc WB 690 */ 691 __le32 fd_id; 692 } hi_dword; 693 } qword0; 694 struct { 695 /* status/error/pktype/length */ 696 __le64 status_error_len; 697 } qword1; 698 struct { 699 __le16 ext_status; /* extended status */ 700 __le16 rsvd; 701 __le16 l2tag2_1; 702 __le16 l2tag2_2; 703 } qword2; 704 struct { 705 union { 706 __le32 flex_bytes_lo; 707 __le32 pe_status; 708 } lo_dword; 709 union { 710 __le32 flex_bytes_hi; 711 __le32 fd_id; 712 } hi_dword; 713 } qword3; 714 } wb; /* writeback */ 715}; 716 717#define I40E_RXD_QW0_MIRROR_STATUS_SHIFT 8 718#define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \ 719 I40E_RXD_QW0_MIRROR_STATUS_SHIFT) 720#define I40E_RXD_QW0_FCOEINDX_SHIFT 0 721#define I40E_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \ 722 I40E_RXD_QW0_FCOEINDX_SHIFT) 723 724enum i40e_rx_desc_status_bits { 725 /* Note: These are predefined bit offsets */ 726 I40E_RX_DESC_STATUS_DD_SHIFT = 0, 727 I40E_RX_DESC_STATUS_EOF_SHIFT = 1, 728 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2, 729 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3, 730 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4, 731 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */ 732 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7, 733 I40E_RX_DESC_STATUS_RESERVED1_SHIFT = 8, 734 735 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */ 736 I40E_RX_DESC_STATUS_FLM_SHIFT = 11, 737 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */ 738 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14, 739 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15, 740 I40E_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */ 741 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18, 742 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */ 743}; 744 745#define I40E_RXD_QW1_STATUS_SHIFT 0 746#define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \ 747 I40E_RXD_QW1_STATUS_SHIFT) 748 749#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT 750#define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \ 751 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT) 752 753#define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT 754#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT) 755 756#define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT I40E_RX_DESC_STATUS_UMBCAST 757#define I40E_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \ 758 I40E_RXD_QW1_STATUS_UMBCAST_SHIFT) 759 760enum i40e_rx_desc_fltstat_values { 761 I40E_RX_DESC_FLTSTAT_NO_DATA = 0, 762 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */ 763 I40E_RX_DESC_FLTSTAT_RSV = 2, 764 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3, 765}; 766 767#define I40E_RXD_PACKET_TYPE_UNICAST 0 768#define I40E_RXD_PACKET_TYPE_MULTICAST 1 769#define I40E_RXD_PACKET_TYPE_BROADCAST 2 770#define I40E_RXD_PACKET_TYPE_MIRRORED 3 771 772#define I40E_RXD_QW1_ERROR_SHIFT 19 773#define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT) 774 775enum i40e_rx_desc_error_bits { 776 /* Note: These are predefined bit offsets */ 777 I40E_RX_DESC_ERROR_RXE_SHIFT = 0, 778 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1, 779 I40E_RX_DESC_ERROR_HBO_SHIFT = 2, 780 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */ 781 I40E_RX_DESC_ERROR_IPE_SHIFT = 3, 782 I40E_RX_DESC_ERROR_L4E_SHIFT = 4, 783 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5, 784 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6, 785 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7 786}; 787 788enum i40e_rx_desc_error_l3l4e_fcoe_masks { 789 I40E_RX_DESC_ERROR_L3L4E_NONE = 0, 790 I40E_RX_DESC_ERROR_L3L4E_PROT = 1, 791 I40E_RX_DESC_ERROR_L3L4E_FC = 2, 792 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3, 793 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4 794}; 795 796#define I40E_RXD_QW1_PTYPE_SHIFT 30 797#define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT) 798 799/* Packet type non-ip values */ 800enum i40e_rx_l2_ptype { 801 I40E_RX_PTYPE_L2_RESERVED = 0, 802 I40E_RX_PTYPE_L2_MAC_PAY2 = 1, 803 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2, 804 I40E_RX_PTYPE_L2_FIP_PAY2 = 3, 805 I40E_RX_PTYPE_L2_OUI_PAY2 = 4, 806 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5, 807 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6, 808 I40E_RX_PTYPE_L2_ECP_PAY2 = 7, 809 I40E_RX_PTYPE_L2_EVB_PAY2 = 8, 810 I40E_RX_PTYPE_L2_QCN_PAY2 = 9, 811 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10, 812 I40E_RX_PTYPE_L2_ARP = 11, 813 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12, 814 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13, 815 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14, 816 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15, 817 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16, 818 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17, 819 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18, 820 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19, 821 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20, 822 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21, 823 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58, 824 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87, 825 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124, 826 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153 827}; 828 829struct i40e_rx_ptype_decoded { 830 u32 ptype:8; 831 u32 known:1; 832 u32 outer_ip:1; 833 u32 outer_ip_ver:1; 834 u32 outer_frag:1; 835 u32 tunnel_type:3; 836 u32 tunnel_end_prot:2; 837 u32 tunnel_end_frag:1; 838 u32 inner_prot:4; 839 u32 payload_layer:3; 840}; 841 842enum i40e_rx_ptype_outer_ip { 843 I40E_RX_PTYPE_OUTER_L2 = 0, 844 I40E_RX_PTYPE_OUTER_IP = 1 845}; 846 847enum i40e_rx_ptype_outer_ip_ver { 848 I40E_RX_PTYPE_OUTER_NONE = 0, 849 I40E_RX_PTYPE_OUTER_IPV4 = 0, 850 I40E_RX_PTYPE_OUTER_IPV6 = 1 851}; 852 853enum i40e_rx_ptype_outer_fragmented { 854 I40E_RX_PTYPE_NOT_FRAG = 0, 855 I40E_RX_PTYPE_FRAG = 1 856}; 857 858enum i40e_rx_ptype_tunnel_type { 859 I40E_RX_PTYPE_TUNNEL_NONE = 0, 860 I40E_RX_PTYPE_TUNNEL_IP_IP = 1, 861 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2, 862 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3, 863 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4, 864}; 865 866enum i40e_rx_ptype_tunnel_end_prot { 867 I40E_RX_PTYPE_TUNNEL_END_NONE = 0, 868 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1, 869 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2, 870}; 871 872enum i40e_rx_ptype_inner_prot { 873 I40E_RX_PTYPE_INNER_PROT_NONE = 0, 874 I40E_RX_PTYPE_INNER_PROT_UDP = 1, 875 I40E_RX_PTYPE_INNER_PROT_TCP = 2, 876 I40E_RX_PTYPE_INNER_PROT_SCTP = 3, 877 I40E_RX_PTYPE_INNER_PROT_ICMP = 4, 878 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5 879}; 880 881enum i40e_rx_ptype_payload_layer { 882 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0, 883 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1, 884 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2, 885 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3, 886}; 887 888#define I40E_RX_PTYPE_BIT_MASK 0x0FFFFFFF 889#define I40E_RX_PTYPE_SHIFT 56 890 891#define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38 892#define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \ 893 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) 894 895#define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52 896#define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \ 897 I40E_RXD_QW1_LENGTH_HBUF_SHIFT) 898 899#define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63 900#define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT) 901 902#define I40E_RXD_QW1_NEXTP_SHIFT 38 903#define I40E_RXD_QW1_NEXTP_MASK (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT) 904 905#define I40E_RXD_QW2_EXT_STATUS_SHIFT 0 906#define I40E_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \ 907 I40E_RXD_QW2_EXT_STATUS_SHIFT) 908 909enum i40e_rx_desc_ext_status_bits { 910 /* Note: These are predefined bit offsets */ 911 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0, 912 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1, 913 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */ 914 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */ 915 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9, 916 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10, 917 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11, 918}; 919 920#define I40E_RXD_QW2_L2TAG2_SHIFT 0 921#define I40E_RXD_QW2_L2TAG2_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT) 922 923#define I40E_RXD_QW2_L2TAG3_SHIFT 16 924#define I40E_RXD_QW2_L2TAG3_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT) 925 926enum i40e_rx_desc_pe_status_bits { 927 /* Note: These are predefined bit offsets */ 928 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */ 929 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */ 930 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */ 931 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24, 932 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25, 933 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26, 934 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27, 935 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28, 936 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29 937}; 938 939#define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38 940#define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000 941 942#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2 943#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \ 944 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT) 945 946#define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0 947#define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \ 948 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT) 949 950#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19 951#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \ 952 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT) 953 954enum i40e_rx_prog_status_desc_status_bits { 955 /* Note: These are predefined bit offsets */ 956 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0, 957 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */ 958}; 959 960enum i40e_rx_prog_status_desc_prog_id_masks { 961 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1, 962 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2, 963 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4, 964}; 965 966enum i40e_rx_prog_status_desc_error_bits { 967 /* Note: These are predefined bit offsets */ 968 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0, 969 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1, 970 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2, 971 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3 972}; 973 974#define I40E_TWO_BIT_MASK 0x3 975#define I40E_THREE_BIT_MASK 0x7 976#define I40E_FOUR_BIT_MASK 0xF 977#define I40E_EIGHTEEN_BIT_MASK 0x3FFFF 978 979/* TX Descriptor */ 980struct i40e_tx_desc { 981 __le64 buffer_addr; /* Address of descriptor's data buf */ 982 __le64 cmd_type_offset_bsz; 983}; 984 985#define I40E_TXD_QW1_DTYPE_SHIFT 0 986#define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT) 987 988enum i40e_tx_desc_dtype_value { 989 I40E_TX_DESC_DTYPE_DATA = 0x0, 990 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */ 991 I40E_TX_DESC_DTYPE_CONTEXT = 0x1, 992 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2, 993 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8, 994 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9, 995 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB, 996 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC, 997 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD, 998 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF 999}; 1000 1001#define I40E_TXD_QW1_CMD_SHIFT 4 1002#define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT) 1003 1004enum i40e_tx_desc_cmd_bits { 1005 I40E_TX_DESC_CMD_EOP = 0x0001, 1006 I40E_TX_DESC_CMD_RS = 0x0002, 1007 I40E_TX_DESC_CMD_ICRC = 0x0004, 1008 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008, 1009 I40E_TX_DESC_CMD_DUMMY = 0x0010, 1010 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */ 1011 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */ 1012 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */ 1013 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */ 1014 I40E_TX_DESC_CMD_FCOET = 0x0080, 1015 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */ 1016 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */ 1017 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */ 1018 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */ 1019 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */ 1020 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */ 1021 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */ 1022 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */ 1023}; 1024 1025#define I40E_TXD_QW1_OFFSET_SHIFT 16 1026#define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \ 1027 I40E_TXD_QW1_OFFSET_SHIFT) 1028 1029enum i40e_tx_desc_length_fields { 1030 /* Note: These are predefined bit offsets */ 1031 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */ 1032 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */ 1033 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */ 1034}; 1035 1036#define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT) 1037#define I40E_TXD_QW1_IPLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT) 1038#define I40E_TXD_QW1_L4LEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT) 1039#define I40E_TXD_QW1_FCLEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT) 1040 1041#define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34 1042#define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \ 1043 I40E_TXD_QW1_TX_BUF_SZ_SHIFT) 1044 1045#define I40E_TXD_QW1_L2TAG1_SHIFT 48 1046#define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT) 1047 1048/* Context descriptors */ 1049struct i40e_tx_context_desc { 1050 __le32 tunneling_params; 1051 __le16 l2tag2; 1052 __le16 rsvd; 1053 __le64 type_cmd_tso_mss; 1054}; 1055 1056#define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0 1057#define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT) 1058 1059#define I40E_TXD_CTX_QW1_CMD_SHIFT 4 1060#define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT) 1061 1062enum i40e_tx_ctx_desc_cmd_bits { 1063 I40E_TX_CTX_DESC_TSO = 0x01, 1064 I40E_TX_CTX_DESC_TSYN = 0x02, 1065 I40E_TX_CTX_DESC_IL2TAG2 = 0x04, 1066 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08, 1067 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00, 1068 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10, 1069 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20, 1070 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30, 1071 I40E_TX_CTX_DESC_SWPE = 0x40 1072}; 1073 1074#define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30 1075#define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \ 1076 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) 1077 1078#define I40E_TXD_CTX_QW1_MSS_SHIFT 50 1079#define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \ 1080 I40E_TXD_CTX_QW1_MSS_SHIFT) 1081 1082#define I40E_TXD_CTX_QW1_VSI_SHIFT 50 1083#define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT) 1084 1085#define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0 1086#define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \ 1087 I40E_TXD_CTX_QW0_EXT_IP_SHIFT) 1088 1089enum i40e_tx_ctx_desc_eipt_offload { 1090 I40E_TX_CTX_EXT_IP_NONE = 0x0, 1091 I40E_TX_CTX_EXT_IP_IPV6 = 0x1, 1092 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2, 1093 I40E_TX_CTX_EXT_IP_IPV4 = 0x3 1094}; 1095 1096#define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2 1097#define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \ 1098 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT) 1099 1100#define I40E_TXD_CTX_QW0_NATT_SHIFT 9 1101#define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) 1102 1103#define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT) 1104#define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) 1105 1106#define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11 1107#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT) 1108 1109#define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK 1110 1111#define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12 1112#define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \ 1113 I40E_TXD_CTX_QW0_NATLEN_SHIFT) 1114 1115#define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19 1116#define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \ 1117 I40E_TXD_CTX_QW0_DECTTL_SHIFT) 1118 1119struct i40e_nop_desc { 1120 __le64 rsvd; 1121 __le64 dtype_cmd; 1122}; 1123 1124#define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0 1125#define I40E_TXD_NOP_QW1_DTYPE_MASK (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT) 1126 1127#define I40E_TXD_NOP_QW1_CMD_SHIFT 4 1128#define I40E_TXD_NOP_QW1_CMD_MASK (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT) 1129 1130enum i40e_tx_nop_desc_cmd_bits { 1131 /* Note: These are predefined bit offsets */ 1132 I40E_TX_NOP_DESC_EOP_SHIFT = 0, 1133 I40E_TX_NOP_DESC_RS_SHIFT = 1, 1134 I40E_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */ 1135}; 1136 1137struct i40e_filter_program_desc { 1138 __le32 qindex_flex_ptype_vsi; 1139 __le32 rsvd; 1140 __le32 dtype_cmd_cntindex; 1141 __le32 fd_id; 1142}; 1143#define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0 1144#define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \ 1145 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) 1146#define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11 1147#define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \ 1148 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) 1149#define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17 1150#define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \ 1151 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) 1152 1153/* Packet Classifier Types for filters */ 1154enum i40e_filter_pctype { 1155 /* Note: Values 0-30 are reserved for future use */ 1156 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31, 1157 /* Note: Value 32 is reserved for future use */ 1158 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33, 1159 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34, 1160 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35, 1161 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36, 1162 /* Note: Values 37-40 are reserved for future use */ 1163 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41, 1164 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43, 1165 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44, 1166 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45, 1167 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46, 1168 /* Note: Value 47 is reserved for future use */ 1169 I40E_FILTER_PCTYPE_FCOE_OX = 48, 1170 I40E_FILTER_PCTYPE_FCOE_RX = 49, 1171 I40E_FILTER_PCTYPE_FCOE_OTHER = 50, 1172 /* Note: Values 51-62 are reserved for future use */ 1173 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63, 1174}; 1175 1176enum i40e_filter_program_desc_dest { 1177 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0, 1178 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1, 1179 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2, 1180}; 1181 1182enum i40e_filter_program_desc_fd_status { 1183 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0, 1184 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1, 1185 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2, 1186 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3, 1187}; 1188 1189#define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23 1190#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \ 1191 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) 1192 1193#define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0 1194#define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT) 1195 1196#define I40E_TXD_FLTR_QW1_CMD_SHIFT 4 1197#define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \ 1198 I40E_TXD_FLTR_QW1_CMD_SHIFT) 1199 1200#define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 1201#define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT) 1202 1203enum i40e_filter_program_desc_pcmd { 1204 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1, 1205 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2, 1206}; 1207 1208#define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 1209#define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT) 1210 1211#define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 1212#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT) 1213 1214#define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \ 1215 I40E_TXD_FLTR_QW1_CMD_SHIFT) 1216#define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \ 1217 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) 1218 1219#define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20 1220#define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \ 1221 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) 1222 1223enum i40e_filter_type { 1224 I40E_FLOW_DIRECTOR_FLTR = 0, 1225 I40E_PE_QUAD_HASH_FLTR = 1, 1226 I40E_ETHERTYPE_FLTR, 1227 I40E_FCOE_CTX_FLTR, 1228 I40E_MAC_VLAN_FLTR, 1229 I40E_HASH_FLTR 1230}; 1231 1232struct i40e_vsi_context { 1233 u16 seid; 1234 u16 uplink_seid; 1235 u16 vsi_number; 1236 u16 vsis_allocated; 1237 u16 vsis_unallocated; 1238 u16 flags; 1239 u8 pf_num; 1240 u8 vf_num; 1241 u8 connection_type; 1242 struct i40e_aqc_vsi_properties_data info; 1243}; 1244 1245struct i40e_veb_context { 1246 u16 seid; 1247 u16 uplink_seid; 1248 u16 veb_number; 1249 u16 vebs_allocated; 1250 u16 vebs_unallocated; 1251 u16 flags; 1252 struct i40e_aqc_get_veb_parameters_completion info; 1253}; 1254 1255/* Statistics collected by each port, VSI, VEB, and S-channel */ 1256struct i40e_eth_stats { 1257 u64 rx_bytes; /* gorc */ 1258 u64 rx_unicast; /* uprc */ 1259 u64 rx_multicast; /* mprc */ 1260 u64 rx_broadcast; /* bprc */ 1261 u64 rx_discards; /* rdpc */ 1262 u64 rx_unknown_protocol; /* rupp */ 1263 u64 tx_bytes; /* gotc */ 1264 u64 tx_unicast; /* uptc */ 1265 u64 tx_multicast; /* mptc */ 1266 u64 tx_broadcast; /* bptc */ 1267 u64 tx_discards; /* tdpc */ 1268 u64 tx_errors; /* tepc */ 1269}; 1270 1271/* Statistics collected per VEB per TC */ 1272struct i40e_veb_tc_stats { 1273 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS]; 1274 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS]; 1275 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS]; 1276 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS]; 1277}; 1278 1279/* Statistics collected by the MAC */ 1280struct i40e_hw_port_stats { 1281 /* eth stats collected by the port */ 1282 struct i40e_eth_stats eth; 1283 1284 /* additional port specific stats */ 1285 u64 tx_dropped_link_down; /* tdold */ 1286 u64 crc_errors; /* crcerrs */ 1287 u64 illegal_bytes; /* illerrc */ 1288 u64 error_bytes; /* errbc */ 1289 u64 mac_local_faults; /* mlfc */ 1290 u64 mac_remote_faults; /* mrfc */ 1291 u64 rx_length_errors; /* rlec */ 1292 u64 link_xon_rx; /* lxonrxc */ 1293 u64 link_xoff_rx; /* lxoffrxc */ 1294 u64 priority_xon_rx[8]; /* pxonrxc[8] */ 1295 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 1296 u64 link_xon_tx; /* lxontxc */ 1297 u64 link_xoff_tx; /* lxofftxc */ 1298 u64 priority_xon_tx[8]; /* pxontxc[8] */ 1299 u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 1300 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 1301 u64 rx_size_64; /* prc64 */ 1302 u64 rx_size_127; /* prc127 */ 1303 u64 rx_size_255; /* prc255 */ 1304 u64 rx_size_511; /* prc511 */ 1305 u64 rx_size_1023; /* prc1023 */ 1306 u64 rx_size_1522; /* prc1522 */ 1307 u64 rx_size_big; /* prc9522 */ 1308 u64 rx_undersize; /* ruc */ 1309 u64 rx_fragments; /* rfc */ 1310 u64 rx_oversize; /* roc */ 1311 u64 rx_jabber; /* rjc */ 1312 u64 tx_size_64; /* ptc64 */ 1313 u64 tx_size_127; /* ptc127 */ 1314 u64 tx_size_255; /* ptc255 */ 1315 u64 tx_size_511; /* ptc511 */ 1316 u64 tx_size_1023; /* ptc1023 */ 1317 u64 tx_size_1522; /* ptc1522 */ 1318 u64 tx_size_big; /* ptc9522 */ 1319 u64 mac_short_packet_dropped; /* mspdc */ 1320 u64 checksum_error; /* xec */ 1321 /* flow director stats */ 1322 u64 fd_atr_match; 1323 u64 fd_sb_match; 1324 u64 fd_atr_tunnel_match; 1325 u32 fd_atr_status; 1326 u32 fd_sb_status; 1327 /* EEE LPI */ 1328 u32 tx_lpi_status; 1329 u32 rx_lpi_status; 1330 u64 tx_lpi_count; /* etlpic */ 1331 u64 rx_lpi_count; /* erlpic */ 1332}; 1333 1334/* Checksum and Shadow RAM pointers */ 1335#define I40E_SR_NVM_CONTROL_WORD 0x00 1336#define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03 1337#define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04 1338#define I40E_SR_OPTION_ROM_PTR 0x05 1339#define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06 1340#define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07 1341#define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08 1342#define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09 1343#define I40E_SR_RO_PCIE_LCB_PTR 0x0A 1344#define I40E_SR_EMP_IMAGE_PTR 0x0B 1345#define I40E_SR_PE_IMAGE_PTR 0x0C 1346#define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D 1347#define I40E_SR_MNG_CONFIG_PTR 0x0E 1348#define I40E_SR_EMP_MODULE_PTR 0x0F 1349#define I40E_SR_PBA_FLAGS 0x15 1350#define I40E_SR_PBA_BLOCK_PTR 0x16 1351#define I40E_SR_BOOT_CONFIG_PTR 0x17 1352#define I40E_NVM_OEM_VER_OFF 0x83 1353#define I40E_SR_NVM_DEV_STARTER_VERSION 0x18 1354#define I40E_SR_NVM_WAKE_ON_LAN 0x19 1355#define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27 1356#define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28 1357#define I40E_SR_NVM_MAP_VERSION 0x29 1358#define I40E_SR_NVM_IMAGE_VERSION 0x2A 1359#define I40E_SR_NVM_STRUCTURE_VERSION 0x2B 1360#define I40E_SR_NVM_EETRACK_LO 0x2D 1361#define I40E_SR_NVM_EETRACK_HI 0x2E 1362#define I40E_SR_VPD_PTR 0x2F 1363#define I40E_SR_PXE_SETUP_PTR 0x30 1364#define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31 1365#define I40E_SR_NVM_ORIGINAL_EETRACK_LO 0x34 1366#define I40E_SR_NVM_ORIGINAL_EETRACK_HI 0x35 1367#define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37 1368#define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38 1369#define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A 1370#define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B 1371#define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C 1372#define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E 1373#define I40E_SR_SW_CHECKSUM_WORD 0x3F 1374#define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40 1375#define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42 1376#define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44 1377#define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46 1378#define I40E_SR_EMP_SR_SETTINGS_PTR 0x48 1379#define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49 1380#define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D 1381#define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E 1382 1383/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ 1384#define I40E_SR_VPD_MODULE_MAX_SIZE 1024 1385#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024 1386#define I40E_SR_CONTROL_WORD_1_SHIFT 0x06 1387#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT) 1388 1389/* Shadow RAM related */ 1390#define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800 1391#define I40E_SR_BUF_ALIGNMENT 4096 1392#define I40E_SR_WORDS_IN_1KB 512 1393/* Checksum should be calculated such that after adding all the words, 1394 * including the checksum word itself, the sum should be 0xBABA. 1395 */ 1396#define I40E_SR_SW_CHECKSUM_BASE 0xBABA 1397 1398#define I40E_SRRD_SRCTL_ATTEMPTS 100000 1399 1400enum i40e_switch_element_types { 1401 I40E_SWITCH_ELEMENT_TYPE_MAC = 1, 1402 I40E_SWITCH_ELEMENT_TYPE_PF = 2, 1403 I40E_SWITCH_ELEMENT_TYPE_VF = 3, 1404 I40E_SWITCH_ELEMENT_TYPE_EMP = 4, 1405 I40E_SWITCH_ELEMENT_TYPE_BMC = 6, 1406 I40E_SWITCH_ELEMENT_TYPE_PE = 16, 1407 I40E_SWITCH_ELEMENT_TYPE_VEB = 17, 1408 I40E_SWITCH_ELEMENT_TYPE_PA = 18, 1409 I40E_SWITCH_ELEMENT_TYPE_VSI = 19, 1410}; 1411 1412/* Supported EtherType filters */ 1413enum i40e_ether_type_index { 1414 I40E_ETHER_TYPE_1588 = 0, 1415 I40E_ETHER_TYPE_FIP = 1, 1416 I40E_ETHER_TYPE_OUI_EXTENDED = 2, 1417 I40E_ETHER_TYPE_MAC_CONTROL = 3, 1418 I40E_ETHER_TYPE_LLDP = 4, 1419 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5, 1420 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6, 1421 I40E_ETHER_TYPE_QCN_CNM = 7, 1422 I40E_ETHER_TYPE_8021X = 8, 1423 I40E_ETHER_TYPE_ARP = 9, 1424 I40E_ETHER_TYPE_RSV1 = 10, 1425 I40E_ETHER_TYPE_RSV2 = 11, 1426}; 1427 1428/* Filter context base size is 1K */ 1429#define I40E_HASH_FILTER_BASE_SIZE 1024 1430/* Supported Hash filter values */ 1431enum i40e_hash_filter_size { 1432 I40E_HASH_FILTER_SIZE_1K = 0, 1433 I40E_HASH_FILTER_SIZE_2K = 1, 1434 I40E_HASH_FILTER_SIZE_4K = 2, 1435 I40E_HASH_FILTER_SIZE_8K = 3, 1436 I40E_HASH_FILTER_SIZE_16K = 4, 1437 I40E_HASH_FILTER_SIZE_32K = 5, 1438 I40E_HASH_FILTER_SIZE_64K = 6, 1439 I40E_HASH_FILTER_SIZE_128K = 7, 1440 I40E_HASH_FILTER_SIZE_256K = 8, 1441 I40E_HASH_FILTER_SIZE_512K = 9, 1442 I40E_HASH_FILTER_SIZE_1M = 10, 1443}; 1444 1445/* DMA context base size is 0.5K */ 1446#define I40E_DMA_CNTX_BASE_SIZE 512 1447/* Supported DMA context values */ 1448enum i40e_dma_cntx_size { 1449 I40E_DMA_CNTX_SIZE_512 = 0, 1450 I40E_DMA_CNTX_SIZE_1K = 1, 1451 I40E_DMA_CNTX_SIZE_2K = 2, 1452 I40E_DMA_CNTX_SIZE_4K = 3, 1453 I40E_DMA_CNTX_SIZE_8K = 4, 1454 I40E_DMA_CNTX_SIZE_16K = 5, 1455 I40E_DMA_CNTX_SIZE_32K = 6, 1456 I40E_DMA_CNTX_SIZE_64K = 7, 1457 I40E_DMA_CNTX_SIZE_128K = 8, 1458 I40E_DMA_CNTX_SIZE_256K = 9, 1459}; 1460 1461/* Supported Hash look up table (LUT) sizes */ 1462enum i40e_hash_lut_size { 1463 I40E_HASH_LUT_SIZE_128 = 0, 1464 I40E_HASH_LUT_SIZE_512 = 1, 1465}; 1466 1467/* Structure to hold a per PF filter control settings */ 1468struct i40e_filter_control_settings { 1469 /* number of PE Quad Hash filter buckets */ 1470 enum i40e_hash_filter_size pe_filt_num; 1471 /* number of PE Quad Hash contexts */ 1472 enum i40e_dma_cntx_size pe_cntx_num; 1473 /* number of FCoE filter buckets */ 1474 enum i40e_hash_filter_size fcoe_filt_num; 1475 /* number of FCoE DDP contexts */ 1476 enum i40e_dma_cntx_size fcoe_cntx_num; 1477 /* size of the Hash LUT */ 1478 enum i40e_hash_lut_size hash_lut_size; 1479 /* enable FDIR filters for PF and its VFs */ 1480 bool enable_fdir; 1481 /* enable Ethertype filters for PF and its VFs */ 1482 bool enable_ethtype; 1483 /* enable MAC/VLAN filters for PF and its VFs */ 1484 bool enable_macvlan; 1485}; 1486 1487/* Structure to hold device level control filter counts */ 1488struct i40e_control_filter_stats { 1489 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */ 1490 u16 etype_used; /* Used perfect EtherType filters */ 1491 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */ 1492 u16 etype_free; /* Un-used perfect EtherType filters */ 1493}; 1494 1495enum i40e_reset_type { 1496 I40E_RESET_POR = 0, 1497 I40E_RESET_CORER = 1, 1498 I40E_RESET_GLOBR = 2, 1499 I40E_RESET_EMPR = 3, 1500}; 1501 1502/* IEEE 802.1AB LLDP Agent Variables from NVM */ 1503#define I40E_NVM_LLDP_CFG_PTR 0xD 1504struct i40e_lldp_variables { 1505 u16 length; 1506 u16 adminstatus; 1507 u16 msgfasttx; 1508 u16 msgtxinterval; 1509 u16 txparams; 1510 u16 timers; 1511 u16 crc8; 1512}; 1513 1514/* Offsets into Alternate Ram */ 1515#define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */ 1516#define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */ 1517#define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */ 1518#define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */ 1519#define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */ 1520#define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */ 1521 1522/* Alternate Ram Bandwidth Masks */ 1523#define I40E_ALT_BW_VALUE_MASK 0xFF 1524#define I40E_ALT_BW_RELATIVE_MASK 0x40000000 1525#define I40E_ALT_BW_VALID_MASK 0x80000000 1526 1527/* RSS Hash Table Size */ 1528#define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000 1529#endif /* _I40E_TYPE_H_ */ 1530