i40e_type.h revision 277082
1/****************************************************************************** 2 3 Copyright (c) 2013-2014, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/ixl/i40e_type.h 277082 2015-01-12 18:32:45Z jfv $*/ 34 35#ifndef _I40E_TYPE_H_ 36#define _I40E_TYPE_H_ 37 38#include "i40e_status.h" 39#include "i40e_osdep.h" 40#include "i40e_register.h" 41#include "i40e_adminq.h" 42#include "i40e_hmc.h" 43#include "i40e_lan_hmc.h" 44 45#define UNREFERENCED_XPARAMETER 46 47/* Vendor ID */ 48#define I40E_INTEL_VENDOR_ID 0x8086 49 50/* Device IDs */ 51#define I40E_DEV_ID_SFP_XL710 0x1572 52#define I40E_DEV_ID_QEMU 0x1574 53#define I40E_DEV_ID_KX_A 0x157F 54#define I40E_DEV_ID_KX_B 0x1580 55#define I40E_DEV_ID_KX_C 0x1581 56#define I40E_DEV_ID_QSFP_A 0x1583 57#define I40E_DEV_ID_QSFP_B 0x1584 58#define I40E_DEV_ID_QSFP_C 0x1585 59#define I40E_DEV_ID_10G_BASE_T 0x1586 60#define I40E_DEV_ID_VF 0x154C 61#define I40E_DEV_ID_VF_HV 0x1571 62 63#define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \ 64 (d) == I40E_DEV_ID_QSFP_B || \ 65 (d) == I40E_DEV_ID_QSFP_C) 66 67#ifndef I40E_MASK 68/* I40E_MASK is a macro used on 32 bit registers */ 69#define I40E_MASK(mask, shift) (mask << shift) 70#endif 71 72#define I40E_MAX_PF 16 73#define I40E_MAX_PF_VSI 64 74#define I40E_MAX_PF_QP 128 75#define I40E_MAX_VSI_QP 16 76#define I40E_MAX_VF_VSI 3 77#define I40E_MAX_CHAINED_RX_BUFFERS 5 78#define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16 79 80/* something less than 1 minute */ 81#define I40E_HEARTBEAT_TIMEOUT (HZ * 50) 82 83/* Max default timeout in ms, */ 84#define I40E_MAX_NVM_TIMEOUT 18000 85 86/* Check whether address is multicast. */ 87#define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01)) 88 89/* Check whether an address is broadcast. */ 90#define I40E_IS_BROADCAST(address) \ 91 ((((u8 *)(address))[0] == ((u8)0xff)) && \ 92 (((u8 *)(address))[1] == ((u8)0xff))) 93 94/* Switch from ms to the 1usec global time (this is the GTIME resolution) */ 95#define I40E_MS_TO_GTIME(time) ((time) * 1000) 96 97/* forward declaration */ 98struct i40e_hw; 99typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *); 100 101#define I40E_ETH_LENGTH_OF_ADDRESS 6 102/* Data type manipulation macros. */ 103#define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF)) 104#define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF)) 105 106#define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF)) 107#define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF)) 108 109#define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF)) 110#define I40E_LO_BYTE(x) ((u8)((x) & 0xFF)) 111 112/* Number of Transmit Descriptors must be a multiple of 8. */ 113#define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8 114/* Number of Receive Descriptors must be a multiple of 32 if 115 * the number of descriptors is greater than 32. 116 */ 117#define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32 118 119#define I40E_DESC_UNUSED(R) \ 120 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 121 (R)->next_to_clean - (R)->next_to_use - 1) 122 123/* bitfields for Tx queue mapping in QTX_CTL */ 124#define I40E_QTX_CTL_VF_QUEUE 0x0 125#define I40E_QTX_CTL_VM_QUEUE 0x1 126#define I40E_QTX_CTL_PF_QUEUE 0x2 127 128/* debug masks - set these bits in hw->debug_mask to control output */ 129enum i40e_debug_mask { 130 I40E_DEBUG_INIT = 0x00000001, 131 I40E_DEBUG_RELEASE = 0x00000002, 132 133 I40E_DEBUG_LINK = 0x00000010, 134 I40E_DEBUG_PHY = 0x00000020, 135 I40E_DEBUG_HMC = 0x00000040, 136 I40E_DEBUG_NVM = 0x00000080, 137 I40E_DEBUG_LAN = 0x00000100, 138 I40E_DEBUG_FLOW = 0x00000200, 139 I40E_DEBUG_DCB = 0x00000400, 140 I40E_DEBUG_DIAG = 0x00000800, 141 I40E_DEBUG_FD = 0x00001000, 142 143 I40E_DEBUG_AQ_MESSAGE = 0x01000000, 144 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000, 145 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000, 146 I40E_DEBUG_AQ_COMMAND = 0x06000000, 147 I40E_DEBUG_AQ = 0x0F000000, 148 149 I40E_DEBUG_USER = 0xF0000000, 150 151 I40E_DEBUG_ALL = 0xFFFFFFFF 152}; 153 154/* PCI Bus Info */ 155#define I40E_PCI_LINK_STATUS 0xB2 156#define I40E_PCI_LINK_WIDTH 0x3F0 157#define I40E_PCI_LINK_WIDTH_1 0x10 158#define I40E_PCI_LINK_WIDTH_2 0x20 159#define I40E_PCI_LINK_WIDTH_4 0x40 160#define I40E_PCI_LINK_WIDTH_8 0x80 161#define I40E_PCI_LINK_SPEED 0xF 162#define I40E_PCI_LINK_SPEED_2500 0x1 163#define I40E_PCI_LINK_SPEED_5000 0x2 164#define I40E_PCI_LINK_SPEED_8000 0x3 165 166/* Memory types */ 167enum i40e_memset_type { 168 I40E_NONDMA_MEM = 0, 169 I40E_DMA_MEM 170}; 171 172/* Memcpy types */ 173enum i40e_memcpy_type { 174 I40E_NONDMA_TO_NONDMA = 0, 175 I40E_NONDMA_TO_DMA, 176 I40E_DMA_TO_DMA, 177 I40E_DMA_TO_NONDMA 178}; 179 180/* These are structs for managing the hardware information and the operations. 181 * The structures of function pointers are filled out at init time when we 182 * know for sure exactly which hardware we're working with. This gives us the 183 * flexibility of using the same main driver code but adapting to slightly 184 * different hardware needs as new parts are developed. For this architecture, 185 * the Firmware and AdminQ are intended to insulate the driver from most of the 186 * future changes, but these structures will also do part of the job. 187 */ 188enum i40e_mac_type { 189 I40E_MAC_UNKNOWN = 0, 190 I40E_MAC_X710, 191 I40E_MAC_XL710, 192 I40E_MAC_VF, 193 I40E_MAC_GENERIC, 194}; 195 196enum i40e_media_type { 197 I40E_MEDIA_TYPE_UNKNOWN = 0, 198 I40E_MEDIA_TYPE_FIBER, 199 I40E_MEDIA_TYPE_BASET, 200 I40E_MEDIA_TYPE_BACKPLANE, 201 I40E_MEDIA_TYPE_CX4, 202 I40E_MEDIA_TYPE_DA, 203 I40E_MEDIA_TYPE_VIRTUAL 204}; 205 206enum i40e_fc_mode { 207 I40E_FC_NONE = 0, 208 I40E_FC_RX_PAUSE, 209 I40E_FC_TX_PAUSE, 210 I40E_FC_FULL, 211 I40E_FC_PFC, 212 I40E_FC_DEFAULT 213}; 214 215enum i40e_set_fc_aq_failures { 216 I40E_SET_FC_AQ_FAIL_NONE = 0, 217 I40E_SET_FC_AQ_FAIL_GET = 1, 218 I40E_SET_FC_AQ_FAIL_SET = 2, 219 I40E_SET_FC_AQ_FAIL_UPDATE = 4, 220 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6 221}; 222 223enum i40e_vsi_type { 224 I40E_VSI_MAIN = 0, 225 I40E_VSI_VMDQ1, 226 I40E_VSI_VMDQ2, 227 I40E_VSI_CTRL, 228 I40E_VSI_FCOE, 229 I40E_VSI_MIRROR, 230 I40E_VSI_SRIOV, 231 I40E_VSI_FDIR, 232 I40E_VSI_TYPE_UNKNOWN 233}; 234 235enum i40e_queue_type { 236 I40E_QUEUE_TYPE_RX = 0, 237 I40E_QUEUE_TYPE_TX, 238 I40E_QUEUE_TYPE_PE_CEQ, 239 I40E_QUEUE_TYPE_UNKNOWN 240}; 241 242struct i40e_link_status { 243 enum i40e_aq_phy_type phy_type; 244 enum i40e_aq_link_speed link_speed; 245 u8 link_info; 246 u8 an_info; 247 u8 ext_info; 248 u8 loopback; 249 /* is Link Status Event notification to SW enabled */ 250 bool lse_enable; 251 u16 max_frame_size; 252 bool crc_enable; 253 u8 pacing; 254 u8 requested_speeds; 255}; 256 257struct i40e_phy_info { 258 struct i40e_link_status link_info; 259 struct i40e_link_status link_info_old; 260 u32 autoneg_advertised; 261 u32 phy_id; 262 u32 module_type; 263 bool get_link_info; 264 enum i40e_media_type media_type; 265}; 266 267#define I40E_HW_CAP_MAX_GPIO 30 268#define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0 269#define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1 270 271/* Capabilities of a PF or a VF or the whole device */ 272struct i40e_hw_capabilities { 273 u32 switch_mode; 274#define I40E_NVM_IMAGE_TYPE_EVB 0x0 275#define I40E_NVM_IMAGE_TYPE_CLOUD 0x2 276#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3 277 278 u32 management_mode; 279 u32 npar_enable; 280 u32 os2bmc; 281 u32 valid_functions; 282 bool sr_iov_1_1; 283 bool vmdq; 284 bool evb_802_1_qbg; /* Edge Virtual Bridging */ 285 bool evb_802_1_qbh; /* Bridge Port Extension */ 286 bool dcb; 287 bool fcoe; 288 bool iscsi; /* Indicates iSCSI enabled */ 289 bool mfp_mode_1; 290 bool mgmt_cem; 291 bool ieee_1588; 292 bool iwarp; 293 bool fd; 294 u32 fd_filters_guaranteed; 295 u32 fd_filters_best_effort; 296 bool rss; 297 u32 rss_table_size; 298 u32 rss_table_entry_width; 299 bool led[I40E_HW_CAP_MAX_GPIO]; 300 bool sdp[I40E_HW_CAP_MAX_GPIO]; 301 u32 nvm_image_type; 302 u32 num_flow_director_filters; 303 u32 num_vfs; 304 u32 vf_base_id; 305 u32 num_vsis; 306 u32 num_rx_qp; 307 u32 num_tx_qp; 308 u32 base_queue; 309 u32 num_msix_vectors; 310 u32 num_msix_vectors_vf; 311 u32 led_pin_num; 312 u32 sdp_pin_num; 313 u32 mdio_port_num; 314 u32 mdio_port_mode; 315 u8 rx_buf_chain_len; 316 u32 enabled_tcmap; 317 u32 maxtc; 318}; 319 320struct i40e_mac_info { 321 enum i40e_mac_type type; 322 u8 addr[I40E_ETH_LENGTH_OF_ADDRESS]; 323 u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS]; 324 u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS]; 325 u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS]; 326 u16 max_fcoeq; 327}; 328 329enum i40e_aq_resources_ids { 330 I40E_NVM_RESOURCE_ID = 1 331}; 332 333enum i40e_aq_resource_access_type { 334 I40E_RESOURCE_READ = 1, 335 I40E_RESOURCE_WRITE 336}; 337 338struct i40e_nvm_info { 339 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */ 340 u32 timeout; /* [ms] */ 341 u16 sr_size; /* Shadow RAM size in words */ 342 bool blank_nvm_mode; /* is NVM empty (no FW present)*/ 343 u16 version; /* NVM package version */ 344 u32 eetrack; /* NVM data version */ 345}; 346 347/* definitions used in NVM update support */ 348 349enum i40e_nvmupd_cmd { 350 I40E_NVMUPD_INVALID, 351 I40E_NVMUPD_READ_CON, 352 I40E_NVMUPD_READ_SNT, 353 I40E_NVMUPD_READ_LCB, 354 I40E_NVMUPD_READ_SA, 355 I40E_NVMUPD_WRITE_ERA, 356 I40E_NVMUPD_WRITE_CON, 357 I40E_NVMUPD_WRITE_SNT, 358 I40E_NVMUPD_WRITE_LCB, 359 I40E_NVMUPD_WRITE_SA, 360 I40E_NVMUPD_CSUM_CON, 361 I40E_NVMUPD_CSUM_SA, 362 I40E_NVMUPD_CSUM_LCB, 363}; 364 365enum i40e_nvmupd_state { 366 I40E_NVMUPD_STATE_INIT, 367 I40E_NVMUPD_STATE_READING, 368 I40E_NVMUPD_STATE_WRITING 369}; 370 371/* nvm_access definition and its masks/shifts need to be accessible to 372 * application, core driver, and shared code. Where is the right file? 373 */ 374#define I40E_NVM_READ 0xB 375#define I40E_NVM_WRITE 0xC 376 377#define I40E_NVM_MOD_PNT_MASK 0xFF 378 379#define I40E_NVM_TRANS_SHIFT 8 380#define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT) 381#define I40E_NVM_CON 0x0 382#define I40E_NVM_SNT 0x1 383#define I40E_NVM_LCB 0x2 384#define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB) 385#define I40E_NVM_ERA 0x4 386#define I40E_NVM_CSUM 0x8 387 388#define I40E_NVM_ADAPT_SHIFT 16 389#define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT) 390 391#define I40E_NVMUPD_MAX_DATA 4096 392#define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */ 393 394struct i40e_nvm_access { 395 u32 command; 396 u32 config; 397 u32 offset; /* in bytes */ 398 u32 data_size; /* in bytes */ 399 u8 data[1]; 400}; 401 402/* PCI bus types */ 403enum i40e_bus_type { 404 i40e_bus_type_unknown = 0, 405 i40e_bus_type_pci, 406 i40e_bus_type_pcix, 407 i40e_bus_type_pci_express, 408 i40e_bus_type_reserved 409}; 410 411/* PCI bus speeds */ 412enum i40e_bus_speed { 413 i40e_bus_speed_unknown = 0, 414 i40e_bus_speed_33 = 33, 415 i40e_bus_speed_66 = 66, 416 i40e_bus_speed_100 = 100, 417 i40e_bus_speed_120 = 120, 418 i40e_bus_speed_133 = 133, 419 i40e_bus_speed_2500 = 2500, 420 i40e_bus_speed_5000 = 5000, 421 i40e_bus_speed_8000 = 8000, 422 i40e_bus_speed_reserved 423}; 424 425/* PCI bus widths */ 426enum i40e_bus_width { 427 i40e_bus_width_unknown = 0, 428 i40e_bus_width_pcie_x1 = 1, 429 i40e_bus_width_pcie_x2 = 2, 430 i40e_bus_width_pcie_x4 = 4, 431 i40e_bus_width_pcie_x8 = 8, 432 i40e_bus_width_32 = 32, 433 i40e_bus_width_64 = 64, 434 i40e_bus_width_reserved 435}; 436 437/* Bus parameters */ 438struct i40e_bus_info { 439 enum i40e_bus_speed speed; 440 enum i40e_bus_width width; 441 enum i40e_bus_type type; 442 443 u16 func; 444 u16 device; 445 u16 lan_id; 446}; 447 448/* Flow control (FC) parameters */ 449struct i40e_fc_info { 450 enum i40e_fc_mode current_mode; /* FC mode in effect */ 451 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */ 452}; 453 454#define I40E_MAX_TRAFFIC_CLASS 8 455#define I40E_MAX_USER_PRIORITY 8 456#define I40E_DCBX_MAX_APPS 32 457#define I40E_LLDPDU_SIZE 1500 458#define I40E_TLV_STATUS_OPER 0x1 459#define I40E_TLV_STATUS_SYNC 0x2 460#define I40E_TLV_STATUS_ERR 0x4 461#define I40E_CEE_OPER_MAX_APPS 3 462#define I40E_APP_PROTOID_FCOE 0x8906 463#define I40E_APP_PROTOID_ISCSI 0x0cbc 464#define I40E_APP_PROTOID_FIP 0x8914 465#define I40E_APP_SEL_ETHTYPE 0x1 466#define I40E_APP_SEL_TCPIP 0x2 467 468/* CEE or IEEE 802.1Qaz ETS Configuration data */ 469struct i40e_dcb_ets_config { 470 u8 willing; 471 u8 cbs; 472 u8 maxtcs; 473 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS]; 474 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS]; 475 u8 tsatable[I40E_MAX_TRAFFIC_CLASS]; 476}; 477 478/* CEE or IEEE 802.1Qaz PFC Configuration data */ 479struct i40e_dcb_pfc_config { 480 u8 willing; 481 u8 mbc; 482 u8 pfccap; 483 u8 pfcenable; 484}; 485 486/* CEE or IEEE 802.1Qaz Application Priority data */ 487struct i40e_dcb_app_priority_table { 488 u8 priority; 489 u8 selector; 490 u16 protocolid; 491}; 492 493struct i40e_dcbx_config { 494 u8 dcbx_mode; 495#define I40E_DCBX_MODE_CEE 0x1 496#define I40E_DCBX_MODE_IEEE 0x2 497 u32 numapps; 498 struct i40e_dcb_ets_config etscfg; 499 struct i40e_dcb_ets_config etsrec; 500 struct i40e_dcb_pfc_config pfc; 501 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS]; 502}; 503 504/* Port hardware description */ 505struct i40e_hw { 506 u8 *hw_addr; 507 void *back; 508 509 /* subsystem structs */ 510 struct i40e_phy_info phy; 511 struct i40e_mac_info mac; 512 struct i40e_bus_info bus; 513 struct i40e_nvm_info nvm; 514 struct i40e_fc_info fc; 515 516 /* pci info */ 517 u16 device_id; 518 u16 vendor_id; 519 u16 subsystem_device_id; 520 u16 subsystem_vendor_id; 521 u8 revision_id; 522 u8 port; 523 bool adapter_stopped; 524 525 /* capabilities for entire device and PCI func */ 526 struct i40e_hw_capabilities dev_caps; 527 struct i40e_hw_capabilities func_caps; 528 529 /* Flow Director shared filter space */ 530 u16 fdir_shared_filter_count; 531 532 /* device profile info */ 533 u8 pf_id; 534 u16 main_vsi_seid; 535 536 /* for multi-function MACs */ 537 u16 partition_id; 538 u16 num_partitions; 539 u16 num_ports; 540 541 /* Closest numa node to the device */ 542 u16 numa_node; 543 544 /* Admin Queue info */ 545 struct i40e_adminq_info aq; 546 547 /* state of nvm update process */ 548 enum i40e_nvmupd_state nvmupd_state; 549 550 /* HMC info */ 551 struct i40e_hmc_info hmc; /* HMC info struct */ 552 553 /* LLDP/DCBX Status */ 554 u16 dcbx_status; 555 556 /* DCBX info */ 557 struct i40e_dcbx_config local_dcbx_config; 558 struct i40e_dcbx_config remote_dcbx_config; 559 560 /* debug mask */ 561 u32 debug_mask; 562}; 563#define i40e_is_vf(_hw) ((_hw)->mac.type == I40E_MAC_VF) 564 565struct i40e_driver_version { 566 u8 major_version; 567 u8 minor_version; 568 u8 build_version; 569 u8 subbuild_version; 570 u8 driver_string[32]; 571}; 572 573/* RX Descriptors */ 574union i40e_16byte_rx_desc { 575 struct { 576 __le64 pkt_addr; /* Packet buffer address */ 577 __le64 hdr_addr; /* Header buffer address */ 578 } read; 579 struct { 580 struct { 581 struct { 582 union { 583 __le16 mirroring_status; 584 __le16 fcoe_ctx_id; 585 } mirr_fcoe; 586 __le16 l2tag1; 587 } lo_dword; 588 union { 589 __le32 rss; /* RSS Hash */ 590 __le32 fd_id; /* Flow director filter id */ 591 __le32 fcoe_param; /* FCoE DDP Context id */ 592 } hi_dword; 593 } qword0; 594 struct { 595 /* ext status/error/pktype/length */ 596 __le64 status_error_len; 597 } qword1; 598 } wb; /* writeback */ 599}; 600 601union i40e_32byte_rx_desc { 602 struct { 603 __le64 pkt_addr; /* Packet buffer address */ 604 __le64 hdr_addr; /* Header buffer address */ 605 /* bit 0 of hdr_buffer_addr is DD bit */ 606 __le64 rsvd1; 607 __le64 rsvd2; 608 } read; 609 struct { 610 struct { 611 struct { 612 union { 613 __le16 mirroring_status; 614 __le16 fcoe_ctx_id; 615 } mirr_fcoe; 616 __le16 l2tag1; 617 } lo_dword; 618 union { 619 __le32 rss; /* RSS Hash */ 620 __le32 fcoe_param; /* FCoE DDP Context id */ 621 /* Flow director filter id in case of 622 * Programming status desc WB 623 */ 624 __le32 fd_id; 625 } hi_dword; 626 } qword0; 627 struct { 628 /* status/error/pktype/length */ 629 __le64 status_error_len; 630 } qword1; 631 struct { 632 __le16 ext_status; /* extended status */ 633 __le16 rsvd; 634 __le16 l2tag2_1; 635 __le16 l2tag2_2; 636 } qword2; 637 struct { 638 union { 639 __le32 flex_bytes_lo; 640 __le32 pe_status; 641 } lo_dword; 642 union { 643 __le32 flex_bytes_hi; 644 __le32 fd_id; 645 } hi_dword; 646 } qword3; 647 } wb; /* writeback */ 648}; 649 650#define I40E_RXD_QW0_MIRROR_STATUS_SHIFT 8 651#define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \ 652 I40E_RXD_QW0_MIRROR_STATUS_SHIFT) 653#define I40E_RXD_QW0_FCOEINDX_SHIFT 0 654#define I40E_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \ 655 I40E_RXD_QW0_FCOEINDX_SHIFT) 656 657enum i40e_rx_desc_status_bits { 658 /* Note: These are predefined bit offsets */ 659 I40E_RX_DESC_STATUS_DD_SHIFT = 0, 660 I40E_RX_DESC_STATUS_EOF_SHIFT = 1, 661 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2, 662 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3, 663 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4, 664 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */ 665 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7, 666 I40E_RX_DESC_STATUS_RESERVED1_SHIFT = 8, 667 668 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */ 669 I40E_RX_DESC_STATUS_FLM_SHIFT = 11, 670 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */ 671 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14, 672 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15, 673 I40E_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */ 674 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18, 675 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */ 676}; 677 678#define I40E_RXD_QW1_STATUS_SHIFT 0 679#define I40E_RXD_QW1_STATUS_MASK (((1 << I40E_RX_DESC_STATUS_LAST) - 1) << \ 680 I40E_RXD_QW1_STATUS_SHIFT) 681 682#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT 683#define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \ 684 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT) 685 686#define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT 687#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK (0x1UL << \ 688 I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT) 689 690#define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT I40E_RX_DESC_STATUS_UMBCAST 691#define I40E_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \ 692 I40E_RXD_QW1_STATUS_UMBCAST_SHIFT) 693 694enum i40e_rx_desc_fltstat_values { 695 I40E_RX_DESC_FLTSTAT_NO_DATA = 0, 696 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */ 697 I40E_RX_DESC_FLTSTAT_RSV = 2, 698 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3, 699}; 700 701#define I40E_RXD_PACKET_TYPE_UNICAST 0 702#define I40E_RXD_PACKET_TYPE_MULTICAST 1 703#define I40E_RXD_PACKET_TYPE_BROADCAST 2 704#define I40E_RXD_PACKET_TYPE_MIRRORED 3 705 706#define I40E_RXD_QW1_ERROR_SHIFT 19 707#define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT) 708 709enum i40e_rx_desc_error_bits { 710 /* Note: These are predefined bit offsets */ 711 I40E_RX_DESC_ERROR_RXE_SHIFT = 0, 712 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1, 713 I40E_RX_DESC_ERROR_HBO_SHIFT = 2, 714 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */ 715 I40E_RX_DESC_ERROR_IPE_SHIFT = 3, 716 I40E_RX_DESC_ERROR_L4E_SHIFT = 4, 717 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5, 718 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6, 719 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7 720}; 721 722enum i40e_rx_desc_error_l3l4e_fcoe_masks { 723 I40E_RX_DESC_ERROR_L3L4E_NONE = 0, 724 I40E_RX_DESC_ERROR_L3L4E_PROT = 1, 725 I40E_RX_DESC_ERROR_L3L4E_FC = 2, 726 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3, 727 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4 728}; 729 730#define I40E_RXD_QW1_PTYPE_SHIFT 30 731#define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT) 732 733/* Packet type non-ip values */ 734enum i40e_rx_l2_ptype { 735 I40E_RX_PTYPE_L2_RESERVED = 0, 736 I40E_RX_PTYPE_L2_MAC_PAY2 = 1, 737 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2, 738 I40E_RX_PTYPE_L2_FIP_PAY2 = 3, 739 I40E_RX_PTYPE_L2_OUI_PAY2 = 4, 740 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5, 741 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6, 742 I40E_RX_PTYPE_L2_ECP_PAY2 = 7, 743 I40E_RX_PTYPE_L2_EVB_PAY2 = 8, 744 I40E_RX_PTYPE_L2_QCN_PAY2 = 9, 745 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10, 746 I40E_RX_PTYPE_L2_ARP = 11, 747 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12, 748 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13, 749 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14, 750 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15, 751 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16, 752 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17, 753 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18, 754 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19, 755 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20, 756 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21, 757 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58, 758 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87, 759 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124, 760 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153 761}; 762 763struct i40e_rx_ptype_decoded { 764 u32 ptype:8; 765 u32 known:1; 766 u32 outer_ip:1; 767 u32 outer_ip_ver:1; 768 u32 outer_frag:1; 769 u32 tunnel_type:3; 770 u32 tunnel_end_prot:2; 771 u32 tunnel_end_frag:1; 772 u32 inner_prot:4; 773 u32 payload_layer:3; 774}; 775 776enum i40e_rx_ptype_outer_ip { 777 I40E_RX_PTYPE_OUTER_L2 = 0, 778 I40E_RX_PTYPE_OUTER_IP = 1 779}; 780 781enum i40e_rx_ptype_outer_ip_ver { 782 I40E_RX_PTYPE_OUTER_NONE = 0, 783 I40E_RX_PTYPE_OUTER_IPV4 = 0, 784 I40E_RX_PTYPE_OUTER_IPV6 = 1 785}; 786 787enum i40e_rx_ptype_outer_fragmented { 788 I40E_RX_PTYPE_NOT_FRAG = 0, 789 I40E_RX_PTYPE_FRAG = 1 790}; 791 792enum i40e_rx_ptype_tunnel_type { 793 I40E_RX_PTYPE_TUNNEL_NONE = 0, 794 I40E_RX_PTYPE_TUNNEL_IP_IP = 1, 795 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2, 796 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3, 797 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4, 798}; 799 800enum i40e_rx_ptype_tunnel_end_prot { 801 I40E_RX_PTYPE_TUNNEL_END_NONE = 0, 802 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1, 803 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2, 804}; 805 806enum i40e_rx_ptype_inner_prot { 807 I40E_RX_PTYPE_INNER_PROT_NONE = 0, 808 I40E_RX_PTYPE_INNER_PROT_UDP = 1, 809 I40E_RX_PTYPE_INNER_PROT_TCP = 2, 810 I40E_RX_PTYPE_INNER_PROT_SCTP = 3, 811 I40E_RX_PTYPE_INNER_PROT_ICMP = 4, 812 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5 813}; 814 815enum i40e_rx_ptype_payload_layer { 816 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0, 817 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1, 818 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2, 819 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3, 820}; 821 822#define I40E_RX_PTYPE_BIT_MASK 0x0FFFFFFF 823#define I40E_RX_PTYPE_SHIFT 56 824 825#define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38 826#define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \ 827 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) 828 829#define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52 830#define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \ 831 I40E_RXD_QW1_LENGTH_HBUF_SHIFT) 832 833#define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63 834#define I40E_RXD_QW1_LENGTH_SPH_MASK (0x1ULL << \ 835 I40E_RXD_QW1_LENGTH_SPH_SHIFT) 836 837#define I40E_RXD_QW1_NEXTP_SHIFT 38 838#define I40E_RXD_QW1_NEXTP_MASK (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT) 839 840#define I40E_RXD_QW2_EXT_STATUS_SHIFT 0 841#define I40E_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \ 842 I40E_RXD_QW2_EXT_STATUS_SHIFT) 843 844enum i40e_rx_desc_ext_status_bits { 845 /* Note: These are predefined bit offsets */ 846 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0, 847 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1, 848 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */ 849 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */ 850 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9, 851 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10, 852 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11, 853}; 854 855#define I40E_RXD_QW2_L2TAG2_SHIFT 0 856#define I40E_RXD_QW2_L2TAG2_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT) 857 858#define I40E_RXD_QW2_L2TAG3_SHIFT 16 859#define I40E_RXD_QW2_L2TAG3_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT) 860 861enum i40e_rx_desc_pe_status_bits { 862 /* Note: These are predefined bit offsets */ 863 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */ 864 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */ 865 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */ 866 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24, 867 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25, 868 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26, 869 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27, 870 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28, 871 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29 872}; 873 874#define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38 875#define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000 876 877#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2 878#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \ 879 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT) 880 881#define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0 882#define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \ 883 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT) 884 885#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19 886#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \ 887 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT) 888 889enum i40e_rx_prog_status_desc_status_bits { 890 /* Note: These are predefined bit offsets */ 891 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0, 892 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */ 893}; 894 895enum i40e_rx_prog_status_desc_prog_id_masks { 896 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1, 897 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2, 898 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4, 899}; 900 901enum i40e_rx_prog_status_desc_error_bits { 902 /* Note: These are predefined bit offsets */ 903 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0, 904 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1, 905 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2, 906 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3 907}; 908 909#define I40E_TWO_BIT_MASK 0x3 910#define I40E_THREE_BIT_MASK 0x7 911#define I40E_FOUR_BIT_MASK 0xF 912#define I40E_EIGHTEEN_BIT_MASK 0x3FFFF 913 914/* TX Descriptor */ 915struct i40e_tx_desc { 916 __le64 buffer_addr; /* Address of descriptor's data buf */ 917 __le64 cmd_type_offset_bsz; 918}; 919 920#define I40E_TXD_QW1_DTYPE_SHIFT 0 921#define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT) 922 923enum i40e_tx_desc_dtype_value { 924 I40E_TX_DESC_DTYPE_DATA = 0x0, 925 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */ 926 I40E_TX_DESC_DTYPE_CONTEXT = 0x1, 927 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2, 928 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8, 929 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9, 930 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB, 931 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC, 932 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD, 933 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF 934}; 935 936#define I40E_TXD_QW1_CMD_SHIFT 4 937#define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT) 938 939enum i40e_tx_desc_cmd_bits { 940 I40E_TX_DESC_CMD_EOP = 0x0001, 941 I40E_TX_DESC_CMD_RS = 0x0002, 942 I40E_TX_DESC_CMD_ICRC = 0x0004, 943 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008, 944 I40E_TX_DESC_CMD_DUMMY = 0x0010, 945 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */ 946 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */ 947 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */ 948 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */ 949 I40E_TX_DESC_CMD_FCOET = 0x0080, 950 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */ 951 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */ 952 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */ 953 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */ 954 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */ 955 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */ 956 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */ 957 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */ 958}; 959 960#define I40E_TXD_QW1_OFFSET_SHIFT 16 961#define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \ 962 I40E_TXD_QW1_OFFSET_SHIFT) 963 964enum i40e_tx_desc_length_fields { 965 /* Note: These are predefined bit offsets */ 966 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */ 967 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */ 968 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */ 969}; 970 971#define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT) 972#define I40E_TXD_QW1_IPLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT) 973#define I40E_TXD_QW1_L4LEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT) 974#define I40E_TXD_QW1_FCLEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT) 975 976#define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34 977#define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \ 978 I40E_TXD_QW1_TX_BUF_SZ_SHIFT) 979 980#define I40E_TXD_QW1_L2TAG1_SHIFT 48 981#define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT) 982 983/* Context descriptors */ 984struct i40e_tx_context_desc { 985 __le32 tunneling_params; 986 __le16 l2tag2; 987 __le16 rsvd; 988 __le64 type_cmd_tso_mss; 989}; 990 991#define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0 992#define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT) 993 994#define I40E_TXD_CTX_QW1_CMD_SHIFT 4 995#define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT) 996 997enum i40e_tx_ctx_desc_cmd_bits { 998 I40E_TX_CTX_DESC_TSO = 0x01, 999 I40E_TX_CTX_DESC_TSYN = 0x02, 1000 I40E_TX_CTX_DESC_IL2TAG2 = 0x04, 1001 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08, 1002 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00, 1003 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10, 1004 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20, 1005 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30, 1006 I40E_TX_CTX_DESC_SWPE = 0x40 1007}; 1008 1009#define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30 1010#define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \ 1011 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) 1012 1013#define I40E_TXD_CTX_QW1_MSS_SHIFT 50 1014#define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \ 1015 I40E_TXD_CTX_QW1_MSS_SHIFT) 1016 1017#define I40E_TXD_CTX_QW1_VSI_SHIFT 50 1018#define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT) 1019 1020#define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0 1021#define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \ 1022 I40E_TXD_CTX_QW0_EXT_IP_SHIFT) 1023 1024enum i40e_tx_ctx_desc_eipt_offload { 1025 I40E_TX_CTX_EXT_IP_NONE = 0x0, 1026 I40E_TX_CTX_EXT_IP_IPV6 = 0x1, 1027 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2, 1028 I40E_TX_CTX_EXT_IP_IPV4 = 0x3 1029}; 1030 1031#define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2 1032#define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \ 1033 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT) 1034 1035#define I40E_TXD_CTX_QW0_NATT_SHIFT 9 1036#define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) 1037 1038#define I40E_TXD_CTX_UDP_TUNNELING (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) 1039#define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) 1040 1041#define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11 1042#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \ 1043 I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT) 1044 1045#define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK 1046 1047#define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12 1048#define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \ 1049 I40E_TXD_CTX_QW0_NATLEN_SHIFT) 1050 1051#define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19 1052#define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \ 1053 I40E_TXD_CTX_QW0_DECTTL_SHIFT) 1054 1055struct i40e_nop_desc { 1056 __le64 rsvd; 1057 __le64 dtype_cmd; 1058}; 1059 1060#define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0 1061#define I40E_TXD_NOP_QW1_DTYPE_MASK (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT) 1062 1063#define I40E_TXD_NOP_QW1_CMD_SHIFT 4 1064#define I40E_TXD_NOP_QW1_CMD_MASK (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT) 1065 1066enum i40e_tx_nop_desc_cmd_bits { 1067 /* Note: These are predefined bit offsets */ 1068 I40E_TX_NOP_DESC_EOP_SHIFT = 0, 1069 I40E_TX_NOP_DESC_RS_SHIFT = 1, 1070 I40E_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */ 1071}; 1072 1073struct i40e_filter_program_desc { 1074 __le32 qindex_flex_ptype_vsi; 1075 __le32 rsvd; 1076 __le32 dtype_cmd_cntindex; 1077 __le32 fd_id; 1078}; 1079#define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0 1080#define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \ 1081 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) 1082#define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11 1083#define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \ 1084 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) 1085#define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17 1086#define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \ 1087 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) 1088 1089/* Packet Classifier Types for filters */ 1090enum i40e_filter_pctype { 1091 /* Note: Values 0-30 are reserved for future use */ 1092 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31, 1093 /* Note: Value 32 is reserved for future use */ 1094 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33, 1095 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34, 1096 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35, 1097 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36, 1098 /* Note: Values 37-40 are reserved for future use */ 1099 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41, 1100 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43, 1101 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44, 1102 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45, 1103 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46, 1104 /* Note: Value 47 is reserved for future use */ 1105 I40E_FILTER_PCTYPE_FCOE_OX = 48, 1106 I40E_FILTER_PCTYPE_FCOE_RX = 49, 1107 I40E_FILTER_PCTYPE_FCOE_OTHER = 50, 1108 /* Note: Values 51-62 are reserved for future use */ 1109 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63, 1110}; 1111 1112enum i40e_filter_program_desc_dest { 1113 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0, 1114 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1, 1115 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2, 1116}; 1117 1118enum i40e_filter_program_desc_fd_status { 1119 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0, 1120 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1, 1121 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2, 1122 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3, 1123}; 1124 1125#define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23 1126#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \ 1127 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) 1128 1129#define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0 1130#define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT) 1131 1132#define I40E_TXD_FLTR_QW1_CMD_SHIFT 4 1133#define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \ 1134 I40E_TXD_FLTR_QW1_CMD_SHIFT) 1135 1136#define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 1137#define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT) 1138 1139enum i40e_filter_program_desc_pcmd { 1140 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1, 1141 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2, 1142}; 1143 1144#define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 1145#define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT) 1146 1147#define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 1148#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK (0x1ULL << \ 1149 I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT) 1150 1151#define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \ 1152 I40E_TXD_FLTR_QW1_CMD_SHIFT) 1153#define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \ 1154 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) 1155 1156#define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20 1157#define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \ 1158 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) 1159 1160enum i40e_filter_type { 1161 I40E_FLOW_DIRECTOR_FLTR = 0, 1162 I40E_PE_QUAD_HASH_FLTR = 1, 1163 I40E_ETHERTYPE_FLTR, 1164 I40E_FCOE_CTX_FLTR, 1165 I40E_MAC_VLAN_FLTR, 1166 I40E_HASH_FLTR 1167}; 1168 1169struct i40e_vsi_context { 1170 u16 seid; 1171 u16 uplink_seid; 1172 u16 vsi_number; 1173 u16 vsis_allocated; 1174 u16 vsis_unallocated; 1175 u16 flags; 1176 u8 pf_num; 1177 u8 vf_num; 1178 u8 connection_type; 1179 struct i40e_aqc_vsi_properties_data info; 1180}; 1181 1182struct i40e_veb_context { 1183 u16 seid; 1184 u16 uplink_seid; 1185 u16 veb_number; 1186 u16 vebs_allocated; 1187 u16 vebs_unallocated; 1188 u16 flags; 1189 struct i40e_aqc_get_veb_parameters_completion info; 1190}; 1191 1192/* Statistics collected by each port, VSI, VEB, and S-channel */ 1193struct i40e_eth_stats { 1194 u64 rx_bytes; /* gorc */ 1195 u64 rx_unicast; /* uprc */ 1196 u64 rx_multicast; /* mprc */ 1197 u64 rx_broadcast; /* bprc */ 1198 u64 rx_discards; /* rdpc */ 1199 u64 rx_unknown_protocol; /* rupp */ 1200 u64 tx_bytes; /* gotc */ 1201 u64 tx_unicast; /* uptc */ 1202 u64 tx_multicast; /* mptc */ 1203 u64 tx_broadcast; /* bptc */ 1204 u64 tx_discards; /* tdpc */ 1205 u64 tx_errors; /* tepc */ 1206}; 1207 1208/* Statistics collected per VEB per TC */ 1209struct i40e_veb_tc_stats { 1210 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS]; 1211 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS]; 1212 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS]; 1213 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS]; 1214}; 1215 1216/* Statistics collected by the MAC */ 1217struct i40e_hw_port_stats { 1218 /* eth stats collected by the port */ 1219 struct i40e_eth_stats eth; 1220 1221 /* additional port specific stats */ 1222 u64 tx_dropped_link_down; /* tdold */ 1223 u64 crc_errors; /* crcerrs */ 1224 u64 illegal_bytes; /* illerrc */ 1225 u64 error_bytes; /* errbc */ 1226 u64 mac_local_faults; /* mlfc */ 1227 u64 mac_remote_faults; /* mrfc */ 1228 u64 rx_length_errors; /* rlec */ 1229 u64 link_xon_rx; /* lxonrxc */ 1230 u64 link_xoff_rx; /* lxoffrxc */ 1231 u64 priority_xon_rx[8]; /* pxonrxc[8] */ 1232 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 1233 u64 link_xon_tx; /* lxontxc */ 1234 u64 link_xoff_tx; /* lxofftxc */ 1235 u64 priority_xon_tx[8]; /* pxontxc[8] */ 1236 u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 1237 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 1238 u64 rx_size_64; /* prc64 */ 1239 u64 rx_size_127; /* prc127 */ 1240 u64 rx_size_255; /* prc255 */ 1241 u64 rx_size_511; /* prc511 */ 1242 u64 rx_size_1023; /* prc1023 */ 1243 u64 rx_size_1522; /* prc1522 */ 1244 u64 rx_size_big; /* prc9522 */ 1245 u64 rx_undersize; /* ruc */ 1246 u64 rx_fragments; /* rfc */ 1247 u64 rx_oversize; /* roc */ 1248 u64 rx_jabber; /* rjc */ 1249 u64 tx_size_64; /* ptc64 */ 1250 u64 tx_size_127; /* ptc127 */ 1251 u64 tx_size_255; /* ptc255 */ 1252 u64 tx_size_511; /* ptc511 */ 1253 u64 tx_size_1023; /* ptc1023 */ 1254 u64 tx_size_1522; /* ptc1522 */ 1255 u64 tx_size_big; /* ptc9522 */ 1256 u64 mac_short_packet_dropped; /* mspdc */ 1257 u64 checksum_error; /* xec */ 1258 /* flow director stats */ 1259 u64 fd_atr_match; 1260 u64 fd_sb_match; 1261 /* EEE LPI */ 1262 u32 tx_lpi_status; 1263 u32 rx_lpi_status; 1264 u64 tx_lpi_count; /* etlpic */ 1265 u64 rx_lpi_count; /* erlpic */ 1266}; 1267 1268/* Checksum and Shadow RAM pointers */ 1269#define I40E_SR_NVM_CONTROL_WORD 0x00 1270#define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03 1271#define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04 1272#define I40E_SR_OPTION_ROM_PTR 0x05 1273#define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06 1274#define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07 1275#define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08 1276#define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09 1277#define I40E_SR_RO_PCIE_LCB_PTR 0x0A 1278#define I40E_SR_EMP_IMAGE_PTR 0x0B 1279#define I40E_SR_PE_IMAGE_PTR 0x0C 1280#define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D 1281#define I40E_SR_MNG_CONFIG_PTR 0x0E 1282#define I40E_SR_EMP_MODULE_PTR 0x0F 1283#define I40E_SR_PBA_FLAGS 0x15 1284#define I40E_SR_PBA_BLOCK_PTR 0x16 1285#define I40E_SR_BOOT_CONFIG_PTR 0x17 1286#define I40E_SR_NVM_DEV_STARTER_VERSION 0x18 1287#define I40E_SR_NVM_WAKE_ON_LAN 0x19 1288#define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27 1289#define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28 1290#define I40E_SR_NVM_MAP_VERSION 0x29 1291#define I40E_SR_NVM_IMAGE_VERSION 0x2A 1292#define I40E_SR_NVM_STRUCTURE_VERSION 0x2B 1293#define I40E_SR_NVM_EETRACK_LO 0x2D 1294#define I40E_SR_NVM_EETRACK_HI 0x2E 1295#define I40E_SR_VPD_PTR 0x2F 1296#define I40E_SR_PXE_SETUP_PTR 0x30 1297#define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31 1298#define I40E_SR_NVM_ORIGINAL_EETRACK_LO 0x34 1299#define I40E_SR_NVM_ORIGINAL_EETRACK_HI 0x35 1300#define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37 1301#define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38 1302#define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A 1303#define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B 1304#define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C 1305#define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E 1306#define I40E_SR_SW_CHECKSUM_WORD 0x3F 1307#define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40 1308#define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42 1309#define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44 1310#define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46 1311#define I40E_SR_EMP_SR_SETTINGS_PTR 0x48 1312#define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49 1313#define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D 1314#define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E 1315 1316/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ 1317#define I40E_SR_VPD_MODULE_MAX_SIZE 1024 1318#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024 1319#define I40E_SR_CONTROL_WORD_1_SHIFT 0x06 1320#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT) 1321 1322/* Shadow RAM related */ 1323#define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800 1324#define I40E_SR_BUF_ALIGNMENT 4096 1325#define I40E_SR_WORDS_IN_1KB 512 1326/* Checksum should be calculated such that after adding all the words, 1327 * including the checksum word itself, the sum should be 0xBABA. 1328 */ 1329#define I40E_SR_SW_CHECKSUM_BASE 0xBABA 1330 1331#define I40E_SRRD_SRCTL_ATTEMPTS 100000 1332 1333enum i40e_switch_element_types { 1334 I40E_SWITCH_ELEMENT_TYPE_MAC = 1, 1335 I40E_SWITCH_ELEMENT_TYPE_PF = 2, 1336 I40E_SWITCH_ELEMENT_TYPE_VF = 3, 1337 I40E_SWITCH_ELEMENT_TYPE_EMP = 4, 1338 I40E_SWITCH_ELEMENT_TYPE_BMC = 6, 1339 I40E_SWITCH_ELEMENT_TYPE_PE = 16, 1340 I40E_SWITCH_ELEMENT_TYPE_VEB = 17, 1341 I40E_SWITCH_ELEMENT_TYPE_PA = 18, 1342 I40E_SWITCH_ELEMENT_TYPE_VSI = 19, 1343}; 1344 1345/* Supported EtherType filters */ 1346enum i40e_ether_type_index { 1347 I40E_ETHER_TYPE_1588 = 0, 1348 I40E_ETHER_TYPE_FIP = 1, 1349 I40E_ETHER_TYPE_OUI_EXTENDED = 2, 1350 I40E_ETHER_TYPE_MAC_CONTROL = 3, 1351 I40E_ETHER_TYPE_LLDP = 4, 1352 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5, 1353 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6, 1354 I40E_ETHER_TYPE_QCN_CNM = 7, 1355 I40E_ETHER_TYPE_8021X = 8, 1356 I40E_ETHER_TYPE_ARP = 9, 1357 I40E_ETHER_TYPE_RSV1 = 10, 1358 I40E_ETHER_TYPE_RSV2 = 11, 1359}; 1360 1361/* Filter context base size is 1K */ 1362#define I40E_HASH_FILTER_BASE_SIZE 1024 1363/* Supported Hash filter values */ 1364enum i40e_hash_filter_size { 1365 I40E_HASH_FILTER_SIZE_1K = 0, 1366 I40E_HASH_FILTER_SIZE_2K = 1, 1367 I40E_HASH_FILTER_SIZE_4K = 2, 1368 I40E_HASH_FILTER_SIZE_8K = 3, 1369 I40E_HASH_FILTER_SIZE_16K = 4, 1370 I40E_HASH_FILTER_SIZE_32K = 5, 1371 I40E_HASH_FILTER_SIZE_64K = 6, 1372 I40E_HASH_FILTER_SIZE_128K = 7, 1373 I40E_HASH_FILTER_SIZE_256K = 8, 1374 I40E_HASH_FILTER_SIZE_512K = 9, 1375 I40E_HASH_FILTER_SIZE_1M = 10, 1376}; 1377 1378/* DMA context base size is 0.5K */ 1379#define I40E_DMA_CNTX_BASE_SIZE 512 1380/* Supported DMA context values */ 1381enum i40e_dma_cntx_size { 1382 I40E_DMA_CNTX_SIZE_512 = 0, 1383 I40E_DMA_CNTX_SIZE_1K = 1, 1384 I40E_DMA_CNTX_SIZE_2K = 2, 1385 I40E_DMA_CNTX_SIZE_4K = 3, 1386 I40E_DMA_CNTX_SIZE_8K = 4, 1387 I40E_DMA_CNTX_SIZE_16K = 5, 1388 I40E_DMA_CNTX_SIZE_32K = 6, 1389 I40E_DMA_CNTX_SIZE_64K = 7, 1390 I40E_DMA_CNTX_SIZE_128K = 8, 1391 I40E_DMA_CNTX_SIZE_256K = 9, 1392}; 1393 1394/* Supported Hash look up table (LUT) sizes */ 1395enum i40e_hash_lut_size { 1396 I40E_HASH_LUT_SIZE_128 = 0, 1397 I40E_HASH_LUT_SIZE_512 = 1, 1398}; 1399 1400/* Structure to hold a per PF filter control settings */ 1401struct i40e_filter_control_settings { 1402 /* number of PE Quad Hash filter buckets */ 1403 enum i40e_hash_filter_size pe_filt_num; 1404 /* number of PE Quad Hash contexts */ 1405 enum i40e_dma_cntx_size pe_cntx_num; 1406 /* number of FCoE filter buckets */ 1407 enum i40e_hash_filter_size fcoe_filt_num; 1408 /* number of FCoE DDP contexts */ 1409 enum i40e_dma_cntx_size fcoe_cntx_num; 1410 /* size of the Hash LUT */ 1411 enum i40e_hash_lut_size hash_lut_size; 1412 /* enable FDIR filters for PF and its VFs */ 1413 bool enable_fdir; 1414 /* enable Ethertype filters for PF and its VFs */ 1415 bool enable_ethtype; 1416 /* enable MAC/VLAN filters for PF and its VFs */ 1417 bool enable_macvlan; 1418}; 1419 1420/* Structure to hold device level control filter counts */ 1421struct i40e_control_filter_stats { 1422 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */ 1423 u16 etype_used; /* Used perfect EtherType filters */ 1424 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */ 1425 u16 etype_free; /* Un-used perfect EtherType filters */ 1426}; 1427 1428enum i40e_reset_type { 1429 I40E_RESET_POR = 0, 1430 I40E_RESET_CORER = 1, 1431 I40E_RESET_GLOBR = 2, 1432 I40E_RESET_EMPR = 3, 1433}; 1434 1435/* IEEE 802.1AB LLDP Agent Variables from NVM */ 1436#define I40E_NVM_LLDP_CFG_PTR 0xD 1437struct i40e_lldp_variables { 1438 u16 length; 1439 u16 adminstatus; 1440 u16 msgfasttx; 1441 u16 msgtxinterval; 1442 u16 txparams; 1443 u16 timers; 1444 u16 crc8; 1445}; 1446 1447/* Offsets into Alternate Ram */ 1448#define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */ 1449#define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */ 1450#define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */ 1451#define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */ 1452#define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */ 1453#define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */ 1454 1455/* Alternate Ram Bandwidth Masks */ 1456#define I40E_ALT_BW_VALUE_MASK 0xFF 1457#define I40E_ALT_BW_RELATIVE_MASK 0x40000000 1458#define I40E_ALT_BW_VALID_MASK 0x80000000 1459 1460/* RSS Hash Table Size */ 1461#define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000 1462#endif /* _I40E_TYPE_H_ */ 1463