1266423Sjfv/****************************************************************************** 2266423Sjfv 3349163Serj Copyright (c) 2013-2019, Intel Corporation 4266423Sjfv All rights reserved. 5349163Serj 6266423Sjfv Redistribution and use in source and binary forms, with or without 7266423Sjfv modification, are permitted provided that the following conditions are met: 8266423Sjfv 9266423Sjfv 1. Redistributions of source code must retain the above copyright notice, 10266423Sjfv this list of conditions and the following disclaimer. 11266423Sjfv 12266423Sjfv 2. Redistributions in binary form must reproduce the above copyright 13266423Sjfv notice, this list of conditions and the following disclaimer in the 14266423Sjfv documentation and/or other materials provided with the distribution. 15266423Sjfv 16266423Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17266423Sjfv contributors may be used to endorse or promote products derived from 18266423Sjfv this software without specific prior written permission. 19266423Sjfv 20266423Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21266423Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22266423Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23266423Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24266423Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25266423Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26266423Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27266423Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28266423Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29266423Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30266423Sjfv POSSIBILITY OF SUCH DAMAGE. 31266423Sjfv 32266423Sjfv******************************************************************************/ 33266423Sjfv/*$FreeBSD: stable/11/sys/dev/ixl/i40e_type.h 349163 2019-06-18 00:08:02Z erj $*/ 34266423Sjfv 35266423Sjfv#ifndef _I40E_TYPE_H_ 36266423Sjfv#define _I40E_TYPE_H_ 37266423Sjfv 38266423Sjfv#include "i40e_status.h" 39266423Sjfv#include "i40e_osdep.h" 40266423Sjfv#include "i40e_register.h" 41266423Sjfv#include "i40e_adminq.h" 42266423Sjfv#include "i40e_hmc.h" 43266423Sjfv#include "i40e_lan_hmc.h" 44284049Sjfv#include "i40e_devids.h" 45266423Sjfv 46266423Sjfv 47284049Sjfv#define BIT(a) (1UL << (a)) 48284049Sjfv#define BIT_ULL(a) (1ULL << (a)) 49266423Sjfv 50269198Sjfv#ifndef I40E_MASK 51266423Sjfv/* I40E_MASK is a macro used on 32 bit registers */ 52266423Sjfv#define I40E_MASK(mask, shift) (mask << shift) 53269198Sjfv#endif 54266423Sjfv 55266423Sjfv#define I40E_MAX_PF 16 56266423Sjfv#define I40E_MAX_PF_VSI 64 57266423Sjfv#define I40E_MAX_PF_QP 128 58266423Sjfv#define I40E_MAX_VSI_QP 16 59349163Serj#define I40E_MAX_VF_VSI 4 60266423Sjfv#define I40E_MAX_CHAINED_RX_BUFFERS 5 61266423Sjfv#define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16 62266423Sjfv 63266423Sjfv/* something less than 1 minute */ 64266423Sjfv#define I40E_HEARTBEAT_TIMEOUT (HZ * 50) 65266423Sjfv 66266423Sjfv/* Max default timeout in ms, */ 67266423Sjfv#define I40E_MAX_NVM_TIMEOUT 18000 68266423Sjfv 69333343Serj/* Max timeout in ms for the phy to respond */ 70333343Serj#define I40E_MAX_PHY_TIMEOUT 500 71333343Serj 72266423Sjfv/* Check whether address is multicast. */ 73266423Sjfv#define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01)) 74266423Sjfv 75266423Sjfv/* Check whether an address is broadcast. */ 76266423Sjfv#define I40E_IS_BROADCAST(address) \ 77266423Sjfv ((((u8 *)(address))[0] == ((u8)0xff)) && \ 78266423Sjfv (((u8 *)(address))[1] == ((u8)0xff))) 79266423Sjfv 80266423Sjfv/* Switch from ms to the 1usec global time (this is the GTIME resolution) */ 81266423Sjfv#define I40E_MS_TO_GTIME(time) ((time) * 1000) 82266423Sjfv 83266423Sjfv/* forward declaration */ 84266423Sjfvstruct i40e_hw; 85266423Sjfvtypedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *); 86266423Sjfv 87333343Serj#define ETH_ALEN 6 88266423Sjfv/* Data type manipulation macros. */ 89266423Sjfv#define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF)) 90266423Sjfv#define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF)) 91266423Sjfv 92266423Sjfv#define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF)) 93266423Sjfv#define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF)) 94266423Sjfv 95266423Sjfv#define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF)) 96266423Sjfv#define I40E_LO_BYTE(x) ((u8)((x) & 0xFF)) 97266423Sjfv 98266423Sjfv/* Number of Transmit Descriptors must be a multiple of 8. */ 99266423Sjfv#define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8 100266423Sjfv/* Number of Receive Descriptors must be a multiple of 32 if 101266423Sjfv * the number of descriptors is greater than 32. 102266423Sjfv */ 103266423Sjfv#define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32 104266423Sjfv 105266423Sjfv#define I40E_DESC_UNUSED(R) \ 106266423Sjfv ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 107266423Sjfv (R)->next_to_clean - (R)->next_to_use - 1) 108266423Sjfv 109266423Sjfv/* bitfields for Tx queue mapping in QTX_CTL */ 110266423Sjfv#define I40E_QTX_CTL_VF_QUEUE 0x0 111266423Sjfv#define I40E_QTX_CTL_VM_QUEUE 0x1 112266423Sjfv#define I40E_QTX_CTL_PF_QUEUE 0x2 113266423Sjfv 114266423Sjfv/* debug masks - set these bits in hw->debug_mask to control output */ 115266423Sjfvenum i40e_debug_mask { 116266423Sjfv I40E_DEBUG_INIT = 0x00000001, 117266423Sjfv I40E_DEBUG_RELEASE = 0x00000002, 118266423Sjfv 119266423Sjfv I40E_DEBUG_LINK = 0x00000010, 120266423Sjfv I40E_DEBUG_PHY = 0x00000020, 121266423Sjfv I40E_DEBUG_HMC = 0x00000040, 122266423Sjfv I40E_DEBUG_NVM = 0x00000080, 123266423Sjfv I40E_DEBUG_LAN = 0x00000100, 124266423Sjfv I40E_DEBUG_FLOW = 0x00000200, 125266423Sjfv I40E_DEBUG_DCB = 0x00000400, 126266423Sjfv I40E_DEBUG_DIAG = 0x00000800, 127266423Sjfv I40E_DEBUG_FD = 0x00001000, 128266423Sjfv 129266423Sjfv I40E_DEBUG_AQ_MESSAGE = 0x01000000, 130266423Sjfv I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000, 131266423Sjfv I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000, 132266423Sjfv I40E_DEBUG_AQ_COMMAND = 0x06000000, 133266423Sjfv I40E_DEBUG_AQ = 0x0F000000, 134266423Sjfv 135266423Sjfv I40E_DEBUG_USER = 0xF0000000, 136266423Sjfv 137266423Sjfv I40E_DEBUG_ALL = 0xFFFFFFFF 138266423Sjfv}; 139266423Sjfv 140266423Sjfv/* PCI Bus Info */ 141266423Sjfv#define I40E_PCI_LINK_STATUS 0xB2 142266423Sjfv#define I40E_PCI_LINK_WIDTH 0x3F0 143266423Sjfv#define I40E_PCI_LINK_WIDTH_1 0x10 144266423Sjfv#define I40E_PCI_LINK_WIDTH_2 0x20 145266423Sjfv#define I40E_PCI_LINK_WIDTH_4 0x40 146266423Sjfv#define I40E_PCI_LINK_WIDTH_8 0x80 147266423Sjfv#define I40E_PCI_LINK_SPEED 0xF 148266423Sjfv#define I40E_PCI_LINK_SPEED_2500 0x1 149266423Sjfv#define I40E_PCI_LINK_SPEED_5000 0x2 150266423Sjfv#define I40E_PCI_LINK_SPEED_8000 0x3 151266423Sjfv 152318357Serj#define I40E_MDIO_CLAUSE22_STCODE_MASK I40E_MASK(1, \ 153303967Ssbruno I40E_GLGEN_MSCA_STCODE_SHIFT) 154318357Serj#define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK I40E_MASK(1, \ 155303967Ssbruno I40E_GLGEN_MSCA_OPCODE_SHIFT) 156318357Serj#define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK I40E_MASK(2, \ 157299553Serj I40E_GLGEN_MSCA_OPCODE_SHIFT) 158318357Serj 159318357Serj#define I40E_MDIO_CLAUSE45_STCODE_MASK I40E_MASK(0, \ 160318357Serj I40E_GLGEN_MSCA_STCODE_SHIFT) 161318357Serj#define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK I40E_MASK(0, \ 162299553Serj I40E_GLGEN_MSCA_OPCODE_SHIFT) 163318357Serj#define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK I40E_MASK(1, \ 164299553Serj I40E_GLGEN_MSCA_OPCODE_SHIFT) 165318357Serj#define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK I40E_MASK(2, \ 166318357Serj I40E_GLGEN_MSCA_OPCODE_SHIFT) 167318357Serj#define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK I40E_MASK(3, \ 168318357Serj I40E_GLGEN_MSCA_OPCODE_SHIFT) 169299553Serj 170299553Serj#define I40E_PHY_COM_REG_PAGE 0x1E 171299553Serj#define I40E_PHY_LED_LINK_MODE_MASK 0xF0 172299553Serj#define I40E_PHY_LED_MANUAL_ON 0x100 173299553Serj#define I40E_PHY_LED_PROV_REG_1 0xC430 174299553Serj#define I40E_PHY_LED_MODE_MASK 0xFFFF 175299553Serj#define I40E_PHY_LED_MODE_ORIG 0x80000000 176299553Serj 177266423Sjfv/* Memory types */ 178266423Sjfvenum i40e_memset_type { 179266423Sjfv I40E_NONDMA_MEM = 0, 180266423Sjfv I40E_DMA_MEM 181266423Sjfv}; 182266423Sjfv 183266423Sjfv/* Memcpy types */ 184266423Sjfvenum i40e_memcpy_type { 185266423Sjfv I40E_NONDMA_TO_NONDMA = 0, 186266423Sjfv I40E_NONDMA_TO_DMA, 187266423Sjfv I40E_DMA_TO_DMA, 188266423Sjfv I40E_DMA_TO_NONDMA 189266423Sjfv}; 190266423Sjfv 191299546Serj 192266423Sjfv/* These are structs for managing the hardware information and the operations. 193266423Sjfv * The structures of function pointers are filled out at init time when we 194266423Sjfv * know for sure exactly which hardware we're working with. This gives us the 195266423Sjfv * flexibility of using the same main driver code but adapting to slightly 196266423Sjfv * different hardware needs as new parts are developed. For this architecture, 197266423Sjfv * the Firmware and AdminQ are intended to insulate the driver from most of the 198266423Sjfv * future changes, but these structures will also do part of the job. 199266423Sjfv */ 200266423Sjfvenum i40e_mac_type { 201266423Sjfv I40E_MAC_UNKNOWN = 0, 202266423Sjfv I40E_MAC_XL710, 203266423Sjfv I40E_MAC_VF, 204303967Ssbruno I40E_MAC_X722, 205303967Ssbruno I40E_MAC_X722_VF, 206266423Sjfv I40E_MAC_GENERIC, 207266423Sjfv}; 208266423Sjfv 209266423Sjfvenum i40e_media_type { 210266423Sjfv I40E_MEDIA_TYPE_UNKNOWN = 0, 211266423Sjfv I40E_MEDIA_TYPE_FIBER, 212266423Sjfv I40E_MEDIA_TYPE_BASET, 213266423Sjfv I40E_MEDIA_TYPE_BACKPLANE, 214266423Sjfv I40E_MEDIA_TYPE_CX4, 215266423Sjfv I40E_MEDIA_TYPE_DA, 216266423Sjfv I40E_MEDIA_TYPE_VIRTUAL 217266423Sjfv}; 218266423Sjfv 219266423Sjfvenum i40e_fc_mode { 220266423Sjfv I40E_FC_NONE = 0, 221266423Sjfv I40E_FC_RX_PAUSE, 222266423Sjfv I40E_FC_TX_PAUSE, 223266423Sjfv I40E_FC_FULL, 224266423Sjfv I40E_FC_PFC, 225266423Sjfv I40E_FC_DEFAULT 226266423Sjfv}; 227266423Sjfv 228266423Sjfvenum i40e_set_fc_aq_failures { 229266423Sjfv I40E_SET_FC_AQ_FAIL_NONE = 0, 230269198Sjfv I40E_SET_FC_AQ_FAIL_GET = 1, 231266423Sjfv I40E_SET_FC_AQ_FAIL_SET = 2, 232269198Sjfv I40E_SET_FC_AQ_FAIL_UPDATE = 4, 233269198Sjfv I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6 234266423Sjfv}; 235266423Sjfv 236266423Sjfvenum i40e_vsi_type { 237284049Sjfv I40E_VSI_MAIN = 0, 238284049Sjfv I40E_VSI_VMDQ1 = 1, 239284049Sjfv I40E_VSI_VMDQ2 = 2, 240284049Sjfv I40E_VSI_CTRL = 3, 241284049Sjfv I40E_VSI_FCOE = 4, 242284049Sjfv I40E_VSI_MIRROR = 5, 243284049Sjfv I40E_VSI_SRIOV = 6, 244284049Sjfv I40E_VSI_FDIR = 7, 245266423Sjfv I40E_VSI_TYPE_UNKNOWN 246266423Sjfv}; 247266423Sjfv 248266423Sjfvenum i40e_queue_type { 249266423Sjfv I40E_QUEUE_TYPE_RX = 0, 250266423Sjfv I40E_QUEUE_TYPE_TX, 251266423Sjfv I40E_QUEUE_TYPE_PE_CEQ, 252266423Sjfv I40E_QUEUE_TYPE_UNKNOWN 253266423Sjfv}; 254266423Sjfv 255266423Sjfvstruct i40e_link_status { 256266423Sjfv enum i40e_aq_phy_type phy_type; 257266423Sjfv enum i40e_aq_link_speed link_speed; 258266423Sjfv u8 link_info; 259266423Sjfv u8 an_info; 260333343Serj u8 req_fec_info; 261318357Serj u8 fec_info; 262266423Sjfv u8 ext_info; 263266423Sjfv u8 loopback; 264266423Sjfv /* is Link Status Event notification to SW enabled */ 265266423Sjfv bool lse_enable; 266266423Sjfv u16 max_frame_size; 267266423Sjfv bool crc_enable; 268266423Sjfv u8 pacing; 269277082Sjfv u8 requested_speeds; 270284049Sjfv u8 module_type[3]; 271284049Sjfv /* 1st byte: module identifier */ 272284049Sjfv#define I40E_MODULE_TYPE_SFP 0x03 273284049Sjfv#define I40E_MODULE_TYPE_QSFP 0x0D 274284049Sjfv /* 2nd byte: ethernet compliance codes for 10/40G */ 275284049Sjfv#define I40E_MODULE_TYPE_40G_ACTIVE 0x01 276284049Sjfv#define I40E_MODULE_TYPE_40G_LR4 0x02 277284049Sjfv#define I40E_MODULE_TYPE_40G_SR4 0x04 278284049Sjfv#define I40E_MODULE_TYPE_40G_CR4 0x08 279284049Sjfv#define I40E_MODULE_TYPE_10G_BASE_SR 0x10 280284049Sjfv#define I40E_MODULE_TYPE_10G_BASE_LR 0x20 281284049Sjfv#define I40E_MODULE_TYPE_10G_BASE_LRM 0x40 282284049Sjfv#define I40E_MODULE_TYPE_10G_BASE_ER 0x80 283284049Sjfv /* 3rd byte: ethernet compliance codes for 1G */ 284284049Sjfv#define I40E_MODULE_TYPE_1000BASE_SX 0x01 285284049Sjfv#define I40E_MODULE_TYPE_1000BASE_LX 0x02 286284049Sjfv#define I40E_MODULE_TYPE_1000BASE_CX 0x04 287284049Sjfv#define I40E_MODULE_TYPE_1000BASE_T 0x08 288266423Sjfv}; 289266423Sjfv 290266423Sjfvstruct i40e_phy_info { 291266423Sjfv struct i40e_link_status link_info; 292266423Sjfv struct i40e_link_status link_info_old; 293266423Sjfv bool get_link_info; 294266423Sjfv enum i40e_media_type media_type; 295284049Sjfv /* all the phy types the NVM is capable of */ 296303967Ssbruno u64 phy_types; 297266423Sjfv}; 298266423Sjfv 299303967Ssbruno#define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII) 300303967Ssbruno#define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) 301303967Ssbruno#define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) 302303967Ssbruno#define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) 303303967Ssbruno#define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) 304303967Ssbruno#define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI) 305303967Ssbruno#define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI) 306303967Ssbruno#define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI) 307303967Ssbruno#define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI) 308303967Ssbruno#define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI) 309303967Ssbruno#define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) 310303967Ssbruno#define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) 311303967Ssbruno#define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) 312303967Ssbruno#define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) 313303967Ssbruno#define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX) 314303967Ssbruno#define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T) 315303967Ssbruno#define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T) 316303967Ssbruno#define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) 317303967Ssbruno#define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) 318303967Ssbruno#define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) 319303967Ssbruno#define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) 320303967Ssbruno#define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) 321303967Ssbruno#define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) 322303967Ssbruno#define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) 323303967Ssbruno#define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) 324303967Ssbruno#define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) 325303967Ssbruno#define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \ 326303967Ssbruno BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) 327303967Ssbruno#define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) 328318357Serj/* 329318357Serj * Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some 330318357Serj * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit 331318357Serj * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So, 332318357Serj * a shift is needed to adjust for this with values larger than 31. The 333318357Serj * only affected values are I40E_PHY_TYPE_25GBASE_*. 334318357Serj */ 335318357Serj#define I40E_PHY_TYPE_OFFSET 1 336318357Serj#define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \ 337318357Serj I40E_PHY_TYPE_OFFSET) 338318357Serj#define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \ 339318357Serj I40E_PHY_TYPE_OFFSET) 340318357Serj#define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \ 341318357Serj I40E_PHY_TYPE_OFFSET) 342318357Serj#define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \ 343318357Serj I40E_PHY_TYPE_OFFSET) 344333343Serj#define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \ 345333343Serj I40E_PHY_TYPE_OFFSET) 346333343Serj#define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \ 347333343Serj I40E_PHY_TYPE_OFFSET) 348349163Serj/* Offset for 2.5G/5G PHY Types value to bit number conversion */ 349349163Serj#define I40E_PHY_TYPE_OFFSET2 (-10) 350349163Serj#define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T + \ 351349163Serj I40E_PHY_TYPE_OFFSET2) 352349163Serj#define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T + \ 353349163Serj I40E_PHY_TYPE_OFFSET2) 354266423Sjfv#define I40E_HW_CAP_MAX_GPIO 30 355266423Sjfv#define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0 356266423Sjfv#define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1 357266423Sjfv 358303967Ssbrunoenum i40e_acpi_programming_method { 359303967Ssbruno I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0, 360303967Ssbruno I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1 361303967Ssbruno}; 362303967Ssbruno 363318357Serj#define I40E_WOL_SUPPORT_MASK 0x1 364318357Serj#define I40E_ACPI_PROGRAMMING_METHOD_MASK 0x2 365318357Serj#define I40E_PROXY_SUPPORT_MASK 0x4 366303967Ssbruno 367266423Sjfv/* Capabilities of a PF or a VF or the whole device */ 368266423Sjfvstruct i40e_hw_capabilities { 369266423Sjfv u32 switch_mode; 370266423Sjfv#define I40E_NVM_IMAGE_TYPE_EVB 0x0 371266423Sjfv#define I40E_NVM_IMAGE_TYPE_CLOUD 0x2 372266423Sjfv#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3 373266423Sjfv 374333343Serj /* Cloud filter modes: 375333343Serj * Mode1: Filter on L4 port only 376333343Serj * Mode2: Filter for non-tunneled traffic 377333343Serj * Mode3: Filter for tunnel traffic 378333343Serj */ 379333343Serj#define I40E_CLOUD_FILTER_MODE1 0x6 380333343Serj#define I40E_CLOUD_FILTER_MODE2 0x7 381333343Serj#define I40E_CLOUD_FILTER_MODE3 0x8 382333343Serj 383266423Sjfv u32 management_mode; 384318357Serj u32 mng_protocols_over_mctp; 385318357Serj#define I40E_MNG_PROTOCOL_PLDM 0x2 386318357Serj#define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4 387318357Serj#define I40E_MNG_PROTOCOL_NCSI 0x8 388266423Sjfv u32 npar_enable; 389266423Sjfv u32 os2bmc; 390266423Sjfv u32 valid_functions; 391266423Sjfv bool sr_iov_1_1; 392266423Sjfv bool vmdq; 393266423Sjfv bool evb_802_1_qbg; /* Edge Virtual Bridging */ 394266423Sjfv bool evb_802_1_qbh; /* Bridge Port Extension */ 395266423Sjfv bool dcb; 396266423Sjfv bool fcoe; 397277082Sjfv bool iscsi; /* Indicates iSCSI enabled */ 398284049Sjfv bool flex10_enable; 399284049Sjfv bool flex10_capable; 400284049Sjfv u32 flex10_mode; 401284049Sjfv#define I40E_FLEX10_MODE_UNKNOWN 0x0 402284049Sjfv#define I40E_FLEX10_MODE_DCC 0x1 403284049Sjfv#define I40E_FLEX10_MODE_DCI 0x2 404284049Sjfv 405284049Sjfv u32 flex10_status; 406284049Sjfv#define I40E_FLEX10_STATUS_DCC_ERROR 0x1 407284049Sjfv#define I40E_FLEX10_STATUS_VC_MODE 0x2 408284049Sjfv 409303967Ssbruno bool sec_rev_disabled; 410303967Ssbruno bool update_disabled; 411303967Ssbruno#define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1 412303967Ssbruno#define I40E_NVM_MGMT_UPDATE_DISABLED 0x2 413303967Ssbruno 414266423Sjfv bool mgmt_cem; 415266423Sjfv bool ieee_1588; 416266423Sjfv bool iwarp; 417266423Sjfv bool fd; 418266423Sjfv u32 fd_filters_guaranteed; 419266423Sjfv u32 fd_filters_best_effort; 420266423Sjfv bool rss; 421266423Sjfv u32 rss_table_size; 422266423Sjfv u32 rss_table_entry_width; 423266423Sjfv bool led[I40E_HW_CAP_MAX_GPIO]; 424266423Sjfv bool sdp[I40E_HW_CAP_MAX_GPIO]; 425266423Sjfv u32 nvm_image_type; 426266423Sjfv u32 num_flow_director_filters; 427266423Sjfv u32 num_vfs; 428266423Sjfv u32 vf_base_id; 429266423Sjfv u32 num_vsis; 430266423Sjfv u32 num_rx_qp; 431266423Sjfv u32 num_tx_qp; 432266423Sjfv u32 base_queue; 433266423Sjfv u32 num_msix_vectors; 434266423Sjfv u32 num_msix_vectors_vf; 435266423Sjfv u32 led_pin_num; 436266423Sjfv u32 sdp_pin_num; 437266423Sjfv u32 mdio_port_num; 438266423Sjfv u32 mdio_port_mode; 439266423Sjfv u8 rx_buf_chain_len; 440266423Sjfv u32 enabled_tcmap; 441266423Sjfv u32 maxtc; 442284049Sjfv u64 wr_csr_prot; 443303967Ssbruno bool apm_wol_support; 444303967Ssbruno enum i40e_acpi_programming_method acpi_prog_method; 445303967Ssbruno bool proxy_support; 446266423Sjfv}; 447266423Sjfv 448266423Sjfvstruct i40e_mac_info { 449266423Sjfv enum i40e_mac_type type; 450333343Serj u8 addr[ETH_ALEN]; 451333343Serj u8 perm_addr[ETH_ALEN]; 452333343Serj u8 san_addr[ETH_ALEN]; 453333343Serj u8 port_addr[ETH_ALEN]; 454266423Sjfv u16 max_fcoeq; 455266423Sjfv}; 456266423Sjfv 457266423Sjfvenum i40e_aq_resources_ids { 458266423Sjfv I40E_NVM_RESOURCE_ID = 1 459266423Sjfv}; 460266423Sjfv 461266423Sjfvenum i40e_aq_resource_access_type { 462266423Sjfv I40E_RESOURCE_READ = 1, 463266423Sjfv I40E_RESOURCE_WRITE 464266423Sjfv}; 465266423Sjfv 466266423Sjfvstruct i40e_nvm_info { 467277082Sjfv u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */ 468266423Sjfv u32 timeout; /* [ms] */ 469266423Sjfv u16 sr_size; /* Shadow RAM size in words */ 470266423Sjfv bool blank_nvm_mode; /* is NVM empty (no FW present)*/ 471266423Sjfv u16 version; /* NVM package version */ 472266423Sjfv u32 eetrack; /* NVM data version */ 473284049Sjfv u32 oem_ver; /* OEM version info */ 474266423Sjfv}; 475266423Sjfv 476266423Sjfv/* definitions used in NVM update support */ 477266423Sjfv 478266423Sjfvenum i40e_nvmupd_cmd { 479266423Sjfv I40E_NVMUPD_INVALID, 480266423Sjfv I40E_NVMUPD_READ_CON, 481266423Sjfv I40E_NVMUPD_READ_SNT, 482266423Sjfv I40E_NVMUPD_READ_LCB, 483266423Sjfv I40E_NVMUPD_READ_SA, 484266423Sjfv I40E_NVMUPD_WRITE_ERA, 485266423Sjfv I40E_NVMUPD_WRITE_CON, 486266423Sjfv I40E_NVMUPD_WRITE_SNT, 487266423Sjfv I40E_NVMUPD_WRITE_LCB, 488266423Sjfv I40E_NVMUPD_WRITE_SA, 489266423Sjfv I40E_NVMUPD_CSUM_CON, 490266423Sjfv I40E_NVMUPD_CSUM_SA, 491266423Sjfv I40E_NVMUPD_CSUM_LCB, 492284049Sjfv I40E_NVMUPD_STATUS, 493284049Sjfv I40E_NVMUPD_EXEC_AQ, 494284049Sjfv I40E_NVMUPD_GET_AQ_RESULT, 495333343Serj I40E_NVMUPD_GET_AQ_EVENT, 496349163Serj I40E_NVMUPD_FEATURES, 497266423Sjfv}; 498266423Sjfv 499266423Sjfvenum i40e_nvmupd_state { 500266423Sjfv I40E_NVMUPD_STATE_INIT, 501266423Sjfv I40E_NVMUPD_STATE_READING, 502284049Sjfv I40E_NVMUPD_STATE_WRITING, 503284049Sjfv I40E_NVMUPD_STATE_INIT_WAIT, 504284049Sjfv I40E_NVMUPD_STATE_WRITE_WAIT, 505318357Serj I40E_NVMUPD_STATE_ERROR 506266423Sjfv}; 507266423Sjfv 508266423Sjfv/* nvm_access definition and its masks/shifts need to be accessible to 509266423Sjfv * application, core driver, and shared code. Where is the right file? 510266423Sjfv */ 511266423Sjfv#define I40E_NVM_READ 0xB 512266423Sjfv#define I40E_NVM_WRITE 0xC 513266423Sjfv 514266423Sjfv#define I40E_NVM_MOD_PNT_MASK 0xFF 515266423Sjfv 516333343Serj#define I40E_NVM_TRANS_SHIFT 8 517333343Serj#define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT) 518333343Serj#define I40E_NVM_PRESERVATION_FLAGS_SHIFT 12 519333343Serj#define I40E_NVM_PRESERVATION_FLAGS_MASK \ 520333343Serj (0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT) 521333343Serj#define I40E_NVM_PRESERVATION_FLAGS_SELECTED 0x01 522333343Serj#define I40E_NVM_PRESERVATION_FLAGS_ALL 0x02 523333343Serj#define I40E_NVM_CON 0x0 524333343Serj#define I40E_NVM_SNT 0x1 525333343Serj#define I40E_NVM_LCB 0x2 526333343Serj#define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB) 527333343Serj#define I40E_NVM_ERA 0x4 528333343Serj#define I40E_NVM_CSUM 0x8 529333343Serj#define I40E_NVM_AQE 0xe 530333343Serj#define I40E_NVM_EXEC 0xf 531266423Sjfv 532349163Serj#define I40E_NVM_EXEC_GET_AQ_RESULT 0x0 533349163Serj#define I40E_NVM_EXEC_FEATURES 0xe 534349163Serj#define I40E_NVM_EXEC_STATUS 0xf 535349163Serj 536266423Sjfv#define I40E_NVM_ADAPT_SHIFT 16 537266423Sjfv#define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT) 538266423Sjfv 539266423Sjfv#define I40E_NVMUPD_MAX_DATA 4096 540266423Sjfv#define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */ 541266423Sjfv 542266423Sjfvstruct i40e_nvm_access { 543266423Sjfv u32 command; 544266423Sjfv u32 config; 545266423Sjfv u32 offset; /* in bytes */ 546266423Sjfv u32 data_size; /* in bytes */ 547266423Sjfv u8 data[1]; 548266423Sjfv}; 549266423Sjfv 550349163Serj/* NVMUpdate features API */ 551349163Serj#define I40E_NVMUPD_FEATURES_API_VER_MAJOR 0 552349163Serj#define I40E_NVMUPD_FEATURES_API_VER_MINOR 14 553349163Serj#define I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN 12 554349163Serj 555349163Serj#define I40E_NVMUPD_FEATURE_FLAT_NVM_SUPPORT BIT(0) 556349163Serj 557349163Serjstruct i40e_nvmupd_features { 558349163Serj u8 major; 559349163Serj u8 minor; 560349163Serj u16 size; 561349163Serj u8 features[I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN]; 562349163Serj}; 563349163Serj 564333343Serj/* (Q)SFP module access definitions */ 565333343Serj#define I40E_I2C_EEPROM_DEV_ADDR 0xA0 566333343Serj#define I40E_I2C_EEPROM_DEV_ADDR2 0xA2 567333343Serj#define I40E_MODULE_TYPE_ADDR 0x00 568333343Serj#define I40E_MODULE_REVISION_ADDR 0x01 569333343Serj#define I40E_MODULE_SFF_8472_COMP 0x5E 570333343Serj#define I40E_MODULE_SFF_8472_SWAP 0x5C 571333343Serj#define I40E_MODULE_SFF_ADDR_MODE 0x04 572333343Serj#define I40E_MODULE_SFF_DIAG_CAPAB 0x40 573333343Serj#define I40E_MODULE_TYPE_QSFP_PLUS 0x0D 574333343Serj#define I40E_MODULE_TYPE_QSFP28 0x11 575333343Serj#define I40E_MODULE_QSFP_MAX_LEN 640 576333343Serj 577266423Sjfv/* PCI bus types */ 578266423Sjfvenum i40e_bus_type { 579266423Sjfv i40e_bus_type_unknown = 0, 580266423Sjfv i40e_bus_type_pci, 581266423Sjfv i40e_bus_type_pcix, 582266423Sjfv i40e_bus_type_pci_express, 583266423Sjfv i40e_bus_type_reserved 584266423Sjfv}; 585266423Sjfv 586266423Sjfv/* PCI bus speeds */ 587266423Sjfvenum i40e_bus_speed { 588266423Sjfv i40e_bus_speed_unknown = 0, 589266423Sjfv i40e_bus_speed_33 = 33, 590266423Sjfv i40e_bus_speed_66 = 66, 591266423Sjfv i40e_bus_speed_100 = 100, 592266423Sjfv i40e_bus_speed_120 = 120, 593266423Sjfv i40e_bus_speed_133 = 133, 594266423Sjfv i40e_bus_speed_2500 = 2500, 595266423Sjfv i40e_bus_speed_5000 = 5000, 596266423Sjfv i40e_bus_speed_8000 = 8000, 597266423Sjfv i40e_bus_speed_reserved 598266423Sjfv}; 599266423Sjfv 600266423Sjfv/* PCI bus widths */ 601266423Sjfvenum i40e_bus_width { 602266423Sjfv i40e_bus_width_unknown = 0, 603266423Sjfv i40e_bus_width_pcie_x1 = 1, 604266423Sjfv i40e_bus_width_pcie_x2 = 2, 605266423Sjfv i40e_bus_width_pcie_x4 = 4, 606266423Sjfv i40e_bus_width_pcie_x8 = 8, 607266423Sjfv i40e_bus_width_32 = 32, 608266423Sjfv i40e_bus_width_64 = 64, 609266423Sjfv i40e_bus_width_reserved 610266423Sjfv}; 611266423Sjfv 612266423Sjfv/* Bus parameters */ 613266423Sjfvstruct i40e_bus_info { 614266423Sjfv enum i40e_bus_speed speed; 615266423Sjfv enum i40e_bus_width width; 616266423Sjfv enum i40e_bus_type type; 617266423Sjfv 618266423Sjfv u16 func; 619266423Sjfv u16 device; 620266423Sjfv u16 lan_id; 621318357Serj u16 bus_id; 622266423Sjfv}; 623266423Sjfv 624266423Sjfv/* Flow control (FC) parameters */ 625266423Sjfvstruct i40e_fc_info { 626266423Sjfv enum i40e_fc_mode current_mode; /* FC mode in effect */ 627266423Sjfv enum i40e_fc_mode requested_mode; /* FC mode requested by caller */ 628266423Sjfv}; 629266423Sjfv 630266423Sjfv#define I40E_MAX_TRAFFIC_CLASS 8 631266423Sjfv#define I40E_MAX_USER_PRIORITY 8 632266423Sjfv#define I40E_DCBX_MAX_APPS 32 633266423Sjfv#define I40E_LLDPDU_SIZE 1500 634277082Sjfv#define I40E_TLV_STATUS_OPER 0x1 635277082Sjfv#define I40E_TLV_STATUS_SYNC 0x2 636277082Sjfv#define I40E_TLV_STATUS_ERR 0x4 637277082Sjfv#define I40E_CEE_OPER_MAX_APPS 3 638277082Sjfv#define I40E_APP_PROTOID_FCOE 0x8906 639277082Sjfv#define I40E_APP_PROTOID_ISCSI 0x0cbc 640277082Sjfv#define I40E_APP_PROTOID_FIP 0x8914 641277082Sjfv#define I40E_APP_SEL_ETHTYPE 0x1 642277082Sjfv#define I40E_APP_SEL_TCPIP 0x2 643284049Sjfv#define I40E_CEE_APP_SEL_ETHTYPE 0x0 644284049Sjfv#define I40E_CEE_APP_SEL_TCPIP 0x1 645266423Sjfv 646277082Sjfv/* CEE or IEEE 802.1Qaz ETS Configuration data */ 647277082Sjfvstruct i40e_dcb_ets_config { 648266423Sjfv u8 willing; 649266423Sjfv u8 cbs; 650266423Sjfv u8 maxtcs; 651266423Sjfv u8 prioritytable[I40E_MAX_TRAFFIC_CLASS]; 652266423Sjfv u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS]; 653266423Sjfv u8 tsatable[I40E_MAX_TRAFFIC_CLASS]; 654266423Sjfv}; 655266423Sjfv 656277082Sjfv/* CEE or IEEE 802.1Qaz PFC Configuration data */ 657277082Sjfvstruct i40e_dcb_pfc_config { 658266423Sjfv u8 willing; 659266423Sjfv u8 mbc; 660266423Sjfv u8 pfccap; 661266423Sjfv u8 pfcenable; 662266423Sjfv}; 663266423Sjfv 664277082Sjfv/* CEE or IEEE 802.1Qaz Application Priority data */ 665277082Sjfvstruct i40e_dcb_app_priority_table { 666266423Sjfv u8 priority; 667266423Sjfv u8 selector; 668266423Sjfv u16 protocolid; 669266423Sjfv}; 670266423Sjfv 671266423Sjfvstruct i40e_dcbx_config { 672277082Sjfv u8 dcbx_mode; 673277082Sjfv#define I40E_DCBX_MODE_CEE 0x1 674277082Sjfv#define I40E_DCBX_MODE_IEEE 0x2 675299545Serj u8 app_mode; 676299545Serj#define I40E_DCBX_APPS_NON_WILLING 0x1 677266423Sjfv u32 numapps; 678284049Sjfv u32 tlv_status; /* CEE mode TLV status */ 679277082Sjfv struct i40e_dcb_ets_config etscfg; 680277082Sjfv struct i40e_dcb_ets_config etsrec; 681277082Sjfv struct i40e_dcb_pfc_config pfc; 682277082Sjfv struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS]; 683266423Sjfv}; 684266423Sjfv 685266423Sjfv/* Port hardware description */ 686266423Sjfvstruct i40e_hw { 687266423Sjfv u8 *hw_addr; 688266423Sjfv void *back; 689266423Sjfv 690277082Sjfv /* subsystem structs */ 691266423Sjfv struct i40e_phy_info phy; 692266423Sjfv struct i40e_mac_info mac; 693266423Sjfv struct i40e_bus_info bus; 694266423Sjfv struct i40e_nvm_info nvm; 695266423Sjfv struct i40e_fc_info fc; 696266423Sjfv 697266423Sjfv /* pci info */ 698266423Sjfv u16 device_id; 699266423Sjfv u16 vendor_id; 700266423Sjfv u16 subsystem_device_id; 701266423Sjfv u16 subsystem_vendor_id; 702266423Sjfv u8 revision_id; 703266423Sjfv u8 port; 704266423Sjfv bool adapter_stopped; 705266423Sjfv 706266423Sjfv /* capabilities for entire device and PCI func */ 707266423Sjfv struct i40e_hw_capabilities dev_caps; 708266423Sjfv struct i40e_hw_capabilities func_caps; 709266423Sjfv 710266423Sjfv /* Flow Director shared filter space */ 711266423Sjfv u16 fdir_shared_filter_count; 712266423Sjfv 713266423Sjfv /* device profile info */ 714266423Sjfv u8 pf_id; 715266423Sjfv u16 main_vsi_seid; 716266423Sjfv 717277082Sjfv /* for multi-function MACs */ 718277082Sjfv u16 partition_id; 719277082Sjfv u16 num_partitions; 720277082Sjfv u16 num_ports; 721277082Sjfv 722266423Sjfv /* Closest numa node to the device */ 723266423Sjfv u16 numa_node; 724266423Sjfv 725266423Sjfv /* Admin Queue info */ 726266423Sjfv struct i40e_adminq_info aq; 727266423Sjfv 728266423Sjfv /* state of nvm update process */ 729266423Sjfv enum i40e_nvmupd_state nvmupd_state; 730284049Sjfv struct i40e_aq_desc nvm_wb_desc; 731333343Serj struct i40e_aq_desc nvm_aq_event_desc; 732284049Sjfv struct i40e_virt_mem nvm_buff; 733303967Ssbruno bool nvm_release_on_done; 734303967Ssbruno u16 nvm_wait_opcode; 735266423Sjfv 736266423Sjfv /* HMC info */ 737266423Sjfv struct i40e_hmc_info hmc; /* HMC info struct */ 738266423Sjfv 739266423Sjfv /* LLDP/DCBX Status */ 740266423Sjfv u16 dcbx_status; 741266423Sjfv 742266423Sjfv /* DCBX info */ 743284049Sjfv struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */ 744284049Sjfv struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */ 745284049Sjfv struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */ 746266423Sjfv 747303967Ssbruno /* WoL and proxy support */ 748303967Ssbruno u16 num_wol_proxy_filters; 749303967Ssbruno u16 wol_proxy_vsi_seid; 750303967Ssbruno 751299547Serj#define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0) 752333343Serj#define I40E_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1) 753333343Serj#define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2) 754333343Serj#define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3) 755349163Serj#define I40E_HW_FLAG_FW_LLDP_STOPPABLE BIT_ULL(4) 756349163Serj#define I40E_HW_FLAG_FW_LLDP_PERSISTENT BIT_ULL(5) 757299547Serj u64 flags; 758299547Serj 759333343Serj /* Used in set switch config AQ command */ 760333343Serj u16 switch_tag; 761333343Serj u16 first_tag; 762333343Serj u16 second_tag; 763333343Serj 764349163Serj /* NVMUpdate features */ 765349163Serj struct i40e_nvmupd_features nvmupd_features; 766349163Serj 767266423Sjfv /* debug mask */ 768266423Sjfv u32 debug_mask; 769284049Sjfv char err_str[16]; 770266423Sjfv}; 771266423Sjfv 772284049Sjfvstatic INLINE bool i40e_is_vf(struct i40e_hw *hw) 773279033Sjfv{ 774303967Ssbruno return (hw->mac.type == I40E_MAC_VF || 775303967Ssbruno hw->mac.type == I40E_MAC_X722_VF); 776279033Sjfv} 777279033Sjfv 778266423Sjfvstruct i40e_driver_version { 779266423Sjfv u8 major_version; 780266423Sjfv u8 minor_version; 781266423Sjfv u8 build_version; 782266423Sjfv u8 subbuild_version; 783266423Sjfv u8 driver_string[32]; 784266423Sjfv}; 785266423Sjfv 786266423Sjfv/* RX Descriptors */ 787266423Sjfvunion i40e_16byte_rx_desc { 788266423Sjfv struct { 789266423Sjfv __le64 pkt_addr; /* Packet buffer address */ 790266423Sjfv __le64 hdr_addr; /* Header buffer address */ 791266423Sjfv } read; 792266423Sjfv struct { 793266423Sjfv struct { 794266423Sjfv struct { 795266423Sjfv union { 796266423Sjfv __le16 mirroring_status; 797266423Sjfv __le16 fcoe_ctx_id; 798266423Sjfv } mirr_fcoe; 799266423Sjfv __le16 l2tag1; 800266423Sjfv } lo_dword; 801266423Sjfv union { 802266423Sjfv __le32 rss; /* RSS Hash */ 803266423Sjfv __le32 fd_id; /* Flow director filter id */ 804266423Sjfv __le32 fcoe_param; /* FCoE DDP Context id */ 805266423Sjfv } hi_dword; 806266423Sjfv } qword0; 807266423Sjfv struct { 808266423Sjfv /* ext status/error/pktype/length */ 809266423Sjfv __le64 status_error_len; 810266423Sjfv } qword1; 811266423Sjfv } wb; /* writeback */ 812266423Sjfv}; 813266423Sjfv 814266423Sjfvunion i40e_32byte_rx_desc { 815266423Sjfv struct { 816266423Sjfv __le64 pkt_addr; /* Packet buffer address */ 817266423Sjfv __le64 hdr_addr; /* Header buffer address */ 818266423Sjfv /* bit 0 of hdr_buffer_addr is DD bit */ 819266423Sjfv __le64 rsvd1; 820266423Sjfv __le64 rsvd2; 821266423Sjfv } read; 822266423Sjfv struct { 823266423Sjfv struct { 824266423Sjfv struct { 825266423Sjfv union { 826266423Sjfv __le16 mirroring_status; 827266423Sjfv __le16 fcoe_ctx_id; 828266423Sjfv } mirr_fcoe; 829266423Sjfv __le16 l2tag1; 830266423Sjfv } lo_dword; 831266423Sjfv union { 832266423Sjfv __le32 rss; /* RSS Hash */ 833266423Sjfv __le32 fcoe_param; /* FCoE DDP Context id */ 834266423Sjfv /* Flow director filter id in case of 835266423Sjfv * Programming status desc WB 836266423Sjfv */ 837266423Sjfv __le32 fd_id; 838266423Sjfv } hi_dword; 839266423Sjfv } qword0; 840266423Sjfv struct { 841266423Sjfv /* status/error/pktype/length */ 842266423Sjfv __le64 status_error_len; 843266423Sjfv } qword1; 844266423Sjfv struct { 845266423Sjfv __le16 ext_status; /* extended status */ 846266423Sjfv __le16 rsvd; 847266423Sjfv __le16 l2tag2_1; 848266423Sjfv __le16 l2tag2_2; 849266423Sjfv } qword2; 850266423Sjfv struct { 851266423Sjfv union { 852266423Sjfv __le32 flex_bytes_lo; 853266423Sjfv __le32 pe_status; 854266423Sjfv } lo_dword; 855266423Sjfv union { 856266423Sjfv __le32 flex_bytes_hi; 857266423Sjfv __le32 fd_id; 858266423Sjfv } hi_dword; 859266423Sjfv } qword3; 860266423Sjfv } wb; /* writeback */ 861266423Sjfv}; 862266423Sjfv 863266423Sjfv#define I40E_RXD_QW0_MIRROR_STATUS_SHIFT 8 864266423Sjfv#define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \ 865266423Sjfv I40E_RXD_QW0_MIRROR_STATUS_SHIFT) 866266423Sjfv#define I40E_RXD_QW0_FCOEINDX_SHIFT 0 867266423Sjfv#define I40E_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \ 868266423Sjfv I40E_RXD_QW0_FCOEINDX_SHIFT) 869266423Sjfv 870266423Sjfvenum i40e_rx_desc_status_bits { 871266423Sjfv /* Note: These are predefined bit offsets */ 872266423Sjfv I40E_RX_DESC_STATUS_DD_SHIFT = 0, 873266423Sjfv I40E_RX_DESC_STATUS_EOF_SHIFT = 1, 874266423Sjfv I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2, 875266423Sjfv I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3, 876266423Sjfv I40E_RX_DESC_STATUS_CRCP_SHIFT = 4, 877266423Sjfv I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */ 878266423Sjfv I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7, 879303967Ssbruno I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8, 880277082Sjfv 881266423Sjfv I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */ 882266423Sjfv I40E_RX_DESC_STATUS_FLM_SHIFT = 11, 883266423Sjfv I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */ 884266423Sjfv I40E_RX_DESC_STATUS_LPBK_SHIFT = 14, 885266423Sjfv I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15, 886277082Sjfv I40E_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */ 887303967Ssbruno I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18, 888266423Sjfv I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */ 889266423Sjfv}; 890266423Sjfv 891266423Sjfv#define I40E_RXD_QW1_STATUS_SHIFT 0 892284049Sjfv#define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \ 893266423Sjfv I40E_RXD_QW1_STATUS_SHIFT) 894266423Sjfv 895266423Sjfv#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT 896266423Sjfv#define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \ 897266423Sjfv I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT) 898266423Sjfv 899266423Sjfv#define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT 900284049Sjfv#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT) 901266423Sjfv 902266423Sjfv#define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT I40E_RX_DESC_STATUS_UMBCAST 903266423Sjfv#define I40E_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \ 904266423Sjfv I40E_RXD_QW1_STATUS_UMBCAST_SHIFT) 905266423Sjfv 906266423Sjfvenum i40e_rx_desc_fltstat_values { 907266423Sjfv I40E_RX_DESC_FLTSTAT_NO_DATA = 0, 908266423Sjfv I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */ 909266423Sjfv I40E_RX_DESC_FLTSTAT_RSV = 2, 910266423Sjfv I40E_RX_DESC_FLTSTAT_RSS_HASH = 3, 911266423Sjfv}; 912266423Sjfv 913266423Sjfv#define I40E_RXD_PACKET_TYPE_UNICAST 0 914266423Sjfv#define I40E_RXD_PACKET_TYPE_MULTICAST 1 915266423Sjfv#define I40E_RXD_PACKET_TYPE_BROADCAST 2 916266423Sjfv#define I40E_RXD_PACKET_TYPE_MIRRORED 3 917266423Sjfv 918266423Sjfv#define I40E_RXD_QW1_ERROR_SHIFT 19 919266423Sjfv#define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT) 920266423Sjfv 921266423Sjfvenum i40e_rx_desc_error_bits { 922266423Sjfv /* Note: These are predefined bit offsets */ 923266423Sjfv I40E_RX_DESC_ERROR_RXE_SHIFT = 0, 924266423Sjfv I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1, 925266423Sjfv I40E_RX_DESC_ERROR_HBO_SHIFT = 2, 926266423Sjfv I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */ 927266423Sjfv I40E_RX_DESC_ERROR_IPE_SHIFT = 3, 928266423Sjfv I40E_RX_DESC_ERROR_L4E_SHIFT = 4, 929266423Sjfv I40E_RX_DESC_ERROR_EIPE_SHIFT = 5, 930266423Sjfv I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6, 931266423Sjfv I40E_RX_DESC_ERROR_PPRS_SHIFT = 7 932266423Sjfv}; 933266423Sjfv 934266423Sjfvenum i40e_rx_desc_error_l3l4e_fcoe_masks { 935266423Sjfv I40E_RX_DESC_ERROR_L3L4E_NONE = 0, 936266423Sjfv I40E_RX_DESC_ERROR_L3L4E_PROT = 1, 937266423Sjfv I40E_RX_DESC_ERROR_L3L4E_FC = 2, 938266423Sjfv I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3, 939266423Sjfv I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4 940266423Sjfv}; 941266423Sjfv 942266423Sjfv#define I40E_RXD_QW1_PTYPE_SHIFT 30 943266423Sjfv#define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT) 944266423Sjfv 945266423Sjfv/* Packet type non-ip values */ 946266423Sjfvenum i40e_rx_l2_ptype { 947266423Sjfv I40E_RX_PTYPE_L2_RESERVED = 0, 948266423Sjfv I40E_RX_PTYPE_L2_MAC_PAY2 = 1, 949266423Sjfv I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2, 950266423Sjfv I40E_RX_PTYPE_L2_FIP_PAY2 = 3, 951266423Sjfv I40E_RX_PTYPE_L2_OUI_PAY2 = 4, 952266423Sjfv I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5, 953266423Sjfv I40E_RX_PTYPE_L2_LLDP_PAY2 = 6, 954266423Sjfv I40E_RX_PTYPE_L2_ECP_PAY2 = 7, 955266423Sjfv I40E_RX_PTYPE_L2_EVB_PAY2 = 8, 956266423Sjfv I40E_RX_PTYPE_L2_QCN_PAY2 = 9, 957266423Sjfv I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10, 958266423Sjfv I40E_RX_PTYPE_L2_ARP = 11, 959266423Sjfv I40E_RX_PTYPE_L2_FCOE_PAY3 = 12, 960266423Sjfv I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13, 961266423Sjfv I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14, 962266423Sjfv I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15, 963266423Sjfv I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16, 964266423Sjfv I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17, 965266423Sjfv I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18, 966266423Sjfv I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19, 967266423Sjfv I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20, 968266423Sjfv I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21, 969266423Sjfv I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58, 970266423Sjfv I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87, 971266423Sjfv I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124, 972266423Sjfv I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153 973266423Sjfv}; 974266423Sjfv 975266423Sjfvstruct i40e_rx_ptype_decoded { 976266423Sjfv u32 ptype:8; 977266423Sjfv u32 known:1; 978266423Sjfv u32 outer_ip:1; 979266423Sjfv u32 outer_ip_ver:1; 980266423Sjfv u32 outer_frag:1; 981266423Sjfv u32 tunnel_type:3; 982266423Sjfv u32 tunnel_end_prot:2; 983266423Sjfv u32 tunnel_end_frag:1; 984266423Sjfv u32 inner_prot:4; 985266423Sjfv u32 payload_layer:3; 986266423Sjfv}; 987266423Sjfv 988266423Sjfvenum i40e_rx_ptype_outer_ip { 989266423Sjfv I40E_RX_PTYPE_OUTER_L2 = 0, 990266423Sjfv I40E_RX_PTYPE_OUTER_IP = 1 991266423Sjfv}; 992266423Sjfv 993266423Sjfvenum i40e_rx_ptype_outer_ip_ver { 994266423Sjfv I40E_RX_PTYPE_OUTER_NONE = 0, 995266423Sjfv I40E_RX_PTYPE_OUTER_IPV4 = 0, 996266423Sjfv I40E_RX_PTYPE_OUTER_IPV6 = 1 997266423Sjfv}; 998266423Sjfv 999266423Sjfvenum i40e_rx_ptype_outer_fragmented { 1000266423Sjfv I40E_RX_PTYPE_NOT_FRAG = 0, 1001266423Sjfv I40E_RX_PTYPE_FRAG = 1 1002266423Sjfv}; 1003266423Sjfv 1004266423Sjfvenum i40e_rx_ptype_tunnel_type { 1005266423Sjfv I40E_RX_PTYPE_TUNNEL_NONE = 0, 1006266423Sjfv I40E_RX_PTYPE_TUNNEL_IP_IP = 1, 1007266423Sjfv I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2, 1008266423Sjfv I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3, 1009266423Sjfv I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4, 1010266423Sjfv}; 1011266423Sjfv 1012266423Sjfvenum i40e_rx_ptype_tunnel_end_prot { 1013266423Sjfv I40E_RX_PTYPE_TUNNEL_END_NONE = 0, 1014266423Sjfv I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1, 1015266423Sjfv I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2, 1016266423Sjfv}; 1017266423Sjfv 1018266423Sjfvenum i40e_rx_ptype_inner_prot { 1019266423Sjfv I40E_RX_PTYPE_INNER_PROT_NONE = 0, 1020266423Sjfv I40E_RX_PTYPE_INNER_PROT_UDP = 1, 1021266423Sjfv I40E_RX_PTYPE_INNER_PROT_TCP = 2, 1022266423Sjfv I40E_RX_PTYPE_INNER_PROT_SCTP = 3, 1023266423Sjfv I40E_RX_PTYPE_INNER_PROT_ICMP = 4, 1024266423Sjfv I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5 1025266423Sjfv}; 1026266423Sjfv 1027266423Sjfvenum i40e_rx_ptype_payload_layer { 1028266423Sjfv I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0, 1029266423Sjfv I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1, 1030266423Sjfv I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2, 1031266423Sjfv I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3, 1032266423Sjfv}; 1033266423Sjfv 1034266423Sjfv#define I40E_RX_PTYPE_BIT_MASK 0x0FFFFFFF 1035266423Sjfv#define I40E_RX_PTYPE_SHIFT 56 1036266423Sjfv 1037266423Sjfv#define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38 1038266423Sjfv#define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \ 1039266423Sjfv I40E_RXD_QW1_LENGTH_PBUF_SHIFT) 1040266423Sjfv 1041266423Sjfv#define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52 1042266423Sjfv#define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \ 1043266423Sjfv I40E_RXD_QW1_LENGTH_HBUF_SHIFT) 1044266423Sjfv 1045266423Sjfv#define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63 1046284049Sjfv#define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT) 1047266423Sjfv 1048266423Sjfv#define I40E_RXD_QW1_NEXTP_SHIFT 38 1049266423Sjfv#define I40E_RXD_QW1_NEXTP_MASK (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT) 1050266423Sjfv 1051266423Sjfv#define I40E_RXD_QW2_EXT_STATUS_SHIFT 0 1052266423Sjfv#define I40E_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \ 1053266423Sjfv I40E_RXD_QW2_EXT_STATUS_SHIFT) 1054266423Sjfv 1055266423Sjfvenum i40e_rx_desc_ext_status_bits { 1056266423Sjfv /* Note: These are predefined bit offsets */ 1057266423Sjfv I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0, 1058266423Sjfv I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1, 1059266423Sjfv I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */ 1060266423Sjfv I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */ 1061266423Sjfv I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9, 1062266423Sjfv I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10, 1063266423Sjfv I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11, 1064266423Sjfv}; 1065266423Sjfv 1066266423Sjfv#define I40E_RXD_QW2_L2TAG2_SHIFT 0 1067266423Sjfv#define I40E_RXD_QW2_L2TAG2_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT) 1068266423Sjfv 1069266423Sjfv#define I40E_RXD_QW2_L2TAG3_SHIFT 16 1070266423Sjfv#define I40E_RXD_QW2_L2TAG3_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT) 1071266423Sjfv 1072266423Sjfvenum i40e_rx_desc_pe_status_bits { 1073266423Sjfv /* Note: These are predefined bit offsets */ 1074266423Sjfv I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */ 1075266423Sjfv I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */ 1076266423Sjfv I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */ 1077266423Sjfv I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24, 1078266423Sjfv I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25, 1079266423Sjfv I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26, 1080266423Sjfv I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27, 1081266423Sjfv I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28, 1082266423Sjfv I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29 1083266423Sjfv}; 1084266423Sjfv 1085266423Sjfv#define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38 1086266423Sjfv#define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000 1087266423Sjfv 1088266423Sjfv#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2 1089266423Sjfv#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \ 1090266423Sjfv I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT) 1091266423Sjfv 1092266423Sjfv#define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0 1093266423Sjfv#define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \ 1094266423Sjfv I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT) 1095266423Sjfv 1096266423Sjfv#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19 1097266423Sjfv#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \ 1098266423Sjfv I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT) 1099266423Sjfv 1100266423Sjfvenum i40e_rx_prog_status_desc_status_bits { 1101266423Sjfv /* Note: These are predefined bit offsets */ 1102266423Sjfv I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0, 1103266423Sjfv I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */ 1104266423Sjfv}; 1105266423Sjfv 1106266423Sjfvenum i40e_rx_prog_status_desc_prog_id_masks { 1107266423Sjfv I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1, 1108266423Sjfv I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2, 1109266423Sjfv I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4, 1110266423Sjfv}; 1111266423Sjfv 1112266423Sjfvenum i40e_rx_prog_status_desc_error_bits { 1113266423Sjfv /* Note: These are predefined bit offsets */ 1114266423Sjfv I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0, 1115266423Sjfv I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1, 1116266423Sjfv I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2, 1117266423Sjfv I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3 1118266423Sjfv}; 1119266423Sjfv 1120266423Sjfv#define I40E_TWO_BIT_MASK 0x3 1121266423Sjfv#define I40E_THREE_BIT_MASK 0x7 1122266423Sjfv#define I40E_FOUR_BIT_MASK 0xF 1123266423Sjfv#define I40E_EIGHTEEN_BIT_MASK 0x3FFFF 1124266423Sjfv 1125266423Sjfv/* TX Descriptor */ 1126266423Sjfvstruct i40e_tx_desc { 1127266423Sjfv __le64 buffer_addr; /* Address of descriptor's data buf */ 1128266423Sjfv __le64 cmd_type_offset_bsz; 1129266423Sjfv}; 1130266423Sjfv 1131266423Sjfv#define I40E_TXD_QW1_DTYPE_SHIFT 0 1132266423Sjfv#define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT) 1133266423Sjfv 1134266423Sjfvenum i40e_tx_desc_dtype_value { 1135266423Sjfv I40E_TX_DESC_DTYPE_DATA = 0x0, 1136266423Sjfv I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */ 1137266423Sjfv I40E_TX_DESC_DTYPE_CONTEXT = 0x1, 1138266423Sjfv I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2, 1139266423Sjfv I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8, 1140266423Sjfv I40E_TX_DESC_DTYPE_DDP_CTX = 0x9, 1141266423Sjfv I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB, 1142266423Sjfv I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC, 1143266423Sjfv I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD, 1144266423Sjfv I40E_TX_DESC_DTYPE_DESC_DONE = 0xF 1145266423Sjfv}; 1146266423Sjfv 1147266423Sjfv#define I40E_TXD_QW1_CMD_SHIFT 4 1148266423Sjfv#define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT) 1149266423Sjfv 1150266423Sjfvenum i40e_tx_desc_cmd_bits { 1151266423Sjfv I40E_TX_DESC_CMD_EOP = 0x0001, 1152266423Sjfv I40E_TX_DESC_CMD_RS = 0x0002, 1153266423Sjfv I40E_TX_DESC_CMD_ICRC = 0x0004, 1154266423Sjfv I40E_TX_DESC_CMD_IL2TAG1 = 0x0008, 1155266423Sjfv I40E_TX_DESC_CMD_DUMMY = 0x0010, 1156266423Sjfv I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */ 1157266423Sjfv I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */ 1158266423Sjfv I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */ 1159266423Sjfv I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */ 1160266423Sjfv I40E_TX_DESC_CMD_FCOET = 0x0080, 1161266423Sjfv I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */ 1162266423Sjfv I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */ 1163266423Sjfv I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */ 1164266423Sjfv I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */ 1165266423Sjfv I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */ 1166266423Sjfv I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */ 1167266423Sjfv I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */ 1168266423Sjfv I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */ 1169266423Sjfv}; 1170266423Sjfv 1171266423Sjfv#define I40E_TXD_QW1_OFFSET_SHIFT 16 1172266423Sjfv#define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \ 1173266423Sjfv I40E_TXD_QW1_OFFSET_SHIFT) 1174266423Sjfv 1175266423Sjfvenum i40e_tx_desc_length_fields { 1176266423Sjfv /* Note: These are predefined bit offsets */ 1177266423Sjfv I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */ 1178266423Sjfv I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */ 1179266423Sjfv I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */ 1180266423Sjfv}; 1181266423Sjfv 1182266423Sjfv#define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT) 1183266423Sjfv#define I40E_TXD_QW1_IPLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT) 1184266423Sjfv#define I40E_TXD_QW1_L4LEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT) 1185266423Sjfv#define I40E_TXD_QW1_FCLEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT) 1186266423Sjfv 1187266423Sjfv#define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34 1188266423Sjfv#define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \ 1189266423Sjfv I40E_TXD_QW1_TX_BUF_SZ_SHIFT) 1190266423Sjfv 1191266423Sjfv#define I40E_TXD_QW1_L2TAG1_SHIFT 48 1192266423Sjfv#define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT) 1193266423Sjfv 1194266423Sjfv/* Context descriptors */ 1195266423Sjfvstruct i40e_tx_context_desc { 1196266423Sjfv __le32 tunneling_params; 1197266423Sjfv __le16 l2tag2; 1198266423Sjfv __le16 rsvd; 1199266423Sjfv __le64 type_cmd_tso_mss; 1200266423Sjfv}; 1201266423Sjfv 1202266423Sjfv#define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0 1203266423Sjfv#define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT) 1204266423Sjfv 1205266423Sjfv#define I40E_TXD_CTX_QW1_CMD_SHIFT 4 1206266423Sjfv#define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT) 1207266423Sjfv 1208266423Sjfvenum i40e_tx_ctx_desc_cmd_bits { 1209266423Sjfv I40E_TX_CTX_DESC_TSO = 0x01, 1210266423Sjfv I40E_TX_CTX_DESC_TSYN = 0x02, 1211266423Sjfv I40E_TX_CTX_DESC_IL2TAG2 = 0x04, 1212266423Sjfv I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08, 1213266423Sjfv I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00, 1214266423Sjfv I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10, 1215266423Sjfv I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20, 1216266423Sjfv I40E_TX_CTX_DESC_SWTCH_VSI = 0x30, 1217266423Sjfv I40E_TX_CTX_DESC_SWPE = 0x40 1218266423Sjfv}; 1219266423Sjfv 1220266423Sjfv#define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30 1221266423Sjfv#define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \ 1222266423Sjfv I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) 1223266423Sjfv 1224266423Sjfv#define I40E_TXD_CTX_QW1_MSS_SHIFT 50 1225266423Sjfv#define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \ 1226266423Sjfv I40E_TXD_CTX_QW1_MSS_SHIFT) 1227266423Sjfv 1228266423Sjfv#define I40E_TXD_CTX_QW1_VSI_SHIFT 50 1229266423Sjfv#define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT) 1230266423Sjfv 1231266423Sjfv#define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0 1232266423Sjfv#define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \ 1233266423Sjfv I40E_TXD_CTX_QW0_EXT_IP_SHIFT) 1234266423Sjfv 1235266423Sjfvenum i40e_tx_ctx_desc_eipt_offload { 1236266423Sjfv I40E_TX_CTX_EXT_IP_NONE = 0x0, 1237266423Sjfv I40E_TX_CTX_EXT_IP_IPV6 = 0x1, 1238266423Sjfv I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2, 1239266423Sjfv I40E_TX_CTX_EXT_IP_IPV4 = 0x3 1240266423Sjfv}; 1241266423Sjfv 1242266423Sjfv#define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2 1243266423Sjfv#define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \ 1244266423Sjfv I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT) 1245266423Sjfv 1246266423Sjfv#define I40E_TXD_CTX_QW0_NATT_SHIFT 9 1247266423Sjfv#define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) 1248266423Sjfv 1249284049Sjfv#define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT) 1250266423Sjfv#define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) 1251266423Sjfv 1252266423Sjfv#define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11 1253284049Sjfv#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT) 1254266423Sjfv 1255266423Sjfv#define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK 1256266423Sjfv 1257266423Sjfv#define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12 1258266423Sjfv#define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \ 1259266423Sjfv I40E_TXD_CTX_QW0_NATLEN_SHIFT) 1260266423Sjfv 1261266423Sjfv#define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19 1262266423Sjfv#define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \ 1263266423Sjfv I40E_TXD_CTX_QW0_DECTTL_SHIFT) 1264266423Sjfv 1265303967Ssbruno#define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23 1266303967Ssbruno#define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT) 1267266423Sjfvstruct i40e_nop_desc { 1268266423Sjfv __le64 rsvd; 1269266423Sjfv __le64 dtype_cmd; 1270266423Sjfv}; 1271266423Sjfv 1272266423Sjfv#define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0 1273266423Sjfv#define I40E_TXD_NOP_QW1_DTYPE_MASK (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT) 1274266423Sjfv 1275266423Sjfv#define I40E_TXD_NOP_QW1_CMD_SHIFT 4 1276266423Sjfv#define I40E_TXD_NOP_QW1_CMD_MASK (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT) 1277266423Sjfv 1278266423Sjfvenum i40e_tx_nop_desc_cmd_bits { 1279266423Sjfv /* Note: These are predefined bit offsets */ 1280266423Sjfv I40E_TX_NOP_DESC_EOP_SHIFT = 0, 1281266423Sjfv I40E_TX_NOP_DESC_RS_SHIFT = 1, 1282266423Sjfv I40E_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */ 1283266423Sjfv}; 1284266423Sjfv 1285266423Sjfvstruct i40e_filter_program_desc { 1286266423Sjfv __le32 qindex_flex_ptype_vsi; 1287266423Sjfv __le32 rsvd; 1288266423Sjfv __le32 dtype_cmd_cntindex; 1289266423Sjfv __le32 fd_id; 1290266423Sjfv}; 1291266423Sjfv#define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0 1292266423Sjfv#define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \ 1293266423Sjfv I40E_TXD_FLTR_QW0_QINDEX_SHIFT) 1294266423Sjfv#define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11 1295266423Sjfv#define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \ 1296266423Sjfv I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) 1297266423Sjfv#define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17 1298266423Sjfv#define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \ 1299266423Sjfv I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) 1300266423Sjfv 1301266423Sjfv/* Packet Classifier Types for filters */ 1302266423Sjfvenum i40e_filter_pctype { 1303303967Ssbruno /* Note: Values 0-28 are reserved for future use. 1304303967Ssbruno * Value 29, 30, 32 are not supported on XL710 and X710. 1305303967Ssbruno */ 1306303967Ssbruno I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29, 1307303967Ssbruno I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30, 1308266423Sjfv I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31, 1309303967Ssbruno I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32, 1310266423Sjfv I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33, 1311266423Sjfv I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34, 1312266423Sjfv I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35, 1313266423Sjfv I40E_FILTER_PCTYPE_FRAG_IPV4 = 36, 1314303967Ssbruno /* Note: Values 37-38 are reserved for future use. 1315303967Ssbruno * Value 39, 40, 42 are not supported on XL710 and X710. 1316303967Ssbruno */ 1317303967Ssbruno I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39, 1318303967Ssbruno I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40, 1319266423Sjfv I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41, 1320303967Ssbruno I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42, 1321266423Sjfv I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43, 1322266423Sjfv I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44, 1323266423Sjfv I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45, 1324266423Sjfv I40E_FILTER_PCTYPE_FRAG_IPV6 = 46, 1325266423Sjfv /* Note: Value 47 is reserved for future use */ 1326266423Sjfv I40E_FILTER_PCTYPE_FCOE_OX = 48, 1327266423Sjfv I40E_FILTER_PCTYPE_FCOE_RX = 49, 1328266423Sjfv I40E_FILTER_PCTYPE_FCOE_OTHER = 50, 1329266423Sjfv /* Note: Values 51-62 are reserved for future use */ 1330266423Sjfv I40E_FILTER_PCTYPE_L2_PAYLOAD = 63, 1331266423Sjfv}; 1332266423Sjfv 1333266423Sjfvenum i40e_filter_program_desc_dest { 1334266423Sjfv I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0, 1335266423Sjfv I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1, 1336266423Sjfv I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2, 1337266423Sjfv}; 1338266423Sjfv 1339266423Sjfvenum i40e_filter_program_desc_fd_status { 1340266423Sjfv I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0, 1341266423Sjfv I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1, 1342266423Sjfv I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2, 1343266423Sjfv I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3, 1344266423Sjfv}; 1345266423Sjfv 1346266423Sjfv#define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23 1347299546Serj#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \ 1348299546Serj I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) 1349266423Sjfv 1350266423Sjfv#define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0 1351266423Sjfv#define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT) 1352266423Sjfv 1353266423Sjfv#define I40E_TXD_FLTR_QW1_CMD_SHIFT 4 1354266423Sjfv#define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \ 1355266423Sjfv I40E_TXD_FLTR_QW1_CMD_SHIFT) 1356266423Sjfv 1357266423Sjfv#define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 1358266423Sjfv#define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT) 1359266423Sjfv 1360266423Sjfvenum i40e_filter_program_desc_pcmd { 1361266423Sjfv I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1, 1362266423Sjfv I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2, 1363266423Sjfv}; 1364266423Sjfv 1365266423Sjfv#define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 1366266423Sjfv#define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT) 1367266423Sjfv 1368266423Sjfv#define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 1369284049Sjfv#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT) 1370266423Sjfv 1371266423Sjfv#define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \ 1372266423Sjfv I40E_TXD_FLTR_QW1_CMD_SHIFT) 1373266423Sjfv#define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \ 1374266423Sjfv I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) 1375266423Sjfv 1376303967Ssbruno#define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \ 1377303967Ssbruno I40E_TXD_FLTR_QW1_CMD_SHIFT) 1378303967Ssbruno#define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT) 1379303967Ssbruno 1380266423Sjfv#define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20 1381266423Sjfv#define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \ 1382266423Sjfv I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) 1383266423Sjfv 1384266423Sjfvenum i40e_filter_type { 1385266423Sjfv I40E_FLOW_DIRECTOR_FLTR = 0, 1386266423Sjfv I40E_PE_QUAD_HASH_FLTR = 1, 1387266423Sjfv I40E_ETHERTYPE_FLTR, 1388266423Sjfv I40E_FCOE_CTX_FLTR, 1389266423Sjfv I40E_MAC_VLAN_FLTR, 1390266423Sjfv I40E_HASH_FLTR 1391266423Sjfv}; 1392266423Sjfv 1393266423Sjfvstruct i40e_vsi_context { 1394266423Sjfv u16 seid; 1395266423Sjfv u16 uplink_seid; 1396266423Sjfv u16 vsi_number; 1397266423Sjfv u16 vsis_allocated; 1398266423Sjfv u16 vsis_unallocated; 1399266423Sjfv u16 flags; 1400266423Sjfv u8 pf_num; 1401266423Sjfv u8 vf_num; 1402266423Sjfv u8 connection_type; 1403266423Sjfv struct i40e_aqc_vsi_properties_data info; 1404266423Sjfv}; 1405266423Sjfv 1406266423Sjfvstruct i40e_veb_context { 1407266423Sjfv u16 seid; 1408266423Sjfv u16 uplink_seid; 1409266423Sjfv u16 veb_number; 1410266423Sjfv u16 vebs_allocated; 1411266423Sjfv u16 vebs_unallocated; 1412266423Sjfv u16 flags; 1413266423Sjfv struct i40e_aqc_get_veb_parameters_completion info; 1414266423Sjfv}; 1415266423Sjfv 1416266423Sjfv/* Statistics collected by each port, VSI, VEB, and S-channel */ 1417266423Sjfvstruct i40e_eth_stats { 1418266423Sjfv u64 rx_bytes; /* gorc */ 1419266423Sjfv u64 rx_unicast; /* uprc */ 1420266423Sjfv u64 rx_multicast; /* mprc */ 1421266423Sjfv u64 rx_broadcast; /* bprc */ 1422266423Sjfv u64 rx_discards; /* rdpc */ 1423266423Sjfv u64 rx_unknown_protocol; /* rupp */ 1424266423Sjfv u64 tx_bytes; /* gotc */ 1425266423Sjfv u64 tx_unicast; /* uptc */ 1426266423Sjfv u64 tx_multicast; /* mptc */ 1427266423Sjfv u64 tx_broadcast; /* bptc */ 1428266423Sjfv u64 tx_discards; /* tdpc */ 1429266423Sjfv u64 tx_errors; /* tepc */ 1430266423Sjfv}; 1431266423Sjfv 1432277082Sjfv/* Statistics collected per VEB per TC */ 1433277082Sjfvstruct i40e_veb_tc_stats { 1434277082Sjfv u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS]; 1435277082Sjfv u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS]; 1436277082Sjfv u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS]; 1437277082Sjfv u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS]; 1438277082Sjfv}; 1439277082Sjfv 1440266423Sjfv/* Statistics collected by the MAC */ 1441266423Sjfvstruct i40e_hw_port_stats { 1442266423Sjfv /* eth stats collected by the port */ 1443266423Sjfv struct i40e_eth_stats eth; 1444266423Sjfv 1445266423Sjfv /* additional port specific stats */ 1446266423Sjfv u64 tx_dropped_link_down; /* tdold */ 1447266423Sjfv u64 crc_errors; /* crcerrs */ 1448266423Sjfv u64 illegal_bytes; /* illerrc */ 1449266423Sjfv u64 error_bytes; /* errbc */ 1450266423Sjfv u64 mac_local_faults; /* mlfc */ 1451266423Sjfv u64 mac_remote_faults; /* mrfc */ 1452266423Sjfv u64 rx_length_errors; /* rlec */ 1453266423Sjfv u64 link_xon_rx; /* lxonrxc */ 1454266423Sjfv u64 link_xoff_rx; /* lxoffrxc */ 1455266423Sjfv u64 priority_xon_rx[8]; /* pxonrxc[8] */ 1456266423Sjfv u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 1457266423Sjfv u64 link_xon_tx; /* lxontxc */ 1458266423Sjfv u64 link_xoff_tx; /* lxofftxc */ 1459266423Sjfv u64 priority_xon_tx[8]; /* pxontxc[8] */ 1460266423Sjfv u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 1461266423Sjfv u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 1462266423Sjfv u64 rx_size_64; /* prc64 */ 1463266423Sjfv u64 rx_size_127; /* prc127 */ 1464266423Sjfv u64 rx_size_255; /* prc255 */ 1465266423Sjfv u64 rx_size_511; /* prc511 */ 1466266423Sjfv u64 rx_size_1023; /* prc1023 */ 1467266423Sjfv u64 rx_size_1522; /* prc1522 */ 1468266423Sjfv u64 rx_size_big; /* prc9522 */ 1469266423Sjfv u64 rx_undersize; /* ruc */ 1470266423Sjfv u64 rx_fragments; /* rfc */ 1471266423Sjfv u64 rx_oversize; /* roc */ 1472266423Sjfv u64 rx_jabber; /* rjc */ 1473266423Sjfv u64 tx_size_64; /* ptc64 */ 1474266423Sjfv u64 tx_size_127; /* ptc127 */ 1475266423Sjfv u64 tx_size_255; /* ptc255 */ 1476266423Sjfv u64 tx_size_511; /* ptc511 */ 1477266423Sjfv u64 tx_size_1023; /* ptc1023 */ 1478266423Sjfv u64 tx_size_1522; /* ptc1522 */ 1479266423Sjfv u64 tx_size_big; /* ptc9522 */ 1480266423Sjfv u64 mac_short_packet_dropped; /* mspdc */ 1481266423Sjfv u64 checksum_error; /* xec */ 1482266423Sjfv /* flow director stats */ 1483266423Sjfv u64 fd_atr_match; 1484266423Sjfv u64 fd_sb_match; 1485284049Sjfv u64 fd_atr_tunnel_match; 1486284049Sjfv u32 fd_atr_status; 1487284049Sjfv u32 fd_sb_status; 1488266423Sjfv /* EEE LPI */ 1489266423Sjfv u32 tx_lpi_status; 1490266423Sjfv u32 rx_lpi_status; 1491266423Sjfv u64 tx_lpi_count; /* etlpic */ 1492266423Sjfv u64 rx_lpi_count; /* erlpic */ 1493266423Sjfv}; 1494266423Sjfv 1495266423Sjfv/* Checksum and Shadow RAM pointers */ 1496266423Sjfv#define I40E_SR_NVM_CONTROL_WORD 0x00 1497266423Sjfv#define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03 1498266423Sjfv#define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04 1499266423Sjfv#define I40E_SR_OPTION_ROM_PTR 0x05 1500266423Sjfv#define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06 1501266423Sjfv#define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07 1502266423Sjfv#define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08 1503266423Sjfv#define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09 1504266423Sjfv#define I40E_SR_RO_PCIE_LCB_PTR 0x0A 1505266423Sjfv#define I40E_SR_EMP_IMAGE_PTR 0x0B 1506266423Sjfv#define I40E_SR_PE_IMAGE_PTR 0x0C 1507266423Sjfv#define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D 1508266423Sjfv#define I40E_SR_MNG_CONFIG_PTR 0x0E 1509333343Serj#define I40E_EMP_MODULE_PTR 0x0F 1510333343Serj#define I40E_SR_EMP_MODULE_PTR 0x48 1511277082Sjfv#define I40E_SR_PBA_FLAGS 0x15 1512266423Sjfv#define I40E_SR_PBA_BLOCK_PTR 0x16 1513266423Sjfv#define I40E_SR_BOOT_CONFIG_PTR 0x17 1514284049Sjfv#define I40E_NVM_OEM_VER_OFF 0x83 1515277082Sjfv#define I40E_SR_NVM_DEV_STARTER_VERSION 0x18 1516266423Sjfv#define I40E_SR_NVM_WAKE_ON_LAN 0x19 1517266423Sjfv#define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27 1518266423Sjfv#define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28 1519277082Sjfv#define I40E_SR_NVM_MAP_VERSION 0x29 1520277082Sjfv#define I40E_SR_NVM_IMAGE_VERSION 0x2A 1521277082Sjfv#define I40E_SR_NVM_STRUCTURE_VERSION 0x2B 1522266423Sjfv#define I40E_SR_NVM_EETRACK_LO 0x2D 1523266423Sjfv#define I40E_SR_NVM_EETRACK_HI 0x2E 1524266423Sjfv#define I40E_SR_VPD_PTR 0x2F 1525266423Sjfv#define I40E_SR_PXE_SETUP_PTR 0x30 1526266423Sjfv#define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31 1527277082Sjfv#define I40E_SR_NVM_ORIGINAL_EETRACK_LO 0x34 1528277082Sjfv#define I40E_SR_NVM_ORIGINAL_EETRACK_HI 0x35 1529266423Sjfv#define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37 1530266423Sjfv#define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38 1531266423Sjfv#define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A 1532266423Sjfv#define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B 1533266423Sjfv#define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C 1534318357Serj#define I40E_SR_PHY_ACTIVITY_LIST_PTR 0x3D 1535266423Sjfv#define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E 1536266423Sjfv#define I40E_SR_SW_CHECKSUM_WORD 0x3F 1537266423Sjfv#define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40 1538266423Sjfv#define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42 1539266423Sjfv#define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44 1540266423Sjfv#define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46 1541266423Sjfv#define I40E_SR_EMP_SR_SETTINGS_PTR 0x48 1542277082Sjfv#define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49 1543277082Sjfv#define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D 1544277082Sjfv#define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E 1545266423Sjfv 1546266423Sjfv/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ 1547266423Sjfv#define I40E_SR_VPD_MODULE_MAX_SIZE 1024 1548266423Sjfv#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024 1549266423Sjfv#define I40E_SR_CONTROL_WORD_1_SHIFT 0x06 1550266423Sjfv#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT) 1551333343Serj#define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5) 1552333343Serj#define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12) 1553333343Serj#define I40E_PTR_TYPE BIT(15) 1554333343Serj#define I40E_SR_OCP_CFG_WORD0 0x2B 1555333343Serj#define I40E_SR_OCP_ENABLED BIT(15) 1556266423Sjfv 1557266423Sjfv/* Shadow RAM related */ 1558266423Sjfv#define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800 1559266423Sjfv#define I40E_SR_BUF_ALIGNMENT 4096 1560266423Sjfv#define I40E_SR_WORDS_IN_1KB 512 1561266423Sjfv/* Checksum should be calculated such that after adding all the words, 1562266423Sjfv * including the checksum word itself, the sum should be 0xBABA. 1563266423Sjfv */ 1564266423Sjfv#define I40E_SR_SW_CHECKSUM_BASE 0xBABA 1565266423Sjfv 1566266423Sjfv#define I40E_SRRD_SRCTL_ATTEMPTS 100000 1567266423Sjfv 1568266423Sjfvenum i40e_switch_element_types { 1569266423Sjfv I40E_SWITCH_ELEMENT_TYPE_MAC = 1, 1570266423Sjfv I40E_SWITCH_ELEMENT_TYPE_PF = 2, 1571266423Sjfv I40E_SWITCH_ELEMENT_TYPE_VF = 3, 1572266423Sjfv I40E_SWITCH_ELEMENT_TYPE_EMP = 4, 1573266423Sjfv I40E_SWITCH_ELEMENT_TYPE_BMC = 6, 1574266423Sjfv I40E_SWITCH_ELEMENT_TYPE_PE = 16, 1575266423Sjfv I40E_SWITCH_ELEMENT_TYPE_VEB = 17, 1576266423Sjfv I40E_SWITCH_ELEMENT_TYPE_PA = 18, 1577266423Sjfv I40E_SWITCH_ELEMENT_TYPE_VSI = 19, 1578266423Sjfv}; 1579266423Sjfv 1580266423Sjfv/* Supported EtherType filters */ 1581266423Sjfvenum i40e_ether_type_index { 1582266423Sjfv I40E_ETHER_TYPE_1588 = 0, 1583266423Sjfv I40E_ETHER_TYPE_FIP = 1, 1584266423Sjfv I40E_ETHER_TYPE_OUI_EXTENDED = 2, 1585266423Sjfv I40E_ETHER_TYPE_MAC_CONTROL = 3, 1586266423Sjfv I40E_ETHER_TYPE_LLDP = 4, 1587266423Sjfv I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5, 1588266423Sjfv I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6, 1589266423Sjfv I40E_ETHER_TYPE_QCN_CNM = 7, 1590266423Sjfv I40E_ETHER_TYPE_8021X = 8, 1591266423Sjfv I40E_ETHER_TYPE_ARP = 9, 1592266423Sjfv I40E_ETHER_TYPE_RSV1 = 10, 1593266423Sjfv I40E_ETHER_TYPE_RSV2 = 11, 1594266423Sjfv}; 1595266423Sjfv 1596266423Sjfv/* Filter context base size is 1K */ 1597266423Sjfv#define I40E_HASH_FILTER_BASE_SIZE 1024 1598266423Sjfv/* Supported Hash filter values */ 1599266423Sjfvenum i40e_hash_filter_size { 1600266423Sjfv I40E_HASH_FILTER_SIZE_1K = 0, 1601266423Sjfv I40E_HASH_FILTER_SIZE_2K = 1, 1602266423Sjfv I40E_HASH_FILTER_SIZE_4K = 2, 1603266423Sjfv I40E_HASH_FILTER_SIZE_8K = 3, 1604266423Sjfv I40E_HASH_FILTER_SIZE_16K = 4, 1605266423Sjfv I40E_HASH_FILTER_SIZE_32K = 5, 1606266423Sjfv I40E_HASH_FILTER_SIZE_64K = 6, 1607266423Sjfv I40E_HASH_FILTER_SIZE_128K = 7, 1608266423Sjfv I40E_HASH_FILTER_SIZE_256K = 8, 1609266423Sjfv I40E_HASH_FILTER_SIZE_512K = 9, 1610266423Sjfv I40E_HASH_FILTER_SIZE_1M = 10, 1611266423Sjfv}; 1612266423Sjfv 1613266423Sjfv/* DMA context base size is 0.5K */ 1614266423Sjfv#define I40E_DMA_CNTX_BASE_SIZE 512 1615266423Sjfv/* Supported DMA context values */ 1616266423Sjfvenum i40e_dma_cntx_size { 1617266423Sjfv I40E_DMA_CNTX_SIZE_512 = 0, 1618266423Sjfv I40E_DMA_CNTX_SIZE_1K = 1, 1619266423Sjfv I40E_DMA_CNTX_SIZE_2K = 2, 1620266423Sjfv I40E_DMA_CNTX_SIZE_4K = 3, 1621266423Sjfv I40E_DMA_CNTX_SIZE_8K = 4, 1622266423Sjfv I40E_DMA_CNTX_SIZE_16K = 5, 1623266423Sjfv I40E_DMA_CNTX_SIZE_32K = 6, 1624266423Sjfv I40E_DMA_CNTX_SIZE_64K = 7, 1625266423Sjfv I40E_DMA_CNTX_SIZE_128K = 8, 1626266423Sjfv I40E_DMA_CNTX_SIZE_256K = 9, 1627266423Sjfv}; 1628266423Sjfv 1629266423Sjfv/* Supported Hash look up table (LUT) sizes */ 1630266423Sjfvenum i40e_hash_lut_size { 1631266423Sjfv I40E_HASH_LUT_SIZE_128 = 0, 1632266423Sjfv I40E_HASH_LUT_SIZE_512 = 1, 1633266423Sjfv}; 1634266423Sjfv 1635266423Sjfv/* Structure to hold a per PF filter control settings */ 1636266423Sjfvstruct i40e_filter_control_settings { 1637266423Sjfv /* number of PE Quad Hash filter buckets */ 1638266423Sjfv enum i40e_hash_filter_size pe_filt_num; 1639266423Sjfv /* number of PE Quad Hash contexts */ 1640266423Sjfv enum i40e_dma_cntx_size pe_cntx_num; 1641266423Sjfv /* number of FCoE filter buckets */ 1642266423Sjfv enum i40e_hash_filter_size fcoe_filt_num; 1643266423Sjfv /* number of FCoE DDP contexts */ 1644266423Sjfv enum i40e_dma_cntx_size fcoe_cntx_num; 1645266423Sjfv /* size of the Hash LUT */ 1646266423Sjfv enum i40e_hash_lut_size hash_lut_size; 1647266423Sjfv /* enable FDIR filters for PF and its VFs */ 1648266423Sjfv bool enable_fdir; 1649266423Sjfv /* enable Ethertype filters for PF and its VFs */ 1650266423Sjfv bool enable_ethtype; 1651266423Sjfv /* enable MAC/VLAN filters for PF and its VFs */ 1652266423Sjfv bool enable_macvlan; 1653266423Sjfv}; 1654266423Sjfv 1655266423Sjfv/* Structure to hold device level control filter counts */ 1656266423Sjfvstruct i40e_control_filter_stats { 1657266423Sjfv u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */ 1658266423Sjfv u16 etype_used; /* Used perfect EtherType filters */ 1659266423Sjfv u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */ 1660266423Sjfv u16 etype_free; /* Un-used perfect EtherType filters */ 1661266423Sjfv}; 1662266423Sjfv 1663266423Sjfvenum i40e_reset_type { 1664266423Sjfv I40E_RESET_POR = 0, 1665266423Sjfv I40E_RESET_CORER = 1, 1666266423Sjfv I40E_RESET_GLOBR = 2, 1667266423Sjfv I40E_RESET_EMPR = 3, 1668266423Sjfv}; 1669266423Sjfv 1670277082Sjfv/* IEEE 802.1AB LLDP Agent Variables from NVM */ 1671333343Serj#define I40E_NVM_LLDP_CFG_PTR 0x06 1672333343Serj#define I40E_SR_LLDP_CFG_PTR 0x31 1673277082Sjfvstruct i40e_lldp_variables { 1674277082Sjfv u16 length; 1675277082Sjfv u16 adminstatus; 1676277082Sjfv u16 msgfasttx; 1677277082Sjfv u16 msgtxinterval; 1678277082Sjfv u16 txparams; 1679277082Sjfv u16 timers; 1680277082Sjfv u16 crc8; 1681277082Sjfv}; 1682277082Sjfv 1683266423Sjfv/* Offsets into Alternate Ram */ 1684266423Sjfv#define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */ 1685266423Sjfv#define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */ 1686266423Sjfv#define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */ 1687266423Sjfv#define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */ 1688266423Sjfv#define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */ 1689266423Sjfv#define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */ 1690266423Sjfv 1691266423Sjfv/* Alternate Ram Bandwidth Masks */ 1692266423Sjfv#define I40E_ALT_BW_VALUE_MASK 0xFF 1693266423Sjfv#define I40E_ALT_BW_RELATIVE_MASK 0x40000000 1694266423Sjfv#define I40E_ALT_BW_VALID_MASK 0x80000000 1695266423Sjfv 1696266423Sjfv/* RSS Hash Table Size */ 1697266423Sjfv#define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000 1698303967Ssbruno 1699303967Ssbruno/* INPUT SET MASK for RSS, flow director, and flexible payload */ 1700303967Ssbruno#define I40E_L3_SRC_SHIFT 47 1701303967Ssbruno#define I40E_L3_SRC_MASK (0x3ULL << I40E_L3_SRC_SHIFT) 1702303967Ssbruno#define I40E_L3_V6_SRC_SHIFT 43 1703303967Ssbruno#define I40E_L3_V6_SRC_MASK (0xFFULL << I40E_L3_V6_SRC_SHIFT) 1704303967Ssbruno#define I40E_L3_DST_SHIFT 35 1705303967Ssbruno#define I40E_L3_DST_MASK (0x3ULL << I40E_L3_DST_SHIFT) 1706303967Ssbruno#define I40E_L3_V6_DST_SHIFT 35 1707303967Ssbruno#define I40E_L3_V6_DST_MASK (0xFFULL << I40E_L3_V6_DST_SHIFT) 1708303967Ssbruno#define I40E_L4_SRC_SHIFT 34 1709303967Ssbruno#define I40E_L4_SRC_MASK (0x1ULL << I40E_L4_SRC_SHIFT) 1710303967Ssbruno#define I40E_L4_DST_SHIFT 33 1711303967Ssbruno#define I40E_L4_DST_MASK (0x1ULL << I40E_L4_DST_SHIFT) 1712303967Ssbruno#define I40E_VERIFY_TAG_SHIFT 31 1713303967Ssbruno#define I40E_VERIFY_TAG_MASK (0x3ULL << I40E_VERIFY_TAG_SHIFT) 1714303967Ssbruno 1715303967Ssbruno#define I40E_FLEX_50_SHIFT 13 1716303967Ssbruno#define I40E_FLEX_50_MASK (0x1ULL << I40E_FLEX_50_SHIFT) 1717303967Ssbruno#define I40E_FLEX_51_SHIFT 12 1718303967Ssbruno#define I40E_FLEX_51_MASK (0x1ULL << I40E_FLEX_51_SHIFT) 1719303967Ssbruno#define I40E_FLEX_52_SHIFT 11 1720303967Ssbruno#define I40E_FLEX_52_MASK (0x1ULL << I40E_FLEX_52_SHIFT) 1721303967Ssbruno#define I40E_FLEX_53_SHIFT 10 1722303967Ssbruno#define I40E_FLEX_53_MASK (0x1ULL << I40E_FLEX_53_SHIFT) 1723303967Ssbruno#define I40E_FLEX_54_SHIFT 9 1724303967Ssbruno#define I40E_FLEX_54_MASK (0x1ULL << I40E_FLEX_54_SHIFT) 1725303967Ssbruno#define I40E_FLEX_55_SHIFT 8 1726303967Ssbruno#define I40E_FLEX_55_MASK (0x1ULL << I40E_FLEX_55_SHIFT) 1727303967Ssbruno#define I40E_FLEX_56_SHIFT 7 1728303967Ssbruno#define I40E_FLEX_56_MASK (0x1ULL << I40E_FLEX_56_SHIFT) 1729303967Ssbruno#define I40E_FLEX_57_SHIFT 6 1730303967Ssbruno#define I40E_FLEX_57_MASK (0x1ULL << I40E_FLEX_57_SHIFT) 1731349163Serj 1732349163Serj#define I40E_BCM_PHY_PCS_STATUS1_PAGE 0x3 1733349163Serj#define I40E_BCM_PHY_PCS_STATUS1_REG 0x0001 1734349163Serj#define I40E_BCM_PHY_PCS_STATUS1_RX_LPI BIT(8) 1735349163Serj#define I40E_BCM_PHY_PCS_STATUS1_TX_LPI BIT(9) 1736349163Serj 1737266423Sjfv#endif /* _I40E_TYPE_H_ */ 1738