i40e_common.c revision 318357
1/****************************************************************************** 2 3 Copyright (c) 2013-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: stable/11/sys/dev/ixl/i40e_common.c 318357 2017-05-16 17:49:15Z erj $*/ 34 35#include "i40e_type.h" 36#include "i40e_adminq.h" 37#include "i40e_prototype.h" 38#include "i40e_virtchnl.h" 39 40 41/** 42 * i40e_set_mac_type - Sets MAC type 43 * @hw: pointer to the HW structure 44 * 45 * This function sets the mac type of the adapter based on the 46 * vendor ID and device ID stored in the hw structure. 47 **/ 48enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw) 49{ 50 enum i40e_status_code status = I40E_SUCCESS; 51 52 DEBUGFUNC("i40e_set_mac_type\n"); 53 54 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) { 55 switch (hw->device_id) { 56 case I40E_DEV_ID_SFP_XL710: 57 case I40E_DEV_ID_QEMU: 58 case I40E_DEV_ID_KX_B: 59 case I40E_DEV_ID_KX_C: 60 case I40E_DEV_ID_QSFP_A: 61 case I40E_DEV_ID_QSFP_B: 62 case I40E_DEV_ID_QSFP_C: 63 case I40E_DEV_ID_10G_BASE_T: 64 case I40E_DEV_ID_10G_BASE_T4: 65 case I40E_DEV_ID_20G_KR2: 66 case I40E_DEV_ID_20G_KR2_A: 67 case I40E_DEV_ID_25G_B: 68 case I40E_DEV_ID_25G_SFP28: 69 hw->mac.type = I40E_MAC_XL710; 70 break; 71 case I40E_DEV_ID_X722_A0: 72 case I40E_DEV_ID_KX_X722: 73 case I40E_DEV_ID_QSFP_X722: 74 case I40E_DEV_ID_SFP_X722: 75 case I40E_DEV_ID_1G_BASE_T_X722: 76 case I40E_DEV_ID_10G_BASE_T_X722: 77 case I40E_DEV_ID_SFP_I_X722: 78 hw->mac.type = I40E_MAC_X722; 79 break; 80 case I40E_DEV_ID_X722_VF: 81 case I40E_DEV_ID_X722_A0_VF: 82 hw->mac.type = I40E_MAC_X722_VF; 83 break; 84 case I40E_DEV_ID_VF: 85 case I40E_DEV_ID_VF_HV: 86 hw->mac.type = I40E_MAC_VF; 87 break; 88 default: 89 hw->mac.type = I40E_MAC_GENERIC; 90 break; 91 } 92 } else { 93 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 94 } 95 96 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n", 97 hw->mac.type, status); 98 return status; 99} 100 101/** 102 * i40e_aq_str - convert AQ err code to a string 103 * @hw: pointer to the HW structure 104 * @aq_err: the AQ error code to convert 105 **/ 106const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 107{ 108 switch (aq_err) { 109 case I40E_AQ_RC_OK: 110 return "OK"; 111 case I40E_AQ_RC_EPERM: 112 return "I40E_AQ_RC_EPERM"; 113 case I40E_AQ_RC_ENOENT: 114 return "I40E_AQ_RC_ENOENT"; 115 case I40E_AQ_RC_ESRCH: 116 return "I40E_AQ_RC_ESRCH"; 117 case I40E_AQ_RC_EINTR: 118 return "I40E_AQ_RC_EINTR"; 119 case I40E_AQ_RC_EIO: 120 return "I40E_AQ_RC_EIO"; 121 case I40E_AQ_RC_ENXIO: 122 return "I40E_AQ_RC_ENXIO"; 123 case I40E_AQ_RC_E2BIG: 124 return "I40E_AQ_RC_E2BIG"; 125 case I40E_AQ_RC_EAGAIN: 126 return "I40E_AQ_RC_EAGAIN"; 127 case I40E_AQ_RC_ENOMEM: 128 return "I40E_AQ_RC_ENOMEM"; 129 case I40E_AQ_RC_EACCES: 130 return "I40E_AQ_RC_EACCES"; 131 case I40E_AQ_RC_EFAULT: 132 return "I40E_AQ_RC_EFAULT"; 133 case I40E_AQ_RC_EBUSY: 134 return "I40E_AQ_RC_EBUSY"; 135 case I40E_AQ_RC_EEXIST: 136 return "I40E_AQ_RC_EEXIST"; 137 case I40E_AQ_RC_EINVAL: 138 return "I40E_AQ_RC_EINVAL"; 139 case I40E_AQ_RC_ENOTTY: 140 return "I40E_AQ_RC_ENOTTY"; 141 case I40E_AQ_RC_ENOSPC: 142 return "I40E_AQ_RC_ENOSPC"; 143 case I40E_AQ_RC_ENOSYS: 144 return "I40E_AQ_RC_ENOSYS"; 145 case I40E_AQ_RC_ERANGE: 146 return "I40E_AQ_RC_ERANGE"; 147 case I40E_AQ_RC_EFLUSHED: 148 return "I40E_AQ_RC_EFLUSHED"; 149 case I40E_AQ_RC_BAD_ADDR: 150 return "I40E_AQ_RC_BAD_ADDR"; 151 case I40E_AQ_RC_EMODE: 152 return "I40E_AQ_RC_EMODE"; 153 case I40E_AQ_RC_EFBIG: 154 return "I40E_AQ_RC_EFBIG"; 155 } 156 157 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 158 return hw->err_str; 159} 160 161/** 162 * i40e_stat_str - convert status err code to a string 163 * @hw: pointer to the HW structure 164 * @stat_err: the status error code to convert 165 **/ 166const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err) 167{ 168 switch (stat_err) { 169 case I40E_SUCCESS: 170 return "OK"; 171 case I40E_ERR_NVM: 172 return "I40E_ERR_NVM"; 173 case I40E_ERR_NVM_CHECKSUM: 174 return "I40E_ERR_NVM_CHECKSUM"; 175 case I40E_ERR_PHY: 176 return "I40E_ERR_PHY"; 177 case I40E_ERR_CONFIG: 178 return "I40E_ERR_CONFIG"; 179 case I40E_ERR_PARAM: 180 return "I40E_ERR_PARAM"; 181 case I40E_ERR_MAC_TYPE: 182 return "I40E_ERR_MAC_TYPE"; 183 case I40E_ERR_UNKNOWN_PHY: 184 return "I40E_ERR_UNKNOWN_PHY"; 185 case I40E_ERR_LINK_SETUP: 186 return "I40E_ERR_LINK_SETUP"; 187 case I40E_ERR_ADAPTER_STOPPED: 188 return "I40E_ERR_ADAPTER_STOPPED"; 189 case I40E_ERR_INVALID_MAC_ADDR: 190 return "I40E_ERR_INVALID_MAC_ADDR"; 191 case I40E_ERR_DEVICE_NOT_SUPPORTED: 192 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 193 case I40E_ERR_MASTER_REQUESTS_PENDING: 194 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 195 case I40E_ERR_INVALID_LINK_SETTINGS: 196 return "I40E_ERR_INVALID_LINK_SETTINGS"; 197 case I40E_ERR_AUTONEG_NOT_COMPLETE: 198 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 199 case I40E_ERR_RESET_FAILED: 200 return "I40E_ERR_RESET_FAILED"; 201 case I40E_ERR_SWFW_SYNC: 202 return "I40E_ERR_SWFW_SYNC"; 203 case I40E_ERR_NO_AVAILABLE_VSI: 204 return "I40E_ERR_NO_AVAILABLE_VSI"; 205 case I40E_ERR_NO_MEMORY: 206 return "I40E_ERR_NO_MEMORY"; 207 case I40E_ERR_BAD_PTR: 208 return "I40E_ERR_BAD_PTR"; 209 case I40E_ERR_RING_FULL: 210 return "I40E_ERR_RING_FULL"; 211 case I40E_ERR_INVALID_PD_ID: 212 return "I40E_ERR_INVALID_PD_ID"; 213 case I40E_ERR_INVALID_QP_ID: 214 return "I40E_ERR_INVALID_QP_ID"; 215 case I40E_ERR_INVALID_CQ_ID: 216 return "I40E_ERR_INVALID_CQ_ID"; 217 case I40E_ERR_INVALID_CEQ_ID: 218 return "I40E_ERR_INVALID_CEQ_ID"; 219 case I40E_ERR_INVALID_AEQ_ID: 220 return "I40E_ERR_INVALID_AEQ_ID"; 221 case I40E_ERR_INVALID_SIZE: 222 return "I40E_ERR_INVALID_SIZE"; 223 case I40E_ERR_INVALID_ARP_INDEX: 224 return "I40E_ERR_INVALID_ARP_INDEX"; 225 case I40E_ERR_INVALID_FPM_FUNC_ID: 226 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 227 case I40E_ERR_QP_INVALID_MSG_SIZE: 228 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 229 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 230 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 231 case I40E_ERR_INVALID_FRAG_COUNT: 232 return "I40E_ERR_INVALID_FRAG_COUNT"; 233 case I40E_ERR_QUEUE_EMPTY: 234 return "I40E_ERR_QUEUE_EMPTY"; 235 case I40E_ERR_INVALID_ALIGNMENT: 236 return "I40E_ERR_INVALID_ALIGNMENT"; 237 case I40E_ERR_FLUSHED_QUEUE: 238 return "I40E_ERR_FLUSHED_QUEUE"; 239 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 240 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 241 case I40E_ERR_INVALID_IMM_DATA_SIZE: 242 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 243 case I40E_ERR_TIMEOUT: 244 return "I40E_ERR_TIMEOUT"; 245 case I40E_ERR_OPCODE_MISMATCH: 246 return "I40E_ERR_OPCODE_MISMATCH"; 247 case I40E_ERR_CQP_COMPL_ERROR: 248 return "I40E_ERR_CQP_COMPL_ERROR"; 249 case I40E_ERR_INVALID_VF_ID: 250 return "I40E_ERR_INVALID_VF_ID"; 251 case I40E_ERR_INVALID_HMCFN_ID: 252 return "I40E_ERR_INVALID_HMCFN_ID"; 253 case I40E_ERR_BACKING_PAGE_ERROR: 254 return "I40E_ERR_BACKING_PAGE_ERROR"; 255 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 256 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 257 case I40E_ERR_INVALID_PBLE_INDEX: 258 return "I40E_ERR_INVALID_PBLE_INDEX"; 259 case I40E_ERR_INVALID_SD_INDEX: 260 return "I40E_ERR_INVALID_SD_INDEX"; 261 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 262 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 263 case I40E_ERR_INVALID_SD_TYPE: 264 return "I40E_ERR_INVALID_SD_TYPE"; 265 case I40E_ERR_MEMCPY_FAILED: 266 return "I40E_ERR_MEMCPY_FAILED"; 267 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 268 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 269 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 270 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 271 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 272 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 273 case I40E_ERR_SRQ_ENABLED: 274 return "I40E_ERR_SRQ_ENABLED"; 275 case I40E_ERR_ADMIN_QUEUE_ERROR: 276 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 277 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 278 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 279 case I40E_ERR_BUF_TOO_SHORT: 280 return "I40E_ERR_BUF_TOO_SHORT"; 281 case I40E_ERR_ADMIN_QUEUE_FULL: 282 return "I40E_ERR_ADMIN_QUEUE_FULL"; 283 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 284 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 285 case I40E_ERR_BAD_IWARP_CQE: 286 return "I40E_ERR_BAD_IWARP_CQE"; 287 case I40E_ERR_NVM_BLANK_MODE: 288 return "I40E_ERR_NVM_BLANK_MODE"; 289 case I40E_ERR_NOT_IMPLEMENTED: 290 return "I40E_ERR_NOT_IMPLEMENTED"; 291 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 292 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 293 case I40E_ERR_DIAG_TEST_FAILED: 294 return "I40E_ERR_DIAG_TEST_FAILED"; 295 case I40E_ERR_NOT_READY: 296 return "I40E_ERR_NOT_READY"; 297 case I40E_NOT_SUPPORTED: 298 return "I40E_NOT_SUPPORTED"; 299 case I40E_ERR_FIRMWARE_API_VERSION: 300 return "I40E_ERR_FIRMWARE_API_VERSION"; 301 } 302 303 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 304 return hw->err_str; 305} 306 307/** 308 * i40e_debug_aq 309 * @hw: debug mask related to admin queue 310 * @mask: debug mask 311 * @desc: pointer to admin queue descriptor 312 * @buffer: pointer to command buffer 313 * @buf_len: max length of buffer 314 * 315 * Dumps debug log about adminq command with descriptor contents. 316 **/ 317void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 318 void *buffer, u16 buf_len) 319{ 320 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 321 u16 len = LE16_TO_CPU(aq_desc->datalen); 322 u8 *buf = (u8 *)buffer; 323 u16 i = 0; 324 325 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 326 return; 327 328 i40e_debug(hw, mask, 329 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 330 LE16_TO_CPU(aq_desc->opcode), 331 LE16_TO_CPU(aq_desc->flags), 332 LE16_TO_CPU(aq_desc->datalen), 333 LE16_TO_CPU(aq_desc->retval)); 334 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 335 LE32_TO_CPU(aq_desc->cookie_high), 336 LE32_TO_CPU(aq_desc->cookie_low)); 337 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 338 LE32_TO_CPU(aq_desc->params.internal.param0), 339 LE32_TO_CPU(aq_desc->params.internal.param1)); 340 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 341 LE32_TO_CPU(aq_desc->params.external.addr_high), 342 LE32_TO_CPU(aq_desc->params.external.addr_low)); 343 344 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 345 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 346 if (buf_len < len) 347 len = buf_len; 348 /* write the full 16-byte chunks */ 349 for (i = 0; i < (len - 16); i += 16) 350 i40e_debug(hw, mask, 351 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 352 i, buf[i], buf[i+1], buf[i+2], buf[i+3], 353 buf[i+4], buf[i+5], buf[i+6], buf[i+7], 354 buf[i+8], buf[i+9], buf[i+10], buf[i+11], 355 buf[i+12], buf[i+13], buf[i+14], buf[i+15]); 356 /* the most we could have left is 16 bytes, pad with zeros */ 357 if (i < len) { 358 char d_buf[16]; 359 int j, i_sav; 360 361 i_sav = i; 362 memset(d_buf, 0, sizeof(d_buf)); 363 for (j = 0; i < len; j++, i++) 364 d_buf[j] = buf[i]; 365 i40e_debug(hw, mask, 366 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 367 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3], 368 d_buf[4], d_buf[5], d_buf[6], d_buf[7], 369 d_buf[8], d_buf[9], d_buf[10], d_buf[11], 370 d_buf[12], d_buf[13], d_buf[14], d_buf[15]); 371 } 372 } 373} 374 375/** 376 * i40e_check_asq_alive 377 * @hw: pointer to the hw struct 378 * 379 * Returns TRUE if Queue is enabled else FALSE. 380 **/ 381bool i40e_check_asq_alive(struct i40e_hw *hw) 382{ 383 if (hw->aq.asq.len) 384 if (!i40e_is_vf(hw)) 385 return !!(rd32(hw, hw->aq.asq.len) & 386 I40E_PF_ATQLEN_ATQENABLE_MASK); 387 if (i40e_is_vf(hw)) 388 return !!(rd32(hw, hw->aq.asq.len) & 389 I40E_VF_ATQLEN1_ATQENABLE_MASK); 390 return FALSE; 391} 392 393/** 394 * i40e_aq_queue_shutdown 395 * @hw: pointer to the hw struct 396 * @unloading: is the driver unloading itself 397 * 398 * Tell the Firmware that we're shutting down the AdminQ and whether 399 * or not the driver is unloading as well. 400 **/ 401enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw, 402 bool unloading) 403{ 404 struct i40e_aq_desc desc; 405 struct i40e_aqc_queue_shutdown *cmd = 406 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 407 enum i40e_status_code status; 408 409 i40e_fill_default_direct_cmd_desc(&desc, 410 i40e_aqc_opc_queue_shutdown); 411 412 if (unloading) 413 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING); 414 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 415 416 return status; 417} 418 419/** 420 * i40e_aq_get_set_rss_lut 421 * @hw: pointer to the hardware structure 422 * @vsi_id: vsi fw index 423 * @pf_lut: for PF table set TRUE, for VSI table set FALSE 424 * @lut: pointer to the lut buffer provided by the caller 425 * @lut_size: size of the lut buffer 426 * @set: set TRUE to set the table, FALSE to get the table 427 * 428 * Internal function to get or set RSS look up table 429 **/ 430static enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 431 u16 vsi_id, bool pf_lut, 432 u8 *lut, u16 lut_size, 433 bool set) 434{ 435 enum i40e_status_code status; 436 struct i40e_aq_desc desc; 437 struct i40e_aqc_get_set_rss_lut *cmd_resp = 438 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 439 440 if (set) 441 i40e_fill_default_direct_cmd_desc(&desc, 442 i40e_aqc_opc_set_rss_lut); 443 else 444 i40e_fill_default_direct_cmd_desc(&desc, 445 i40e_aqc_opc_get_rss_lut); 446 447 /* Indirect command */ 448 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 449 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 450 451 cmd_resp->vsi_id = 452 CPU_TO_LE16((u16)((vsi_id << 453 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 454 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 455 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 456 457 if (pf_lut) 458 cmd_resp->flags |= CPU_TO_LE16((u16) 459 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 460 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 461 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 462 else 463 cmd_resp->flags |= CPU_TO_LE16((u16) 464 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 465 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 466 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 467 468 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 469 470 return status; 471} 472 473/** 474 * i40e_aq_get_rss_lut 475 * @hw: pointer to the hardware structure 476 * @vsi_id: vsi fw index 477 * @pf_lut: for PF table set TRUE, for VSI table set FALSE 478 * @lut: pointer to the lut buffer provided by the caller 479 * @lut_size: size of the lut buffer 480 * 481 * get the RSS lookup table, PF or VSI type 482 **/ 483enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 484 bool pf_lut, u8 *lut, u16 lut_size) 485{ 486 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 487 FALSE); 488} 489 490/** 491 * i40e_aq_set_rss_lut 492 * @hw: pointer to the hardware structure 493 * @vsi_id: vsi fw index 494 * @pf_lut: for PF table set TRUE, for VSI table set FALSE 495 * @lut: pointer to the lut buffer provided by the caller 496 * @lut_size: size of the lut buffer 497 * 498 * set the RSS lookup table, PF or VSI type 499 **/ 500enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 501 bool pf_lut, u8 *lut, u16 lut_size) 502{ 503 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, TRUE); 504} 505 506/** 507 * i40e_aq_get_set_rss_key 508 * @hw: pointer to the hw struct 509 * @vsi_id: vsi fw index 510 * @key: pointer to key info struct 511 * @set: set TRUE to set the key, FALSE to get the key 512 * 513 * get the RSS key per VSI 514 **/ 515static enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw, 516 u16 vsi_id, 517 struct i40e_aqc_get_set_rss_key_data *key, 518 bool set) 519{ 520 enum i40e_status_code status; 521 struct i40e_aq_desc desc; 522 struct i40e_aqc_get_set_rss_key *cmd_resp = 523 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 524 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 525 526 if (set) 527 i40e_fill_default_direct_cmd_desc(&desc, 528 i40e_aqc_opc_set_rss_key); 529 else 530 i40e_fill_default_direct_cmd_desc(&desc, 531 i40e_aqc_opc_get_rss_key); 532 533 /* Indirect command */ 534 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 535 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 536 537 cmd_resp->vsi_id = 538 CPU_TO_LE16((u16)((vsi_id << 539 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 540 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 541 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 542 543 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 544 545 return status; 546} 547 548/** 549 * i40e_aq_get_rss_key 550 * @hw: pointer to the hw struct 551 * @vsi_id: vsi fw index 552 * @key: pointer to key info struct 553 * 554 **/ 555enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw, 556 u16 vsi_id, 557 struct i40e_aqc_get_set_rss_key_data *key) 558{ 559 return i40e_aq_get_set_rss_key(hw, vsi_id, key, FALSE); 560} 561 562/** 563 * i40e_aq_set_rss_key 564 * @hw: pointer to the hw struct 565 * @vsi_id: vsi fw index 566 * @key: pointer to key info struct 567 * 568 * set the RSS key per VSI 569 **/ 570enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw, 571 u16 vsi_id, 572 struct i40e_aqc_get_set_rss_key_data *key) 573{ 574 return i40e_aq_get_set_rss_key(hw, vsi_id, key, TRUE); 575} 576 577/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 578 * hardware to a bit-field that can be used by SW to more easily determine the 579 * packet type. 580 * 581 * Macros are used to shorten the table lines and make this table human 582 * readable. 583 * 584 * We store the PTYPE in the top byte of the bit field - this is just so that 585 * we can check that the table doesn't have a row missing, as the index into 586 * the table should be the PTYPE. 587 * 588 * Typical work flow: 589 * 590 * IF NOT i40e_ptype_lookup[ptype].known 591 * THEN 592 * Packet is unknown 593 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 594 * Use the rest of the fields to look at the tunnels, inner protocols, etc 595 * ELSE 596 * Use the enum i40e_rx_l2_ptype to decode the packet type 597 * ENDIF 598 */ 599 600/* macro to make the table lines short */ 601#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 602 { PTYPE, \ 603 1, \ 604 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 605 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 606 I40E_RX_PTYPE_##OUTER_FRAG, \ 607 I40E_RX_PTYPE_TUNNEL_##T, \ 608 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 609 I40E_RX_PTYPE_##TEF, \ 610 I40E_RX_PTYPE_INNER_PROT_##I, \ 611 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 612 613#define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 614 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 615 616/* shorter macros makes the table fit but are terse */ 617#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 618#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 619#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 620 621/* Lookup table mapping the HW PTYPE to the bit field for decoding */ 622struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 623 /* L2 Packet types */ 624 I40E_PTT_UNUSED_ENTRY(0), 625 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 626 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 627 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 628 I40E_PTT_UNUSED_ENTRY(4), 629 I40E_PTT_UNUSED_ENTRY(5), 630 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 631 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 632 I40E_PTT_UNUSED_ENTRY(8), 633 I40E_PTT_UNUSED_ENTRY(9), 634 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 635 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 636 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 637 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 638 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 639 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 640 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 641 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 642 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 643 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 644 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 645 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 646 647 /* Non Tunneled IPv4 */ 648 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 649 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 650 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 651 I40E_PTT_UNUSED_ENTRY(25), 652 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 653 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 654 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 655 656 /* IPv4 --> IPv4 */ 657 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 658 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 659 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 660 I40E_PTT_UNUSED_ENTRY(32), 661 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 662 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 663 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 664 665 /* IPv4 --> IPv6 */ 666 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 667 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 668 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 669 I40E_PTT_UNUSED_ENTRY(39), 670 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 671 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 672 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 673 674 /* IPv4 --> GRE/NAT */ 675 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 676 677 /* IPv4 --> GRE/NAT --> IPv4 */ 678 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 679 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 680 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 681 I40E_PTT_UNUSED_ENTRY(47), 682 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 683 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 684 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 685 686 /* IPv4 --> GRE/NAT --> IPv6 */ 687 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 688 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 689 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 690 I40E_PTT_UNUSED_ENTRY(54), 691 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 692 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 693 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 694 695 /* IPv4 --> GRE/NAT --> MAC */ 696 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 697 698 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 699 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 700 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 701 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 702 I40E_PTT_UNUSED_ENTRY(62), 703 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 704 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 705 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 706 707 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 708 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 709 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 710 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 711 I40E_PTT_UNUSED_ENTRY(69), 712 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 713 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 714 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 715 716 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 717 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 718 719 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 720 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 721 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 722 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 723 I40E_PTT_UNUSED_ENTRY(77), 724 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 725 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 726 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 727 728 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 729 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 730 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 731 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 732 I40E_PTT_UNUSED_ENTRY(84), 733 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 734 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 735 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 736 737 /* Non Tunneled IPv6 */ 738 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 739 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 740 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), 741 I40E_PTT_UNUSED_ENTRY(91), 742 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 743 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 744 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 745 746 /* IPv6 --> IPv4 */ 747 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 748 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 749 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 750 I40E_PTT_UNUSED_ENTRY(98), 751 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 752 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 753 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 754 755 /* IPv6 --> IPv6 */ 756 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 757 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 758 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 759 I40E_PTT_UNUSED_ENTRY(105), 760 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 761 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 762 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 763 764 /* IPv6 --> GRE/NAT */ 765 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 766 767 /* IPv6 --> GRE/NAT -> IPv4 */ 768 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 769 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 770 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 771 I40E_PTT_UNUSED_ENTRY(113), 772 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 773 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 774 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 775 776 /* IPv6 --> GRE/NAT -> IPv6 */ 777 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 778 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 779 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 780 I40E_PTT_UNUSED_ENTRY(120), 781 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 782 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 783 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 784 785 /* IPv6 --> GRE/NAT -> MAC */ 786 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 787 788 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 789 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 790 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 791 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 792 I40E_PTT_UNUSED_ENTRY(128), 793 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 794 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 795 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 796 797 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 798 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 799 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 800 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 801 I40E_PTT_UNUSED_ENTRY(135), 802 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 803 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 804 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 805 806 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 807 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 808 809 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 810 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 811 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 812 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 813 I40E_PTT_UNUSED_ENTRY(143), 814 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 815 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 816 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 817 818 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 819 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 820 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 821 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 822 I40E_PTT_UNUSED_ENTRY(150), 823 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 824 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 825 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 826 827 /* unused entries */ 828 I40E_PTT_UNUSED_ENTRY(154), 829 I40E_PTT_UNUSED_ENTRY(155), 830 I40E_PTT_UNUSED_ENTRY(156), 831 I40E_PTT_UNUSED_ENTRY(157), 832 I40E_PTT_UNUSED_ENTRY(158), 833 I40E_PTT_UNUSED_ENTRY(159), 834 835 I40E_PTT_UNUSED_ENTRY(160), 836 I40E_PTT_UNUSED_ENTRY(161), 837 I40E_PTT_UNUSED_ENTRY(162), 838 I40E_PTT_UNUSED_ENTRY(163), 839 I40E_PTT_UNUSED_ENTRY(164), 840 I40E_PTT_UNUSED_ENTRY(165), 841 I40E_PTT_UNUSED_ENTRY(166), 842 I40E_PTT_UNUSED_ENTRY(167), 843 I40E_PTT_UNUSED_ENTRY(168), 844 I40E_PTT_UNUSED_ENTRY(169), 845 846 I40E_PTT_UNUSED_ENTRY(170), 847 I40E_PTT_UNUSED_ENTRY(171), 848 I40E_PTT_UNUSED_ENTRY(172), 849 I40E_PTT_UNUSED_ENTRY(173), 850 I40E_PTT_UNUSED_ENTRY(174), 851 I40E_PTT_UNUSED_ENTRY(175), 852 I40E_PTT_UNUSED_ENTRY(176), 853 I40E_PTT_UNUSED_ENTRY(177), 854 I40E_PTT_UNUSED_ENTRY(178), 855 I40E_PTT_UNUSED_ENTRY(179), 856 857 I40E_PTT_UNUSED_ENTRY(180), 858 I40E_PTT_UNUSED_ENTRY(181), 859 I40E_PTT_UNUSED_ENTRY(182), 860 I40E_PTT_UNUSED_ENTRY(183), 861 I40E_PTT_UNUSED_ENTRY(184), 862 I40E_PTT_UNUSED_ENTRY(185), 863 I40E_PTT_UNUSED_ENTRY(186), 864 I40E_PTT_UNUSED_ENTRY(187), 865 I40E_PTT_UNUSED_ENTRY(188), 866 I40E_PTT_UNUSED_ENTRY(189), 867 868 I40E_PTT_UNUSED_ENTRY(190), 869 I40E_PTT_UNUSED_ENTRY(191), 870 I40E_PTT_UNUSED_ENTRY(192), 871 I40E_PTT_UNUSED_ENTRY(193), 872 I40E_PTT_UNUSED_ENTRY(194), 873 I40E_PTT_UNUSED_ENTRY(195), 874 I40E_PTT_UNUSED_ENTRY(196), 875 I40E_PTT_UNUSED_ENTRY(197), 876 I40E_PTT_UNUSED_ENTRY(198), 877 I40E_PTT_UNUSED_ENTRY(199), 878 879 I40E_PTT_UNUSED_ENTRY(200), 880 I40E_PTT_UNUSED_ENTRY(201), 881 I40E_PTT_UNUSED_ENTRY(202), 882 I40E_PTT_UNUSED_ENTRY(203), 883 I40E_PTT_UNUSED_ENTRY(204), 884 I40E_PTT_UNUSED_ENTRY(205), 885 I40E_PTT_UNUSED_ENTRY(206), 886 I40E_PTT_UNUSED_ENTRY(207), 887 I40E_PTT_UNUSED_ENTRY(208), 888 I40E_PTT_UNUSED_ENTRY(209), 889 890 I40E_PTT_UNUSED_ENTRY(210), 891 I40E_PTT_UNUSED_ENTRY(211), 892 I40E_PTT_UNUSED_ENTRY(212), 893 I40E_PTT_UNUSED_ENTRY(213), 894 I40E_PTT_UNUSED_ENTRY(214), 895 I40E_PTT_UNUSED_ENTRY(215), 896 I40E_PTT_UNUSED_ENTRY(216), 897 I40E_PTT_UNUSED_ENTRY(217), 898 I40E_PTT_UNUSED_ENTRY(218), 899 I40E_PTT_UNUSED_ENTRY(219), 900 901 I40E_PTT_UNUSED_ENTRY(220), 902 I40E_PTT_UNUSED_ENTRY(221), 903 I40E_PTT_UNUSED_ENTRY(222), 904 I40E_PTT_UNUSED_ENTRY(223), 905 I40E_PTT_UNUSED_ENTRY(224), 906 I40E_PTT_UNUSED_ENTRY(225), 907 I40E_PTT_UNUSED_ENTRY(226), 908 I40E_PTT_UNUSED_ENTRY(227), 909 I40E_PTT_UNUSED_ENTRY(228), 910 I40E_PTT_UNUSED_ENTRY(229), 911 912 I40E_PTT_UNUSED_ENTRY(230), 913 I40E_PTT_UNUSED_ENTRY(231), 914 I40E_PTT_UNUSED_ENTRY(232), 915 I40E_PTT_UNUSED_ENTRY(233), 916 I40E_PTT_UNUSED_ENTRY(234), 917 I40E_PTT_UNUSED_ENTRY(235), 918 I40E_PTT_UNUSED_ENTRY(236), 919 I40E_PTT_UNUSED_ENTRY(237), 920 I40E_PTT_UNUSED_ENTRY(238), 921 I40E_PTT_UNUSED_ENTRY(239), 922 923 I40E_PTT_UNUSED_ENTRY(240), 924 I40E_PTT_UNUSED_ENTRY(241), 925 I40E_PTT_UNUSED_ENTRY(242), 926 I40E_PTT_UNUSED_ENTRY(243), 927 I40E_PTT_UNUSED_ENTRY(244), 928 I40E_PTT_UNUSED_ENTRY(245), 929 I40E_PTT_UNUSED_ENTRY(246), 930 I40E_PTT_UNUSED_ENTRY(247), 931 I40E_PTT_UNUSED_ENTRY(248), 932 I40E_PTT_UNUSED_ENTRY(249), 933 934 I40E_PTT_UNUSED_ENTRY(250), 935 I40E_PTT_UNUSED_ENTRY(251), 936 I40E_PTT_UNUSED_ENTRY(252), 937 I40E_PTT_UNUSED_ENTRY(253), 938 I40E_PTT_UNUSED_ENTRY(254), 939 I40E_PTT_UNUSED_ENTRY(255) 940}; 941 942 943/** 944 * i40e_validate_mac_addr - Validate unicast MAC address 945 * @mac_addr: pointer to MAC address 946 * 947 * Tests a MAC address to ensure it is a valid Individual Address 948 **/ 949enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr) 950{ 951 enum i40e_status_code status = I40E_SUCCESS; 952 953 DEBUGFUNC("i40e_validate_mac_addr"); 954 955 /* Broadcast addresses ARE multicast addresses 956 * Make sure it is not a multicast address 957 * Reject the zero address 958 */ 959 if (I40E_IS_MULTICAST(mac_addr) || 960 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 961 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)) 962 status = I40E_ERR_INVALID_MAC_ADDR; 963 964 return status; 965} 966 967/** 968 * i40e_init_shared_code - Initialize the shared code 969 * @hw: pointer to hardware structure 970 * 971 * This assigns the MAC type and PHY code and inits the NVM. 972 * Does not touch the hardware. This function must be called prior to any 973 * other function in the shared code. The i40e_hw structure should be 974 * memset to 0 prior to calling this function. The following fields in 975 * hw structure should be filled in prior to calling this function: 976 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 977 * subsystem_vendor_id, and revision_id 978 **/ 979enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw) 980{ 981 enum i40e_status_code status = I40E_SUCCESS; 982 u32 port, ari, func_rid; 983 984 DEBUGFUNC("i40e_init_shared_code"); 985 986 i40e_set_mac_type(hw); 987 988 switch (hw->mac.type) { 989 case I40E_MAC_XL710: 990 case I40E_MAC_X722: 991 break; 992 default: 993 return I40E_ERR_DEVICE_NOT_SUPPORTED; 994 } 995 996 hw->phy.get_link_info = TRUE; 997 998 /* Determine port number and PF number*/ 999 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 1000 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 1001 hw->port = (u8)port; 1002 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 1003 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 1004 func_rid = rd32(hw, I40E_PF_FUNC_RID); 1005 if (ari) 1006 hw->pf_id = (u8)(func_rid & 0xff); 1007 else 1008 hw->pf_id = (u8)(func_rid & 0x7); 1009 1010 if (hw->mac.type == I40E_MAC_X722) 1011 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE; 1012 1013 status = i40e_init_nvm(hw); 1014 return status; 1015} 1016 1017/** 1018 * i40e_aq_mac_address_read - Retrieve the MAC addresses 1019 * @hw: pointer to the hw struct 1020 * @flags: a return indicator of what addresses were added to the addr store 1021 * @addrs: the requestor's mac addr store 1022 * @cmd_details: pointer to command details structure or NULL 1023 **/ 1024static enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw, 1025 u16 *flags, 1026 struct i40e_aqc_mac_address_read_data *addrs, 1027 struct i40e_asq_cmd_details *cmd_details) 1028{ 1029 struct i40e_aq_desc desc; 1030 struct i40e_aqc_mac_address_read *cmd_data = 1031 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 1032 enum i40e_status_code status; 1033 1034 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 1035 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 1036 1037 status = i40e_asq_send_command(hw, &desc, addrs, 1038 sizeof(*addrs), cmd_details); 1039 *flags = LE16_TO_CPU(cmd_data->command_flags); 1040 1041 return status; 1042} 1043 1044/** 1045 * i40e_aq_mac_address_write - Change the MAC addresses 1046 * @hw: pointer to the hw struct 1047 * @flags: indicates which MAC to be written 1048 * @mac_addr: address to write 1049 * @cmd_details: pointer to command details structure or NULL 1050 **/ 1051enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw, 1052 u16 flags, u8 *mac_addr, 1053 struct i40e_asq_cmd_details *cmd_details) 1054{ 1055 struct i40e_aq_desc desc; 1056 struct i40e_aqc_mac_address_write *cmd_data = 1057 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 1058 enum i40e_status_code status; 1059 1060 i40e_fill_default_direct_cmd_desc(&desc, 1061 i40e_aqc_opc_mac_address_write); 1062 cmd_data->command_flags = CPU_TO_LE16(flags); 1063 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]); 1064 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) | 1065 ((u32)mac_addr[3] << 16) | 1066 ((u32)mac_addr[4] << 8) | 1067 mac_addr[5]); 1068 1069 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1070 1071 return status; 1072} 1073 1074/** 1075 * i40e_get_mac_addr - get MAC address 1076 * @hw: pointer to the HW structure 1077 * @mac_addr: pointer to MAC address 1078 * 1079 * Reads the adapter's MAC address from register 1080 **/ 1081enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1082{ 1083 struct i40e_aqc_mac_address_read_data addrs; 1084 enum i40e_status_code status; 1085 u16 flags = 0; 1086 1087 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1088 1089 if (flags & I40E_AQC_LAN_ADDR_VALID) 1090 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac), 1091 I40E_NONDMA_TO_NONDMA); 1092 1093 return status; 1094} 1095 1096/** 1097 * i40e_get_port_mac_addr - get Port MAC address 1098 * @hw: pointer to the HW structure 1099 * @mac_addr: pointer to Port MAC address 1100 * 1101 * Reads the adapter's Port MAC address 1102 **/ 1103enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1104{ 1105 struct i40e_aqc_mac_address_read_data addrs; 1106 enum i40e_status_code status; 1107 u16 flags = 0; 1108 1109 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1110 if (status) 1111 return status; 1112 1113 if (flags & I40E_AQC_PORT_ADDR_VALID) 1114 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac), 1115 I40E_NONDMA_TO_NONDMA); 1116 else 1117 status = I40E_ERR_INVALID_MAC_ADDR; 1118 1119 return status; 1120} 1121 1122/** 1123 * i40e_pre_tx_queue_cfg - pre tx queue configure 1124 * @hw: pointer to the HW structure 1125 * @queue: target pf queue index 1126 * @enable: state change request 1127 * 1128 * Handles hw requirement to indicate intention to enable 1129 * or disable target queue. 1130 **/ 1131void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 1132{ 1133 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 1134 u32 reg_block = 0; 1135 u32 reg_val; 1136 1137 if (abs_queue_idx >= 128) { 1138 reg_block = abs_queue_idx / 128; 1139 abs_queue_idx %= 128; 1140 } 1141 1142 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1143 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1144 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1145 1146 if (enable) 1147 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 1148 else 1149 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1150 1151 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 1152} 1153 1154/** 1155 * i40e_read_pba_string - Reads part number string from EEPROM 1156 * @hw: pointer to hardware structure 1157 * @pba_num: stores the part number string from the EEPROM 1158 * @pba_num_size: part number string buffer length 1159 * 1160 * Reads the part number string from the EEPROM. 1161 **/ 1162enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 1163 u32 pba_num_size) 1164{ 1165 enum i40e_status_code status = I40E_SUCCESS; 1166 u16 pba_word = 0; 1167 u16 pba_size = 0; 1168 u16 pba_ptr = 0; 1169 u16 i = 0; 1170 1171 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 1172 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) { 1173 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n"); 1174 return status; 1175 } 1176 1177 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 1178 if (status != I40E_SUCCESS) { 1179 DEBUGOUT("Failed to read PBA Block pointer.\n"); 1180 return status; 1181 } 1182 1183 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1184 if (status != I40E_SUCCESS) { 1185 DEBUGOUT("Failed to read PBA Block size.\n"); 1186 return status; 1187 } 1188 1189 /* Subtract one to get PBA word count (PBA Size word is included in 1190 * total size) 1191 */ 1192 pba_size--; 1193 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1194 DEBUGOUT("Buffer to small for PBA data.\n"); 1195 return I40E_ERR_PARAM; 1196 } 1197 1198 for (i = 0; i < pba_size; i++) { 1199 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1200 if (status != I40E_SUCCESS) { 1201 DEBUGOUT1("Failed to read PBA Block word %d.\n", i); 1202 return status; 1203 } 1204 1205 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1206 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1207 } 1208 pba_num[(pba_size * 2)] = '\0'; 1209 1210 return status; 1211} 1212 1213/** 1214 * i40e_get_media_type - Gets media type 1215 * @hw: pointer to the hardware structure 1216 **/ 1217static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1218{ 1219 enum i40e_media_type media; 1220 1221 switch (hw->phy.link_info.phy_type) { 1222 case I40E_PHY_TYPE_10GBASE_SR: 1223 case I40E_PHY_TYPE_10GBASE_LR: 1224 case I40E_PHY_TYPE_1000BASE_SX: 1225 case I40E_PHY_TYPE_1000BASE_LX: 1226 case I40E_PHY_TYPE_40GBASE_SR4: 1227 case I40E_PHY_TYPE_40GBASE_LR4: 1228 case I40E_PHY_TYPE_25GBASE_LR: 1229 case I40E_PHY_TYPE_25GBASE_SR: 1230 media = I40E_MEDIA_TYPE_FIBER; 1231 break; 1232 case I40E_PHY_TYPE_100BASE_TX: 1233 case I40E_PHY_TYPE_1000BASE_T: 1234 case I40E_PHY_TYPE_10GBASE_T: 1235 media = I40E_MEDIA_TYPE_BASET; 1236 break; 1237 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1238 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1239 case I40E_PHY_TYPE_10GBASE_CR1: 1240 case I40E_PHY_TYPE_40GBASE_CR4: 1241 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1242 case I40E_PHY_TYPE_40GBASE_AOC: 1243 case I40E_PHY_TYPE_10GBASE_AOC: 1244 case I40E_PHY_TYPE_25GBASE_CR: 1245 media = I40E_MEDIA_TYPE_DA; 1246 break; 1247 case I40E_PHY_TYPE_1000BASE_KX: 1248 case I40E_PHY_TYPE_10GBASE_KX4: 1249 case I40E_PHY_TYPE_10GBASE_KR: 1250 case I40E_PHY_TYPE_40GBASE_KR4: 1251 case I40E_PHY_TYPE_20GBASE_KR2: 1252 case I40E_PHY_TYPE_25GBASE_KR: 1253 media = I40E_MEDIA_TYPE_BACKPLANE; 1254 break; 1255 case I40E_PHY_TYPE_SGMII: 1256 case I40E_PHY_TYPE_XAUI: 1257 case I40E_PHY_TYPE_XFI: 1258 case I40E_PHY_TYPE_XLAUI: 1259 case I40E_PHY_TYPE_XLPPI: 1260 default: 1261 media = I40E_MEDIA_TYPE_UNKNOWN; 1262 break; 1263 } 1264 1265 return media; 1266} 1267 1268#define I40E_PF_RESET_WAIT_COUNT 200 1269/** 1270 * i40e_pf_reset - Reset the PF 1271 * @hw: pointer to the hardware structure 1272 * 1273 * Assuming someone else has triggered a global reset, 1274 * assure the global reset is complete and then reset the PF 1275 **/ 1276enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw) 1277{ 1278 u32 cnt = 0; 1279 u32 cnt1 = 0; 1280 u32 reg = 0; 1281 u32 grst_del; 1282 1283 /* Poll for Global Reset steady state in case of recent GRST. 1284 * The grst delay value is in 100ms units, and we'll wait a 1285 * couple counts longer to be sure we don't just miss the end. 1286 */ 1287 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1288 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1289 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1290 1291 grst_del = grst_del * 20; 1292 1293 for (cnt = 0; cnt < grst_del; cnt++) { 1294 reg = rd32(hw, I40E_GLGEN_RSTAT); 1295 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1296 break; 1297 i40e_msec_delay(100); 1298 } 1299 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1300 DEBUGOUT("Global reset polling failed to complete.\n"); 1301 return I40E_ERR_RESET_FAILED; 1302 } 1303 1304 /* Now Wait for the FW to be ready */ 1305 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1306 reg = rd32(hw, I40E_GLNVM_ULD); 1307 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1308 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1309 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1310 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1311 DEBUGOUT1("Core and Global modules ready %d\n", cnt1); 1312 break; 1313 } 1314 i40e_msec_delay(10); 1315 } 1316 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1317 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1318 DEBUGOUT("wait for FW Reset complete timedout\n"); 1319 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg); 1320 return I40E_ERR_RESET_FAILED; 1321 } 1322 1323 /* If there was a Global Reset in progress when we got here, 1324 * we don't need to do the PF Reset 1325 */ 1326 if (!cnt) { 1327 reg = rd32(hw, I40E_PFGEN_CTRL); 1328 wr32(hw, I40E_PFGEN_CTRL, 1329 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1330 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { 1331 reg = rd32(hw, I40E_PFGEN_CTRL); 1332 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1333 break; 1334 i40e_msec_delay(1); 1335 } 1336 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1337 DEBUGOUT("PF reset polling failed to complete.\n"); 1338 return I40E_ERR_RESET_FAILED; 1339 } 1340 } 1341 1342 i40e_clear_pxe_mode(hw); 1343 1344 1345 return I40E_SUCCESS; 1346} 1347 1348/** 1349 * i40e_clear_hw - clear out any left over hw state 1350 * @hw: pointer to the hw struct 1351 * 1352 * Clear queues and interrupts, typically called at init time, 1353 * but after the capabilities have been found so we know how many 1354 * queues and msix vectors have been allocated. 1355 **/ 1356void i40e_clear_hw(struct i40e_hw *hw) 1357{ 1358 u32 num_queues, base_queue; 1359 u32 num_pf_int; 1360 u32 num_vf_int; 1361 u32 num_vfs; 1362 u32 i, j; 1363 u32 val; 1364 u32 eol = 0x7ff; 1365 1366 /* get number of interrupts, queues, and vfs */ 1367 val = rd32(hw, I40E_GLPCI_CNF2); 1368 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1369 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1370 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1371 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1372 1373 val = rd32(hw, I40E_PFLAN_QALLOC); 1374 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1375 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1376 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1377 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1378 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1379 num_queues = (j - base_queue) + 1; 1380 else 1381 num_queues = 0; 1382 1383 val = rd32(hw, I40E_PF_VT_PFALLOC); 1384 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1385 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1386 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1387 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1388 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1389 num_vfs = (j - i) + 1; 1390 else 1391 num_vfs = 0; 1392 1393 /* stop all the interrupts */ 1394 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1395 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1396 for (i = 0; i < num_pf_int - 2; i++) 1397 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1398 1399 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1400 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1401 wr32(hw, I40E_PFINT_LNKLST0, val); 1402 for (i = 0; i < num_pf_int - 2; i++) 1403 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1404 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1405 for (i = 0; i < num_vfs; i++) 1406 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1407 for (i = 0; i < num_vf_int - 2; i++) 1408 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1409 1410 /* warn the HW of the coming Tx disables */ 1411 for (i = 0; i < num_queues; i++) { 1412 u32 abs_queue_idx = base_queue + i; 1413 u32 reg_block = 0; 1414 1415 if (abs_queue_idx >= 128) { 1416 reg_block = abs_queue_idx / 128; 1417 abs_queue_idx %= 128; 1418 } 1419 1420 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1421 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1422 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1423 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1424 1425 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1426 } 1427 i40e_usec_delay(400); 1428 1429 /* stop all the queues */ 1430 for (i = 0; i < num_queues; i++) { 1431 wr32(hw, I40E_QINT_TQCTL(i), 0); 1432 wr32(hw, I40E_QTX_ENA(i), 0); 1433 wr32(hw, I40E_QINT_RQCTL(i), 0); 1434 wr32(hw, I40E_QRX_ENA(i), 0); 1435 } 1436 1437 /* short wait for all queue disables to settle */ 1438 i40e_usec_delay(50); 1439} 1440 1441/** 1442 * i40e_clear_pxe_mode - clear pxe operations mode 1443 * @hw: pointer to the hw struct 1444 * 1445 * Make sure all PXE mode settings are cleared, including things 1446 * like descriptor fetch/write-back mode. 1447 **/ 1448void i40e_clear_pxe_mode(struct i40e_hw *hw) 1449{ 1450 if (i40e_check_asq_alive(hw)) 1451 i40e_aq_clear_pxe_mode(hw, NULL); 1452} 1453 1454/** 1455 * i40e_led_is_mine - helper to find matching led 1456 * @hw: pointer to the hw struct 1457 * @idx: index into GPIO registers 1458 * 1459 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1460 */ 1461static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1462{ 1463 u32 gpio_val = 0; 1464 u32 port; 1465 1466 if (!hw->func_caps.led[idx]) 1467 return 0; 1468 1469 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1470 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1471 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1472 1473 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1474 * if it is not our port then ignore 1475 */ 1476 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1477 (port != hw->port)) 1478 return 0; 1479 1480 return gpio_val; 1481} 1482 1483#define I40E_COMBINED_ACTIVITY 0xA 1484#define I40E_FILTER_ACTIVITY 0xE 1485#define I40E_LINK_ACTIVITY 0xC 1486#define I40E_MAC_ACTIVITY 0xD 1487#define I40E_LED0 22 1488 1489/** 1490 * i40e_led_get - return current on/off mode 1491 * @hw: pointer to the hw struct 1492 * 1493 * The value returned is the 'mode' field as defined in the 1494 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1495 * values are variations of possible behaviors relating to 1496 * blink, link, and wire. 1497 **/ 1498u32 i40e_led_get(struct i40e_hw *hw) 1499{ 1500 u32 current_mode = 0; 1501 u32 mode = 0; 1502 int i; 1503 1504 /* as per the documentation GPIO 22-29 are the LED 1505 * GPIO pins named LED0..LED7 1506 */ 1507 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1508 u32 gpio_val = i40e_led_is_mine(hw, i); 1509 1510 if (!gpio_val) 1511 continue; 1512 1513 /* ignore gpio LED src mode entries related to the activity 1514 * LEDs 1515 */ 1516 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1517 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1518 switch (current_mode) { 1519 case I40E_COMBINED_ACTIVITY: 1520 case I40E_FILTER_ACTIVITY: 1521 case I40E_MAC_ACTIVITY: 1522 continue; 1523 default: 1524 break; 1525 } 1526 1527 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1528 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1529 break; 1530 } 1531 1532 return mode; 1533} 1534 1535/** 1536 * i40e_led_set - set new on/off mode 1537 * @hw: pointer to the hw struct 1538 * @mode: 0=off, 0xf=on (else see manual for mode details) 1539 * @blink: TRUE if the LED should blink when on, FALSE if steady 1540 * 1541 * if this function is used to turn on the blink it should 1542 * be used to disable the blink when restoring the original state. 1543 **/ 1544void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1545{ 1546 u32 current_mode = 0; 1547 int i; 1548 1549 if (mode & 0xfffffff0) 1550 DEBUGOUT1("invalid mode passed in %X\n", mode); 1551 1552 /* as per the documentation GPIO 22-29 are the LED 1553 * GPIO pins named LED0..LED7 1554 */ 1555 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1556 u32 gpio_val = i40e_led_is_mine(hw, i); 1557 1558 if (!gpio_val) 1559 continue; 1560 1561 /* ignore gpio LED src mode entries related to the activity 1562 * LEDs 1563 */ 1564 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1565 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1566 switch (current_mode) { 1567 case I40E_COMBINED_ACTIVITY: 1568 case I40E_FILTER_ACTIVITY: 1569 case I40E_MAC_ACTIVITY: 1570 continue; 1571 default: 1572 break; 1573 } 1574 1575 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1576 /* this & is a bit of paranoia, but serves as a range check */ 1577 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1578 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1579 1580 if (mode == I40E_LINK_ACTIVITY) 1581 blink = FALSE; 1582 1583 if (blink) 1584 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1585 else 1586 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1587 1588 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1589 break; 1590 } 1591} 1592 1593/* Admin command wrappers */ 1594 1595/** 1596 * i40e_aq_get_phy_capabilities 1597 * @hw: pointer to the hw struct 1598 * @abilities: structure for PHY capabilities to be filled 1599 * @qualified_modules: report Qualified Modules 1600 * @report_init: report init capabilities (active are default) 1601 * @cmd_details: pointer to command details structure or NULL 1602 * 1603 * Returns the various PHY abilities supported on the Port. 1604 **/ 1605enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1606 bool qualified_modules, bool report_init, 1607 struct i40e_aq_get_phy_abilities_resp *abilities, 1608 struct i40e_asq_cmd_details *cmd_details) 1609{ 1610 struct i40e_aq_desc desc; 1611 enum i40e_status_code status; 1612 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1613 1614 if (!abilities) 1615 return I40E_ERR_PARAM; 1616 1617 i40e_fill_default_direct_cmd_desc(&desc, 1618 i40e_aqc_opc_get_phy_abilities); 1619 1620 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 1621 if (abilities_size > I40E_AQ_LARGE_BUF) 1622 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 1623 1624 if (qualified_modules) 1625 desc.params.external.param0 |= 1626 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1627 1628 if (report_init) 1629 desc.params.external.param0 |= 1630 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1631 1632 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size, 1633 cmd_details); 1634 1635 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) 1636 status = I40E_ERR_UNKNOWN_PHY; 1637 1638 if (report_init) { 1639 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type); 1640 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32); 1641 } 1642 1643 return status; 1644} 1645 1646/** 1647 * i40e_aq_set_phy_config 1648 * @hw: pointer to the hw struct 1649 * @config: structure with PHY configuration to be set 1650 * @cmd_details: pointer to command details structure or NULL 1651 * 1652 * Set the various PHY configuration parameters 1653 * supported on the Port.One or more of the Set PHY config parameters may be 1654 * ignored in an MFP mode as the PF may not have the privilege to set some 1655 * of the PHY Config parameters. This status will be indicated by the 1656 * command response. 1657 **/ 1658enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1659 struct i40e_aq_set_phy_config *config, 1660 struct i40e_asq_cmd_details *cmd_details) 1661{ 1662 struct i40e_aq_desc desc; 1663 struct i40e_aq_set_phy_config *cmd = 1664 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1665 enum i40e_status_code status; 1666 1667 if (!config) 1668 return I40E_ERR_PARAM; 1669 1670 i40e_fill_default_direct_cmd_desc(&desc, 1671 i40e_aqc_opc_set_phy_config); 1672 1673 *cmd = *config; 1674 1675 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1676 1677 return status; 1678} 1679 1680/** 1681 * i40e_set_fc 1682 * @hw: pointer to the hw struct 1683 * 1684 * Set the requested flow control mode using set_phy_config. 1685 **/ 1686enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1687 bool atomic_restart) 1688{ 1689 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1690 struct i40e_aq_get_phy_abilities_resp abilities; 1691 struct i40e_aq_set_phy_config config; 1692 enum i40e_status_code status; 1693 u8 pause_mask = 0x0; 1694 1695 *aq_failures = 0x0; 1696 1697 switch (fc_mode) { 1698 case I40E_FC_FULL: 1699 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1700 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1701 break; 1702 case I40E_FC_RX_PAUSE: 1703 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1704 break; 1705 case I40E_FC_TX_PAUSE: 1706 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1707 break; 1708 default: 1709 break; 1710 } 1711 1712 /* Get the current phy config */ 1713 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities, 1714 NULL); 1715 if (status) { 1716 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1717 return status; 1718 } 1719 1720 memset(&config, 0, sizeof(config)); 1721 /* clear the old pause settings */ 1722 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1723 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1724 /* set the new abilities */ 1725 config.abilities |= pause_mask; 1726 /* If the abilities have changed, then set the new config */ 1727 if (config.abilities != abilities.abilities) { 1728 /* Auto restart link so settings take effect */ 1729 if (atomic_restart) 1730 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1731 /* Copy over all the old settings */ 1732 config.phy_type = abilities.phy_type; 1733 config.phy_type_ext = abilities.phy_type_ext; 1734 config.link_speed = abilities.link_speed; 1735 config.eee_capability = abilities.eee_capability; 1736 config.eeer = abilities.eeer_val; 1737 config.low_power_ctrl = abilities.d3_lpan; 1738 config.fec_config = abilities.fec_cfg_curr_mod_ext_info & 1739 I40E_AQ_PHY_FEC_CONFIG_MASK; 1740 status = i40e_aq_set_phy_config(hw, &config, NULL); 1741 1742 if (status) 1743 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1744 } 1745 /* Update the link info */ 1746 status = i40e_update_link_info(hw); 1747 if (status) { 1748 /* Wait a little bit (on 40G cards it sometimes takes a really 1749 * long time for link to come back from the atomic reset) 1750 * and try once more 1751 */ 1752 i40e_msec_delay(1000); 1753 status = i40e_update_link_info(hw); 1754 } 1755 if (status) 1756 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1757 1758 return status; 1759} 1760 1761/** 1762 * i40e_aq_set_mac_config 1763 * @hw: pointer to the hw struct 1764 * @max_frame_size: Maximum Frame Size to be supported by the port 1765 * @crc_en: Tell HW to append a CRC to outgoing frames 1766 * @pacing: Pacing configurations 1767 * @cmd_details: pointer to command details structure or NULL 1768 * 1769 * Configure MAC settings for frame size, jumbo frame support and the 1770 * addition of a CRC by the hardware. 1771 **/ 1772enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw, 1773 u16 max_frame_size, 1774 bool crc_en, u16 pacing, 1775 struct i40e_asq_cmd_details *cmd_details) 1776{ 1777 struct i40e_aq_desc desc; 1778 struct i40e_aq_set_mac_config *cmd = 1779 (struct i40e_aq_set_mac_config *)&desc.params.raw; 1780 enum i40e_status_code status; 1781 1782 if (max_frame_size == 0) 1783 return I40E_ERR_PARAM; 1784 1785 i40e_fill_default_direct_cmd_desc(&desc, 1786 i40e_aqc_opc_set_mac_config); 1787 1788 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 1789 cmd->params = ((u8)pacing & 0x0F) << 3; 1790 if (crc_en) 1791 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN; 1792 1793 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1794 1795 return status; 1796} 1797 1798/** 1799 * i40e_aq_clear_pxe_mode 1800 * @hw: pointer to the hw struct 1801 * @cmd_details: pointer to command details structure or NULL 1802 * 1803 * Tell the firmware that the driver is taking over from PXE 1804 **/ 1805enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1806 struct i40e_asq_cmd_details *cmd_details) 1807{ 1808 enum i40e_status_code status; 1809 struct i40e_aq_desc desc; 1810 struct i40e_aqc_clear_pxe *cmd = 1811 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1812 1813 i40e_fill_default_direct_cmd_desc(&desc, 1814 i40e_aqc_opc_clear_pxe_mode); 1815 1816 cmd->rx_cnt = 0x2; 1817 1818 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1819 1820 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1821 1822 return status; 1823} 1824 1825/** 1826 * i40e_aq_set_link_restart_an 1827 * @hw: pointer to the hw struct 1828 * @enable_link: if TRUE: enable link, if FALSE: disable link 1829 * @cmd_details: pointer to command details structure or NULL 1830 * 1831 * Sets up the link and restarts the Auto-Negotiation over the link. 1832 **/ 1833enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1834 bool enable_link, struct i40e_asq_cmd_details *cmd_details) 1835{ 1836 struct i40e_aq_desc desc; 1837 struct i40e_aqc_set_link_restart_an *cmd = 1838 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1839 enum i40e_status_code status; 1840 1841 i40e_fill_default_direct_cmd_desc(&desc, 1842 i40e_aqc_opc_set_link_restart_an); 1843 1844 cmd->command = I40E_AQ_PHY_RESTART_AN; 1845 if (enable_link) 1846 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1847 else 1848 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1849 1850 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1851 1852 return status; 1853} 1854 1855/** 1856 * i40e_aq_get_link_info 1857 * @hw: pointer to the hw struct 1858 * @enable_lse: enable/disable LinkStatusEvent reporting 1859 * @link: pointer to link status structure - optional 1860 * @cmd_details: pointer to command details structure or NULL 1861 * 1862 * Returns the link status of the adapter. 1863 **/ 1864enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw, 1865 bool enable_lse, struct i40e_link_status *link, 1866 struct i40e_asq_cmd_details *cmd_details) 1867{ 1868 struct i40e_aq_desc desc; 1869 struct i40e_aqc_get_link_status *resp = 1870 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1871 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1872 enum i40e_status_code status; 1873 bool tx_pause, rx_pause; 1874 u16 command_flags; 1875 1876 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1877 1878 if (enable_lse) 1879 command_flags = I40E_AQ_LSE_ENABLE; 1880 else 1881 command_flags = I40E_AQ_LSE_DISABLE; 1882 resp->command_flags = CPU_TO_LE16(command_flags); 1883 1884 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1885 1886 if (status != I40E_SUCCESS) 1887 goto aq_get_link_info_exit; 1888 1889 /* save off old link status information */ 1890 i40e_memcpy(&hw->phy.link_info_old, hw_link_info, 1891 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA); 1892 1893 /* update link status */ 1894 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1895 hw->phy.media_type = i40e_get_media_type(hw); 1896 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1897 hw_link_info->link_info = resp->link_info; 1898 hw_link_info->an_info = resp->an_info; 1899 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA | 1900 I40E_AQ_CONFIG_FEC_RS_ENA); 1901 hw_link_info->ext_info = resp->ext_info; 1902 hw_link_info->loopback = resp->loopback; 1903 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size); 1904 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1905 1906 /* update fc info */ 1907 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1908 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1909 if (tx_pause & rx_pause) 1910 hw->fc.current_mode = I40E_FC_FULL; 1911 else if (tx_pause) 1912 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1913 else if (rx_pause) 1914 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1915 else 1916 hw->fc.current_mode = I40E_FC_NONE; 1917 1918 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1919 hw_link_info->crc_enable = TRUE; 1920 else 1921 hw_link_info->crc_enable = FALSE; 1922 1923 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED)) 1924 hw_link_info->lse_enable = TRUE; 1925 else 1926 hw_link_info->lse_enable = FALSE; 1927 1928 if ((hw->mac.type == I40E_MAC_XL710) && 1929 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 1930 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 1931 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1932 1933 /* save link status information */ 1934 if (link) 1935 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info), 1936 I40E_NONDMA_TO_NONDMA); 1937 1938 /* flag cleared so helper functions don't call AQ again */ 1939 hw->phy.get_link_info = FALSE; 1940 1941aq_get_link_info_exit: 1942 return status; 1943} 1944 1945/** 1946 * i40e_aq_set_phy_int_mask 1947 * @hw: pointer to the hw struct 1948 * @mask: interrupt mask to be set 1949 * @cmd_details: pointer to command details structure or NULL 1950 * 1951 * Set link interrupt mask. 1952 **/ 1953enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1954 u16 mask, 1955 struct i40e_asq_cmd_details *cmd_details) 1956{ 1957 struct i40e_aq_desc desc; 1958 struct i40e_aqc_set_phy_int_mask *cmd = 1959 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1960 enum i40e_status_code status; 1961 1962 i40e_fill_default_direct_cmd_desc(&desc, 1963 i40e_aqc_opc_set_phy_int_mask); 1964 1965 cmd->event_mask = CPU_TO_LE16(mask); 1966 1967 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1968 1969 return status; 1970} 1971 1972/** 1973 * i40e_aq_get_local_advt_reg 1974 * @hw: pointer to the hw struct 1975 * @advt_reg: local AN advertisement register value 1976 * @cmd_details: pointer to command details structure or NULL 1977 * 1978 * Get the Local AN advertisement register value. 1979 **/ 1980enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw, 1981 u64 *advt_reg, 1982 struct i40e_asq_cmd_details *cmd_details) 1983{ 1984 struct i40e_aq_desc desc; 1985 struct i40e_aqc_an_advt_reg *resp = 1986 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 1987 enum i40e_status_code status; 1988 1989 i40e_fill_default_direct_cmd_desc(&desc, 1990 i40e_aqc_opc_get_local_advt_reg); 1991 1992 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1993 1994 if (status != I40E_SUCCESS) 1995 goto aq_get_local_advt_reg_exit; 1996 1997 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 1998 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 1999 2000aq_get_local_advt_reg_exit: 2001 return status; 2002} 2003 2004/** 2005 * i40e_aq_set_local_advt_reg 2006 * @hw: pointer to the hw struct 2007 * @advt_reg: local AN advertisement register value 2008 * @cmd_details: pointer to command details structure or NULL 2009 * 2010 * Get the Local AN advertisement register value. 2011 **/ 2012enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw, 2013 u64 advt_reg, 2014 struct i40e_asq_cmd_details *cmd_details) 2015{ 2016 struct i40e_aq_desc desc; 2017 struct i40e_aqc_an_advt_reg *cmd = 2018 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2019 enum i40e_status_code status; 2020 2021 i40e_fill_default_direct_cmd_desc(&desc, 2022 i40e_aqc_opc_get_local_advt_reg); 2023 2024 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg)); 2025 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg)); 2026 2027 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2028 2029 return status; 2030} 2031 2032/** 2033 * i40e_aq_get_partner_advt 2034 * @hw: pointer to the hw struct 2035 * @advt_reg: AN partner advertisement register value 2036 * @cmd_details: pointer to command details structure or NULL 2037 * 2038 * Get the link partner AN advertisement register value. 2039 **/ 2040enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw, 2041 u64 *advt_reg, 2042 struct i40e_asq_cmd_details *cmd_details) 2043{ 2044 struct i40e_aq_desc desc; 2045 struct i40e_aqc_an_advt_reg *resp = 2046 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2047 enum i40e_status_code status; 2048 2049 i40e_fill_default_direct_cmd_desc(&desc, 2050 i40e_aqc_opc_get_partner_advt); 2051 2052 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2053 2054 if (status != I40E_SUCCESS) 2055 goto aq_get_partner_advt_exit; 2056 2057 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 2058 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 2059 2060aq_get_partner_advt_exit: 2061 return status; 2062} 2063 2064/** 2065 * i40e_aq_set_lb_modes 2066 * @hw: pointer to the hw struct 2067 * @lb_modes: loopback mode to be set 2068 * @cmd_details: pointer to command details structure or NULL 2069 * 2070 * Sets loopback modes. 2071 **/ 2072enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw, 2073 u16 lb_modes, 2074 struct i40e_asq_cmd_details *cmd_details) 2075{ 2076 struct i40e_aq_desc desc; 2077 struct i40e_aqc_set_lb_mode *cmd = 2078 (struct i40e_aqc_set_lb_mode *)&desc.params.raw; 2079 enum i40e_status_code status; 2080 2081 i40e_fill_default_direct_cmd_desc(&desc, 2082 i40e_aqc_opc_set_lb_modes); 2083 2084 cmd->lb_mode = CPU_TO_LE16(lb_modes); 2085 2086 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2087 2088 return status; 2089} 2090 2091/** 2092 * i40e_aq_set_phy_debug 2093 * @hw: pointer to the hw struct 2094 * @cmd_flags: debug command flags 2095 * @cmd_details: pointer to command details structure or NULL 2096 * 2097 * Reset the external PHY. 2098 **/ 2099enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 2100 struct i40e_asq_cmd_details *cmd_details) 2101{ 2102 struct i40e_aq_desc desc; 2103 struct i40e_aqc_set_phy_debug *cmd = 2104 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 2105 enum i40e_status_code status; 2106 2107 i40e_fill_default_direct_cmd_desc(&desc, 2108 i40e_aqc_opc_set_phy_debug); 2109 2110 cmd->command_flags = cmd_flags; 2111 2112 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2113 2114 return status; 2115} 2116 2117/** 2118 * i40e_aq_add_vsi 2119 * @hw: pointer to the hw struct 2120 * @vsi_ctx: pointer to a vsi context struct 2121 * @cmd_details: pointer to command details structure or NULL 2122 * 2123 * Add a VSI context to the hardware. 2124**/ 2125enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw, 2126 struct i40e_vsi_context *vsi_ctx, 2127 struct i40e_asq_cmd_details *cmd_details) 2128{ 2129 struct i40e_aq_desc desc; 2130 struct i40e_aqc_add_get_update_vsi *cmd = 2131 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2132 struct i40e_aqc_add_get_update_vsi_completion *resp = 2133 (struct i40e_aqc_add_get_update_vsi_completion *) 2134 &desc.params.raw; 2135 enum i40e_status_code status; 2136 2137 i40e_fill_default_direct_cmd_desc(&desc, 2138 i40e_aqc_opc_add_vsi); 2139 2140 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid); 2141 cmd->connection_type = vsi_ctx->connection_type; 2142 cmd->vf_id = vsi_ctx->vf_num; 2143 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags); 2144 2145 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2146 2147 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2148 sizeof(vsi_ctx->info), cmd_details); 2149 2150 if (status != I40E_SUCCESS) 2151 goto aq_add_vsi_exit; 2152 2153 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2154 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2155 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2156 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2157 2158aq_add_vsi_exit: 2159 return status; 2160} 2161 2162/** 2163 * i40e_aq_set_default_vsi 2164 * @hw: pointer to the hw struct 2165 * @seid: vsi number 2166 * @cmd_details: pointer to command details structure or NULL 2167 **/ 2168enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw, 2169 u16 seid, 2170 struct i40e_asq_cmd_details *cmd_details) 2171{ 2172 struct i40e_aq_desc desc; 2173 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2174 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2175 &desc.params.raw; 2176 enum i40e_status_code status; 2177 2178 i40e_fill_default_direct_cmd_desc(&desc, 2179 i40e_aqc_opc_set_vsi_promiscuous_modes); 2180 2181 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2182 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2183 cmd->seid = CPU_TO_LE16(seid); 2184 2185 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2186 2187 return status; 2188} 2189 2190/** 2191 * i40e_aq_clear_default_vsi 2192 * @hw: pointer to the hw struct 2193 * @seid: vsi number 2194 * @cmd_details: pointer to command details structure or NULL 2195 **/ 2196enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw, 2197 u16 seid, 2198 struct i40e_asq_cmd_details *cmd_details) 2199{ 2200 struct i40e_aq_desc desc; 2201 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2202 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2203 &desc.params.raw; 2204 enum i40e_status_code status; 2205 2206 i40e_fill_default_direct_cmd_desc(&desc, 2207 i40e_aqc_opc_set_vsi_promiscuous_modes); 2208 2209 cmd->promiscuous_flags = CPU_TO_LE16(0); 2210 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2211 cmd->seid = CPU_TO_LE16(seid); 2212 2213 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2214 2215 return status; 2216} 2217 2218/** 2219 * i40e_aq_set_vsi_unicast_promiscuous 2220 * @hw: pointer to the hw struct 2221 * @seid: vsi number 2222 * @set: set unicast promiscuous enable/disable 2223 * @cmd_details: pointer to command details structure or NULL 2224 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 2225 **/ 2226enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 2227 u16 seid, bool set, 2228 struct i40e_asq_cmd_details *cmd_details, 2229 bool rx_only_promisc) 2230{ 2231 struct i40e_aq_desc desc; 2232 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2233 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2234 enum i40e_status_code status; 2235 u16 flags = 0; 2236 2237 i40e_fill_default_direct_cmd_desc(&desc, 2238 i40e_aqc_opc_set_vsi_promiscuous_modes); 2239 2240 if (set) { 2241 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2242 if (rx_only_promisc && 2243 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) || 2244 (hw->aq.api_maj_ver > 1))) 2245 flags |= I40E_AQC_SET_VSI_PROMISC_TX; 2246 } 2247 2248 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2249 2250 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2251 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) || 2252 (hw->aq.api_maj_ver > 1)) 2253 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX); 2254 2255 cmd->seid = CPU_TO_LE16(seid); 2256 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2257 2258 return status; 2259} 2260 2261/** 2262 * i40e_aq_set_vsi_multicast_promiscuous 2263 * @hw: pointer to the hw struct 2264 * @seid: vsi number 2265 * @set: set multicast promiscuous enable/disable 2266 * @cmd_details: pointer to command details structure or NULL 2267 **/ 2268enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 2269 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 2270{ 2271 struct i40e_aq_desc desc; 2272 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2273 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2274 enum i40e_status_code status; 2275 u16 flags = 0; 2276 2277 i40e_fill_default_direct_cmd_desc(&desc, 2278 i40e_aqc_opc_set_vsi_promiscuous_modes); 2279 2280 if (set) 2281 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2282 2283 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2284 2285 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2286 2287 cmd->seid = CPU_TO_LE16(seid); 2288 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2289 2290 return status; 2291} 2292 2293/** 2294* i40e_aq_set_vsi_full_promiscuous 2295* @hw: pointer to the hw struct 2296* @seid: VSI number 2297* @set: set promiscuous enable/disable 2298* @cmd_details: pointer to command details structure or NULL 2299**/ 2300enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw, 2301 u16 seid, bool set, 2302 struct i40e_asq_cmd_details *cmd_details) 2303{ 2304 struct i40e_aq_desc desc; 2305 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2306 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2307 enum i40e_status_code status; 2308 u16 flags = 0; 2309 2310 i40e_fill_default_direct_cmd_desc(&desc, 2311 i40e_aqc_opc_set_vsi_promiscuous_modes); 2312 2313 if (set) 2314 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST | 2315 I40E_AQC_SET_VSI_PROMISC_MULTICAST | 2316 I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2317 2318 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2319 2320 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST | 2321 I40E_AQC_SET_VSI_PROMISC_MULTICAST | 2322 I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2323 2324 cmd->seid = CPU_TO_LE16(seid); 2325 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2326 2327 return status; 2328} 2329 2330/** 2331 * i40e_aq_set_vsi_mc_promisc_on_vlan 2332 * @hw: pointer to the hw struct 2333 * @seid: vsi number 2334 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2335 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 2336 * @cmd_details: pointer to command details structure or NULL 2337 **/ 2338enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 2339 u16 seid, bool enable, u16 vid, 2340 struct i40e_asq_cmd_details *cmd_details) 2341{ 2342 struct i40e_aq_desc desc; 2343 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2344 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2345 enum i40e_status_code status; 2346 u16 flags = 0; 2347 2348 i40e_fill_default_direct_cmd_desc(&desc, 2349 i40e_aqc_opc_set_vsi_promiscuous_modes); 2350 2351 if (enable) 2352 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2353 2354 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2355 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2356 cmd->seid = CPU_TO_LE16(seid); 2357 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2358 2359 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2360 2361 return status; 2362} 2363 2364/** 2365 * i40e_aq_set_vsi_uc_promisc_on_vlan 2366 * @hw: pointer to the hw struct 2367 * @seid: vsi number 2368 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2369 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 2370 * @cmd_details: pointer to command details structure or NULL 2371 **/ 2372enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 2373 u16 seid, bool enable, u16 vid, 2374 struct i40e_asq_cmd_details *cmd_details) 2375{ 2376 struct i40e_aq_desc desc; 2377 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2378 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2379 enum i40e_status_code status; 2380 u16 flags = 0; 2381 2382 i40e_fill_default_direct_cmd_desc(&desc, 2383 i40e_aqc_opc_set_vsi_promiscuous_modes); 2384 2385 if (enable) 2386 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2387 2388 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2389 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2390 cmd->seid = CPU_TO_LE16(seid); 2391 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2392 2393 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2394 2395 return status; 2396} 2397 2398/** 2399 * i40e_aq_set_vsi_bc_promisc_on_vlan 2400 * @hw: pointer to the hw struct 2401 * @seid: vsi number 2402 * @enable: set broadcast promiscuous enable/disable for a given VLAN 2403 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 2404 * @cmd_details: pointer to command details structure or NULL 2405 **/ 2406enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 2407 u16 seid, bool enable, u16 vid, 2408 struct i40e_asq_cmd_details *cmd_details) 2409{ 2410 struct i40e_aq_desc desc; 2411 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2412 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2413 enum i40e_status_code status; 2414 u16 flags = 0; 2415 2416 i40e_fill_default_direct_cmd_desc(&desc, 2417 i40e_aqc_opc_set_vsi_promiscuous_modes); 2418 2419 if (enable) 2420 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2421 2422 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2423 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2424 cmd->seid = CPU_TO_LE16(seid); 2425 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2426 2427 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2428 2429 return status; 2430} 2431 2432/** 2433 * i40e_aq_set_vsi_broadcast 2434 * @hw: pointer to the hw struct 2435 * @seid: vsi number 2436 * @set_filter: TRUE to set filter, FALSE to clear filter 2437 * @cmd_details: pointer to command details structure or NULL 2438 * 2439 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2440 **/ 2441enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2442 u16 seid, bool set_filter, 2443 struct i40e_asq_cmd_details *cmd_details) 2444{ 2445 struct i40e_aq_desc desc; 2446 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2447 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2448 enum i40e_status_code status; 2449 2450 i40e_fill_default_direct_cmd_desc(&desc, 2451 i40e_aqc_opc_set_vsi_promiscuous_modes); 2452 2453 if (set_filter) 2454 cmd->promiscuous_flags 2455 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2456 else 2457 cmd->promiscuous_flags 2458 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2459 2460 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2461 cmd->seid = CPU_TO_LE16(seid); 2462 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2463 2464 return status; 2465} 2466 2467/** 2468 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting 2469 * @hw: pointer to the hw struct 2470 * @seid: vsi number 2471 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2472 * @cmd_details: pointer to command details structure or NULL 2473 **/ 2474enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw, 2475 u16 seid, bool enable, 2476 struct i40e_asq_cmd_details *cmd_details) 2477{ 2478 struct i40e_aq_desc desc; 2479 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2480 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2481 enum i40e_status_code status; 2482 u16 flags = 0; 2483 2484 i40e_fill_default_direct_cmd_desc(&desc, 2485 i40e_aqc_opc_set_vsi_promiscuous_modes); 2486 if (enable) 2487 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN; 2488 2489 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2490 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN); 2491 cmd->seid = CPU_TO_LE16(seid); 2492 2493 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2494 2495 return status; 2496} 2497 2498/** 2499 * i40e_get_vsi_params - get VSI configuration info 2500 * @hw: pointer to the hw struct 2501 * @vsi_ctx: pointer to a vsi context struct 2502 * @cmd_details: pointer to command details structure or NULL 2503 **/ 2504enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw, 2505 struct i40e_vsi_context *vsi_ctx, 2506 struct i40e_asq_cmd_details *cmd_details) 2507{ 2508 struct i40e_aq_desc desc; 2509 struct i40e_aqc_add_get_update_vsi *cmd = 2510 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2511 struct i40e_aqc_add_get_update_vsi_completion *resp = 2512 (struct i40e_aqc_add_get_update_vsi_completion *) 2513 &desc.params.raw; 2514 enum i40e_status_code status; 2515 2516 i40e_fill_default_direct_cmd_desc(&desc, 2517 i40e_aqc_opc_get_vsi_parameters); 2518 2519 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2520 2521 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2522 2523 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2524 sizeof(vsi_ctx->info), NULL); 2525 2526 if (status != I40E_SUCCESS) 2527 goto aq_get_vsi_params_exit; 2528 2529 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2530 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2531 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2532 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2533 2534aq_get_vsi_params_exit: 2535 return status; 2536} 2537 2538/** 2539 * i40e_aq_update_vsi_params 2540 * @hw: pointer to the hw struct 2541 * @vsi_ctx: pointer to a vsi context struct 2542 * @cmd_details: pointer to command details structure or NULL 2543 * 2544 * Update a VSI context. 2545 **/ 2546enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw, 2547 struct i40e_vsi_context *vsi_ctx, 2548 struct i40e_asq_cmd_details *cmd_details) 2549{ 2550 struct i40e_aq_desc desc; 2551 struct i40e_aqc_add_get_update_vsi *cmd = 2552 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2553 struct i40e_aqc_add_get_update_vsi_completion *resp = 2554 (struct i40e_aqc_add_get_update_vsi_completion *) 2555 &desc.params.raw; 2556 enum i40e_status_code status; 2557 2558 i40e_fill_default_direct_cmd_desc(&desc, 2559 i40e_aqc_opc_update_vsi_parameters); 2560 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2561 2562 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2563 2564 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2565 sizeof(vsi_ctx->info), cmd_details); 2566 2567 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2568 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2569 2570 return status; 2571} 2572 2573/** 2574 * i40e_aq_get_switch_config 2575 * @hw: pointer to the hardware structure 2576 * @buf: pointer to the result buffer 2577 * @buf_size: length of input buffer 2578 * @start_seid: seid to start for the report, 0 == beginning 2579 * @cmd_details: pointer to command details structure or NULL 2580 * 2581 * Fill the buf with switch configuration returned from AdminQ command 2582 **/ 2583enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw, 2584 struct i40e_aqc_get_switch_config_resp *buf, 2585 u16 buf_size, u16 *start_seid, 2586 struct i40e_asq_cmd_details *cmd_details) 2587{ 2588 struct i40e_aq_desc desc; 2589 struct i40e_aqc_switch_seid *scfg = 2590 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2591 enum i40e_status_code status; 2592 2593 i40e_fill_default_direct_cmd_desc(&desc, 2594 i40e_aqc_opc_get_switch_config); 2595 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2596 if (buf_size > I40E_AQ_LARGE_BUF) 2597 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2598 scfg->seid = CPU_TO_LE16(*start_seid); 2599 2600 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2601 *start_seid = LE16_TO_CPU(scfg->seid); 2602 2603 return status; 2604} 2605 2606/** 2607 * i40e_aq_set_switch_config 2608 * @hw: pointer to the hardware structure 2609 * @flags: bit flag values to set 2610 * @valid_flags: which bit flags to set 2611 * @cmd_details: pointer to command details structure or NULL 2612 * 2613 * Set switch configuration bits 2614 **/ 2615enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, 2616 u16 flags, u16 valid_flags, 2617 struct i40e_asq_cmd_details *cmd_details) 2618{ 2619 struct i40e_aq_desc desc; 2620 struct i40e_aqc_set_switch_config *scfg = 2621 (struct i40e_aqc_set_switch_config *)&desc.params.raw; 2622 enum i40e_status_code status; 2623 2624 i40e_fill_default_direct_cmd_desc(&desc, 2625 i40e_aqc_opc_set_switch_config); 2626 scfg->flags = CPU_TO_LE16(flags); 2627 scfg->valid_flags = CPU_TO_LE16(valid_flags); 2628 2629 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2630 2631 return status; 2632} 2633 2634/** 2635 * i40e_aq_get_firmware_version 2636 * @hw: pointer to the hw struct 2637 * @fw_major_version: firmware major version 2638 * @fw_minor_version: firmware minor version 2639 * @fw_build: firmware build number 2640 * @api_major_version: major queue version 2641 * @api_minor_version: minor queue version 2642 * @cmd_details: pointer to command details structure or NULL 2643 * 2644 * Get the firmware version from the admin queue commands 2645 **/ 2646enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw, 2647 u16 *fw_major_version, u16 *fw_minor_version, 2648 u32 *fw_build, 2649 u16 *api_major_version, u16 *api_minor_version, 2650 struct i40e_asq_cmd_details *cmd_details) 2651{ 2652 struct i40e_aq_desc desc; 2653 struct i40e_aqc_get_version *resp = 2654 (struct i40e_aqc_get_version *)&desc.params.raw; 2655 enum i40e_status_code status; 2656 2657 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2658 2659 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2660 2661 if (status == I40E_SUCCESS) { 2662 if (fw_major_version != NULL) 2663 *fw_major_version = LE16_TO_CPU(resp->fw_major); 2664 if (fw_minor_version != NULL) 2665 *fw_minor_version = LE16_TO_CPU(resp->fw_minor); 2666 if (fw_build != NULL) 2667 *fw_build = LE32_TO_CPU(resp->fw_build); 2668 if (api_major_version != NULL) 2669 *api_major_version = LE16_TO_CPU(resp->api_major); 2670 if (api_minor_version != NULL) 2671 *api_minor_version = LE16_TO_CPU(resp->api_minor); 2672 2673 /* A workaround to fix the API version in SW */ 2674 if (api_major_version && api_minor_version && 2675 fw_major_version && fw_minor_version && 2676 ((*api_major_version == 1) && (*api_minor_version == 1)) && 2677 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) || 2678 (*fw_major_version > 4))) 2679 *api_minor_version = 2; 2680 } 2681 2682 return status; 2683} 2684 2685/** 2686 * i40e_aq_send_driver_version 2687 * @hw: pointer to the hw struct 2688 * @dv: driver's major, minor version 2689 * @cmd_details: pointer to command details structure or NULL 2690 * 2691 * Send the driver version to the firmware 2692 **/ 2693enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw, 2694 struct i40e_driver_version *dv, 2695 struct i40e_asq_cmd_details *cmd_details) 2696{ 2697 struct i40e_aq_desc desc; 2698 struct i40e_aqc_driver_version *cmd = 2699 (struct i40e_aqc_driver_version *)&desc.params.raw; 2700 enum i40e_status_code status; 2701 u16 len; 2702 2703 if (dv == NULL) 2704 return I40E_ERR_PARAM; 2705 2706 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2707 2708 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2709 cmd->driver_major_ver = dv->major_version; 2710 cmd->driver_minor_ver = dv->minor_version; 2711 cmd->driver_build_ver = dv->build_version; 2712 cmd->driver_subbuild_ver = dv->subbuild_version; 2713 2714 len = 0; 2715 while (len < sizeof(dv->driver_string) && 2716 (dv->driver_string[len] < 0x80) && 2717 dv->driver_string[len]) 2718 len++; 2719 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2720 len, cmd_details); 2721 2722 return status; 2723} 2724 2725/** 2726 * i40e_get_link_status - get status of the HW network link 2727 * @hw: pointer to the hw struct 2728 * @link_up: pointer to bool (TRUE/FALSE = linkup/linkdown) 2729 * 2730 * Variable link_up TRUE if link is up, FALSE if link is down. 2731 * The variable link_up is invalid if returned value of status != I40E_SUCCESS 2732 * 2733 * Side effect: LinkStatusEvent reporting becomes enabled 2734 **/ 2735enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2736{ 2737 enum i40e_status_code status = I40E_SUCCESS; 2738 2739 if (hw->phy.get_link_info) { 2740 status = i40e_update_link_info(hw); 2741 2742 if (status != I40E_SUCCESS) 2743 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2744 status); 2745 } 2746 2747 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2748 2749 return status; 2750} 2751 2752/** 2753 * i40e_updatelink_status - update status of the HW network link 2754 * @hw: pointer to the hw struct 2755 **/ 2756enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw) 2757{ 2758 struct i40e_aq_get_phy_abilities_resp abilities; 2759 enum i40e_status_code status = I40E_SUCCESS; 2760 2761 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2762 if (status) 2763 return status; 2764 2765 /* extra checking needed to ensure link info to user is timely */ 2766 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2767 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2768 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { 2769 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, 2770 &abilities, NULL); 2771 if (status) 2772 return status; 2773 2774 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2775 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA); 2776 } 2777 return status; 2778} 2779 2780 2781/** 2782 * i40e_get_link_speed 2783 * @hw: pointer to the hw struct 2784 * 2785 * Returns the link speed of the adapter. 2786 **/ 2787enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw) 2788{ 2789 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN; 2790 enum i40e_status_code status = I40E_SUCCESS; 2791 2792 if (hw->phy.get_link_info) { 2793 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2794 2795 if (status != I40E_SUCCESS) 2796 goto i40e_link_speed_exit; 2797 } 2798 2799 speed = hw->phy.link_info.link_speed; 2800 2801i40e_link_speed_exit: 2802 return speed; 2803} 2804 2805/** 2806 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2807 * @hw: pointer to the hw struct 2808 * @uplink_seid: the MAC or other gizmo SEID 2809 * @downlink_seid: the VSI SEID 2810 * @enabled_tc: bitmap of TCs to be enabled 2811 * @default_port: TRUE for default port VSI, FALSE for control port 2812 * @veb_seid: pointer to where to put the resulting VEB SEID 2813 * @enable_stats: TRUE to turn on VEB stats 2814 * @cmd_details: pointer to command details structure or NULL 2815 * 2816 * This asks the FW to add a VEB between the uplink and downlink 2817 * elements. If the uplink SEID is 0, this will be a floating VEB. 2818 **/ 2819enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2820 u16 downlink_seid, u8 enabled_tc, 2821 bool default_port, u16 *veb_seid, 2822 bool enable_stats, 2823 struct i40e_asq_cmd_details *cmd_details) 2824{ 2825 struct i40e_aq_desc desc; 2826 struct i40e_aqc_add_veb *cmd = 2827 (struct i40e_aqc_add_veb *)&desc.params.raw; 2828 struct i40e_aqc_add_veb_completion *resp = 2829 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2830 enum i40e_status_code status; 2831 u16 veb_flags = 0; 2832 2833 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2834 if (!!uplink_seid != !!downlink_seid) 2835 return I40E_ERR_PARAM; 2836 2837 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2838 2839 cmd->uplink_seid = CPU_TO_LE16(uplink_seid); 2840 cmd->downlink_seid = CPU_TO_LE16(downlink_seid); 2841 cmd->enable_tcs = enabled_tc; 2842 if (!uplink_seid) 2843 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2844 if (default_port) 2845 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2846 else 2847 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2848 2849 /* reverse logic here: set the bitflag to disable the stats */ 2850 if (!enable_stats) 2851 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2852 2853 cmd->veb_flags = CPU_TO_LE16(veb_flags); 2854 2855 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2856 2857 if (!status && veb_seid) 2858 *veb_seid = LE16_TO_CPU(resp->veb_seid); 2859 2860 return status; 2861} 2862 2863/** 2864 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2865 * @hw: pointer to the hw struct 2866 * @veb_seid: the SEID of the VEB to query 2867 * @switch_id: the uplink switch id 2868 * @floating: set to TRUE if the VEB is floating 2869 * @statistic_index: index of the stats counter block for this VEB 2870 * @vebs_used: number of VEB's used by function 2871 * @vebs_free: total VEB's not reserved by any function 2872 * @cmd_details: pointer to command details structure or NULL 2873 * 2874 * This retrieves the parameters for a particular VEB, specified by 2875 * uplink_seid, and returns them to the caller. 2876 **/ 2877enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2878 u16 veb_seid, u16 *switch_id, 2879 bool *floating, u16 *statistic_index, 2880 u16 *vebs_used, u16 *vebs_free, 2881 struct i40e_asq_cmd_details *cmd_details) 2882{ 2883 struct i40e_aq_desc desc; 2884 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2885 (struct i40e_aqc_get_veb_parameters_completion *) 2886 &desc.params.raw; 2887 enum i40e_status_code status; 2888 2889 if (veb_seid == 0) 2890 return I40E_ERR_PARAM; 2891 2892 i40e_fill_default_direct_cmd_desc(&desc, 2893 i40e_aqc_opc_get_veb_parameters); 2894 cmd_resp->seid = CPU_TO_LE16(veb_seid); 2895 2896 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2897 if (status) 2898 goto get_veb_exit; 2899 2900 if (switch_id) 2901 *switch_id = LE16_TO_CPU(cmd_resp->switch_id); 2902 if (statistic_index) 2903 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index); 2904 if (vebs_used) 2905 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used); 2906 if (vebs_free) 2907 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free); 2908 if (floating) { 2909 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags); 2910 2911 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2912 *floating = TRUE; 2913 else 2914 *floating = FALSE; 2915 } 2916 2917get_veb_exit: 2918 return status; 2919} 2920 2921/** 2922 * i40e_aq_add_macvlan 2923 * @hw: pointer to the hw struct 2924 * @seid: VSI for the mac address 2925 * @mv_list: list of macvlans to be added 2926 * @count: length of the list 2927 * @cmd_details: pointer to command details structure or NULL 2928 * 2929 * Add MAC/VLAN addresses to the HW filtering 2930 **/ 2931enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2932 struct i40e_aqc_add_macvlan_element_data *mv_list, 2933 u16 count, struct i40e_asq_cmd_details *cmd_details) 2934{ 2935 struct i40e_aq_desc desc; 2936 struct i40e_aqc_macvlan *cmd = 2937 (struct i40e_aqc_macvlan *)&desc.params.raw; 2938 enum i40e_status_code status; 2939 u16 buf_size; 2940 int i; 2941 2942 if (count == 0 || !mv_list || !hw) 2943 return I40E_ERR_PARAM; 2944 2945 buf_size = count * sizeof(*mv_list); 2946 2947 /* prep the rest of the request */ 2948 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2949 cmd->num_addresses = CPU_TO_LE16(count); 2950 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2951 cmd->seid[1] = 0; 2952 cmd->seid[2] = 0; 2953 2954 for (i = 0; i < count; i++) 2955 if (I40E_IS_MULTICAST(mv_list[i].mac_addr)) 2956 mv_list[i].flags |= 2957 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 2958 2959 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2960 if (buf_size > I40E_AQ_LARGE_BUF) 2961 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2962 2963 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2964 cmd_details); 2965 2966 return status; 2967} 2968 2969/** 2970 * i40e_aq_remove_macvlan 2971 * @hw: pointer to the hw struct 2972 * @seid: VSI for the mac address 2973 * @mv_list: list of macvlans to be removed 2974 * @count: length of the list 2975 * @cmd_details: pointer to command details structure or NULL 2976 * 2977 * Remove MAC/VLAN addresses from the HW filtering 2978 **/ 2979enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2980 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2981 u16 count, struct i40e_asq_cmd_details *cmd_details) 2982{ 2983 struct i40e_aq_desc desc; 2984 struct i40e_aqc_macvlan *cmd = 2985 (struct i40e_aqc_macvlan *)&desc.params.raw; 2986 enum i40e_status_code status; 2987 u16 buf_size; 2988 2989 if (count == 0 || !mv_list || !hw) 2990 return I40E_ERR_PARAM; 2991 2992 buf_size = count * sizeof(*mv_list); 2993 2994 /* prep the rest of the request */ 2995 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2996 cmd->num_addresses = CPU_TO_LE16(count); 2997 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2998 cmd->seid[1] = 0; 2999 cmd->seid[2] = 0; 3000 3001 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3002 if (buf_size > I40E_AQ_LARGE_BUF) 3003 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3004 3005 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 3006 cmd_details); 3007 3008 return status; 3009} 3010 3011/** 3012 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule 3013 * @hw: pointer to the hw struct 3014 * @opcode: AQ opcode for add or delete mirror rule 3015 * @sw_seid: Switch SEID (to which rule refers) 3016 * @rule_type: Rule Type (ingress/egress/VLAN) 3017 * @id: Destination VSI SEID or Rule ID 3018 * @count: length of the list 3019 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 3020 * @cmd_details: pointer to command details structure or NULL 3021 * @rule_id: Rule ID returned from FW 3022 * @rule_used: Number of rules used in internal switch 3023 * @rule_free: Number of rules free in internal switch 3024 * 3025 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for 3026 * VEBs/VEPA elements only 3027 **/ 3028static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw, 3029 u16 opcode, u16 sw_seid, u16 rule_type, u16 id, 3030 u16 count, __le16 *mr_list, 3031 struct i40e_asq_cmd_details *cmd_details, 3032 u16 *rule_id, u16 *rules_used, u16 *rules_free) 3033{ 3034 struct i40e_aq_desc desc; 3035 struct i40e_aqc_add_delete_mirror_rule *cmd = 3036 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw; 3037 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 3038 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw; 3039 enum i40e_status_code status; 3040 u16 buf_size; 3041 3042 buf_size = count * sizeof(*mr_list); 3043 3044 /* prep the rest of the request */ 3045 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3046 cmd->seid = CPU_TO_LE16(sw_seid); 3047 cmd->rule_type = CPU_TO_LE16(rule_type & 3048 I40E_AQC_MIRROR_RULE_TYPE_MASK); 3049 cmd->num_entries = CPU_TO_LE16(count); 3050 /* Dest VSI for add, rule_id for delete */ 3051 cmd->destination = CPU_TO_LE16(id); 3052 if (mr_list) { 3053 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 3054 I40E_AQ_FLAG_RD)); 3055 if (buf_size > I40E_AQ_LARGE_BUF) 3056 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3057 } 3058 3059 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size, 3060 cmd_details); 3061 if (status == I40E_SUCCESS || 3062 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) { 3063 if (rule_id) 3064 *rule_id = LE16_TO_CPU(resp->rule_id); 3065 if (rules_used) 3066 *rules_used = LE16_TO_CPU(resp->mirror_rules_used); 3067 if (rules_free) 3068 *rules_free = LE16_TO_CPU(resp->mirror_rules_free); 3069 } 3070 return status; 3071} 3072 3073/** 3074 * i40e_aq_add_mirrorrule - add a mirror rule 3075 * @hw: pointer to the hw struct 3076 * @sw_seid: Switch SEID (to which rule refers) 3077 * @rule_type: Rule Type (ingress/egress/VLAN) 3078 * @dest_vsi: SEID of VSI to which packets will be mirrored 3079 * @count: length of the list 3080 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 3081 * @cmd_details: pointer to command details structure or NULL 3082 * @rule_id: Rule ID returned from FW 3083 * @rule_used: Number of rules used in internal switch 3084 * @rule_free: Number of rules free in internal switch 3085 * 3086 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only 3087 **/ 3088enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 3089 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list, 3090 struct i40e_asq_cmd_details *cmd_details, 3091 u16 *rule_id, u16 *rules_used, u16 *rules_free) 3092{ 3093 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS || 3094 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) { 3095 if (count == 0 || !mr_list) 3096 return I40E_ERR_PARAM; 3097 } 3098 3099 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid, 3100 rule_type, dest_vsi, count, mr_list, 3101 cmd_details, rule_id, rules_used, rules_free); 3102} 3103 3104/** 3105 * i40e_aq_delete_mirrorrule - delete a mirror rule 3106 * @hw: pointer to the hw struct 3107 * @sw_seid: Switch SEID (to which rule refers) 3108 * @rule_type: Rule Type (ingress/egress/VLAN) 3109 * @count: length of the list 3110 * @rule_id: Rule ID that is returned in the receive desc as part of 3111 * add_mirrorrule. 3112 * @mr_list: list of mirrored VLAN IDs to be removed 3113 * @cmd_details: pointer to command details structure or NULL 3114 * @rule_used: Number of rules used in internal switch 3115 * @rule_free: Number of rules free in internal switch 3116 * 3117 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only 3118 **/ 3119enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 3120 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list, 3121 struct i40e_asq_cmd_details *cmd_details, 3122 u16 *rules_used, u16 *rules_free) 3123{ 3124 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */ 3125 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 3126 /* count and mr_list shall be valid for rule_type INGRESS VLAN 3127 * mirroring. For other rule_type, count and rule_type should 3128 * not matter. 3129 */ 3130 if (count == 0 || !mr_list) 3131 return I40E_ERR_PARAM; 3132 } 3133 3134 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid, 3135 rule_type, rule_id, count, mr_list, 3136 cmd_details, NULL, rules_used, rules_free); 3137} 3138 3139/** 3140 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering 3141 * @hw: pointer to the hw struct 3142 * @seid: VSI for the vlan filters 3143 * @v_list: list of vlan filters to be added 3144 * @count: length of the list 3145 * @cmd_details: pointer to command details structure or NULL 3146 **/ 3147enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid, 3148 struct i40e_aqc_add_remove_vlan_element_data *v_list, 3149 u8 count, struct i40e_asq_cmd_details *cmd_details) 3150{ 3151 struct i40e_aq_desc desc; 3152 struct i40e_aqc_macvlan *cmd = 3153 (struct i40e_aqc_macvlan *)&desc.params.raw; 3154 enum i40e_status_code status; 3155 u16 buf_size; 3156 3157 if (count == 0 || !v_list || !hw) 3158 return I40E_ERR_PARAM; 3159 3160 buf_size = count * sizeof(*v_list); 3161 3162 /* prep the rest of the request */ 3163 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan); 3164 cmd->num_addresses = CPU_TO_LE16(count); 3165 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 3166 cmd->seid[1] = 0; 3167 cmd->seid[2] = 0; 3168 3169 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3170 if (buf_size > I40E_AQ_LARGE_BUF) 3171 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3172 3173 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 3174 cmd_details); 3175 3176 return status; 3177} 3178 3179/** 3180 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering 3181 * @hw: pointer to the hw struct 3182 * @seid: VSI for the vlan filters 3183 * @v_list: list of macvlans to be removed 3184 * @count: length of the list 3185 * @cmd_details: pointer to command details structure or NULL 3186 **/ 3187enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid, 3188 struct i40e_aqc_add_remove_vlan_element_data *v_list, 3189 u8 count, struct i40e_asq_cmd_details *cmd_details) 3190{ 3191 struct i40e_aq_desc desc; 3192 struct i40e_aqc_macvlan *cmd = 3193 (struct i40e_aqc_macvlan *)&desc.params.raw; 3194 enum i40e_status_code status; 3195 u16 buf_size; 3196 3197 if (count == 0 || !v_list || !hw) 3198 return I40E_ERR_PARAM; 3199 3200 buf_size = count * sizeof(*v_list); 3201 3202 /* prep the rest of the request */ 3203 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan); 3204 cmd->num_addresses = CPU_TO_LE16(count); 3205 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 3206 cmd->seid[1] = 0; 3207 cmd->seid[2] = 0; 3208 3209 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3210 if (buf_size > I40E_AQ_LARGE_BUF) 3211 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3212 3213 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 3214 cmd_details); 3215 3216 return status; 3217} 3218 3219/** 3220 * i40e_aq_send_msg_to_vf 3221 * @hw: pointer to the hardware structure 3222 * @vfid: vf id to send msg 3223 * @v_opcode: opcodes for VF-PF communication 3224 * @v_retval: return error code 3225 * @msg: pointer to the msg buffer 3226 * @msglen: msg length 3227 * @cmd_details: pointer to command details 3228 * 3229 * send msg to vf 3230 **/ 3231enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 3232 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 3233 struct i40e_asq_cmd_details *cmd_details) 3234{ 3235 struct i40e_aq_desc desc; 3236 struct i40e_aqc_pf_vf_message *cmd = 3237 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 3238 enum i40e_status_code status; 3239 3240 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 3241 cmd->id = CPU_TO_LE32(vfid); 3242 desc.cookie_high = CPU_TO_LE32(v_opcode); 3243 desc.cookie_low = CPU_TO_LE32(v_retval); 3244 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 3245 if (msglen) { 3246 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 3247 I40E_AQ_FLAG_RD)); 3248 if (msglen > I40E_AQ_LARGE_BUF) 3249 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3250 desc.datalen = CPU_TO_LE16(msglen); 3251 } 3252 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 3253 3254 return status; 3255} 3256 3257/** 3258 * i40e_aq_debug_read_register 3259 * @hw: pointer to the hw struct 3260 * @reg_addr: register address 3261 * @reg_val: register value 3262 * @cmd_details: pointer to command details structure or NULL 3263 * 3264 * Read the register using the admin queue commands 3265 **/ 3266enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw, 3267 u32 reg_addr, u64 *reg_val, 3268 struct i40e_asq_cmd_details *cmd_details) 3269{ 3270 struct i40e_aq_desc desc; 3271 struct i40e_aqc_debug_reg_read_write *cmd_resp = 3272 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3273 enum i40e_status_code status; 3274 3275 if (reg_val == NULL) 3276 return I40E_ERR_PARAM; 3277 3278 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 3279 3280 cmd_resp->address = CPU_TO_LE32(reg_addr); 3281 3282 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3283 3284 if (status == I40E_SUCCESS) { 3285 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) | 3286 (u64)LE32_TO_CPU(cmd_resp->value_low); 3287 } 3288 3289 return status; 3290} 3291 3292/** 3293 * i40e_aq_debug_write_register 3294 * @hw: pointer to the hw struct 3295 * @reg_addr: register address 3296 * @reg_val: register value 3297 * @cmd_details: pointer to command details structure or NULL 3298 * 3299 * Write to a register using the admin queue commands 3300 **/ 3301enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw, 3302 u32 reg_addr, u64 reg_val, 3303 struct i40e_asq_cmd_details *cmd_details) 3304{ 3305 struct i40e_aq_desc desc; 3306 struct i40e_aqc_debug_reg_read_write *cmd = 3307 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3308 enum i40e_status_code status; 3309 3310 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 3311 3312 cmd->address = CPU_TO_LE32(reg_addr); 3313 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32)); 3314 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF)); 3315 3316 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3317 3318 return status; 3319} 3320 3321/** 3322 * i40e_aq_request_resource 3323 * @hw: pointer to the hw struct 3324 * @resource: resource id 3325 * @access: access type 3326 * @sdp_number: resource number 3327 * @timeout: the maximum time in ms that the driver may hold the resource 3328 * @cmd_details: pointer to command details structure or NULL 3329 * 3330 * requests common resource using the admin queue commands 3331 **/ 3332enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw, 3333 enum i40e_aq_resources_ids resource, 3334 enum i40e_aq_resource_access_type access, 3335 u8 sdp_number, u64 *timeout, 3336 struct i40e_asq_cmd_details *cmd_details) 3337{ 3338 struct i40e_aq_desc desc; 3339 struct i40e_aqc_request_resource *cmd_resp = 3340 (struct i40e_aqc_request_resource *)&desc.params.raw; 3341 enum i40e_status_code status; 3342 3343 DEBUGFUNC("i40e_aq_request_resource"); 3344 3345 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 3346 3347 cmd_resp->resource_id = CPU_TO_LE16(resource); 3348 cmd_resp->access_type = CPU_TO_LE16(access); 3349 cmd_resp->resource_number = CPU_TO_LE32(sdp_number); 3350 3351 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3352 /* The completion specifies the maximum time in ms that the driver 3353 * may hold the resource in the Timeout field. 3354 * If the resource is held by someone else, the command completes with 3355 * busy return value and the timeout field indicates the maximum time 3356 * the current owner of the resource has to free it. 3357 */ 3358 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 3359 *timeout = LE32_TO_CPU(cmd_resp->timeout); 3360 3361 return status; 3362} 3363 3364/** 3365 * i40e_aq_release_resource 3366 * @hw: pointer to the hw struct 3367 * @resource: resource id 3368 * @sdp_number: resource number 3369 * @cmd_details: pointer to command details structure or NULL 3370 * 3371 * release common resource using the admin queue commands 3372 **/ 3373enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw, 3374 enum i40e_aq_resources_ids resource, 3375 u8 sdp_number, 3376 struct i40e_asq_cmd_details *cmd_details) 3377{ 3378 struct i40e_aq_desc desc; 3379 struct i40e_aqc_request_resource *cmd = 3380 (struct i40e_aqc_request_resource *)&desc.params.raw; 3381 enum i40e_status_code status; 3382 3383 DEBUGFUNC("i40e_aq_release_resource"); 3384 3385 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 3386 3387 cmd->resource_id = CPU_TO_LE16(resource); 3388 cmd->resource_number = CPU_TO_LE32(sdp_number); 3389 3390 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3391 3392 return status; 3393} 3394 3395/** 3396 * i40e_aq_read_nvm 3397 * @hw: pointer to the hw struct 3398 * @module_pointer: module pointer location in words from the NVM beginning 3399 * @offset: byte offset from the module beginning 3400 * @length: length of the section to be read (in bytes from the offset) 3401 * @data: command buffer (size [bytes] = length) 3402 * @last_command: tells if this is the last command in a series 3403 * @cmd_details: pointer to command details structure or NULL 3404 * 3405 * Read the NVM using the admin queue commands 3406 **/ 3407enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 3408 u32 offset, u16 length, void *data, 3409 bool last_command, 3410 struct i40e_asq_cmd_details *cmd_details) 3411{ 3412 struct i40e_aq_desc desc; 3413 struct i40e_aqc_nvm_update *cmd = 3414 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3415 enum i40e_status_code status; 3416 3417 DEBUGFUNC("i40e_aq_read_nvm"); 3418 3419 /* In offset the highest byte must be zeroed. */ 3420 if (offset & 0xFF000000) { 3421 status = I40E_ERR_PARAM; 3422 goto i40e_aq_read_nvm_exit; 3423 } 3424 3425 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 3426 3427 /* If this is the last command in a series, set the proper flag. */ 3428 if (last_command) 3429 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3430 cmd->module_pointer = module_pointer; 3431 cmd->offset = CPU_TO_LE32(offset); 3432 cmd->length = CPU_TO_LE16(length); 3433 3434 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3435 if (length > I40E_AQ_LARGE_BUF) 3436 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3437 3438 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3439 3440i40e_aq_read_nvm_exit: 3441 return status; 3442} 3443 3444/** 3445 * i40e_aq_read_nvm_config - read an nvm config block 3446 * @hw: pointer to the hw struct 3447 * @cmd_flags: NVM access admin command bits 3448 * @field_id: field or feature id 3449 * @data: buffer for result 3450 * @buf_size: buffer size 3451 * @element_count: pointer to count of elements read by FW 3452 * @cmd_details: pointer to command details structure or NULL 3453 **/ 3454enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw, 3455 u8 cmd_flags, u32 field_id, void *data, 3456 u16 buf_size, u16 *element_count, 3457 struct i40e_asq_cmd_details *cmd_details) 3458{ 3459 struct i40e_aq_desc desc; 3460 struct i40e_aqc_nvm_config_read *cmd = 3461 (struct i40e_aqc_nvm_config_read *)&desc.params.raw; 3462 enum i40e_status_code status; 3463 3464 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read); 3465 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF)); 3466 if (buf_size > I40E_AQ_LARGE_BUF) 3467 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3468 3469 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3470 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id)); 3471 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK) 3472 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16)); 3473 else 3474 cmd->element_id_msw = 0; 3475 3476 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3477 3478 if (!status && element_count) 3479 *element_count = LE16_TO_CPU(cmd->element_count); 3480 3481 return status; 3482} 3483 3484/** 3485 * i40e_aq_write_nvm_config - write an nvm config block 3486 * @hw: pointer to the hw struct 3487 * @cmd_flags: NVM access admin command bits 3488 * @data: buffer for result 3489 * @buf_size: buffer size 3490 * @element_count: count of elements to be written 3491 * @cmd_details: pointer to command details structure or NULL 3492 **/ 3493enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw, 3494 u8 cmd_flags, void *data, u16 buf_size, 3495 u16 element_count, 3496 struct i40e_asq_cmd_details *cmd_details) 3497{ 3498 struct i40e_aq_desc desc; 3499 struct i40e_aqc_nvm_config_write *cmd = 3500 (struct i40e_aqc_nvm_config_write *)&desc.params.raw; 3501 enum i40e_status_code status; 3502 3503 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write); 3504 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3505 if (buf_size > I40E_AQ_LARGE_BUF) 3506 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3507 3508 cmd->element_count = CPU_TO_LE16(element_count); 3509 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3510 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3511 3512 return status; 3513} 3514 3515/** 3516 * i40e_aq_oem_post_update - triggers an OEM specific flow after update 3517 * @hw: pointer to the hw struct 3518 * @cmd_details: pointer to command details structure or NULL 3519 **/ 3520enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw, 3521 void *buff, u16 buff_size, 3522 struct i40e_asq_cmd_details *cmd_details) 3523{ 3524 struct i40e_aq_desc desc; 3525 enum i40e_status_code status; 3526 3527 3528 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update); 3529 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3530 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH) 3531 status = I40E_ERR_NOT_IMPLEMENTED; 3532 3533 return status; 3534} 3535 3536/** 3537 * i40e_aq_erase_nvm 3538 * @hw: pointer to the hw struct 3539 * @module_pointer: module pointer location in words from the NVM beginning 3540 * @offset: offset in the module (expressed in 4 KB from module's beginning) 3541 * @length: length of the section to be erased (expressed in 4 KB) 3542 * @last_command: tells if this is the last command in a series 3543 * @cmd_details: pointer to command details structure or NULL 3544 * 3545 * Erase the NVM sector using the admin queue commands 3546 **/ 3547enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 3548 u32 offset, u16 length, bool last_command, 3549 struct i40e_asq_cmd_details *cmd_details) 3550{ 3551 struct i40e_aq_desc desc; 3552 struct i40e_aqc_nvm_update *cmd = 3553 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3554 enum i40e_status_code status; 3555 3556 DEBUGFUNC("i40e_aq_erase_nvm"); 3557 3558 /* In offset the highest byte must be zeroed. */ 3559 if (offset & 0xFF000000) { 3560 status = I40E_ERR_PARAM; 3561 goto i40e_aq_erase_nvm_exit; 3562 } 3563 3564 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 3565 3566 /* If this is the last command in a series, set the proper flag. */ 3567 if (last_command) 3568 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3569 cmd->module_pointer = module_pointer; 3570 cmd->offset = CPU_TO_LE32(offset); 3571 cmd->length = CPU_TO_LE16(length); 3572 3573 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3574 3575i40e_aq_erase_nvm_exit: 3576 return status; 3577} 3578 3579/** 3580 * i40e_parse_discover_capabilities 3581 * @hw: pointer to the hw struct 3582 * @buff: pointer to a buffer containing device/function capability records 3583 * @cap_count: number of capability records in the list 3584 * @list_type_opc: type of capabilities list to parse 3585 * 3586 * Parse the device/function capabilities list. 3587 **/ 3588static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 3589 u32 cap_count, 3590 enum i40e_admin_queue_opc list_type_opc) 3591{ 3592 struct i40e_aqc_list_capabilities_element_resp *cap; 3593 u32 valid_functions, num_functions; 3594 u32 number, logical_id, phys_id; 3595 struct i40e_hw_capabilities *p; 3596 u8 major_rev; 3597 u32 i = 0; 3598 u16 id; 3599 3600 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 3601 3602 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 3603 p = (struct i40e_hw_capabilities *)&hw->dev_caps; 3604 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 3605 p = (struct i40e_hw_capabilities *)&hw->func_caps; 3606 else 3607 return; 3608 3609 for (i = 0; i < cap_count; i++, cap++) { 3610 id = LE16_TO_CPU(cap->id); 3611 number = LE32_TO_CPU(cap->number); 3612 logical_id = LE32_TO_CPU(cap->logical_id); 3613 phys_id = LE32_TO_CPU(cap->phys_id); 3614 major_rev = cap->major_rev; 3615 3616 switch (id) { 3617 case I40E_AQ_CAP_ID_SWITCH_MODE: 3618 p->switch_mode = number; 3619 i40e_debug(hw, I40E_DEBUG_INIT, 3620 "HW Capability: Switch mode = %d\n", 3621 p->switch_mode); 3622 break; 3623 case I40E_AQ_CAP_ID_MNG_MODE: 3624 p->management_mode = number; 3625 if (major_rev > 1) { 3626 p->mng_protocols_over_mctp = logical_id; 3627 i40e_debug(hw, I40E_DEBUG_INIT, 3628 "HW Capability: Protocols over MCTP = %d\n", 3629 p->mng_protocols_over_mctp); 3630 } else { 3631 p->mng_protocols_over_mctp = 0; 3632 } 3633 i40e_debug(hw, I40E_DEBUG_INIT, 3634 "HW Capability: Management Mode = %d\n", 3635 p->management_mode); 3636 break; 3637 case I40E_AQ_CAP_ID_NPAR_ACTIVE: 3638 p->npar_enable = number; 3639 i40e_debug(hw, I40E_DEBUG_INIT, 3640 "HW Capability: NPAR enable = %d\n", 3641 p->npar_enable); 3642 break; 3643 case I40E_AQ_CAP_ID_OS2BMC_CAP: 3644 p->os2bmc = number; 3645 i40e_debug(hw, I40E_DEBUG_INIT, 3646 "HW Capability: OS2BMC = %d\n", p->os2bmc); 3647 break; 3648 case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 3649 p->valid_functions = number; 3650 i40e_debug(hw, I40E_DEBUG_INIT, 3651 "HW Capability: Valid Functions = %d\n", 3652 p->valid_functions); 3653 break; 3654 case I40E_AQ_CAP_ID_SRIOV: 3655 if (number == 1) 3656 p->sr_iov_1_1 = TRUE; 3657 i40e_debug(hw, I40E_DEBUG_INIT, 3658 "HW Capability: SR-IOV = %d\n", 3659 p->sr_iov_1_1); 3660 break; 3661 case I40E_AQ_CAP_ID_VF: 3662 p->num_vfs = number; 3663 p->vf_base_id = logical_id; 3664 i40e_debug(hw, I40E_DEBUG_INIT, 3665 "HW Capability: VF count = %d\n", 3666 p->num_vfs); 3667 i40e_debug(hw, I40E_DEBUG_INIT, 3668 "HW Capability: VF base_id = %d\n", 3669 p->vf_base_id); 3670 break; 3671 case I40E_AQ_CAP_ID_VMDQ: 3672 if (number == 1) 3673 p->vmdq = TRUE; 3674 i40e_debug(hw, I40E_DEBUG_INIT, 3675 "HW Capability: VMDQ = %d\n", p->vmdq); 3676 break; 3677 case I40E_AQ_CAP_ID_8021QBG: 3678 if (number == 1) 3679 p->evb_802_1_qbg = TRUE; 3680 i40e_debug(hw, I40E_DEBUG_INIT, 3681 "HW Capability: 802.1Qbg = %d\n", number); 3682 break; 3683 case I40E_AQ_CAP_ID_8021QBR: 3684 if (number == 1) 3685 p->evb_802_1_qbh = TRUE; 3686 i40e_debug(hw, I40E_DEBUG_INIT, 3687 "HW Capability: 802.1Qbh = %d\n", number); 3688 break; 3689 case I40E_AQ_CAP_ID_VSI: 3690 p->num_vsis = number; 3691 i40e_debug(hw, I40E_DEBUG_INIT, 3692 "HW Capability: VSI count = %d\n", 3693 p->num_vsis); 3694 break; 3695 case I40E_AQ_CAP_ID_DCB: 3696 if (number == 1) { 3697 p->dcb = TRUE; 3698 p->enabled_tcmap = logical_id; 3699 p->maxtc = phys_id; 3700 } 3701 i40e_debug(hw, I40E_DEBUG_INIT, 3702 "HW Capability: DCB = %d\n", p->dcb); 3703 i40e_debug(hw, I40E_DEBUG_INIT, 3704 "HW Capability: TC Mapping = %d\n", 3705 logical_id); 3706 i40e_debug(hw, I40E_DEBUG_INIT, 3707 "HW Capability: TC Max = %d\n", p->maxtc); 3708 break; 3709 case I40E_AQ_CAP_ID_FCOE: 3710 if (number == 1) 3711 p->fcoe = TRUE; 3712 i40e_debug(hw, I40E_DEBUG_INIT, 3713 "HW Capability: FCOE = %d\n", p->fcoe); 3714 break; 3715 case I40E_AQ_CAP_ID_ISCSI: 3716 if (number == 1) 3717 p->iscsi = TRUE; 3718 i40e_debug(hw, I40E_DEBUG_INIT, 3719 "HW Capability: iSCSI = %d\n", p->iscsi); 3720 break; 3721 case I40E_AQ_CAP_ID_RSS: 3722 p->rss = TRUE; 3723 p->rss_table_size = number; 3724 p->rss_table_entry_width = logical_id; 3725 i40e_debug(hw, I40E_DEBUG_INIT, 3726 "HW Capability: RSS = %d\n", p->rss); 3727 i40e_debug(hw, I40E_DEBUG_INIT, 3728 "HW Capability: RSS table size = %d\n", 3729 p->rss_table_size); 3730 i40e_debug(hw, I40E_DEBUG_INIT, 3731 "HW Capability: RSS table width = %d\n", 3732 p->rss_table_entry_width); 3733 break; 3734 case I40E_AQ_CAP_ID_RXQ: 3735 p->num_rx_qp = number; 3736 p->base_queue = phys_id; 3737 i40e_debug(hw, I40E_DEBUG_INIT, 3738 "HW Capability: Rx QP = %d\n", number); 3739 i40e_debug(hw, I40E_DEBUG_INIT, 3740 "HW Capability: base_queue = %d\n", 3741 p->base_queue); 3742 break; 3743 case I40E_AQ_CAP_ID_TXQ: 3744 p->num_tx_qp = number; 3745 p->base_queue = phys_id; 3746 i40e_debug(hw, I40E_DEBUG_INIT, 3747 "HW Capability: Tx QP = %d\n", number); 3748 i40e_debug(hw, I40E_DEBUG_INIT, 3749 "HW Capability: base_queue = %d\n", 3750 p->base_queue); 3751 break; 3752 case I40E_AQ_CAP_ID_MSIX: 3753 p->num_msix_vectors = number; 3754 i40e_debug(hw, I40E_DEBUG_INIT, 3755 "HW Capability: MSIX vector count = %d\n", 3756 p->num_msix_vectors); 3757 break; 3758 case I40E_AQ_CAP_ID_VF_MSIX: 3759 p->num_msix_vectors_vf = number; 3760 i40e_debug(hw, I40E_DEBUG_INIT, 3761 "HW Capability: MSIX VF vector count = %d\n", 3762 p->num_msix_vectors_vf); 3763 break; 3764 case I40E_AQ_CAP_ID_FLEX10: 3765 if (major_rev == 1) { 3766 if (number == 1) { 3767 p->flex10_enable = TRUE; 3768 p->flex10_capable = TRUE; 3769 } 3770 } else { 3771 /* Capability revision >= 2 */ 3772 if (number & 1) 3773 p->flex10_enable = TRUE; 3774 if (number & 2) 3775 p->flex10_capable = TRUE; 3776 } 3777 p->flex10_mode = logical_id; 3778 p->flex10_status = phys_id; 3779 i40e_debug(hw, I40E_DEBUG_INIT, 3780 "HW Capability: Flex10 mode = %d\n", 3781 p->flex10_mode); 3782 i40e_debug(hw, I40E_DEBUG_INIT, 3783 "HW Capability: Flex10 status = %d\n", 3784 p->flex10_status); 3785 break; 3786 case I40E_AQ_CAP_ID_CEM: 3787 if (number == 1) 3788 p->mgmt_cem = TRUE; 3789 i40e_debug(hw, I40E_DEBUG_INIT, 3790 "HW Capability: CEM = %d\n", p->mgmt_cem); 3791 break; 3792 case I40E_AQ_CAP_ID_IWARP: 3793 if (number == 1) 3794 p->iwarp = TRUE; 3795 i40e_debug(hw, I40E_DEBUG_INIT, 3796 "HW Capability: iWARP = %d\n", p->iwarp); 3797 break; 3798 case I40E_AQ_CAP_ID_LED: 3799 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3800 p->led[phys_id] = TRUE; 3801 i40e_debug(hw, I40E_DEBUG_INIT, 3802 "HW Capability: LED - PIN %d\n", phys_id); 3803 break; 3804 case I40E_AQ_CAP_ID_SDP: 3805 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3806 p->sdp[phys_id] = TRUE; 3807 i40e_debug(hw, I40E_DEBUG_INIT, 3808 "HW Capability: SDP - PIN %d\n", phys_id); 3809 break; 3810 case I40E_AQ_CAP_ID_MDIO: 3811 if (number == 1) { 3812 p->mdio_port_num = phys_id; 3813 p->mdio_port_mode = logical_id; 3814 } 3815 i40e_debug(hw, I40E_DEBUG_INIT, 3816 "HW Capability: MDIO port number = %d\n", 3817 p->mdio_port_num); 3818 i40e_debug(hw, I40E_DEBUG_INIT, 3819 "HW Capability: MDIO port mode = %d\n", 3820 p->mdio_port_mode); 3821 break; 3822 case I40E_AQ_CAP_ID_1588: 3823 if (number == 1) 3824 p->ieee_1588 = TRUE; 3825 i40e_debug(hw, I40E_DEBUG_INIT, 3826 "HW Capability: IEEE 1588 = %d\n", 3827 p->ieee_1588); 3828 break; 3829 case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 3830 p->fd = TRUE; 3831 p->fd_filters_guaranteed = number; 3832 p->fd_filters_best_effort = logical_id; 3833 i40e_debug(hw, I40E_DEBUG_INIT, 3834 "HW Capability: Flow Director = 1\n"); 3835 i40e_debug(hw, I40E_DEBUG_INIT, 3836 "HW Capability: Guaranteed FD filters = %d\n", 3837 p->fd_filters_guaranteed); 3838 break; 3839 case I40E_AQ_CAP_ID_WSR_PROT: 3840 p->wr_csr_prot = (u64)number; 3841 p->wr_csr_prot |= (u64)logical_id << 32; 3842 i40e_debug(hw, I40E_DEBUG_INIT, 3843 "HW Capability: wr_csr_prot = 0x%llX\n\n", 3844 (p->wr_csr_prot & 0xffff)); 3845 break; 3846 case I40E_AQ_CAP_ID_NVM_MGMT: 3847 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 3848 p->sec_rev_disabled = TRUE; 3849 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 3850 p->update_disabled = TRUE; 3851 break; 3852 case I40E_AQ_CAP_ID_WOL_AND_PROXY: 3853 hw->num_wol_proxy_filters = (u16)number; 3854 hw->wol_proxy_vsi_seid = (u16)logical_id; 3855 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK; 3856 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK) 3857 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK; 3858 else 3859 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL; 3860 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0; 3861 i40e_debug(hw, I40E_DEBUG_INIT, 3862 "HW Capability: WOL proxy filters = %d\n", 3863 hw->num_wol_proxy_filters); 3864 break; 3865 default: 3866 break; 3867 } 3868 } 3869 3870 if (p->fcoe) 3871 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 3872 3873 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */ 3874 p->fcoe = FALSE; 3875 3876 /* count the enabled ports (aka the "not disabled" ports) */ 3877 hw->num_ports = 0; 3878 for (i = 0; i < 4; i++) { 3879 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i); 3880 u64 port_cfg = 0; 3881 3882 /* use AQ read to get the physical register offset instead 3883 * of the port relative offset 3884 */ 3885 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 3886 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) 3887 hw->num_ports++; 3888 } 3889 3890 valid_functions = p->valid_functions; 3891 num_functions = 0; 3892 while (valid_functions) { 3893 if (valid_functions & 1) 3894 num_functions++; 3895 valid_functions >>= 1; 3896 } 3897 3898 /* partition id is 1-based, and functions are evenly spread 3899 * across the ports as partitions 3900 */ 3901 if (hw->num_ports != 0) { 3902 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 3903 hw->num_partitions = num_functions / hw->num_ports; 3904 } 3905 3906 /* additional HW specific goodies that might 3907 * someday be HW version specific 3908 */ 3909 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 3910} 3911 3912/** 3913 * i40e_aq_discover_capabilities 3914 * @hw: pointer to the hw struct 3915 * @buff: a virtual buffer to hold the capabilities 3916 * @buff_size: Size of the virtual buffer 3917 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 3918 * @list_type_opc: capabilities type to discover - pass in the command opcode 3919 * @cmd_details: pointer to command details structure or NULL 3920 * 3921 * Get the device capabilities descriptions from the firmware 3922 **/ 3923enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw, 3924 void *buff, u16 buff_size, u16 *data_size, 3925 enum i40e_admin_queue_opc list_type_opc, 3926 struct i40e_asq_cmd_details *cmd_details) 3927{ 3928 struct i40e_aqc_list_capabilites *cmd; 3929 struct i40e_aq_desc desc; 3930 enum i40e_status_code status = I40E_SUCCESS; 3931 3932 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 3933 3934 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 3935 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 3936 status = I40E_ERR_PARAM; 3937 goto exit; 3938 } 3939 3940 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 3941 3942 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3943 if (buff_size > I40E_AQ_LARGE_BUF) 3944 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3945 3946 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3947 *data_size = LE16_TO_CPU(desc.datalen); 3948 3949 if (status) 3950 goto exit; 3951 3952 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count), 3953 list_type_opc); 3954 3955exit: 3956 return status; 3957} 3958 3959/** 3960 * i40e_aq_update_nvm 3961 * @hw: pointer to the hw struct 3962 * @module_pointer: module pointer location in words from the NVM beginning 3963 * @offset: byte offset from the module beginning 3964 * @length: length of the section to be written (in bytes from the offset) 3965 * @data: command buffer (size [bytes] = length) 3966 * @last_command: tells if this is the last command in a series 3967 * @cmd_details: pointer to command details structure or NULL 3968 * 3969 * Update the NVM using the admin queue commands 3970 **/ 3971enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 3972 u32 offset, u16 length, void *data, 3973 bool last_command, 3974 struct i40e_asq_cmd_details *cmd_details) 3975{ 3976 struct i40e_aq_desc desc; 3977 struct i40e_aqc_nvm_update *cmd = 3978 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3979 enum i40e_status_code status; 3980 3981 DEBUGFUNC("i40e_aq_update_nvm"); 3982 3983 /* In offset the highest byte must be zeroed. */ 3984 if (offset & 0xFF000000) { 3985 status = I40E_ERR_PARAM; 3986 goto i40e_aq_update_nvm_exit; 3987 } 3988 3989 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 3990 3991 /* If this is the last command in a series, set the proper flag. */ 3992 if (last_command) 3993 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3994 cmd->module_pointer = module_pointer; 3995 cmd->offset = CPU_TO_LE32(offset); 3996 cmd->length = CPU_TO_LE16(length); 3997 3998 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3999 if (length > I40E_AQ_LARGE_BUF) 4000 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4001 4002 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 4003 4004i40e_aq_update_nvm_exit: 4005 return status; 4006} 4007 4008/** 4009 * i40e_aq_get_lldp_mib 4010 * @hw: pointer to the hw struct 4011 * @bridge_type: type of bridge requested 4012 * @mib_type: Local, Remote or both Local and Remote MIBs 4013 * @buff: pointer to a user supplied buffer to store the MIB block 4014 * @buff_size: size of the buffer (in bytes) 4015 * @local_len : length of the returned Local LLDP MIB 4016 * @remote_len: length of the returned Remote LLDP MIB 4017 * @cmd_details: pointer to command details structure or NULL 4018 * 4019 * Requests the complete LLDP MIB (entire packet). 4020 **/ 4021enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 4022 u8 mib_type, void *buff, u16 buff_size, 4023 u16 *local_len, u16 *remote_len, 4024 struct i40e_asq_cmd_details *cmd_details) 4025{ 4026 struct i40e_aq_desc desc; 4027 struct i40e_aqc_lldp_get_mib *cmd = 4028 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 4029 struct i40e_aqc_lldp_get_mib *resp = 4030 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 4031 enum i40e_status_code status; 4032 4033 if (buff_size == 0 || !buff) 4034 return I40E_ERR_PARAM; 4035 4036 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 4037 /* Indirect Command */ 4038 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4039 4040 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 4041 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4042 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4043 4044 desc.datalen = CPU_TO_LE16(buff_size); 4045 4046 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4047 if (buff_size > I40E_AQ_LARGE_BUF) 4048 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4049 4050 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4051 if (!status) { 4052 if (local_len != NULL) 4053 *local_len = LE16_TO_CPU(resp->local_len); 4054 if (remote_len != NULL) 4055 *remote_len = LE16_TO_CPU(resp->remote_len); 4056 } 4057 4058 return status; 4059} 4060 4061 /** 4062 * i40e_aq_set_lldp_mib - Set the LLDP MIB 4063 * @hw: pointer to the hw struct 4064 * @mib_type: Local, Remote or both Local and Remote MIBs 4065 * @buff: pointer to a user supplied buffer to store the MIB block 4066 * @buff_size: size of the buffer (in bytes) 4067 * @cmd_details: pointer to command details structure or NULL 4068 * 4069 * Set the LLDP MIB. 4070 **/ 4071enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw, 4072 u8 mib_type, void *buff, u16 buff_size, 4073 struct i40e_asq_cmd_details *cmd_details) 4074{ 4075 struct i40e_aq_desc desc; 4076 struct i40e_aqc_lldp_set_local_mib *cmd = 4077 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw; 4078 enum i40e_status_code status; 4079 4080 if (buff_size == 0 || !buff) 4081 return I40E_ERR_PARAM; 4082 4083 i40e_fill_default_direct_cmd_desc(&desc, 4084 i40e_aqc_opc_lldp_set_local_mib); 4085 /* Indirect Command */ 4086 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4087 if (buff_size > I40E_AQ_LARGE_BUF) 4088 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4089 desc.datalen = CPU_TO_LE16(buff_size); 4090 4091 cmd->type = mib_type; 4092 cmd->length = CPU_TO_LE16(buff_size); 4093 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff)); 4094 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff)); 4095 4096 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4097 return status; 4098} 4099 4100/** 4101 * i40e_aq_cfg_lldp_mib_change_event 4102 * @hw: pointer to the hw struct 4103 * @enable_update: Enable or Disable event posting 4104 * @cmd_details: pointer to command details structure or NULL 4105 * 4106 * Enable or Disable posting of an event on ARQ when LLDP MIB 4107 * associated with the interface changes 4108 **/ 4109enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 4110 bool enable_update, 4111 struct i40e_asq_cmd_details *cmd_details) 4112{ 4113 struct i40e_aq_desc desc; 4114 struct i40e_aqc_lldp_update_mib *cmd = 4115 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 4116 enum i40e_status_code status; 4117 4118 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 4119 4120 if (!enable_update) 4121 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 4122 4123 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4124 4125 return status; 4126} 4127 4128/** 4129 * i40e_aq_add_lldp_tlv 4130 * @hw: pointer to the hw struct 4131 * @bridge_type: type of bridge 4132 * @buff: buffer with TLV to add 4133 * @buff_size: length of the buffer 4134 * @tlv_len: length of the TLV to be added 4135 * @mib_len: length of the LLDP MIB returned in response 4136 * @cmd_details: pointer to command details structure or NULL 4137 * 4138 * Add the specified TLV to LLDP Local MIB for the given bridge type, 4139 * it is responsibility of the caller to make sure that the TLV is not 4140 * already present in the LLDPDU. 4141 * In return firmware will write the complete LLDP MIB with the newly 4142 * added TLV in the response buffer. 4143 **/ 4144enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type, 4145 void *buff, u16 buff_size, u16 tlv_len, 4146 u16 *mib_len, 4147 struct i40e_asq_cmd_details *cmd_details) 4148{ 4149 struct i40e_aq_desc desc; 4150 struct i40e_aqc_lldp_add_tlv *cmd = 4151 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 4152 enum i40e_status_code status; 4153 4154 if (buff_size == 0 || !buff || tlv_len == 0) 4155 return I40E_ERR_PARAM; 4156 4157 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv); 4158 4159 /* Indirect Command */ 4160 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4161 if (buff_size > I40E_AQ_LARGE_BUF) 4162 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4163 desc.datalen = CPU_TO_LE16(buff_size); 4164 4165 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4166 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4167 cmd->len = CPU_TO_LE16(tlv_len); 4168 4169 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4170 if (!status) { 4171 if (mib_len != NULL) 4172 *mib_len = LE16_TO_CPU(desc.datalen); 4173 } 4174 4175 return status; 4176} 4177 4178/** 4179 * i40e_aq_update_lldp_tlv 4180 * @hw: pointer to the hw struct 4181 * @bridge_type: type of bridge 4182 * @buff: buffer with TLV to update 4183 * @buff_size: size of the buffer holding original and updated TLVs 4184 * @old_len: Length of the Original TLV 4185 * @new_len: Length of the Updated TLV 4186 * @offset: offset of the updated TLV in the buff 4187 * @mib_len: length of the returned LLDP MIB 4188 * @cmd_details: pointer to command details structure or NULL 4189 * 4190 * Update the specified TLV to the LLDP Local MIB for the given bridge type. 4191 * Firmware will place the complete LLDP MIB in response buffer with the 4192 * updated TLV. 4193 **/ 4194enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw, 4195 u8 bridge_type, void *buff, u16 buff_size, 4196 u16 old_len, u16 new_len, u16 offset, 4197 u16 *mib_len, 4198 struct i40e_asq_cmd_details *cmd_details) 4199{ 4200 struct i40e_aq_desc desc; 4201 struct i40e_aqc_lldp_update_tlv *cmd = 4202 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw; 4203 enum i40e_status_code status; 4204 4205 if (buff_size == 0 || !buff || offset == 0 || 4206 old_len == 0 || new_len == 0) 4207 return I40E_ERR_PARAM; 4208 4209 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv); 4210 4211 /* Indirect Command */ 4212 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4213 if (buff_size > I40E_AQ_LARGE_BUF) 4214 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4215 desc.datalen = CPU_TO_LE16(buff_size); 4216 4217 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4218 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4219 cmd->old_len = CPU_TO_LE16(old_len); 4220 cmd->new_offset = CPU_TO_LE16(offset); 4221 cmd->new_len = CPU_TO_LE16(new_len); 4222 4223 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4224 if (!status) { 4225 if (mib_len != NULL) 4226 *mib_len = LE16_TO_CPU(desc.datalen); 4227 } 4228 4229 return status; 4230} 4231 4232/** 4233 * i40e_aq_delete_lldp_tlv 4234 * @hw: pointer to the hw struct 4235 * @bridge_type: type of bridge 4236 * @buff: pointer to a user supplied buffer that has the TLV 4237 * @buff_size: length of the buffer 4238 * @tlv_len: length of the TLV to be deleted 4239 * @mib_len: length of the returned LLDP MIB 4240 * @cmd_details: pointer to command details structure or NULL 4241 * 4242 * Delete the specified TLV from LLDP Local MIB for the given bridge type. 4243 * The firmware places the entire LLDP MIB in the response buffer. 4244 **/ 4245enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw, 4246 u8 bridge_type, void *buff, u16 buff_size, 4247 u16 tlv_len, u16 *mib_len, 4248 struct i40e_asq_cmd_details *cmd_details) 4249{ 4250 struct i40e_aq_desc desc; 4251 struct i40e_aqc_lldp_add_tlv *cmd = 4252 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 4253 enum i40e_status_code status; 4254 4255 if (buff_size == 0 || !buff) 4256 return I40E_ERR_PARAM; 4257 4258 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv); 4259 4260 /* Indirect Command */ 4261 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4262 if (buff_size > I40E_AQ_LARGE_BUF) 4263 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4264 desc.datalen = CPU_TO_LE16(buff_size); 4265 cmd->len = CPU_TO_LE16(tlv_len); 4266 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4267 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4268 4269 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4270 if (!status) { 4271 if (mib_len != NULL) 4272 *mib_len = LE16_TO_CPU(desc.datalen); 4273 } 4274 4275 return status; 4276} 4277 4278/** 4279 * i40e_aq_stop_lldp 4280 * @hw: pointer to the hw struct 4281 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 4282 * @cmd_details: pointer to command details structure or NULL 4283 * 4284 * Stop or Shutdown the embedded LLDP Agent 4285 **/ 4286enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 4287 struct i40e_asq_cmd_details *cmd_details) 4288{ 4289 struct i40e_aq_desc desc; 4290 struct i40e_aqc_lldp_stop *cmd = 4291 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 4292 enum i40e_status_code status; 4293 4294 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 4295 4296 if (shutdown_agent) 4297 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 4298 4299 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4300 4301 return status; 4302} 4303 4304/** 4305 * i40e_aq_start_lldp 4306 * @hw: pointer to the hw struct 4307 * @cmd_details: pointer to command details structure or NULL 4308 * 4309 * Start the embedded LLDP Agent on all ports. 4310 **/ 4311enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw, 4312 struct i40e_asq_cmd_details *cmd_details) 4313{ 4314 struct i40e_aq_desc desc; 4315 struct i40e_aqc_lldp_start *cmd = 4316 (struct i40e_aqc_lldp_start *)&desc.params.raw; 4317 enum i40e_status_code status; 4318 4319 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 4320 4321 cmd->command = I40E_AQ_LLDP_AGENT_START; 4322 4323 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4324 4325 return status; 4326} 4327 4328/** 4329 * i40e_aq_get_cee_dcb_config 4330 * @hw: pointer to the hw struct 4331 * @buff: response buffer that stores CEE operational configuration 4332 * @buff_size: size of the buffer passed 4333 * @cmd_details: pointer to command details structure or NULL 4334 * 4335 * Get CEE DCBX mode operational configuration from firmware 4336 **/ 4337enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 4338 void *buff, u16 buff_size, 4339 struct i40e_asq_cmd_details *cmd_details) 4340{ 4341 struct i40e_aq_desc desc; 4342 enum i40e_status_code status; 4343 4344 if (buff_size == 0 || !buff) 4345 return I40E_ERR_PARAM; 4346 4347 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 4348 4349 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4350 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 4351 cmd_details); 4352 4353 return status; 4354} 4355 4356/** 4357 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW 4358 * @hw: pointer to the hw struct 4359 * @start_agent: True if DCBx Agent needs to be Started 4360 * False if DCBx Agent needs to be Stopped 4361 * @cmd_details: pointer to command details structure or NULL 4362 * 4363 * Start/Stop the embedded dcbx Agent 4364 **/ 4365enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw, 4366 bool start_agent, 4367 struct i40e_asq_cmd_details *cmd_details) 4368{ 4369 struct i40e_aq_desc desc; 4370 struct i40e_aqc_lldp_stop_start_specific_agent *cmd = 4371 (struct i40e_aqc_lldp_stop_start_specific_agent *) 4372 &desc.params.raw; 4373 enum i40e_status_code status; 4374 4375 i40e_fill_default_direct_cmd_desc(&desc, 4376 i40e_aqc_opc_lldp_stop_start_spec_agent); 4377 4378 if (start_agent) 4379 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK; 4380 4381 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4382 4383 return status; 4384} 4385 4386/** 4387 * i40e_aq_add_udp_tunnel 4388 * @hw: pointer to the hw struct 4389 * @udp_port: the UDP port to add in Host byte order 4390 * @header_len: length of the tunneling header length in DWords 4391 * @protocol_index: protocol index type 4392 * @filter_index: pointer to filter index 4393 * @cmd_details: pointer to command details structure or NULL 4394 * 4395 * Note: Firmware expects the udp_port value to be in Little Endian format, 4396 * and this function will call CPU_TO_LE16 to convert from Host byte order to 4397 * Little Endian order. 4398 **/ 4399enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 4400 u16 udp_port, u8 protocol_index, 4401 u8 *filter_index, 4402 struct i40e_asq_cmd_details *cmd_details) 4403{ 4404 struct i40e_aq_desc desc; 4405 struct i40e_aqc_add_udp_tunnel *cmd = 4406 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 4407 struct i40e_aqc_del_udp_tunnel_completion *resp = 4408 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 4409 enum i40e_status_code status; 4410 4411 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 4412 4413 cmd->udp_port = CPU_TO_LE16(udp_port); 4414 cmd->protocol_type = protocol_index; 4415 4416 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4417 4418 if (!status && filter_index) 4419 *filter_index = resp->index; 4420 4421 return status; 4422} 4423 4424/** 4425 * i40e_aq_del_udp_tunnel 4426 * @hw: pointer to the hw struct 4427 * @index: filter index 4428 * @cmd_details: pointer to command details structure or NULL 4429 **/ 4430enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 4431 struct i40e_asq_cmd_details *cmd_details) 4432{ 4433 struct i40e_aq_desc desc; 4434 struct i40e_aqc_remove_udp_tunnel *cmd = 4435 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 4436 enum i40e_status_code status; 4437 4438 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 4439 4440 cmd->index = index; 4441 4442 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4443 4444 return status; 4445} 4446 4447/** 4448 * i40e_aq_get_switch_resource_alloc (0x0204) 4449 * @hw: pointer to the hw struct 4450 * @num_entries: pointer to u8 to store the number of resource entries returned 4451 * @buf: pointer to a user supplied buffer. This buffer must be large enough 4452 * to store the resource information for all resource types. Each 4453 * resource type is a i40e_aqc_switch_resource_alloc_data structure. 4454 * @count: size, in bytes, of the buffer provided 4455 * @cmd_details: pointer to command details structure or NULL 4456 * 4457 * Query the resources allocated to a function. 4458 **/ 4459enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw, 4460 u8 *num_entries, 4461 struct i40e_aqc_switch_resource_alloc_element_resp *buf, 4462 u16 count, 4463 struct i40e_asq_cmd_details *cmd_details) 4464{ 4465 struct i40e_aq_desc desc; 4466 struct i40e_aqc_get_switch_resource_alloc *cmd_resp = 4467 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw; 4468 enum i40e_status_code status; 4469 u16 length = count * sizeof(*buf); 4470 4471 i40e_fill_default_direct_cmd_desc(&desc, 4472 i40e_aqc_opc_get_switch_resource_alloc); 4473 4474 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4475 if (length > I40E_AQ_LARGE_BUF) 4476 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4477 4478 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 4479 4480 if (!status && num_entries) 4481 *num_entries = cmd_resp->num_entries; 4482 4483 return status; 4484} 4485 4486/** 4487 * i40e_aq_delete_element - Delete switch element 4488 * @hw: pointer to the hw struct 4489 * @seid: the SEID to delete from the switch 4490 * @cmd_details: pointer to command details structure or NULL 4491 * 4492 * This deletes a switch element from the switch. 4493 **/ 4494enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 4495 struct i40e_asq_cmd_details *cmd_details) 4496{ 4497 struct i40e_aq_desc desc; 4498 struct i40e_aqc_switch_seid *cmd = 4499 (struct i40e_aqc_switch_seid *)&desc.params.raw; 4500 enum i40e_status_code status; 4501 4502 if (seid == 0) 4503 return I40E_ERR_PARAM; 4504 4505 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 4506 4507 cmd->seid = CPU_TO_LE16(seid); 4508 4509 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4510 4511 return status; 4512} 4513 4514/** 4515 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port 4516 * @hw: pointer to the hw struct 4517 * @flags: component flags 4518 * @mac_seid: uplink seid (MAC SEID) 4519 * @vsi_seid: connected vsi seid 4520 * @ret_seid: seid of create pv component 4521 * 4522 * This instantiates an i40e port virtualizer with specified flags. 4523 * Depending on specified flags the port virtualizer can act as a 4524 * 802.1Qbr port virtualizer or a 802.1Qbg S-component. 4525 */ 4526enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags, 4527 u16 mac_seid, u16 vsi_seid, 4528 u16 *ret_seid) 4529{ 4530 struct i40e_aq_desc desc; 4531 struct i40e_aqc_add_update_pv *cmd = 4532 (struct i40e_aqc_add_update_pv *)&desc.params.raw; 4533 struct i40e_aqc_add_update_pv_completion *resp = 4534 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw; 4535 enum i40e_status_code status; 4536 4537 if (vsi_seid == 0) 4538 return I40E_ERR_PARAM; 4539 4540 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv); 4541 cmd->command_flags = CPU_TO_LE16(flags); 4542 cmd->uplink_seid = CPU_TO_LE16(mac_seid); 4543 cmd->connected_seid = CPU_TO_LE16(vsi_seid); 4544 4545 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4546 if (!status && ret_seid) 4547 *ret_seid = LE16_TO_CPU(resp->pv_seid); 4548 4549 return status; 4550} 4551 4552/** 4553 * i40e_aq_add_tag - Add an S/E-tag 4554 * @hw: pointer to the hw struct 4555 * @direct_to_queue: should s-tag direct flow to a specific queue 4556 * @vsi_seid: VSI SEID to use this tag 4557 * @tag: value of the tag 4558 * @queue_num: queue number, only valid is direct_to_queue is TRUE 4559 * @tags_used: return value, number of tags in use by this PF 4560 * @tags_free: return value, number of unallocated tags 4561 * @cmd_details: pointer to command details structure or NULL 4562 * 4563 * This associates an S- or E-tag to a VSI in the switch complex. It returns 4564 * the number of tags allocated by the PF, and the number of unallocated 4565 * tags available. 4566 **/ 4567enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue, 4568 u16 vsi_seid, u16 tag, u16 queue_num, 4569 u16 *tags_used, u16 *tags_free, 4570 struct i40e_asq_cmd_details *cmd_details) 4571{ 4572 struct i40e_aq_desc desc; 4573 struct i40e_aqc_add_tag *cmd = 4574 (struct i40e_aqc_add_tag *)&desc.params.raw; 4575 struct i40e_aqc_add_remove_tag_completion *resp = 4576 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 4577 enum i40e_status_code status; 4578 4579 if (vsi_seid == 0) 4580 return I40E_ERR_PARAM; 4581 4582 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag); 4583 4584 cmd->seid = CPU_TO_LE16(vsi_seid); 4585 cmd->tag = CPU_TO_LE16(tag); 4586 if (direct_to_queue) { 4587 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE); 4588 cmd->queue_number = CPU_TO_LE16(queue_num); 4589 } 4590 4591 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4592 4593 if (!status) { 4594 if (tags_used != NULL) 4595 *tags_used = LE16_TO_CPU(resp->tags_used); 4596 if (tags_free != NULL) 4597 *tags_free = LE16_TO_CPU(resp->tags_free); 4598 } 4599 4600 return status; 4601} 4602 4603/** 4604 * i40e_aq_remove_tag - Remove an S- or E-tag 4605 * @hw: pointer to the hw struct 4606 * @vsi_seid: VSI SEID this tag is associated with 4607 * @tag: value of the S-tag to delete 4608 * @tags_used: return value, number of tags in use by this PF 4609 * @tags_free: return value, number of unallocated tags 4610 * @cmd_details: pointer to command details structure or NULL 4611 * 4612 * This deletes an S- or E-tag from a VSI in the switch complex. It returns 4613 * the number of tags allocated by the PF, and the number of unallocated 4614 * tags available. 4615 **/ 4616enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid, 4617 u16 tag, u16 *tags_used, u16 *tags_free, 4618 struct i40e_asq_cmd_details *cmd_details) 4619{ 4620 struct i40e_aq_desc desc; 4621 struct i40e_aqc_remove_tag *cmd = 4622 (struct i40e_aqc_remove_tag *)&desc.params.raw; 4623 struct i40e_aqc_add_remove_tag_completion *resp = 4624 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 4625 enum i40e_status_code status; 4626 4627 if (vsi_seid == 0) 4628 return I40E_ERR_PARAM; 4629 4630 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag); 4631 4632 cmd->seid = CPU_TO_LE16(vsi_seid); 4633 cmd->tag = CPU_TO_LE16(tag); 4634 4635 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4636 4637 if (!status) { 4638 if (tags_used != NULL) 4639 *tags_used = LE16_TO_CPU(resp->tags_used); 4640 if (tags_free != NULL) 4641 *tags_free = LE16_TO_CPU(resp->tags_free); 4642 } 4643 4644 return status; 4645} 4646 4647/** 4648 * i40e_aq_add_mcast_etag - Add a multicast E-tag 4649 * @hw: pointer to the hw struct 4650 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with 4651 * @etag: value of E-tag to add 4652 * @num_tags_in_buf: number of unicast E-tags in indirect buffer 4653 * @buf: address of indirect buffer 4654 * @tags_used: return value, number of E-tags in use by this port 4655 * @tags_free: return value, number of unallocated M-tags 4656 * @cmd_details: pointer to command details structure or NULL 4657 * 4658 * This associates a multicast E-tag to a port virtualizer. It will return 4659 * the number of tags allocated by the PF, and the number of unallocated 4660 * tags available. 4661 * 4662 * The indirect buffer pointed to by buf is a list of 2-byte E-tags, 4663 * num_tags_in_buf long. 4664 **/ 4665enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 4666 u16 etag, u8 num_tags_in_buf, void *buf, 4667 u16 *tags_used, u16 *tags_free, 4668 struct i40e_asq_cmd_details *cmd_details) 4669{ 4670 struct i40e_aq_desc desc; 4671 struct i40e_aqc_add_remove_mcast_etag *cmd = 4672 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 4673 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 4674 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 4675 enum i40e_status_code status; 4676 u16 length = sizeof(u16) * num_tags_in_buf; 4677 4678 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0)) 4679 return I40E_ERR_PARAM; 4680 4681 i40e_fill_default_direct_cmd_desc(&desc, 4682 i40e_aqc_opc_add_multicast_etag); 4683 4684 cmd->pv_seid = CPU_TO_LE16(pv_seid); 4685 cmd->etag = CPU_TO_LE16(etag); 4686 cmd->num_unicast_etags = num_tags_in_buf; 4687 4688 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4689 if (length > I40E_AQ_LARGE_BUF) 4690 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4691 4692 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 4693 4694 if (!status) { 4695 if (tags_used != NULL) 4696 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 4697 if (tags_free != NULL) 4698 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 4699 } 4700 4701 return status; 4702} 4703 4704/** 4705 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag 4706 * @hw: pointer to the hw struct 4707 * @pv_seid: Port Virtualizer SEID this M-tag is associated with 4708 * @etag: value of the E-tag to remove 4709 * @tags_used: return value, number of tags in use by this port 4710 * @tags_free: return value, number of unallocated tags 4711 * @cmd_details: pointer to command details structure or NULL 4712 * 4713 * This deletes an E-tag from the port virtualizer. It will return 4714 * the number of tags allocated by the port, and the number of unallocated 4715 * tags available. 4716 **/ 4717enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 4718 u16 etag, u16 *tags_used, u16 *tags_free, 4719 struct i40e_asq_cmd_details *cmd_details) 4720{ 4721 struct i40e_aq_desc desc; 4722 struct i40e_aqc_add_remove_mcast_etag *cmd = 4723 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 4724 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 4725 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 4726 enum i40e_status_code status; 4727 4728 4729 if (pv_seid == 0) 4730 return I40E_ERR_PARAM; 4731 4732 i40e_fill_default_direct_cmd_desc(&desc, 4733 i40e_aqc_opc_remove_multicast_etag); 4734 4735 cmd->pv_seid = CPU_TO_LE16(pv_seid); 4736 cmd->etag = CPU_TO_LE16(etag); 4737 4738 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4739 4740 if (!status) { 4741 if (tags_used != NULL) 4742 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 4743 if (tags_free != NULL) 4744 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 4745 } 4746 4747 return status; 4748} 4749 4750/** 4751 * i40e_aq_update_tag - Update an S/E-tag 4752 * @hw: pointer to the hw struct 4753 * @vsi_seid: VSI SEID using this S-tag 4754 * @old_tag: old tag value 4755 * @new_tag: new tag value 4756 * @tags_used: return value, number of tags in use by this PF 4757 * @tags_free: return value, number of unallocated tags 4758 * @cmd_details: pointer to command details structure or NULL 4759 * 4760 * This updates the value of the tag currently attached to this VSI 4761 * in the switch complex. It will return the number of tags allocated 4762 * by the PF, and the number of unallocated tags available. 4763 **/ 4764enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid, 4765 u16 old_tag, u16 new_tag, u16 *tags_used, 4766 u16 *tags_free, 4767 struct i40e_asq_cmd_details *cmd_details) 4768{ 4769 struct i40e_aq_desc desc; 4770 struct i40e_aqc_update_tag *cmd = 4771 (struct i40e_aqc_update_tag *)&desc.params.raw; 4772 struct i40e_aqc_update_tag_completion *resp = 4773 (struct i40e_aqc_update_tag_completion *)&desc.params.raw; 4774 enum i40e_status_code status; 4775 4776 if (vsi_seid == 0) 4777 return I40E_ERR_PARAM; 4778 4779 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag); 4780 4781 cmd->seid = CPU_TO_LE16(vsi_seid); 4782 cmd->old_tag = CPU_TO_LE16(old_tag); 4783 cmd->new_tag = CPU_TO_LE16(new_tag); 4784 4785 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4786 4787 if (!status) { 4788 if (tags_used != NULL) 4789 *tags_used = LE16_TO_CPU(resp->tags_used); 4790 if (tags_free != NULL) 4791 *tags_free = LE16_TO_CPU(resp->tags_free); 4792 } 4793 4794 return status; 4795} 4796 4797/** 4798 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs 4799 * @hw: pointer to the hw struct 4800 * @tcmap: TC map for request/release any ignore PFC condition 4801 * @request: request or release ignore PFC condition 4802 * @tcmap_ret: return TCs for which PFC is currently ignored 4803 * @cmd_details: pointer to command details structure or NULL 4804 * 4805 * This sends out request/release to ignore PFC condition for a TC. 4806 * It will return the TCs for which PFC is currently ignored. 4807 **/ 4808enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap, 4809 bool request, u8 *tcmap_ret, 4810 struct i40e_asq_cmd_details *cmd_details) 4811{ 4812 struct i40e_aq_desc desc; 4813 struct i40e_aqc_pfc_ignore *cmd_resp = 4814 (struct i40e_aqc_pfc_ignore *)&desc.params.raw; 4815 enum i40e_status_code status; 4816 4817 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc); 4818 4819 if (request) 4820 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET; 4821 4822 cmd_resp->tc_bitmap = tcmap; 4823 4824 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4825 4826 if (!status) { 4827 if (tcmap_ret != NULL) 4828 *tcmap_ret = cmd_resp->tc_bitmap; 4829 } 4830 4831 return status; 4832} 4833 4834/** 4835 * i40e_aq_dcb_updated - DCB Updated Command 4836 * @hw: pointer to the hw struct 4837 * @cmd_details: pointer to command details structure or NULL 4838 * 4839 * When LLDP is handled in PF this command is used by the PF 4840 * to notify EMP that a DCB setting is modified. 4841 * When LLDP is handled in EMP this command is used by the PF 4842 * to notify EMP whenever one of the following parameters get 4843 * modified: 4844 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA 4845 * - PCIRTT in PRTDCB_GENC.PCIRTT 4846 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME. 4847 * EMP will return when the shared RPB settings have been 4848 * recomputed and modified. The retval field in the descriptor 4849 * will be set to 0 when RPB is modified. 4850 **/ 4851enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw, 4852 struct i40e_asq_cmd_details *cmd_details) 4853{ 4854 struct i40e_aq_desc desc; 4855 enum i40e_status_code status; 4856 4857 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 4858 4859 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4860 4861 return status; 4862} 4863 4864/** 4865 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch. 4866 * @hw: pointer to the hw struct 4867 * @seid: defines the SEID of the switch for which the stats are requested 4868 * @vlan_id: the VLAN ID for which the statistics are requested 4869 * @stat_index: index of the statistics counters block assigned to this VLAN 4870 * @cmd_details: pointer to command details structure or NULL 4871 * 4872 * XL710 supports 128 smonVlanStats counters.This command is used to 4873 * allocate a set of smonVlanStats counters to a specific VLAN in a specific 4874 * switch. 4875 **/ 4876enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid, 4877 u16 vlan_id, u16 *stat_index, 4878 struct i40e_asq_cmd_details *cmd_details) 4879{ 4880 struct i40e_aq_desc desc; 4881 struct i40e_aqc_add_remove_statistics *cmd_resp = 4882 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 4883 enum i40e_status_code status; 4884 4885 if ((seid == 0) || (stat_index == NULL)) 4886 return I40E_ERR_PARAM; 4887 4888 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics); 4889 4890 cmd_resp->seid = CPU_TO_LE16(seid); 4891 cmd_resp->vlan = CPU_TO_LE16(vlan_id); 4892 4893 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4894 4895 if (!status && stat_index) 4896 *stat_index = LE16_TO_CPU(cmd_resp->stat_index); 4897 4898 return status; 4899} 4900 4901/** 4902 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch. 4903 * @hw: pointer to the hw struct 4904 * @seid: defines the SEID of the switch for which the stats are requested 4905 * @vlan_id: the VLAN ID for which the statistics are requested 4906 * @stat_index: index of the statistics counters block assigned to this VLAN 4907 * @cmd_details: pointer to command details structure or NULL 4908 * 4909 * XL710 supports 128 smonVlanStats counters.This command is used to 4910 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific 4911 * switch. 4912 **/ 4913enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid, 4914 u16 vlan_id, u16 stat_index, 4915 struct i40e_asq_cmd_details *cmd_details) 4916{ 4917 struct i40e_aq_desc desc; 4918 struct i40e_aqc_add_remove_statistics *cmd = 4919 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 4920 enum i40e_status_code status; 4921 4922 if (seid == 0) 4923 return I40E_ERR_PARAM; 4924 4925 i40e_fill_default_direct_cmd_desc(&desc, 4926 i40e_aqc_opc_remove_statistics); 4927 4928 cmd->seid = CPU_TO_LE16(seid); 4929 cmd->vlan = CPU_TO_LE16(vlan_id); 4930 cmd->stat_index = CPU_TO_LE16(stat_index); 4931 4932 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4933 4934 return status; 4935} 4936 4937/** 4938 * i40e_aq_set_port_parameters - set physical port parameters. 4939 * @hw: pointer to the hw struct 4940 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded 4941 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI 4942 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded 4943 * @double_vlan: if set double VLAN is enabled 4944 * @cmd_details: pointer to command details structure or NULL 4945 **/ 4946enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw, 4947 u16 bad_frame_vsi, bool save_bad_pac, 4948 bool pad_short_pac, bool double_vlan, 4949 struct i40e_asq_cmd_details *cmd_details) 4950{ 4951 struct i40e_aqc_set_port_parameters *cmd; 4952 enum i40e_status_code status; 4953 struct i40e_aq_desc desc; 4954 u16 command_flags = 0; 4955 4956 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw; 4957 4958 i40e_fill_default_direct_cmd_desc(&desc, 4959 i40e_aqc_opc_set_port_parameters); 4960 4961 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi); 4962 if (save_bad_pac) 4963 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS; 4964 if (pad_short_pac) 4965 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS; 4966 if (double_vlan) 4967 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA; 4968 cmd->command_flags = CPU_TO_LE16(command_flags); 4969 4970 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4971 4972 return status; 4973} 4974 4975/** 4976 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 4977 * @hw: pointer to the hw struct 4978 * @seid: seid for the physical port/switching component/vsi 4979 * @buff: Indirect buffer to hold data parameters and response 4980 * @buff_size: Indirect buffer size 4981 * @opcode: Tx scheduler AQ command opcode 4982 * @cmd_details: pointer to command details structure or NULL 4983 * 4984 * Generic command handler for Tx scheduler AQ commands 4985 **/ 4986static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 4987 void *buff, u16 buff_size, 4988 enum i40e_admin_queue_opc opcode, 4989 struct i40e_asq_cmd_details *cmd_details) 4990{ 4991 struct i40e_aq_desc desc; 4992 struct i40e_aqc_tx_sched_ind *cmd = 4993 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 4994 enum i40e_status_code status; 4995 bool cmd_param_flag = FALSE; 4996 4997 switch (opcode) { 4998 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 4999 case i40e_aqc_opc_configure_vsi_tc_bw: 5000 case i40e_aqc_opc_enable_switching_comp_ets: 5001 case i40e_aqc_opc_modify_switching_comp_ets: 5002 case i40e_aqc_opc_disable_switching_comp_ets: 5003 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 5004 case i40e_aqc_opc_configure_switching_comp_bw_config: 5005 cmd_param_flag = TRUE; 5006 break; 5007 case i40e_aqc_opc_query_vsi_bw_config: 5008 case i40e_aqc_opc_query_vsi_ets_sla_config: 5009 case i40e_aqc_opc_query_switching_comp_ets_config: 5010 case i40e_aqc_opc_query_port_ets_config: 5011 case i40e_aqc_opc_query_switching_comp_bw_config: 5012 cmd_param_flag = FALSE; 5013 break; 5014 default: 5015 return I40E_ERR_PARAM; 5016 } 5017 5018 i40e_fill_default_direct_cmd_desc(&desc, opcode); 5019 5020 /* Indirect command */ 5021 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 5022 if (cmd_param_flag) 5023 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 5024 if (buff_size > I40E_AQ_LARGE_BUF) 5025 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5026 5027 desc.datalen = CPU_TO_LE16(buff_size); 5028 5029 cmd->vsi_seid = CPU_TO_LE16(seid); 5030 5031 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5032 5033 return status; 5034} 5035 5036/** 5037 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 5038 * @hw: pointer to the hw struct 5039 * @seid: VSI seid 5040 * @credit: BW limit credits (0 = disabled) 5041 * @max_credit: Max BW limit credits 5042 * @cmd_details: pointer to command details structure or NULL 5043 **/ 5044enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 5045 u16 seid, u16 credit, u8 max_credit, 5046 struct i40e_asq_cmd_details *cmd_details) 5047{ 5048 struct i40e_aq_desc desc; 5049 struct i40e_aqc_configure_vsi_bw_limit *cmd = 5050 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 5051 enum i40e_status_code status; 5052 5053 i40e_fill_default_direct_cmd_desc(&desc, 5054 i40e_aqc_opc_configure_vsi_bw_limit); 5055 5056 cmd->vsi_seid = CPU_TO_LE16(seid); 5057 cmd->credit = CPU_TO_LE16(credit); 5058 cmd->max_credit = max_credit; 5059 5060 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5061 5062 return status; 5063} 5064 5065/** 5066 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit 5067 * @hw: pointer to the hw struct 5068 * @seid: switching component seid 5069 * @credit: BW limit credits (0 = disabled) 5070 * @max_bw: Max BW limit credits 5071 * @cmd_details: pointer to command details structure or NULL 5072 **/ 5073enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw, 5074 u16 seid, u16 credit, u8 max_bw, 5075 struct i40e_asq_cmd_details *cmd_details) 5076{ 5077 struct i40e_aq_desc desc; 5078 struct i40e_aqc_configure_switching_comp_bw_limit *cmd = 5079 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw; 5080 enum i40e_status_code status; 5081 5082 i40e_fill_default_direct_cmd_desc(&desc, 5083 i40e_aqc_opc_configure_switching_comp_bw_limit); 5084 5085 cmd->seid = CPU_TO_LE16(seid); 5086 cmd->credit = CPU_TO_LE16(credit); 5087 cmd->max_bw = max_bw; 5088 5089 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5090 5091 return status; 5092} 5093 5094/** 5095 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC 5096 * @hw: pointer to the hw struct 5097 * @seid: VSI seid 5098 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 5099 * @cmd_details: pointer to command details structure or NULL 5100 **/ 5101enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw, 5102 u16 seid, 5103 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data, 5104 struct i40e_asq_cmd_details *cmd_details) 5105{ 5106 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5107 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit, 5108 cmd_details); 5109} 5110 5111/** 5112 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 5113 * @hw: pointer to the hw struct 5114 * @seid: VSI seid 5115 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 5116 * @cmd_details: pointer to command details structure or NULL 5117 **/ 5118enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 5119 u16 seid, 5120 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 5121 struct i40e_asq_cmd_details *cmd_details) 5122{ 5123 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5124 i40e_aqc_opc_configure_vsi_tc_bw, 5125 cmd_details); 5126} 5127 5128/** 5129 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC 5130 * @hw: pointer to the hw struct 5131 * @seid: seid of the switching component 5132 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 5133 * @cmd_details: pointer to command details structure or NULL 5134 **/ 5135enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit( 5136 struct i40e_hw *hw, u16 seid, 5137 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data, 5138 struct i40e_asq_cmd_details *cmd_details) 5139{ 5140 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5141 i40e_aqc_opc_configure_switching_comp_ets_bw_limit, 5142 cmd_details); 5143} 5144 5145/** 5146 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 5147 * @hw: pointer to the hw struct 5148 * @seid: seid of the VSI 5149 * @bw_data: Buffer to hold VSI BW configuration 5150 * @cmd_details: pointer to command details structure or NULL 5151 **/ 5152enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 5153 u16 seid, 5154 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 5155 struct i40e_asq_cmd_details *cmd_details) 5156{ 5157 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5158 i40e_aqc_opc_query_vsi_bw_config, 5159 cmd_details); 5160} 5161 5162/** 5163 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 5164 * @hw: pointer to the hw struct 5165 * @seid: seid of the VSI 5166 * @bw_data: Buffer to hold VSI BW configuration per TC 5167 * @cmd_details: pointer to command details structure or NULL 5168 **/ 5169enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 5170 u16 seid, 5171 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 5172 struct i40e_asq_cmd_details *cmd_details) 5173{ 5174 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5175 i40e_aqc_opc_query_vsi_ets_sla_config, 5176 cmd_details); 5177} 5178 5179/** 5180 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 5181 * @hw: pointer to the hw struct 5182 * @seid: seid of the switching component 5183 * @bw_data: Buffer to hold switching component's per TC BW config 5184 * @cmd_details: pointer to command details structure or NULL 5185 **/ 5186enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 5187 u16 seid, 5188 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 5189 struct i40e_asq_cmd_details *cmd_details) 5190{ 5191 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5192 i40e_aqc_opc_query_switching_comp_ets_config, 5193 cmd_details); 5194} 5195 5196/** 5197 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 5198 * @hw: pointer to the hw struct 5199 * @seid: seid of the VSI or switching component connected to Physical Port 5200 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 5201 * @cmd_details: pointer to command details structure or NULL 5202 **/ 5203enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw, 5204 u16 seid, 5205 struct i40e_aqc_query_port_ets_config_resp *bw_data, 5206 struct i40e_asq_cmd_details *cmd_details) 5207{ 5208 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5209 i40e_aqc_opc_query_port_ets_config, 5210 cmd_details); 5211} 5212 5213/** 5214 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 5215 * @hw: pointer to the hw struct 5216 * @seid: seid of the switching component 5217 * @bw_data: Buffer to hold switching component's BW configuration 5218 * @cmd_details: pointer to command details structure or NULL 5219 **/ 5220enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 5221 u16 seid, 5222 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 5223 struct i40e_asq_cmd_details *cmd_details) 5224{ 5225 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5226 i40e_aqc_opc_query_switching_comp_bw_config, 5227 cmd_details); 5228} 5229 5230/** 5231 * i40e_validate_filter_settings 5232 * @hw: pointer to the hardware structure 5233 * @settings: Filter control settings 5234 * 5235 * Check and validate the filter control settings passed. 5236 * The function checks for the valid filter/context sizes being 5237 * passed for FCoE and PE. 5238 * 5239 * Returns I40E_SUCCESS if the values passed are valid and within 5240 * range else returns an error. 5241 **/ 5242static enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw, 5243 struct i40e_filter_control_settings *settings) 5244{ 5245 u32 fcoe_cntx_size, fcoe_filt_size; 5246 u32 pe_cntx_size, pe_filt_size; 5247 u32 fcoe_fmax; 5248 5249 u32 val; 5250 5251 /* Validate FCoE settings passed */ 5252 switch (settings->fcoe_filt_num) { 5253 case I40E_HASH_FILTER_SIZE_1K: 5254 case I40E_HASH_FILTER_SIZE_2K: 5255 case I40E_HASH_FILTER_SIZE_4K: 5256 case I40E_HASH_FILTER_SIZE_8K: 5257 case I40E_HASH_FILTER_SIZE_16K: 5258 case I40E_HASH_FILTER_SIZE_32K: 5259 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 5260 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 5261 break; 5262 default: 5263 return I40E_ERR_PARAM; 5264 } 5265 5266 switch (settings->fcoe_cntx_num) { 5267 case I40E_DMA_CNTX_SIZE_512: 5268 case I40E_DMA_CNTX_SIZE_1K: 5269 case I40E_DMA_CNTX_SIZE_2K: 5270 case I40E_DMA_CNTX_SIZE_4K: 5271 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 5272 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 5273 break; 5274 default: 5275 return I40E_ERR_PARAM; 5276 } 5277 5278 /* Validate PE settings passed */ 5279 switch (settings->pe_filt_num) { 5280 case I40E_HASH_FILTER_SIZE_1K: 5281 case I40E_HASH_FILTER_SIZE_2K: 5282 case I40E_HASH_FILTER_SIZE_4K: 5283 case I40E_HASH_FILTER_SIZE_8K: 5284 case I40E_HASH_FILTER_SIZE_16K: 5285 case I40E_HASH_FILTER_SIZE_32K: 5286 case I40E_HASH_FILTER_SIZE_64K: 5287 case I40E_HASH_FILTER_SIZE_128K: 5288 case I40E_HASH_FILTER_SIZE_256K: 5289 case I40E_HASH_FILTER_SIZE_512K: 5290 case I40E_HASH_FILTER_SIZE_1M: 5291 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 5292 pe_filt_size <<= (u32)settings->pe_filt_num; 5293 break; 5294 default: 5295 return I40E_ERR_PARAM; 5296 } 5297 5298 switch (settings->pe_cntx_num) { 5299 case I40E_DMA_CNTX_SIZE_512: 5300 case I40E_DMA_CNTX_SIZE_1K: 5301 case I40E_DMA_CNTX_SIZE_2K: 5302 case I40E_DMA_CNTX_SIZE_4K: 5303 case I40E_DMA_CNTX_SIZE_8K: 5304 case I40E_DMA_CNTX_SIZE_16K: 5305 case I40E_DMA_CNTX_SIZE_32K: 5306 case I40E_DMA_CNTX_SIZE_64K: 5307 case I40E_DMA_CNTX_SIZE_128K: 5308 case I40E_DMA_CNTX_SIZE_256K: 5309 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 5310 pe_cntx_size <<= (u32)settings->pe_cntx_num; 5311 break; 5312 default: 5313 return I40E_ERR_PARAM; 5314 } 5315 5316 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 5317 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 5318 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 5319 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 5320 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 5321 return I40E_ERR_INVALID_SIZE; 5322 5323 return I40E_SUCCESS; 5324} 5325 5326/** 5327 * i40e_set_filter_control 5328 * @hw: pointer to the hardware structure 5329 * @settings: Filter control settings 5330 * 5331 * Set the Queue Filters for PE/FCoE and enable filters required 5332 * for a single PF. It is expected that these settings are programmed 5333 * at the driver initialization time. 5334 **/ 5335enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw, 5336 struct i40e_filter_control_settings *settings) 5337{ 5338 enum i40e_status_code ret = I40E_SUCCESS; 5339 u32 hash_lut_size = 0; 5340 u32 val; 5341 5342 if (!settings) 5343 return I40E_ERR_PARAM; 5344 5345 /* Validate the input settings */ 5346 ret = i40e_validate_filter_settings(hw, settings); 5347 if (ret) 5348 return ret; 5349 5350 /* Read the PF Queue Filter control register */ 5351 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 5352 5353 /* Program required PE hash buckets for the PF */ 5354 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 5355 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 5356 I40E_PFQF_CTL_0_PEHSIZE_MASK; 5357 /* Program required PE contexts for the PF */ 5358 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 5359 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 5360 I40E_PFQF_CTL_0_PEDSIZE_MASK; 5361 5362 /* Program required FCoE hash buckets for the PF */ 5363 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 5364 val |= ((u32)settings->fcoe_filt_num << 5365 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 5366 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 5367 /* Program required FCoE DDP contexts for the PF */ 5368 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 5369 val |= ((u32)settings->fcoe_cntx_num << 5370 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 5371 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 5372 5373 /* Program Hash LUT size for the PF */ 5374 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 5375 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 5376 hash_lut_size = 1; 5377 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 5378 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 5379 5380 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 5381 if (settings->enable_fdir) 5382 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 5383 if (settings->enable_ethtype) 5384 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 5385 if (settings->enable_macvlan) 5386 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 5387 5388 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 5389 5390 return I40E_SUCCESS; 5391} 5392 5393/** 5394 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 5395 * @hw: pointer to the hw struct 5396 * @mac_addr: MAC address to use in the filter 5397 * @ethtype: Ethertype to use in the filter 5398 * @flags: Flags that needs to be applied to the filter 5399 * @vsi_seid: seid of the control VSI 5400 * @queue: VSI queue number to send the packet to 5401 * @is_add: Add control packet filter if True else remove 5402 * @stats: Structure to hold information on control filter counts 5403 * @cmd_details: pointer to command details structure or NULL 5404 * 5405 * This command will Add or Remove control packet filter for a control VSI. 5406 * In return it will update the total number of perfect filter count in 5407 * the stats member. 5408 **/ 5409enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 5410 u8 *mac_addr, u16 ethtype, u16 flags, 5411 u16 vsi_seid, u16 queue, bool is_add, 5412 struct i40e_control_filter_stats *stats, 5413 struct i40e_asq_cmd_details *cmd_details) 5414{ 5415 struct i40e_aq_desc desc; 5416 struct i40e_aqc_add_remove_control_packet_filter *cmd = 5417 (struct i40e_aqc_add_remove_control_packet_filter *) 5418 &desc.params.raw; 5419 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 5420 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 5421 &desc.params.raw; 5422 enum i40e_status_code status; 5423 5424 if (vsi_seid == 0) 5425 return I40E_ERR_PARAM; 5426 5427 if (is_add) { 5428 i40e_fill_default_direct_cmd_desc(&desc, 5429 i40e_aqc_opc_add_control_packet_filter); 5430 cmd->queue = CPU_TO_LE16(queue); 5431 } else { 5432 i40e_fill_default_direct_cmd_desc(&desc, 5433 i40e_aqc_opc_remove_control_packet_filter); 5434 } 5435 5436 if (mac_addr) 5437 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS, 5438 I40E_NONDMA_TO_NONDMA); 5439 5440 cmd->etype = CPU_TO_LE16(ethtype); 5441 cmd->flags = CPU_TO_LE16(flags); 5442 cmd->seid = CPU_TO_LE16(vsi_seid); 5443 5444 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5445 5446 if (!status && stats) { 5447 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used); 5448 stats->etype_used = LE16_TO_CPU(resp->etype_used); 5449 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free); 5450 stats->etype_free = LE16_TO_CPU(resp->etype_free); 5451 } 5452 5453 return status; 5454} 5455 5456/** 5457 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 5458 * @hw: pointer to the hw struct 5459 * @seid: VSI seid to add ethertype filter from 5460 **/ 5461#define I40E_FLOW_CONTROL_ETHTYPE 0x8808 5462void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 5463 u16 seid) 5464{ 5465 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 5466 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 5467 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 5468 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 5469 enum i40e_status_code status; 5470 5471 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 5472 seid, 0, TRUE, NULL, 5473 NULL); 5474 if (status) 5475 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 5476} 5477 5478/** 5479 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue 5480 * @filters: list of cloud filters 5481 * @filter_count: length of list 5482 * 5483 * There's an issue in the device where the Geneve VNI layout needs 5484 * to be shifted 1 byte over from the VxLAN VNI 5485 **/ 5486static void i40e_fix_up_geneve_vni( 5487 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 5488 u8 filter_count) 5489{ 5490 struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters; 5491 int i; 5492 5493 for (i = 0; i < filter_count; i++) { 5494 u16 tnl_type; 5495 u32 ti; 5496 5497 tnl_type = (LE16_TO_CPU(f[i].flags) & 5498 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5499 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5500 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5501 ti = LE32_TO_CPU(f[i].tenant_id); 5502 f[i].tenant_id = CPU_TO_LE32(ti << 8); 5503 } 5504 } 5505} 5506 5507/** 5508 * i40e_aq_add_cloud_filters 5509 * @hw: pointer to the hardware structure 5510 * @seid: VSI seid to add cloud filters from 5511 * @filters: Buffer which contains the filters to be added 5512 * @filter_count: number of filters contained in the buffer 5513 * 5514 * Set the cloud filters for a given VSI. The contents of the 5515 * i40e_aqc_add_remove_cloud_filters_element_data are filled 5516 * in by the caller of the function. 5517 * 5518 **/ 5519enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw, 5520 u16 seid, 5521 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 5522 u8 filter_count) 5523{ 5524 struct i40e_aq_desc desc; 5525 struct i40e_aqc_add_remove_cloud_filters *cmd = 5526 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5527 enum i40e_status_code status; 5528 u16 buff_len; 5529 5530 i40e_fill_default_direct_cmd_desc(&desc, 5531 i40e_aqc_opc_add_cloud_filters); 5532 5533 buff_len = filter_count * sizeof(*filters); 5534 desc.datalen = CPU_TO_LE16(buff_len); 5535 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5536 cmd->num_filters = filter_count; 5537 cmd->seid = CPU_TO_LE16(seid); 5538 5539 i40e_fix_up_geneve_vni(filters, filter_count); 5540 5541 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5542 5543 return status; 5544} 5545 5546/** 5547 * i40e_aq_remove_cloud_filters 5548 * @hw: pointer to the hardware structure 5549 * @seid: VSI seid to remove cloud filters from 5550 * @filters: Buffer which contains the filters to be removed 5551 * @filter_count: number of filters contained in the buffer 5552 * 5553 * Remove the cloud filters for a given VSI. The contents of the 5554 * i40e_aqc_add_remove_cloud_filters_element_data are filled 5555 * in by the caller of the function. 5556 * 5557 **/ 5558enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw, 5559 u16 seid, 5560 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 5561 u8 filter_count) 5562{ 5563 struct i40e_aq_desc desc; 5564 struct i40e_aqc_add_remove_cloud_filters *cmd = 5565 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5566 enum i40e_status_code status; 5567 u16 buff_len; 5568 5569 i40e_fill_default_direct_cmd_desc(&desc, 5570 i40e_aqc_opc_remove_cloud_filters); 5571 5572 buff_len = filter_count * sizeof(*filters); 5573 desc.datalen = CPU_TO_LE16(buff_len); 5574 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5575 cmd->num_filters = filter_count; 5576 cmd->seid = CPU_TO_LE16(seid); 5577 5578 i40e_fix_up_geneve_vni(filters, filter_count); 5579 5580 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5581 5582 return status; 5583} 5584 5585/** 5586 * i40e_aq_alternate_write 5587 * @hw: pointer to the hardware structure 5588 * @reg_addr0: address of first dword to be read 5589 * @reg_val0: value to be written under 'reg_addr0' 5590 * @reg_addr1: address of second dword to be read 5591 * @reg_val1: value to be written under 'reg_addr1' 5592 * 5593 * Write one or two dwords to alternate structure. Fields are indicated 5594 * by 'reg_addr0' and 'reg_addr1' register numbers. 5595 * 5596 **/ 5597enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw, 5598 u32 reg_addr0, u32 reg_val0, 5599 u32 reg_addr1, u32 reg_val1) 5600{ 5601 struct i40e_aq_desc desc; 5602 struct i40e_aqc_alternate_write *cmd_resp = 5603 (struct i40e_aqc_alternate_write *)&desc.params.raw; 5604 enum i40e_status_code status; 5605 5606 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write); 5607 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 5608 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 5609 cmd_resp->data0 = CPU_TO_LE32(reg_val0); 5610 cmd_resp->data1 = CPU_TO_LE32(reg_val1); 5611 5612 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5613 5614 return status; 5615} 5616 5617/** 5618 * i40e_aq_alternate_write_indirect 5619 * @hw: pointer to the hardware structure 5620 * @addr: address of a first register to be modified 5621 * @dw_count: number of alternate structure fields to write 5622 * @buffer: pointer to the command buffer 5623 * 5624 * Write 'dw_count' dwords from 'buffer' to alternate structure 5625 * starting at 'addr'. 5626 * 5627 **/ 5628enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw, 5629 u32 addr, u32 dw_count, void *buffer) 5630{ 5631 struct i40e_aq_desc desc; 5632 struct i40e_aqc_alternate_ind_write *cmd_resp = 5633 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 5634 enum i40e_status_code status; 5635 5636 if (buffer == NULL) 5637 return I40E_ERR_PARAM; 5638 5639 /* Indirect command */ 5640 i40e_fill_default_direct_cmd_desc(&desc, 5641 i40e_aqc_opc_alternate_write_indirect); 5642 5643 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 5644 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 5645 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 5646 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5647 5648 cmd_resp->address = CPU_TO_LE32(addr); 5649 cmd_resp->length = CPU_TO_LE32(dw_count); 5650 5651 status = i40e_asq_send_command(hw, &desc, buffer, 5652 I40E_LO_DWORD(4*dw_count), NULL); 5653 5654 return status; 5655} 5656 5657/** 5658 * i40e_aq_alternate_read 5659 * @hw: pointer to the hardware structure 5660 * @reg_addr0: address of first dword to be read 5661 * @reg_val0: pointer for data read from 'reg_addr0' 5662 * @reg_addr1: address of second dword to be read 5663 * @reg_val1: pointer for data read from 'reg_addr1' 5664 * 5665 * Read one or two dwords from alternate structure. Fields are indicated 5666 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 5667 * is not passed then only register at 'reg_addr0' is read. 5668 * 5669 **/ 5670enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw, 5671 u32 reg_addr0, u32 *reg_val0, 5672 u32 reg_addr1, u32 *reg_val1) 5673{ 5674 struct i40e_aq_desc desc; 5675 struct i40e_aqc_alternate_write *cmd_resp = 5676 (struct i40e_aqc_alternate_write *)&desc.params.raw; 5677 enum i40e_status_code status; 5678 5679 if (reg_val0 == NULL) 5680 return I40E_ERR_PARAM; 5681 5682 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 5683 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 5684 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 5685 5686 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5687 5688 if (status == I40E_SUCCESS) { 5689 *reg_val0 = LE32_TO_CPU(cmd_resp->data0); 5690 5691 if (reg_val1 != NULL) 5692 *reg_val1 = LE32_TO_CPU(cmd_resp->data1); 5693 } 5694 5695 return status; 5696} 5697 5698/** 5699 * i40e_aq_alternate_read_indirect 5700 * @hw: pointer to the hardware structure 5701 * @addr: address of the alternate structure field 5702 * @dw_count: number of alternate structure fields to read 5703 * @buffer: pointer to the command buffer 5704 * 5705 * Read 'dw_count' dwords from alternate structure starting at 'addr' and 5706 * place them in 'buffer'. The buffer should be allocated by caller. 5707 * 5708 **/ 5709enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw, 5710 u32 addr, u32 dw_count, void *buffer) 5711{ 5712 struct i40e_aq_desc desc; 5713 struct i40e_aqc_alternate_ind_write *cmd_resp = 5714 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 5715 enum i40e_status_code status; 5716 5717 if (buffer == NULL) 5718 return I40E_ERR_PARAM; 5719 5720 /* Indirect command */ 5721 i40e_fill_default_direct_cmd_desc(&desc, 5722 i40e_aqc_opc_alternate_read_indirect); 5723 5724 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 5725 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 5726 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 5727 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5728 5729 cmd_resp->address = CPU_TO_LE32(addr); 5730 cmd_resp->length = CPU_TO_LE32(dw_count); 5731 5732 status = i40e_asq_send_command(hw, &desc, buffer, 5733 I40E_LO_DWORD(4*dw_count), NULL); 5734 5735 return status; 5736} 5737 5738/** 5739 * i40e_aq_alternate_clear 5740 * @hw: pointer to the HW structure. 5741 * 5742 * Clear the alternate structures of the port from which the function 5743 * is called. 5744 * 5745 **/ 5746enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw) 5747{ 5748 struct i40e_aq_desc desc; 5749 enum i40e_status_code status; 5750 5751 i40e_fill_default_direct_cmd_desc(&desc, 5752 i40e_aqc_opc_alternate_clear_port); 5753 5754 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5755 5756 return status; 5757} 5758 5759/** 5760 * i40e_aq_alternate_write_done 5761 * @hw: pointer to the HW structure. 5762 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS 5763 * @reset_needed: indicates the SW should trigger GLOBAL reset 5764 * 5765 * Indicates to the FW that alternate structures have been changed. 5766 * 5767 **/ 5768enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw, 5769 u8 bios_mode, bool *reset_needed) 5770{ 5771 struct i40e_aq_desc desc; 5772 struct i40e_aqc_alternate_write_done *cmd = 5773 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 5774 enum i40e_status_code status; 5775 5776 if (reset_needed == NULL) 5777 return I40E_ERR_PARAM; 5778 5779 i40e_fill_default_direct_cmd_desc(&desc, 5780 i40e_aqc_opc_alternate_write_done); 5781 5782 cmd->cmd_flags = CPU_TO_LE16(bios_mode); 5783 5784 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5785 if (!status && reset_needed) 5786 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) & 5787 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0); 5788 5789 return status; 5790} 5791 5792/** 5793 * i40e_aq_set_oem_mode 5794 * @hw: pointer to the HW structure. 5795 * @oem_mode: the OEM mode to be used 5796 * 5797 * Sets the device to a specific operating mode. Currently the only supported 5798 * mode is no_clp, which causes FW to refrain from using Alternate RAM. 5799 * 5800 **/ 5801enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw, 5802 u8 oem_mode) 5803{ 5804 struct i40e_aq_desc desc; 5805 struct i40e_aqc_alternate_write_done *cmd = 5806 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 5807 enum i40e_status_code status; 5808 5809 i40e_fill_default_direct_cmd_desc(&desc, 5810 i40e_aqc_opc_alternate_set_mode); 5811 5812 cmd->cmd_flags = CPU_TO_LE16(oem_mode); 5813 5814 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5815 5816 return status; 5817} 5818 5819/** 5820 * i40e_aq_resume_port_tx 5821 * @hw: pointer to the hardware structure 5822 * @cmd_details: pointer to command details structure or NULL 5823 * 5824 * Resume port's Tx traffic 5825 **/ 5826enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw, 5827 struct i40e_asq_cmd_details *cmd_details) 5828{ 5829 struct i40e_aq_desc desc; 5830 enum i40e_status_code status; 5831 5832 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 5833 5834 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5835 5836 return status; 5837} 5838 5839/** 5840 * i40e_set_pci_config_data - store PCI bus info 5841 * @hw: pointer to hardware structure 5842 * @link_status: the link status word from PCI config space 5843 * 5844 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 5845 **/ 5846void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 5847{ 5848 hw->bus.type = i40e_bus_type_pci_express; 5849 5850 switch (link_status & I40E_PCI_LINK_WIDTH) { 5851 case I40E_PCI_LINK_WIDTH_1: 5852 hw->bus.width = i40e_bus_width_pcie_x1; 5853 break; 5854 case I40E_PCI_LINK_WIDTH_2: 5855 hw->bus.width = i40e_bus_width_pcie_x2; 5856 break; 5857 case I40E_PCI_LINK_WIDTH_4: 5858 hw->bus.width = i40e_bus_width_pcie_x4; 5859 break; 5860 case I40E_PCI_LINK_WIDTH_8: 5861 hw->bus.width = i40e_bus_width_pcie_x8; 5862 break; 5863 default: 5864 hw->bus.width = i40e_bus_width_unknown; 5865 break; 5866 } 5867 5868 switch (link_status & I40E_PCI_LINK_SPEED) { 5869 case I40E_PCI_LINK_SPEED_2500: 5870 hw->bus.speed = i40e_bus_speed_2500; 5871 break; 5872 case I40E_PCI_LINK_SPEED_5000: 5873 hw->bus.speed = i40e_bus_speed_5000; 5874 break; 5875 case I40E_PCI_LINK_SPEED_8000: 5876 hw->bus.speed = i40e_bus_speed_8000; 5877 break; 5878 default: 5879 hw->bus.speed = i40e_bus_speed_unknown; 5880 break; 5881 } 5882} 5883 5884/** 5885 * i40e_aq_debug_dump 5886 * @hw: pointer to the hardware structure 5887 * @cluster_id: specific cluster to dump 5888 * @table_id: table id within cluster 5889 * @start_index: index of line in the block to read 5890 * @buff_size: dump buffer size 5891 * @buff: dump buffer 5892 * @ret_buff_size: actual buffer size returned 5893 * @ret_next_table: next block to read 5894 * @ret_next_index: next index to read 5895 * 5896 * Dump internal FW/HW data for debug purposes. 5897 * 5898 **/ 5899enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 5900 u8 table_id, u32 start_index, u16 buff_size, 5901 void *buff, u16 *ret_buff_size, 5902 u8 *ret_next_table, u32 *ret_next_index, 5903 struct i40e_asq_cmd_details *cmd_details) 5904{ 5905 struct i40e_aq_desc desc; 5906 struct i40e_aqc_debug_dump_internals *cmd = 5907 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 5908 struct i40e_aqc_debug_dump_internals *resp = 5909 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 5910 enum i40e_status_code status; 5911 5912 if (buff_size == 0 || !buff) 5913 return I40E_ERR_PARAM; 5914 5915 i40e_fill_default_direct_cmd_desc(&desc, 5916 i40e_aqc_opc_debug_dump_internals); 5917 /* Indirect Command */ 5918 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 5919 if (buff_size > I40E_AQ_LARGE_BUF) 5920 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5921 5922 cmd->cluster_id = cluster_id; 5923 cmd->table_id = table_id; 5924 cmd->idx = CPU_TO_LE32(start_index); 5925 5926 desc.datalen = CPU_TO_LE16(buff_size); 5927 5928 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5929 if (!status) { 5930 if (ret_buff_size != NULL) 5931 *ret_buff_size = LE16_TO_CPU(desc.datalen); 5932 if (ret_next_table != NULL) 5933 *ret_next_table = resp->table_id; 5934 if (ret_next_index != NULL) 5935 *ret_next_index = LE32_TO_CPU(resp->idx); 5936 } 5937 5938 return status; 5939} 5940 5941/** 5942 * i40e_read_bw_from_alt_ram 5943 * @hw: pointer to the hardware structure 5944 * @max_bw: pointer for max_bw read 5945 * @min_bw: pointer for min_bw read 5946 * @min_valid: pointer for bool that is TRUE if min_bw is a valid value 5947 * @max_valid: pointer for bool that is TRUE if max_bw is a valid value 5948 * 5949 * Read bw from the alternate ram for the given pf 5950 **/ 5951enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 5952 u32 *max_bw, u32 *min_bw, 5953 bool *min_valid, bool *max_valid) 5954{ 5955 enum i40e_status_code status; 5956 u32 max_bw_addr, min_bw_addr; 5957 5958 /* Calculate the address of the min/max bw registers */ 5959 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 5960 I40E_ALT_STRUCT_MAX_BW_OFFSET + 5961 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 5962 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 5963 I40E_ALT_STRUCT_MIN_BW_OFFSET + 5964 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 5965 5966 /* Read the bandwidths from alt ram */ 5967 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 5968 min_bw_addr, min_bw); 5969 5970 if (*min_bw & I40E_ALT_BW_VALID_MASK) 5971 *min_valid = TRUE; 5972 else 5973 *min_valid = FALSE; 5974 5975 if (*max_bw & I40E_ALT_BW_VALID_MASK) 5976 *max_valid = TRUE; 5977 else 5978 *max_valid = FALSE; 5979 5980 return status; 5981} 5982 5983/** 5984 * i40e_aq_configure_partition_bw 5985 * @hw: pointer to the hardware structure 5986 * @bw_data: Buffer holding valid pfs and bw limits 5987 * @cmd_details: pointer to command details 5988 * 5989 * Configure partitions guaranteed/max bw 5990 **/ 5991enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw, 5992 struct i40e_aqc_configure_partition_bw_data *bw_data, 5993 struct i40e_asq_cmd_details *cmd_details) 5994{ 5995 enum i40e_status_code status; 5996 struct i40e_aq_desc desc; 5997 u16 bwd_size = sizeof(*bw_data); 5998 5999 i40e_fill_default_direct_cmd_desc(&desc, 6000 i40e_aqc_opc_configure_partition_bw); 6001 6002 /* Indirect command */ 6003 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 6004 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 6005 6006 desc.datalen = CPU_TO_LE16(bwd_size); 6007 6008 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details); 6009 6010 return status; 6011} 6012 6013/** 6014 * i40e_read_phy_register_clause22 6015 * @hw: pointer to the HW structure 6016 * @reg: register address in the page 6017 * @phy_adr: PHY address on MDIO interface 6018 * @value: PHY register value 6019 * 6020 * Reads specified PHY register value 6021 **/ 6022enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw, 6023 u16 reg, u8 phy_addr, u16 *value) 6024{ 6025 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6026 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6027 u32 command = 0; 6028 u16 retry = 1000; 6029 6030 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6031 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6032 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) | 6033 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 6034 (I40E_GLGEN_MSCA_MDICMD_MASK); 6035 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6036 do { 6037 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6038 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6039 status = I40E_SUCCESS; 6040 break; 6041 } 6042 i40e_usec_delay(10); 6043 retry--; 6044 } while (retry); 6045 6046 if (status) { 6047 i40e_debug(hw, I40E_DEBUG_PHY, 6048 "PHY: Can't write command to external PHY.\n"); 6049 } else { 6050 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 6051 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 6052 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 6053 } 6054 6055 return status; 6056} 6057 6058/** 6059 * i40e_write_phy_register_clause22 6060 * @hw: pointer to the HW structure 6061 * @reg: register address in the page 6062 * @phy_adr: PHY address on MDIO interface 6063 * @value: PHY register value 6064 * 6065 * Writes specified PHY register value 6066 **/ 6067enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw, 6068 u16 reg, u8 phy_addr, u16 value) 6069{ 6070 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6071 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6072 u32 command = 0; 6073 u16 retry = 1000; 6074 6075 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 6076 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 6077 6078 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6079 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6080 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) | 6081 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 6082 (I40E_GLGEN_MSCA_MDICMD_MASK); 6083 6084 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6085 do { 6086 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6087 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6088 status = I40E_SUCCESS; 6089 break; 6090 } 6091 i40e_usec_delay(10); 6092 retry--; 6093 } while (retry); 6094 6095 return status; 6096} 6097 6098/** 6099 * i40e_read_phy_register_clause45 6100 * @hw: pointer to the HW structure 6101 * @page: registers page number 6102 * @reg: register address in the page 6103 * @phy_adr: PHY address on MDIO interface 6104 * @value: PHY register value 6105 * 6106 * Reads specified PHY register value 6107 **/ 6108enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw, 6109 u8 page, u16 reg, u8 phy_addr, u16 *value) 6110{ 6111 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6112 u32 command = 0; 6113 u16 retry = 1000; 6114 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6115 6116 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 6117 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6118 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6119 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 6120 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6121 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6122 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6123 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6124 do { 6125 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6126 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6127 status = I40E_SUCCESS; 6128 break; 6129 } 6130 i40e_usec_delay(10); 6131 retry--; 6132 } while (retry); 6133 6134 if (status) { 6135 i40e_debug(hw, I40E_DEBUG_PHY, 6136 "PHY: Can't write command to external PHY.\n"); 6137 goto phy_read_end; 6138 } 6139 6140 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6141 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6142 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) | 6143 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6144 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6145 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6146 status = I40E_ERR_TIMEOUT; 6147 retry = 1000; 6148 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6149 do { 6150 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6151 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6152 status = I40E_SUCCESS; 6153 break; 6154 } 6155 i40e_usec_delay(10); 6156 retry--; 6157 } while (retry); 6158 6159 if (!status) { 6160 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 6161 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 6162 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 6163 } else { 6164 i40e_debug(hw, I40E_DEBUG_PHY, 6165 "PHY: Can't read register value from external PHY.\n"); 6166 } 6167 6168phy_read_end: 6169 return status; 6170} 6171 6172/** 6173 * i40e_write_phy_register_clause45 6174 * @hw: pointer to the HW structure 6175 * @page: registers page number 6176 * @reg: register address in the page 6177 * @phy_adr: PHY address on MDIO interface 6178 * @value: PHY register value 6179 * 6180 * Writes value to specified PHY register 6181 **/ 6182enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw, 6183 u8 page, u16 reg, u8 phy_addr, u16 value) 6184{ 6185 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6186 u32 command = 0; 6187 u16 retry = 1000; 6188 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6189 6190 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 6191 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6192 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6193 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 6194 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6195 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6196 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6197 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6198 do { 6199 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6200 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6201 status = I40E_SUCCESS; 6202 break; 6203 } 6204 i40e_usec_delay(10); 6205 retry--; 6206 } while (retry); 6207 if (status) { 6208 i40e_debug(hw, I40E_DEBUG_PHY, 6209 "PHY: Can't write command to external PHY.\n"); 6210 goto phy_write_end; 6211 } 6212 6213 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 6214 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 6215 6216 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6217 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6218 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) | 6219 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6220 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6221 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6222 status = I40E_ERR_TIMEOUT; 6223 retry = 1000; 6224 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6225 do { 6226 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6227 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6228 status = I40E_SUCCESS; 6229 break; 6230 } 6231 i40e_usec_delay(10); 6232 retry--; 6233 } while (retry); 6234 6235phy_write_end: 6236 return status; 6237} 6238 6239/** 6240 * i40e_write_phy_register 6241 * @hw: pointer to the HW structure 6242 * @page: registers page number 6243 * @reg: register address in the page 6244 * @phy_adr: PHY address on MDIO interface 6245 * @value: PHY register value 6246 * 6247 * Writes value to specified PHY register 6248 **/ 6249enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw, 6250 u8 page, u16 reg, u8 phy_addr, u16 value) 6251{ 6252 enum i40e_status_code status; 6253 6254 switch (hw->device_id) { 6255 case I40E_DEV_ID_1G_BASE_T_X722: 6256 status = i40e_write_phy_register_clause22(hw, 6257 reg, phy_addr, value); 6258 break; 6259 case I40E_DEV_ID_10G_BASE_T: 6260 case I40E_DEV_ID_10G_BASE_T4: 6261 case I40E_DEV_ID_10G_BASE_T_X722: 6262 case I40E_DEV_ID_25G_B: 6263 case I40E_DEV_ID_25G_SFP28: 6264 status = i40e_write_phy_register_clause45(hw, 6265 page, reg, phy_addr, value); 6266 break; 6267 default: 6268 status = I40E_ERR_UNKNOWN_PHY; 6269 break; 6270 } 6271 6272 return status; 6273} 6274 6275/** 6276 * i40e_read_phy_register 6277 * @hw: pointer to the HW structure 6278 * @page: registers page number 6279 * @reg: register address in the page 6280 * @phy_adr: PHY address on MDIO interface 6281 * @value: PHY register value 6282 * 6283 * Reads specified PHY register value 6284 **/ 6285enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw, 6286 u8 page, u16 reg, u8 phy_addr, u16 *value) 6287{ 6288 enum i40e_status_code status; 6289 6290 switch (hw->device_id) { 6291 case I40E_DEV_ID_1G_BASE_T_X722: 6292 status = i40e_read_phy_register_clause22(hw, reg, phy_addr, 6293 value); 6294 break; 6295 case I40E_DEV_ID_10G_BASE_T: 6296 case I40E_DEV_ID_10G_BASE_T4: 6297 case I40E_DEV_ID_10G_BASE_T_X722: 6298 case I40E_DEV_ID_25G_B: 6299 case I40E_DEV_ID_25G_SFP28: 6300 status = i40e_read_phy_register_clause45(hw, page, reg, 6301 phy_addr, value); 6302 break; 6303 default: 6304 status = I40E_ERR_UNKNOWN_PHY; 6305 break; 6306 } 6307 6308 return status; 6309} 6310 6311/** 6312 * i40e_get_phy_address 6313 * @hw: pointer to the HW structure 6314 * @dev_num: PHY port num that address we want 6315 * @phy_addr: Returned PHY address 6316 * 6317 * Gets PHY address for current port 6318 **/ 6319u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 6320{ 6321 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6322 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 6323 6324 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 6325} 6326 6327/** 6328 * i40e_blink_phy_led 6329 * @hw: pointer to the HW structure 6330 * @time: time how long led will blinks in secs 6331 * @interval: gap between LED on and off in msecs 6332 * 6333 * Blinks PHY link LED 6334 **/ 6335enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw, 6336 u32 time, u32 interval) 6337{ 6338 enum i40e_status_code status = I40E_SUCCESS; 6339 u32 i; 6340 u16 led_ctl = 0; 6341 u16 gpio_led_port; 6342 u16 led_reg; 6343 u16 led_addr = I40E_PHY_LED_PROV_REG_1; 6344 u8 phy_addr = 0; 6345 u8 port_num; 6346 6347 i = rd32(hw, I40E_PFGEN_PORTNUM); 6348 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 6349 phy_addr = i40e_get_phy_address(hw, port_num); 6350 6351 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 6352 led_addr++) { 6353 status = i40e_read_phy_register_clause45(hw, 6354 I40E_PHY_COM_REG_PAGE, 6355 led_addr, phy_addr, 6356 &led_reg); 6357 if (status) 6358 goto phy_blinking_end; 6359 led_ctl = led_reg; 6360 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 6361 led_reg = 0; 6362 status = i40e_write_phy_register_clause45(hw, 6363 I40E_PHY_COM_REG_PAGE, 6364 led_addr, phy_addr, 6365 led_reg); 6366 if (status) 6367 goto phy_blinking_end; 6368 break; 6369 } 6370 } 6371 6372 if (time > 0 && interval > 0) { 6373 for (i = 0; i < time * 1000; i += interval) { 6374 status = i40e_read_phy_register_clause45(hw, 6375 I40E_PHY_COM_REG_PAGE, 6376 led_addr, phy_addr, &led_reg); 6377 if (status) 6378 goto restore_config; 6379 if (led_reg & I40E_PHY_LED_MANUAL_ON) 6380 led_reg = 0; 6381 else 6382 led_reg = I40E_PHY_LED_MANUAL_ON; 6383 status = i40e_write_phy_register_clause45(hw, 6384 I40E_PHY_COM_REG_PAGE, 6385 led_addr, phy_addr, led_reg); 6386 if (status) 6387 goto restore_config; 6388 i40e_msec_delay(interval); 6389 } 6390 } 6391 6392restore_config: 6393 status = i40e_write_phy_register_clause45(hw, 6394 I40E_PHY_COM_REG_PAGE, 6395 led_addr, phy_addr, led_ctl); 6396 6397phy_blinking_end: 6398 return status; 6399} 6400 6401/** 6402 * i40e_led_get_phy - return current on/off mode 6403 * @hw: pointer to the hw struct 6404 * @led_addr: address of led register to use 6405 * @val: original value of register to use 6406 * 6407 **/ 6408enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 6409 u16 *val) 6410{ 6411 enum i40e_status_code status = I40E_SUCCESS; 6412 u16 gpio_led_port; 6413 u8 phy_addr = 0; 6414 u16 reg_val; 6415 u16 temp_addr; 6416 u8 port_num; 6417 u32 i; 6418 6419 temp_addr = I40E_PHY_LED_PROV_REG_1; 6420 i = rd32(hw, I40E_PFGEN_PORTNUM); 6421 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 6422 phy_addr = i40e_get_phy_address(hw, port_num); 6423 6424 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 6425 temp_addr++) { 6426 status = i40e_read_phy_register_clause45(hw, 6427 I40E_PHY_COM_REG_PAGE, 6428 temp_addr, phy_addr, 6429 ®_val); 6430 if (status) 6431 return status; 6432 *val = reg_val; 6433 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 6434 *led_addr = temp_addr; 6435 break; 6436 } 6437 } 6438 return status; 6439} 6440 6441/** 6442 * i40e_led_set_phy 6443 * @hw: pointer to the HW structure 6444 * @on: TRUE or FALSE 6445 * @mode: original val plus bit for set or ignore 6446 * Set led's on or off when controlled by the PHY 6447 * 6448 **/ 6449enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on, 6450 u16 led_addr, u32 mode) 6451{ 6452 enum i40e_status_code status = I40E_SUCCESS; 6453 u16 led_ctl = 0; 6454 u16 led_reg = 0; 6455 u8 phy_addr = 0; 6456 u8 port_num; 6457 u32 i; 6458 6459 i = rd32(hw, I40E_PFGEN_PORTNUM); 6460 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 6461 phy_addr = i40e_get_phy_address(hw, port_num); 6462 status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE, 6463 led_addr, phy_addr, &led_reg); 6464 if (status) 6465 return status; 6466 led_ctl = led_reg; 6467 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 6468 led_reg = 0; 6469 status = i40e_write_phy_register_clause45(hw, 6470 I40E_PHY_COM_REG_PAGE, 6471 led_addr, phy_addr, 6472 led_reg); 6473 if (status) 6474 return status; 6475 } 6476 status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE, 6477 led_addr, phy_addr, &led_reg); 6478 if (status) 6479 goto restore_config; 6480 if (on) 6481 led_reg = I40E_PHY_LED_MANUAL_ON; 6482 else 6483 led_reg = 0; 6484 status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE, 6485 led_addr, phy_addr, led_reg); 6486 if (status) 6487 goto restore_config; 6488 if (mode & I40E_PHY_LED_MODE_ORIG) { 6489 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 6490 status = i40e_write_phy_register_clause45(hw, 6491 I40E_PHY_COM_REG_PAGE, 6492 led_addr, phy_addr, led_ctl); 6493 } 6494 return status; 6495restore_config: 6496 status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE, 6497 led_addr, phy_addr, led_ctl); 6498 return status; 6499} 6500 6501/** 6502 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 6503 * @hw: pointer to the hw struct 6504 * @reg_addr: register address 6505 * @reg_val: ptr to register value 6506 * @cmd_details: pointer to command details structure or NULL 6507 * 6508 * Use the firmware to read the Rx control register, 6509 * especially useful if the Rx unit is under heavy pressure 6510 **/ 6511enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 6512 u32 reg_addr, u32 *reg_val, 6513 struct i40e_asq_cmd_details *cmd_details) 6514{ 6515 struct i40e_aq_desc desc; 6516 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = 6517 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 6518 enum i40e_status_code status; 6519 6520 if (reg_val == NULL) 6521 return I40E_ERR_PARAM; 6522 6523 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 6524 6525 cmd_resp->address = CPU_TO_LE32(reg_addr); 6526 6527 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6528 6529 if (status == I40E_SUCCESS) 6530 *reg_val = LE32_TO_CPU(cmd_resp->value); 6531 6532 return status; 6533} 6534 6535/** 6536 * i40e_read_rx_ctl - read from an Rx control register 6537 * @hw: pointer to the hw struct 6538 * @reg_addr: register address 6539 **/ 6540u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 6541{ 6542 enum i40e_status_code status = I40E_SUCCESS; 6543 bool use_register; 6544 int retry = 5; 6545 u32 val = 0; 6546 6547 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5); 6548 if (!use_register) { 6549do_retry: 6550 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 6551 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 6552 i40e_msec_delay(1); 6553 retry--; 6554 goto do_retry; 6555 } 6556 } 6557 6558 /* if the AQ access failed, try the old-fashioned way */ 6559 if (status || use_register) 6560 val = rd32(hw, reg_addr); 6561 6562 return val; 6563} 6564 6565/** 6566 * i40e_aq_rx_ctl_write_register 6567 * @hw: pointer to the hw struct 6568 * @reg_addr: register address 6569 * @reg_val: register value 6570 * @cmd_details: pointer to command details structure or NULL 6571 * 6572 * Use the firmware to write to an Rx control register, 6573 * especially useful if the Rx unit is under heavy pressure 6574 **/ 6575enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 6576 u32 reg_addr, u32 reg_val, 6577 struct i40e_asq_cmd_details *cmd_details) 6578{ 6579 struct i40e_aq_desc desc; 6580 struct i40e_aqc_rx_ctl_reg_read_write *cmd = 6581 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 6582 enum i40e_status_code status; 6583 6584 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 6585 6586 cmd->address = CPU_TO_LE32(reg_addr); 6587 cmd->value = CPU_TO_LE32(reg_val); 6588 6589 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6590 6591 return status; 6592} 6593 6594/** 6595 * i40e_write_rx_ctl - write to an Rx control register 6596 * @hw: pointer to the hw struct 6597 * @reg_addr: register address 6598 * @reg_val: register value 6599 **/ 6600void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 6601{ 6602 enum i40e_status_code status = I40E_SUCCESS; 6603 bool use_register; 6604 int retry = 5; 6605 6606 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5); 6607 if (!use_register) { 6608do_retry: 6609 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 6610 reg_val, NULL); 6611 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 6612 i40e_msec_delay(1); 6613 retry--; 6614 goto do_retry; 6615 } 6616 } 6617 6618 /* if the AQ access failed, try the old-fashioned way */ 6619 if (status || use_register) 6620 wr32(hw, reg_addr, reg_val); 6621} 6622 6623/** 6624 * i40e_aq_send_msg_to_pf 6625 * @hw: pointer to the hardware structure 6626 * @v_opcode: opcodes for VF-PF communication 6627 * @v_retval: return error code 6628 * @msg: pointer to the msg buffer 6629 * @msglen: msg length 6630 * @cmd_details: pointer to command details 6631 * 6632 * Send message to PF driver using admin queue. By default, this message 6633 * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for 6634 * completion before returning. 6635 **/ 6636enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw, 6637 enum i40e_virtchnl_ops v_opcode, 6638 enum i40e_status_code v_retval, 6639 u8 *msg, u16 msglen, 6640 struct i40e_asq_cmd_details *cmd_details) 6641{ 6642 struct i40e_aq_desc desc; 6643 struct i40e_asq_cmd_details details; 6644 enum i40e_status_code status; 6645 6646 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf); 6647 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 6648 desc.cookie_high = CPU_TO_LE32(v_opcode); 6649 desc.cookie_low = CPU_TO_LE32(v_retval); 6650 if (msglen) { 6651 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF 6652 | I40E_AQ_FLAG_RD)); 6653 if (msglen > I40E_AQ_LARGE_BUF) 6654 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 6655 desc.datalen = CPU_TO_LE16(msglen); 6656 } 6657 if (!cmd_details) { 6658 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM); 6659 details.async = TRUE; 6660 cmd_details = &details; 6661 } 6662 status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg, 6663 msglen, cmd_details); 6664 return status; 6665} 6666 6667/** 6668 * i40e_vf_parse_hw_config 6669 * @hw: pointer to the hardware structure 6670 * @msg: pointer to the virtual channel VF resource structure 6671 * 6672 * Given a VF resource message from the PF, populate the hw struct 6673 * with appropriate information. 6674 **/ 6675void i40e_vf_parse_hw_config(struct i40e_hw *hw, 6676 struct i40e_virtchnl_vf_resource *msg) 6677{ 6678 struct i40e_virtchnl_vsi_resource *vsi_res; 6679 int i; 6680 6681 vsi_res = &msg->vsi_res[0]; 6682 6683 hw->dev_caps.num_vsis = msg->num_vsis; 6684 hw->dev_caps.num_rx_qp = msg->num_queue_pairs; 6685 hw->dev_caps.num_tx_qp = msg->num_queue_pairs; 6686 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors; 6687 hw->dev_caps.dcb = msg->vf_offload_flags & 6688 I40E_VIRTCHNL_VF_OFFLOAD_L2; 6689 hw->dev_caps.fcoe = (msg->vf_offload_flags & 6690 I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0; 6691 hw->dev_caps.iwarp = (msg->vf_offload_flags & 6692 I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0; 6693 for (i = 0; i < msg->num_vsis; i++) { 6694 if (vsi_res->vsi_type == I40E_VSI_SRIOV) { 6695 i40e_memcpy(hw->mac.perm_addr, 6696 vsi_res->default_mac_addr, 6697 I40E_ETH_LENGTH_OF_ADDRESS, 6698 I40E_NONDMA_TO_NONDMA); 6699 i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr, 6700 I40E_ETH_LENGTH_OF_ADDRESS, 6701 I40E_NONDMA_TO_NONDMA); 6702 } 6703 vsi_res++; 6704 } 6705} 6706 6707/** 6708 * i40e_vf_reset 6709 * @hw: pointer to the hardware structure 6710 * 6711 * Send a VF_RESET message to the PF. Does not wait for response from PF 6712 * as none will be forthcoming. Immediately after calling this function, 6713 * the admin queue should be shut down and (optionally) reinitialized. 6714 **/ 6715enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw) 6716{ 6717 return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF, 6718 I40E_SUCCESS, NULL, 0, NULL); 6719} 6720 6721/** 6722 * i40e_aq_set_arp_proxy_config 6723 * @hw: pointer to the HW structure 6724 * @proxy_config - pointer to proxy config command table struct 6725 * @cmd_details: pointer to command details 6726 * 6727 * Set ARP offload parameters from pre-populated 6728 * i40e_aqc_arp_proxy_data struct 6729 **/ 6730enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw, 6731 struct i40e_aqc_arp_proxy_data *proxy_config, 6732 struct i40e_asq_cmd_details *cmd_details) 6733{ 6734 struct i40e_aq_desc desc; 6735 enum i40e_status_code status; 6736 6737 if (!proxy_config) 6738 return I40E_ERR_PARAM; 6739 6740 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config); 6741 6742 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 6743 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 6744 desc.params.external.addr_high = 6745 CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config)); 6746 desc.params.external.addr_low = 6747 CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config)); 6748 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data)); 6749 6750 status = i40e_asq_send_command(hw, &desc, proxy_config, 6751 sizeof(struct i40e_aqc_arp_proxy_data), 6752 cmd_details); 6753 6754 return status; 6755} 6756 6757/** 6758 * i40e_aq_opc_set_ns_proxy_table_entry 6759 * @hw: pointer to the HW structure 6760 * @ns_proxy_table_entry: pointer to NS table entry command struct 6761 * @cmd_details: pointer to command details 6762 * 6763 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters 6764 * from pre-populated i40e_aqc_ns_proxy_data struct 6765 **/ 6766enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw, 6767 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry, 6768 struct i40e_asq_cmd_details *cmd_details) 6769{ 6770 struct i40e_aq_desc desc; 6771 enum i40e_status_code status; 6772 6773 if (!ns_proxy_table_entry) 6774 return I40E_ERR_PARAM; 6775 6776 i40e_fill_default_direct_cmd_desc(&desc, 6777 i40e_aqc_opc_set_ns_proxy_table_entry); 6778 6779 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 6780 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 6781 desc.params.external.addr_high = 6782 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry)); 6783 desc.params.external.addr_low = 6784 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry)); 6785 desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data)); 6786 6787 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry, 6788 sizeof(struct i40e_aqc_ns_proxy_data), 6789 cmd_details); 6790 6791 return status; 6792} 6793 6794/** 6795 * i40e_aq_set_clear_wol_filter 6796 * @hw: pointer to the hw struct 6797 * @filter_index: index of filter to modify (0-7) 6798 * @filter: buffer containing filter to be set 6799 * @set_filter: TRUE to set filter, FALSE to clear filter 6800 * @no_wol_tco: if TRUE, pass through packets cannot cause wake-up 6801 * if FALSE, pass through packets may cause wake-up 6802 * @filter_valid: TRUE if filter action is valid 6803 * @no_wol_tco_valid: TRUE if no WoL in TCO traffic action valid 6804 * @cmd_details: pointer to command details structure or NULL 6805 * 6806 * Set or clear WoL filter for port attached to the PF 6807 **/ 6808enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw, 6809 u8 filter_index, 6810 struct i40e_aqc_set_wol_filter_data *filter, 6811 bool set_filter, bool no_wol_tco, 6812 bool filter_valid, bool no_wol_tco_valid, 6813 struct i40e_asq_cmd_details *cmd_details) 6814{ 6815 struct i40e_aq_desc desc; 6816 struct i40e_aqc_set_wol_filter *cmd = 6817 (struct i40e_aqc_set_wol_filter *)&desc.params.raw; 6818 enum i40e_status_code status; 6819 u16 cmd_flags = 0; 6820 u16 valid_flags = 0; 6821 u16 buff_len = 0; 6822 6823 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter); 6824 6825 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS) 6826 return I40E_ERR_PARAM; 6827 cmd->filter_index = CPU_TO_LE16(filter_index); 6828 6829 if (set_filter) { 6830 if (!filter) 6831 return I40E_ERR_PARAM; 6832 6833 cmd_flags |= I40E_AQC_SET_WOL_FILTER; 6834 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR; 6835 } 6836 6837 if (no_wol_tco) 6838 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL; 6839 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 6840 6841 if (filter_valid) 6842 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID; 6843 if (no_wol_tco_valid) 6844 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID; 6845 cmd->valid_flags = CPU_TO_LE16(valid_flags); 6846 6847 buff_len = sizeof(*filter); 6848 desc.datalen = CPU_TO_LE16(buff_len); 6849 6850 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 6851 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 6852 6853 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter)); 6854 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter)); 6855 6856 status = i40e_asq_send_command(hw, &desc, filter, 6857 buff_len, cmd_details); 6858 6859 return status; 6860} 6861 6862/** 6863 * i40e_aq_get_wake_event_reason 6864 * @hw: pointer to the hw struct 6865 * @wake_reason: return value, index of matching filter 6866 * @cmd_details: pointer to command details structure or NULL 6867 * 6868 * Get information for the reason of a Wake Up event 6869 **/ 6870enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw, 6871 u16 *wake_reason, 6872 struct i40e_asq_cmd_details *cmd_details) 6873{ 6874 struct i40e_aq_desc desc; 6875 struct i40e_aqc_get_wake_reason_completion *resp = 6876 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw; 6877 enum i40e_status_code status; 6878 6879 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason); 6880 6881 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6882 6883 if (status == I40E_SUCCESS) 6884 *wake_reason = LE16_TO_CPU(resp->wake_reason); 6885 6886 return status; 6887} 6888 6889/** 6890* i40e_aq_clear_all_wol_filters 6891* @hw: pointer to the hw struct 6892* @cmd_details: pointer to command details structure or NULL 6893* 6894* Get information for the reason of a Wake Up event 6895**/ 6896enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw, 6897 struct i40e_asq_cmd_details *cmd_details) 6898{ 6899 struct i40e_aq_desc desc; 6900 enum i40e_status_code status; 6901 6902 i40e_fill_default_direct_cmd_desc(&desc, 6903 i40e_aqc_opc_clear_all_wol_filters); 6904 6905 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6906 6907 return status; 6908} 6909 6910