i40e_adminq_cmd.h revision 349163
1/****************************************************************************** 2 3 Copyright (c) 2013-2019, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: stable/11/sys/dev/ixl/i40e_adminq_cmd.h 349163 2019-06-18 00:08:02Z erj $*/ 34 35#ifndef _I40E_ADMINQ_CMD_H_ 36#define _I40E_ADMINQ_CMD_H_ 37 38/* This header file defines the i40e Admin Queue commands and is shared between 39 * i40e Firmware and Software. 40 * 41 * This file needs to comply with the Linux Kernel coding style. 42 */ 43 44 45#define I40E_FW_API_VERSION_MAJOR 0x0001 46#define I40E_FW_API_VERSION_MINOR_X722 0x0008 47#define I40E_FW_API_VERSION_MINOR_X710 0x0008 48 49#define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \ 50 I40E_FW_API_VERSION_MINOR_X710 : \ 51 I40E_FW_API_VERSION_MINOR_X722) 52 53/* API version 1.7 implements additional link and PHY-specific APIs */ 54#define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007 55/* API version 1.6 for X722 devices adds ability to stop FW LLDP agent */ 56#define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006 57 58struct i40e_aq_desc { 59 __le16 flags; 60 __le16 opcode; 61 __le16 datalen; 62 __le16 retval; 63 __le32 cookie_high; 64 __le32 cookie_low; 65 union { 66 struct { 67 __le32 param0; 68 __le32 param1; 69 __le32 param2; 70 __le32 param3; 71 } internal; 72 struct { 73 __le32 param0; 74 __le32 param1; 75 __le32 addr_high; 76 __le32 addr_low; 77 } external; 78 u8 raw[16]; 79 } params; 80}; 81 82/* Flags sub-structure 83 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 84 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 85 */ 86 87/* command flags and offsets*/ 88#define I40E_AQ_FLAG_DD_SHIFT 0 89#define I40E_AQ_FLAG_CMP_SHIFT 1 90#define I40E_AQ_FLAG_ERR_SHIFT 2 91#define I40E_AQ_FLAG_VFE_SHIFT 3 92#define I40E_AQ_FLAG_LB_SHIFT 9 93#define I40E_AQ_FLAG_RD_SHIFT 10 94#define I40E_AQ_FLAG_VFC_SHIFT 11 95#define I40E_AQ_FLAG_BUF_SHIFT 12 96#define I40E_AQ_FLAG_SI_SHIFT 13 97#define I40E_AQ_FLAG_EI_SHIFT 14 98#define I40E_AQ_FLAG_FE_SHIFT 15 99 100#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 101#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 102#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 103#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 104#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 105#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 106#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 107#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 108#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 109#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 110#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 111 112/* error codes */ 113enum i40e_admin_queue_err { 114 I40E_AQ_RC_OK = 0, /* success */ 115 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 116 I40E_AQ_RC_ENOENT = 2, /* No such element */ 117 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 118 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 119 I40E_AQ_RC_EIO = 5, /* I/O error */ 120 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 121 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 122 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 123 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 124 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 125 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 126 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 127 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 128 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 129 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 130 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 131 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 132 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 133 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 134 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 135 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 136 I40E_AQ_RC_EFBIG = 22, /* File too large */ 137}; 138 139/* Admin Queue command opcodes */ 140enum i40e_admin_queue_opc { 141 /* aq commands */ 142 i40e_aqc_opc_get_version = 0x0001, 143 i40e_aqc_opc_driver_version = 0x0002, 144 i40e_aqc_opc_queue_shutdown = 0x0003, 145 i40e_aqc_opc_set_pf_context = 0x0004, 146 147 /* resource ownership */ 148 i40e_aqc_opc_request_resource = 0x0008, 149 i40e_aqc_opc_release_resource = 0x0009, 150 151 i40e_aqc_opc_list_func_capabilities = 0x000A, 152 i40e_aqc_opc_list_dev_capabilities = 0x000B, 153 154 /* Proxy commands */ 155 i40e_aqc_opc_set_proxy_config = 0x0104, 156 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, 157 158 /* LAA */ 159 i40e_aqc_opc_mac_address_read = 0x0107, 160 i40e_aqc_opc_mac_address_write = 0x0108, 161 162 /* PXE */ 163 i40e_aqc_opc_clear_pxe_mode = 0x0110, 164 165 /* WoL commands */ 166 i40e_aqc_opc_set_wol_filter = 0x0120, 167 i40e_aqc_opc_get_wake_reason = 0x0121, 168 i40e_aqc_opc_clear_all_wol_filters = 0x025E, 169 170 /* internal switch commands */ 171 i40e_aqc_opc_get_switch_config = 0x0200, 172 i40e_aqc_opc_add_statistics = 0x0201, 173 i40e_aqc_opc_remove_statistics = 0x0202, 174 i40e_aqc_opc_set_port_parameters = 0x0203, 175 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 176 i40e_aqc_opc_set_switch_config = 0x0205, 177 i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 178 i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 179 180 i40e_aqc_opc_add_vsi = 0x0210, 181 i40e_aqc_opc_update_vsi_parameters = 0x0211, 182 i40e_aqc_opc_get_vsi_parameters = 0x0212, 183 184 i40e_aqc_opc_add_pv = 0x0220, 185 i40e_aqc_opc_update_pv_parameters = 0x0221, 186 i40e_aqc_opc_get_pv_parameters = 0x0222, 187 188 i40e_aqc_opc_add_veb = 0x0230, 189 i40e_aqc_opc_update_veb_parameters = 0x0231, 190 i40e_aqc_opc_get_veb_parameters = 0x0232, 191 192 i40e_aqc_opc_delete_element = 0x0243, 193 194 i40e_aqc_opc_add_macvlan = 0x0250, 195 i40e_aqc_opc_remove_macvlan = 0x0251, 196 i40e_aqc_opc_add_vlan = 0x0252, 197 i40e_aqc_opc_remove_vlan = 0x0253, 198 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 199 i40e_aqc_opc_add_tag = 0x0255, 200 i40e_aqc_opc_remove_tag = 0x0256, 201 i40e_aqc_opc_add_multicast_etag = 0x0257, 202 i40e_aqc_opc_remove_multicast_etag = 0x0258, 203 i40e_aqc_opc_update_tag = 0x0259, 204 i40e_aqc_opc_add_control_packet_filter = 0x025A, 205 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 206 i40e_aqc_opc_add_cloud_filters = 0x025C, 207 i40e_aqc_opc_remove_cloud_filters = 0x025D, 208 i40e_aqc_opc_clear_wol_switch_filters = 0x025E, 209 210 i40e_aqc_opc_add_mirror_rule = 0x0260, 211 i40e_aqc_opc_delete_mirror_rule = 0x0261, 212 213 /* DCB commands */ 214 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 215 i40e_aqc_opc_dcb_updated = 0x0302, 216 i40e_aqc_opc_set_dcb_parameters = 0x0303, 217 218 /* TX scheduler */ 219 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 220 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 221 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 222 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 223 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 224 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 225 226 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 227 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 228 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 229 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 230 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 231 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 232 i40e_aqc_opc_query_port_ets_config = 0x0419, 233 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 234 i40e_aqc_opc_suspend_port_tx = 0x041B, 235 i40e_aqc_opc_resume_port_tx = 0x041C, 236 i40e_aqc_opc_configure_partition_bw = 0x041D, 237 /* hmc */ 238 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 239 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 240 241 /* phy commands*/ 242 i40e_aqc_opc_get_phy_abilities = 0x0600, 243 i40e_aqc_opc_set_phy_config = 0x0601, 244 i40e_aqc_opc_set_mac_config = 0x0603, 245 i40e_aqc_opc_set_link_restart_an = 0x0605, 246 i40e_aqc_opc_get_link_status = 0x0607, 247 i40e_aqc_opc_set_phy_int_mask = 0x0613, 248 i40e_aqc_opc_get_local_advt_reg = 0x0614, 249 i40e_aqc_opc_set_local_advt_reg = 0x0615, 250 i40e_aqc_opc_get_partner_advt = 0x0616, 251 i40e_aqc_opc_set_lb_modes = 0x0618, 252 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 253 i40e_aqc_opc_set_phy_debug = 0x0622, 254 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 255 i40e_aqc_opc_run_phy_activity = 0x0626, 256 i40e_aqc_opc_set_phy_register = 0x0628, 257 i40e_aqc_opc_get_phy_register = 0x0629, 258 259 /* NVM commands */ 260 i40e_aqc_opc_nvm_read = 0x0701, 261 i40e_aqc_opc_nvm_erase = 0x0702, 262 i40e_aqc_opc_nvm_update = 0x0703, 263 i40e_aqc_opc_nvm_config_read = 0x0704, 264 i40e_aqc_opc_nvm_config_write = 0x0705, 265 i40e_aqc_opc_nvm_progress = 0x0706, 266 i40e_aqc_opc_oem_post_update = 0x0720, 267 i40e_aqc_opc_thermal_sensor = 0x0721, 268 269 /* virtualization commands */ 270 i40e_aqc_opc_send_msg_to_pf = 0x0801, 271 i40e_aqc_opc_send_msg_to_vf = 0x0802, 272 i40e_aqc_opc_send_msg_to_peer = 0x0803, 273 274 /* alternate structure */ 275 i40e_aqc_opc_alternate_write = 0x0900, 276 i40e_aqc_opc_alternate_write_indirect = 0x0901, 277 i40e_aqc_opc_alternate_read = 0x0902, 278 i40e_aqc_opc_alternate_read_indirect = 0x0903, 279 i40e_aqc_opc_alternate_write_done = 0x0904, 280 i40e_aqc_opc_alternate_set_mode = 0x0905, 281 i40e_aqc_opc_alternate_clear_port = 0x0906, 282 283 /* LLDP commands */ 284 i40e_aqc_opc_lldp_get_mib = 0x0A00, 285 i40e_aqc_opc_lldp_update_mib = 0x0A01, 286 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 287 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 288 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 289 i40e_aqc_opc_lldp_stop = 0x0A05, 290 i40e_aqc_opc_lldp_start = 0x0A06, 291 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 292 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 293 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 294 i40e_aqc_opc_lldp_restore = 0x0A0A, 295 296 /* Tunnel commands */ 297 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 298 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 299 i40e_aqc_opc_set_rss_key = 0x0B02, 300 i40e_aqc_opc_set_rss_lut = 0x0B03, 301 i40e_aqc_opc_get_rss_key = 0x0B04, 302 i40e_aqc_opc_get_rss_lut = 0x0B05, 303 304 /* Async Events */ 305 i40e_aqc_opc_event_lan_overflow = 0x1001, 306 307 /* OEM commands */ 308 i40e_aqc_opc_oem_parameter_change = 0xFE00, 309 i40e_aqc_opc_oem_device_status_change = 0xFE01, 310 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 311 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 312 313 /* debug commands */ 314 i40e_aqc_opc_debug_read_reg = 0xFF03, 315 i40e_aqc_opc_debug_write_reg = 0xFF04, 316 i40e_aqc_opc_debug_modify_reg = 0xFF07, 317 i40e_aqc_opc_debug_dump_internals = 0xFF08, 318}; 319 320/* command structures and indirect data structures */ 321 322/* Structure naming conventions: 323 * - no suffix for direct command descriptor structures 324 * - _data for indirect sent data 325 * - _resp for indirect return data (data which is both will use _data) 326 * - _completion for direct return data 327 * - _element_ for repeated elements (may also be _data or _resp) 328 * 329 * Command structures are expected to overlay the params.raw member of the basic 330 * descriptor, and as such cannot exceed 16 bytes in length. 331 */ 332 333/* This macro is used to generate a compilation error if a structure 334 * is not exactly the correct length. It gives a divide by zero error if the 335 * structure is not of the correct size, otherwise it creates an enum that is 336 * never used. 337 */ 338#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 339 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 340 341/* This macro is used extensively to ensure that command structures are 16 342 * bytes in length as they have to map to the raw array of that size. 343 */ 344#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 345 346/* internal (0x00XX) commands */ 347 348/* Get version (direct 0x0001) */ 349struct i40e_aqc_get_version { 350 __le32 rom_ver; 351 __le32 fw_build; 352 __le16 fw_major; 353 __le16 fw_minor; 354 __le16 api_major; 355 __le16 api_minor; 356}; 357 358I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 359 360/* Send driver version (indirect 0x0002) */ 361struct i40e_aqc_driver_version { 362 u8 driver_major_ver; 363 u8 driver_minor_ver; 364 u8 driver_build_ver; 365 u8 driver_subbuild_ver; 366 u8 reserved[4]; 367 __le32 address_high; 368 __le32 address_low; 369}; 370 371I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 372 373/* Queue Shutdown (direct 0x0003) */ 374struct i40e_aqc_queue_shutdown { 375 __le32 driver_unloading; 376#define I40E_AQ_DRIVER_UNLOADING 0x1 377 u8 reserved[12]; 378}; 379 380I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 381 382/* Set PF context (0x0004, direct) */ 383struct i40e_aqc_set_pf_context { 384 u8 pf_id; 385 u8 reserved[15]; 386}; 387 388I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 389 390/* Request resource ownership (direct 0x0008) 391 * Release resource ownership (direct 0x0009) 392 */ 393#define I40E_AQ_RESOURCE_NVM 1 394#define I40E_AQ_RESOURCE_SDP 2 395#define I40E_AQ_RESOURCE_ACCESS_READ 1 396#define I40E_AQ_RESOURCE_ACCESS_WRITE 2 397#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 398#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 399 400struct i40e_aqc_request_resource { 401 __le16 resource_id; 402 __le16 access_type; 403 __le32 timeout; 404 __le32 resource_number; 405 u8 reserved[4]; 406}; 407 408I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 409 410/* Get function capabilities (indirect 0x000A) 411 * Get device capabilities (indirect 0x000B) 412 */ 413struct i40e_aqc_list_capabilites { 414 u8 command_flags; 415#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 416 u8 pf_index; 417 u8 reserved[2]; 418 __le32 count; 419 __le32 addr_high; 420 __le32 addr_low; 421}; 422 423I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 424 425struct i40e_aqc_list_capabilities_element_resp { 426 __le16 id; 427 u8 major_rev; 428 u8 minor_rev; 429 __le32 number; 430 __le32 logical_id; 431 __le32 phys_id; 432 u8 reserved[16]; 433}; 434 435/* list of caps */ 436 437#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 438#define I40E_AQ_CAP_ID_MNG_MODE 0x0002 439#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 440#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 441#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 442#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 443#define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 444#define I40E_AQ_CAP_ID_SRIOV 0x0012 445#define I40E_AQ_CAP_ID_VF 0x0013 446#define I40E_AQ_CAP_ID_VMDQ 0x0014 447#define I40E_AQ_CAP_ID_8021QBG 0x0015 448#define I40E_AQ_CAP_ID_8021QBR 0x0016 449#define I40E_AQ_CAP_ID_VSI 0x0017 450#define I40E_AQ_CAP_ID_DCB 0x0018 451#define I40E_AQ_CAP_ID_FCOE 0x0021 452#define I40E_AQ_CAP_ID_ISCSI 0x0022 453#define I40E_AQ_CAP_ID_RSS 0x0040 454#define I40E_AQ_CAP_ID_RXQ 0x0041 455#define I40E_AQ_CAP_ID_TXQ 0x0042 456#define I40E_AQ_CAP_ID_MSIX 0x0043 457#define I40E_AQ_CAP_ID_VF_MSIX 0x0044 458#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 459#define I40E_AQ_CAP_ID_1588 0x0046 460#define I40E_AQ_CAP_ID_IWARP 0x0051 461#define I40E_AQ_CAP_ID_LED 0x0061 462#define I40E_AQ_CAP_ID_SDP 0x0062 463#define I40E_AQ_CAP_ID_MDIO 0x0063 464#define I40E_AQ_CAP_ID_WSR_PROT 0x0064 465#define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 466#define I40E_AQ_CAP_ID_FLEX10 0x00F1 467#define I40E_AQ_CAP_ID_CEM 0x00F2 468 469/* Set CPPM Configuration (direct 0x0103) */ 470struct i40e_aqc_cppm_configuration { 471 __le16 command_flags; 472#define I40E_AQ_CPPM_EN_LTRC 0x0800 473#define I40E_AQ_CPPM_EN_DMCTH 0x1000 474#define I40E_AQ_CPPM_EN_DMCTLX 0x2000 475#define I40E_AQ_CPPM_EN_HPTC 0x4000 476#define I40E_AQ_CPPM_EN_DMARC 0x8000 477 __le16 ttlx; 478 __le32 dmacr; 479 __le16 dmcth; 480 u8 hptc; 481 u8 reserved; 482 __le32 pfltrc; 483}; 484 485I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 486 487/* Set ARP Proxy command / response (indirect 0x0104) */ 488struct i40e_aqc_arp_proxy_data { 489 __le16 command_flags; 490#define I40E_AQ_ARP_INIT_IPV4 0x0800 491#define I40E_AQ_ARP_UNSUP_CTL 0x1000 492#define I40E_AQ_ARP_ENA 0x2000 493#define I40E_AQ_ARP_ADD_IPV4 0x4000 494#define I40E_AQ_ARP_DEL_IPV4 0x8000 495 __le16 table_id; 496 __le32 enabled_offloads; 497#define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 498#define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 499 __le32 ip_addr; 500 u8 mac_addr[6]; 501 u8 reserved[2]; 502}; 503 504I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 505 506/* Set NS Proxy Table Entry Command (indirect 0x0105) */ 507struct i40e_aqc_ns_proxy_data { 508 __le16 table_idx_mac_addr_0; 509 __le16 table_idx_mac_addr_1; 510 __le16 table_idx_ipv6_0; 511 __le16 table_idx_ipv6_1; 512 __le16 control; 513#define I40E_AQ_NS_PROXY_ADD_0 0x0001 514#define I40E_AQ_NS_PROXY_DEL_0 0x0002 515#define I40E_AQ_NS_PROXY_ADD_1 0x0004 516#define I40E_AQ_NS_PROXY_DEL_1 0x0008 517#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 518#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 519#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 520#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 521#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 522#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 523#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 524#define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 525#define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 526 u8 mac_addr_0[6]; 527 u8 mac_addr_1[6]; 528 u8 local_mac_addr[6]; 529 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 530 u8 ipv6_addr_1[16]; 531}; 532 533I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 534 535/* Manage LAA Command (0x0106) - obsolete */ 536struct i40e_aqc_mng_laa { 537 __le16 command_flags; 538#define I40E_AQ_LAA_FLAG_WR 0x8000 539 u8 reserved[2]; 540 __le32 sal; 541 __le16 sah; 542 u8 reserved2[6]; 543}; 544 545I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 546 547/* Manage MAC Address Read Command (indirect 0x0107) */ 548struct i40e_aqc_mac_address_read { 549 __le16 command_flags; 550#define I40E_AQC_LAN_ADDR_VALID 0x10 551#define I40E_AQC_SAN_ADDR_VALID 0x20 552#define I40E_AQC_PORT_ADDR_VALID 0x40 553#define I40E_AQC_WOL_ADDR_VALID 0x80 554#define I40E_AQC_MC_MAG_EN_VALID 0x100 555#define I40E_AQC_WOL_PRESERVE_STATUS 0x200 556#define I40E_AQC_ADDR_VALID_MASK 0x3F0 557 u8 reserved[6]; 558 __le32 addr_high; 559 __le32 addr_low; 560}; 561 562I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 563 564struct i40e_aqc_mac_address_read_data { 565 u8 pf_lan_mac[6]; 566 u8 pf_san_mac[6]; 567 u8 port_mac[6]; 568 u8 pf_wol_mac[6]; 569}; 570 571I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 572 573/* Manage MAC Address Write Command (0x0108) */ 574struct i40e_aqc_mac_address_write { 575 __le16 command_flags; 576#define I40E_AQC_MC_MAG_EN 0x0100 577#define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200 578#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 579#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 580#define I40E_AQC_WRITE_TYPE_PORT 0x8000 581#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 582#define I40E_AQC_WRITE_TYPE_MASK 0xC000 583 584 __le16 mac_sah; 585 __le32 mac_sal; 586 u8 reserved[8]; 587}; 588 589I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 590 591/* PXE commands (0x011x) */ 592 593/* Clear PXE Command and response (direct 0x0110) */ 594struct i40e_aqc_clear_pxe { 595 u8 rx_cnt; 596 u8 reserved[15]; 597}; 598 599I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 600 601/* Set WoL Filter (0x0120) */ 602 603struct i40e_aqc_set_wol_filter { 604 __le16 filter_index; 605#define I40E_AQC_MAX_NUM_WOL_FILTERS 8 606#define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 607#define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ 608 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) 609 610#define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 611#define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ 612 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) 613 __le16 cmd_flags; 614#define I40E_AQC_SET_WOL_FILTER 0x8000 615#define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 616#define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000 617#define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 618#define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 619 __le16 valid_flags; 620#define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 621#define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 622 u8 reserved[2]; 623 __le32 address_high; 624 __le32 address_low; 625}; 626 627I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); 628 629struct i40e_aqc_set_wol_filter_data { 630 u8 filter[128]; 631 u8 mask[16]; 632}; 633 634I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); 635 636/* Get Wake Reason (0x0121) */ 637 638struct i40e_aqc_get_wake_reason_completion { 639 u8 reserved_1[2]; 640 __le16 wake_reason; 641#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 642#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ 643 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) 644#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 645#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ 646 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) 647 u8 reserved_2[12]; 648}; 649 650I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); 651 652/* Switch configuration commands (0x02xx) */ 653 654/* Used by many indirect commands that only pass an seid and a buffer in the 655 * command 656 */ 657struct i40e_aqc_switch_seid { 658 __le16 seid; 659 u8 reserved[6]; 660 __le32 addr_high; 661 __le32 addr_low; 662}; 663 664I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 665 666/* Get Switch Configuration command (indirect 0x0200) 667 * uses i40e_aqc_switch_seid for the descriptor 668 */ 669struct i40e_aqc_get_switch_config_header_resp { 670 __le16 num_reported; 671 __le16 num_total; 672 u8 reserved[12]; 673}; 674 675I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 676 677struct i40e_aqc_switch_config_element_resp { 678 u8 element_type; 679#define I40E_AQ_SW_ELEM_TYPE_MAC 1 680#define I40E_AQ_SW_ELEM_TYPE_PF 2 681#define I40E_AQ_SW_ELEM_TYPE_VF 3 682#define I40E_AQ_SW_ELEM_TYPE_EMP 4 683#define I40E_AQ_SW_ELEM_TYPE_BMC 5 684#define I40E_AQ_SW_ELEM_TYPE_PV 16 685#define I40E_AQ_SW_ELEM_TYPE_VEB 17 686#define I40E_AQ_SW_ELEM_TYPE_PA 18 687#define I40E_AQ_SW_ELEM_TYPE_VSI 19 688 u8 revision; 689#define I40E_AQ_SW_ELEM_REV_1 1 690 __le16 seid; 691 __le16 uplink_seid; 692 __le16 downlink_seid; 693 u8 reserved[3]; 694 u8 connection_type; 695#define I40E_AQ_CONN_TYPE_REGULAR 0x1 696#define I40E_AQ_CONN_TYPE_DEFAULT 0x2 697#define I40E_AQ_CONN_TYPE_CASCADED 0x3 698 __le16 scheduler_id; 699 __le16 element_info; 700}; 701 702I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 703 704/* Get Switch Configuration (indirect 0x0200) 705 * an array of elements are returned in the response buffer 706 * the first in the array is the header, remainder are elements 707 */ 708struct i40e_aqc_get_switch_config_resp { 709 struct i40e_aqc_get_switch_config_header_resp header; 710 struct i40e_aqc_switch_config_element_resp element[1]; 711}; 712 713I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 714 715/* Add Statistics (direct 0x0201) 716 * Remove Statistics (direct 0x0202) 717 */ 718struct i40e_aqc_add_remove_statistics { 719 __le16 seid; 720 __le16 vlan; 721 __le16 stat_index; 722 u8 reserved[10]; 723}; 724 725I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 726 727/* Set Port Parameters command (direct 0x0203) */ 728struct i40e_aqc_set_port_parameters { 729 __le16 command_flags; 730#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 731#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 732#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 733 __le16 bad_frame_vsi; 734#define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 735#define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF 736 __le16 default_seid; /* reserved for command */ 737 u8 reserved[10]; 738}; 739 740I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 741 742/* Get Switch Resource Allocation (indirect 0x0204) */ 743struct i40e_aqc_get_switch_resource_alloc { 744 u8 num_entries; /* reserved for command */ 745 u8 reserved[7]; 746 __le32 addr_high; 747 __le32 addr_low; 748}; 749 750I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 751 752/* expect an array of these structs in the response buffer */ 753struct i40e_aqc_switch_resource_alloc_element_resp { 754 u8 resource_type; 755#define I40E_AQ_RESOURCE_TYPE_VEB 0x0 756#define I40E_AQ_RESOURCE_TYPE_VSI 0x1 757#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 758#define I40E_AQ_RESOURCE_TYPE_STAG 0x3 759#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 760#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 761#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 762#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 763#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 764#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 765#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 766#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 767#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 768#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 769#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 770#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 771#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 772#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 773#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 774 u8 reserved1; 775 __le16 guaranteed; 776 __le16 total; 777 __le16 used; 778 __le16 total_unalloced; 779 u8 reserved2[6]; 780}; 781 782I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 783 784/* Set Switch Configuration (direct 0x0205) */ 785struct i40e_aqc_set_switch_config { 786 __le16 flags; 787/* flags used for both fields below */ 788#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 789#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 790#define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT 0x0004 791 __le16 valid_flags; 792 /* The ethertype in switch_tag is dropped on ingress and used 793 * internally by the switch. Set this to zero for the default 794 * of 0x88a8 (802.1ad). Should be zero for firmware API 795 * versions lower than 1.7. 796 */ 797 __le16 switch_tag; 798 /* The ethertypes in first_tag and second_tag are used to 799 * match the outer and inner VLAN tags (respectively) when HW 800 * double VLAN tagging is enabled via the set port parameters 801 * AQ command. Otherwise these are both ignored. Set them to 802 * zero for their defaults of 0x8100 (802.1Q). Should be zero 803 * for firmware API versions lower than 1.7. 804 */ 805 __le16 first_tag; 806 __le16 second_tag; 807 /* Next byte is split into following: 808 * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0 809 * Bit 6 : 0 : Destination Port, 1: source port 810 * Bit 5..4 : L4 type 811 * 0: rsvd 812 * 1: TCP 813 * 2: UDP 814 * 3: Both TCP and UDP 815 * Bits 3:0 Mode 816 * 0: default mode 817 * 1: L4 port only mode 818 * 2: non-tunneled mode 819 * 3: tunneled mode 820 */ 821#define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80 822 823#define I40E_AQ_SET_SWITCH_L4_SRC_PORT 0x40 824 825#define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD 0x00 826#define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10 827#define I40E_AQ_SET_SWITCH_L4_TYPE_UDP 0x20 828#define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH 0x30 829 830#define I40E_AQ_SET_SWITCH_MODE_DEFAULT 0x00 831#define I40E_AQ_SET_SWITCH_MODE_L4_PORT 0x01 832#define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02 833#define I40E_AQ_SET_SWITCH_MODE_TUNNEL 0x03 834 u8 mode; 835 u8 rsvd5[5]; 836}; 837 838I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 839 840/* Read Receive control registers (direct 0x0206) 841 * Write Receive control registers (direct 0x0207) 842 * used for accessing Rx control registers that can be 843 * slow and need special handling when under high Rx load 844 */ 845struct i40e_aqc_rx_ctl_reg_read_write { 846 __le32 reserved1; 847 __le32 address; 848 __le32 reserved2; 849 __le32 value; 850}; 851 852I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 853 854/* Add VSI (indirect 0x0210) 855 * this indirect command uses struct i40e_aqc_vsi_properties_data 856 * as the indirect buffer (128 bytes) 857 * 858 * Update VSI (indirect 0x211) 859 * uses the same data structure as Add VSI 860 * 861 * Get VSI (indirect 0x0212) 862 * uses the same completion and data structure as Add VSI 863 */ 864struct i40e_aqc_add_get_update_vsi { 865 __le16 uplink_seid; 866 u8 connection_type; 867#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 868#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 869#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 870 u8 reserved1; 871 u8 vf_id; 872 u8 reserved2; 873 __le16 vsi_flags; 874#define I40E_AQ_VSI_TYPE_SHIFT 0x0 875#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 876#define I40E_AQ_VSI_TYPE_VF 0x0 877#define I40E_AQ_VSI_TYPE_VMDQ2 0x1 878#define I40E_AQ_VSI_TYPE_PF 0x2 879#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 880#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 881 __le32 addr_high; 882 __le32 addr_low; 883}; 884 885I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 886 887struct i40e_aqc_add_get_update_vsi_completion { 888 __le16 seid; 889 __le16 vsi_number; 890 __le16 vsi_used; 891 __le16 vsi_free; 892 __le32 addr_high; 893 __le32 addr_low; 894}; 895 896I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 897 898struct i40e_aqc_vsi_properties_data { 899 /* first 96 byte are written by SW */ 900 __le16 valid_sections; 901#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 902#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 903#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 904#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 905#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 906#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 907#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 908#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 909#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 910#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 911 /* switch section */ 912 __le16 switch_id; /* 12bit id combined with flags below */ 913#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 914#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 915#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 916#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 917#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 918 u8 sw_reserved[2]; 919 /* security section */ 920 u8 sec_flags; 921#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 922#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 923#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 924 u8 sec_reserved; 925 /* VLAN section */ 926 __le16 pvid; /* VLANS include priority bits */ 927 __le16 fcoe_pvid; 928 u8 port_vlan_flags; 929#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 930#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 931 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 932#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 933#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 934#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 935#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 936#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 937#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 938 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 939#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 940#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 941#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 942#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 943 u8 pvlan_reserved[3]; 944 /* ingress egress up sections */ 945 __le32 ingress_table; /* bitmap, 3 bits per up */ 946#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 947#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 948 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 949#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 950#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 951 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 952#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 953#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 954 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 955#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 956#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 957 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 958#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 959#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 960 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 961#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 962#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 963 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 964#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 965#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 966 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 967#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 968#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 969 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 970 __le32 egress_table; /* same defines as for ingress table */ 971 /* cascaded PV section */ 972 __le16 cas_pv_tag; 973 u8 cas_pv_flags; 974#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 975#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 976 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 977#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 978#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 979#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 980#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 981#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 982#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 983 u8 cas_pv_reserved; 984 /* queue mapping section */ 985 __le16 mapping_flags; 986#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 987#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 988 __le16 queue_mapping[16]; 989#define I40E_AQ_VSI_QUEUE_SHIFT 0x0 990#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 991 __le16 tc_mapping[8]; 992#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 993#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 994 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 995#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 996#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 997 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 998 /* queueing option section */ 999 u8 queueing_opt_flags; 1000#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 1001#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 1002#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 1003#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 1004#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 1005#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 1006 u8 queueing_opt_reserved[3]; 1007 /* scheduler section */ 1008 u8 up_enable_bits; 1009 u8 sched_reserved; 1010 /* outer up section */ 1011 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 1012 u8 cmd_reserved[8]; 1013 /* last 32 bytes are written by FW */ 1014 __le16 qs_handle[8]; 1015#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 1016 __le16 stat_counter_idx; 1017 __le16 sched_id; 1018 u8 resp_reserved[12]; 1019}; 1020 1021I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 1022 1023/* Add Port Virtualizer (direct 0x0220) 1024 * also used for update PV (direct 0x0221) but only flags are used 1025 * (IS_CTRL_PORT only works on add PV) 1026 */ 1027struct i40e_aqc_add_update_pv { 1028 __le16 command_flags; 1029#define I40E_AQC_PV_FLAG_PV_TYPE 0x1 1030#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 1031#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 1032#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 1033 __le16 uplink_seid; 1034 __le16 connected_seid; 1035 u8 reserved[10]; 1036}; 1037 1038I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 1039 1040struct i40e_aqc_add_update_pv_completion { 1041 /* reserved for update; for add also encodes error if rc == ENOSPC */ 1042 __le16 pv_seid; 1043#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 1044#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 1045#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 1046#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 1047 u8 reserved[14]; 1048}; 1049 1050I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 1051 1052/* Get PV Params (direct 0x0222) 1053 * uses i40e_aqc_switch_seid for the descriptor 1054 */ 1055 1056struct i40e_aqc_get_pv_params_completion { 1057 __le16 seid; 1058 __le16 default_stag; 1059 __le16 pv_flags; /* same flags as add_pv */ 1060#define I40E_AQC_GET_PV_PV_TYPE 0x1 1061#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 1062#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 1063 u8 reserved[8]; 1064 __le16 default_port_seid; 1065}; 1066 1067I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 1068 1069/* Add VEB (direct 0x0230) */ 1070struct i40e_aqc_add_veb { 1071 __le16 uplink_seid; 1072 __le16 downlink_seid; 1073 __le16 veb_flags; 1074#define I40E_AQC_ADD_VEB_FLOATING 0x1 1075#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 1076#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 1077 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 1078#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 1079#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 1080#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 1081#define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 1082 u8 enable_tcs; 1083 u8 reserved[9]; 1084}; 1085 1086I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 1087 1088struct i40e_aqc_add_veb_completion { 1089 u8 reserved[6]; 1090 __le16 switch_seid; 1091 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 1092 __le16 veb_seid; 1093#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 1094#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 1095#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 1096#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 1097 __le16 statistic_index; 1098 __le16 vebs_used; 1099 __le16 vebs_free; 1100}; 1101 1102I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 1103 1104/* Get VEB Parameters (direct 0x0232) 1105 * uses i40e_aqc_switch_seid for the descriptor 1106 */ 1107struct i40e_aqc_get_veb_parameters_completion { 1108 __le16 seid; 1109 __le16 switch_id; 1110 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 1111 __le16 statistic_index; 1112 __le16 vebs_used; 1113 __le16 vebs_free; 1114 u8 reserved[4]; 1115}; 1116 1117I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 1118 1119/* Delete Element (direct 0x0243) 1120 * uses the generic i40e_aqc_switch_seid 1121 */ 1122 1123/* Add MAC-VLAN (indirect 0x0250) */ 1124 1125/* used for the command for most vlan commands */ 1126struct i40e_aqc_macvlan { 1127 __le16 num_addresses; 1128 __le16 seid[3]; 1129#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 1130#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 1131 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1132#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 1133 __le32 addr_high; 1134 __le32 addr_low; 1135}; 1136 1137I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 1138 1139/* indirect data for command and response */ 1140struct i40e_aqc_add_macvlan_element_data { 1141 u8 mac_addr[6]; 1142 __le16 vlan_tag; 1143 __le16 flags; 1144#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 1145#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 1146#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 1147#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 1148#define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 1149 __le16 queue_number; 1150#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 1151#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 1152 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1153 /* response section */ 1154 u8 match_method; 1155#define I40E_AQC_MM_PERFECT_MATCH 0x01 1156#define I40E_AQC_MM_HASH_MATCH 0x02 1157#define I40E_AQC_MM_ERR_NO_RES 0xFF 1158 u8 reserved1[3]; 1159}; 1160 1161struct i40e_aqc_add_remove_macvlan_completion { 1162 __le16 perfect_mac_used; 1163 __le16 perfect_mac_free; 1164 __le16 unicast_hash_free; 1165 __le16 multicast_hash_free; 1166 __le32 addr_high; 1167 __le32 addr_low; 1168}; 1169 1170I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1171 1172/* Remove MAC-VLAN (indirect 0x0251) 1173 * uses i40e_aqc_macvlan for the descriptor 1174 * data points to an array of num_addresses of elements 1175 */ 1176 1177struct i40e_aqc_remove_macvlan_element_data { 1178 u8 mac_addr[6]; 1179 __le16 vlan_tag; 1180 u8 flags; 1181#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1182#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1183#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1184#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1185 u8 reserved[3]; 1186 /* reply section */ 1187 u8 error_code; 1188#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1189#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1190 u8 reply_reserved[3]; 1191}; 1192 1193/* Add VLAN (indirect 0x0252) 1194 * Remove VLAN (indirect 0x0253) 1195 * use the generic i40e_aqc_macvlan for the command 1196 */ 1197struct i40e_aqc_add_remove_vlan_element_data { 1198 __le16 vlan_tag; 1199 u8 vlan_flags; 1200/* flags for add VLAN */ 1201#define I40E_AQC_ADD_VLAN_LOCAL 0x1 1202#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1203#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1204#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1205#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1206#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1207#define I40E_AQC_VLAN_PTYPE_SHIFT 3 1208#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1209#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1210#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1211#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1212#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1213/* flags for remove VLAN */ 1214#define I40E_AQC_REMOVE_VLAN_ALL 0x1 1215 u8 reserved; 1216 u8 result; 1217/* flags for add VLAN */ 1218#define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1219#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1220#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1221/* flags for remove VLAN */ 1222#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1223#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1224 u8 reserved1[3]; 1225}; 1226 1227struct i40e_aqc_add_remove_vlan_completion { 1228 u8 reserved[4]; 1229 __le16 vlans_used; 1230 __le16 vlans_free; 1231 __le32 addr_high; 1232 __le32 addr_low; 1233}; 1234 1235/* Set VSI Promiscuous Modes (direct 0x0254) */ 1236struct i40e_aqc_set_vsi_promiscuous_modes { 1237 __le16 promiscuous_flags; 1238 __le16 valid_flags; 1239/* flags used for both fields above */ 1240#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1241#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1242#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1243#define I40E_AQC_SET_VSI_DEFAULT 0x08 1244#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1245#define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 1246 __le16 seid; 1247#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1248 __le16 vlan_tag; 1249#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1250#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1251 u8 reserved[8]; 1252}; 1253 1254I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1255 1256/* Add S/E-tag command (direct 0x0255) 1257 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1258 */ 1259struct i40e_aqc_add_tag { 1260 __le16 flags; 1261#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1262 __le16 seid; 1263#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1264#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1265 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1266 __le16 tag; 1267 __le16 queue_number; 1268 u8 reserved[8]; 1269}; 1270 1271I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1272 1273struct i40e_aqc_add_remove_tag_completion { 1274 u8 reserved[12]; 1275 __le16 tags_used; 1276 __le16 tags_free; 1277}; 1278 1279I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1280 1281/* Remove S/E-tag command (direct 0x0256) 1282 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1283 */ 1284struct i40e_aqc_remove_tag { 1285 __le16 seid; 1286#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1287#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1288 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1289 __le16 tag; 1290 u8 reserved[12]; 1291}; 1292 1293I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1294 1295/* Add multicast E-Tag (direct 0x0257) 1296 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1297 * and no external data 1298 */ 1299struct i40e_aqc_add_remove_mcast_etag { 1300 __le16 pv_seid; 1301 __le16 etag; 1302 u8 num_unicast_etags; 1303 u8 reserved[3]; 1304 __le32 addr_high; /* address of array of 2-byte s-tags */ 1305 __le32 addr_low; 1306}; 1307 1308I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1309 1310struct i40e_aqc_add_remove_mcast_etag_completion { 1311 u8 reserved[4]; 1312 __le16 mcast_etags_used; 1313 __le16 mcast_etags_free; 1314 __le32 addr_high; 1315 __le32 addr_low; 1316 1317}; 1318 1319I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1320 1321/* Update S/E-Tag (direct 0x0259) */ 1322struct i40e_aqc_update_tag { 1323 __le16 seid; 1324#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1325#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1326 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1327 __le16 old_tag; 1328 __le16 new_tag; 1329 u8 reserved[10]; 1330}; 1331 1332I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1333 1334struct i40e_aqc_update_tag_completion { 1335 u8 reserved[12]; 1336 __le16 tags_used; 1337 __le16 tags_free; 1338}; 1339 1340I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1341 1342/* Add Control Packet filter (direct 0x025A) 1343 * Remove Control Packet filter (direct 0x025B) 1344 * uses the i40e_aqc_add_oveb_cloud, 1345 * and the generic direct completion structure 1346 */ 1347struct i40e_aqc_add_remove_control_packet_filter { 1348 u8 mac[6]; 1349 __le16 etype; 1350 __le16 flags; 1351#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1352#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1353#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1354#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1355#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1356 __le16 seid; 1357#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1358#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1359 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1360 __le16 queue; 1361 u8 reserved[2]; 1362}; 1363 1364I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1365 1366struct i40e_aqc_add_remove_control_packet_filter_completion { 1367 __le16 mac_etype_used; 1368 __le16 etype_used; 1369 __le16 mac_etype_free; 1370 __le16 etype_free; 1371 u8 reserved[8]; 1372}; 1373 1374I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1375 1376/* Add Cloud filters (indirect 0x025C) 1377 * Remove Cloud filters (indirect 0x025D) 1378 * uses the i40e_aqc_add_remove_cloud_filters, 1379 * and the generic indirect completion structure 1380 */ 1381struct i40e_aqc_add_remove_cloud_filters { 1382 u8 num_filters; 1383 u8 reserved; 1384 __le16 seid; 1385#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1386#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1387 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1388 u8 reserved2[4]; 1389 __le32 addr_high; 1390 __le32 addr_low; 1391}; 1392 1393I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1394 1395struct i40e_aqc_add_remove_cloud_filters_element_data { 1396 u8 outer_mac[6]; 1397 u8 inner_mac[6]; 1398 __le16 inner_vlan; 1399 union { 1400 struct { 1401 u8 reserved[12]; 1402 u8 data[4]; 1403 } v4; 1404 struct { 1405 u8 data[16]; 1406 } v6; 1407 } ipaddr; 1408 __le16 flags; 1409#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1410#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1411 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1412/* 0x0000 reserved */ 1413#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1414/* 0x0002 reserved */ 1415#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1416#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1417/* 0x0005 reserved */ 1418#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1419/* 0x0007 reserved */ 1420/* 0x0008 reserved */ 1421#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1422#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1423#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1424#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1425 1426#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1427#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1428#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1429#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1430#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1431 1432#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1433#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1434#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1435#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1436#define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1437#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1438#define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1439#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1440 1441#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1442#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1443#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1444 1445 __le32 tenant_id; 1446 u8 reserved[4]; 1447 __le16 queue_number; 1448#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1449#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1450 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1451 u8 reserved2[14]; 1452 /* response section */ 1453 u8 allocation_result; 1454#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1455#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1456 u8 response_reserved[7]; 1457}; 1458 1459struct i40e_aqc_remove_cloud_filters_completion { 1460 __le16 perfect_ovlan_used; 1461 __le16 perfect_ovlan_free; 1462 __le16 vlan_used; 1463 __le16 vlan_free; 1464 __le32 addr_high; 1465 __le32 addr_low; 1466}; 1467 1468I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1469 1470/* Add Mirror Rule (indirect or direct 0x0260) 1471 * Delete Mirror Rule (indirect or direct 0x0261) 1472 * note: some rule types (4,5) do not use an external buffer. 1473 * take care to set the flags correctly. 1474 */ 1475struct i40e_aqc_add_delete_mirror_rule { 1476 __le16 seid; 1477 __le16 rule_type; 1478#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1479#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1480 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1481#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1482#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1483#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1484#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1485#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1486 __le16 num_entries; 1487 __le16 destination; /* VSI for add, rule id for delete */ 1488 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1489 __le32 addr_low; 1490}; 1491 1492I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1493 1494struct i40e_aqc_add_delete_mirror_rule_completion { 1495 u8 reserved[2]; 1496 __le16 rule_id; /* only used on add */ 1497 __le16 mirror_rules_used; 1498 __le16 mirror_rules_free; 1499 __le32 addr_high; 1500 __le32 addr_low; 1501}; 1502 1503I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1504 1505/* DCB 0x03xx*/ 1506 1507/* PFC Ignore (direct 0x0301) 1508 * the command and response use the same descriptor structure 1509 */ 1510struct i40e_aqc_pfc_ignore { 1511 u8 tc_bitmap; 1512 u8 command_flags; /* unused on response */ 1513#define I40E_AQC_PFC_IGNORE_SET 0x80 1514#define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1515 u8 reserved[14]; 1516}; 1517 1518I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1519 1520/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1521 * with no parameters 1522 */ 1523 1524/* TX scheduler 0x04xx */ 1525 1526/* Almost all the indirect commands use 1527 * this generic struct to pass the SEID in param0 1528 */ 1529struct i40e_aqc_tx_sched_ind { 1530 __le16 vsi_seid; 1531 u8 reserved[6]; 1532 __le32 addr_high; 1533 __le32 addr_low; 1534}; 1535 1536I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1537 1538/* Several commands respond with a set of queue set handles */ 1539struct i40e_aqc_qs_handles_resp { 1540 __le16 qs_handles[8]; 1541}; 1542 1543/* Configure VSI BW limits (direct 0x0400) */ 1544struct i40e_aqc_configure_vsi_bw_limit { 1545 __le16 vsi_seid; 1546 u8 reserved[2]; 1547 __le16 credit; 1548 u8 reserved1[2]; 1549 u8 max_credit; /* 0-3, limit = 2^max */ 1550 u8 reserved2[7]; 1551}; 1552 1553I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1554 1555/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1556 * responds with i40e_aqc_qs_handles_resp 1557 */ 1558struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1559 u8 tc_valid_bits; 1560 u8 reserved[15]; 1561 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1562 1563 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1564 __le16 tc_bw_max[2]; 1565 u8 reserved1[28]; 1566}; 1567 1568I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1569 1570/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1571 * responds with i40e_aqc_qs_handles_resp 1572 */ 1573struct i40e_aqc_configure_vsi_tc_bw_data { 1574 u8 tc_valid_bits; 1575 u8 reserved[3]; 1576 u8 tc_bw_credits[8]; 1577 u8 reserved1[4]; 1578 __le16 qs_handles[8]; 1579}; 1580 1581I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1582 1583/* Query vsi bw configuration (indirect 0x0408) */ 1584struct i40e_aqc_query_vsi_bw_config_resp { 1585 u8 tc_valid_bits; 1586 u8 tc_suspended_bits; 1587 u8 reserved[14]; 1588 __le16 qs_handles[8]; 1589 u8 reserved1[4]; 1590 __le16 port_bw_limit; 1591 u8 reserved2[2]; 1592 u8 max_bw; /* 0-3, limit = 2^max */ 1593 u8 reserved3[23]; 1594}; 1595 1596I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1597 1598/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1599struct i40e_aqc_query_vsi_ets_sla_config_resp { 1600 u8 tc_valid_bits; 1601 u8 reserved[3]; 1602 u8 share_credits[8]; 1603 __le16 credits[8]; 1604 1605 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1606 __le16 tc_bw_max[2]; 1607}; 1608 1609I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1610 1611/* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1612struct i40e_aqc_configure_switching_comp_bw_limit { 1613 __le16 seid; 1614 u8 reserved[2]; 1615 __le16 credit; 1616 u8 reserved1[2]; 1617 u8 max_bw; /* 0-3, limit = 2^max */ 1618 u8 reserved2[7]; 1619}; 1620 1621I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1622 1623/* Enable Physical Port ETS (indirect 0x0413) 1624 * Modify Physical Port ETS (indirect 0x0414) 1625 * Disable Physical Port ETS (indirect 0x0415) 1626 */ 1627struct i40e_aqc_configure_switching_comp_ets_data { 1628 u8 reserved[4]; 1629 u8 tc_valid_bits; 1630 u8 seepage; 1631#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1632 u8 tc_strict_priority_flags; 1633 u8 reserved1[17]; 1634 u8 tc_bw_share_credits[8]; 1635 u8 reserved2[96]; 1636}; 1637 1638I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1639 1640/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1641struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1642 u8 tc_valid_bits; 1643 u8 reserved[15]; 1644 __le16 tc_bw_credit[8]; 1645 1646 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1647 __le16 tc_bw_max[2]; 1648 u8 reserved1[28]; 1649}; 1650 1651I40E_CHECK_STRUCT_LEN(0x40, 1652 i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1653 1654/* Configure Switching Component Bandwidth Allocation per Tc 1655 * (indirect 0x0417) 1656 */ 1657struct i40e_aqc_configure_switching_comp_bw_config_data { 1658 u8 tc_valid_bits; 1659 u8 reserved[2]; 1660 u8 absolute_credits; /* bool */ 1661 u8 tc_bw_share_credits[8]; 1662 u8 reserved1[20]; 1663}; 1664 1665I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1666 1667/* Query Switching Component Configuration (indirect 0x0418) */ 1668struct i40e_aqc_query_switching_comp_ets_config_resp { 1669 u8 tc_valid_bits; 1670 u8 reserved[35]; 1671 __le16 port_bw_limit; 1672 u8 reserved1[2]; 1673 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1674 u8 reserved2[23]; 1675}; 1676 1677I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1678 1679/* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1680struct i40e_aqc_query_port_ets_config_resp { 1681 u8 reserved[4]; 1682 u8 tc_valid_bits; 1683 u8 reserved1; 1684 u8 tc_strict_priority_bits; 1685 u8 reserved2; 1686 u8 tc_bw_share_credits[8]; 1687 __le16 tc_bw_limits[8]; 1688 1689 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1690 __le16 tc_bw_max[2]; 1691 u8 reserved3[32]; 1692}; 1693 1694I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1695 1696/* Query Switching Component Bandwidth Allocation per Traffic Type 1697 * (indirect 0x041A) 1698 */ 1699struct i40e_aqc_query_switching_comp_bw_config_resp { 1700 u8 tc_valid_bits; 1701 u8 reserved[2]; 1702 u8 absolute_credits_enable; /* bool */ 1703 u8 tc_bw_share_credits[8]; 1704 __le16 tc_bw_limits[8]; 1705 1706 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1707 __le16 tc_bw_max[2]; 1708}; 1709 1710I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1711 1712/* Suspend/resume port TX traffic 1713 * (direct 0x041B and 0x041C) uses the generic SEID struct 1714 */ 1715 1716/* Configure partition BW 1717 * (indirect 0x041D) 1718 */ 1719struct i40e_aqc_configure_partition_bw_data { 1720 __le16 pf_valid_bits; 1721 u8 min_bw[16]; /* guaranteed bandwidth */ 1722 u8 max_bw[16]; /* bandwidth limit */ 1723}; 1724 1725I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1726 1727/* Get and set the active HMC resource profile and status. 1728 * (direct 0x0500) and (direct 0x0501) 1729 */ 1730struct i40e_aq_get_set_hmc_resource_profile { 1731 u8 pm_profile; 1732 u8 pe_vf_enabled; 1733 u8 reserved[14]; 1734}; 1735 1736I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1737 1738enum i40e_aq_hmc_profile { 1739 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1740 I40E_HMC_PROFILE_DEFAULT = 1, 1741 I40E_HMC_PROFILE_FAVOR_VF = 2, 1742 I40E_HMC_PROFILE_EQUAL = 3, 1743}; 1744 1745/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1746 1747/* set in param0 for get phy abilities to report qualified modules */ 1748#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1749#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1750 1751enum i40e_aq_phy_type { 1752 I40E_PHY_TYPE_SGMII = 0x0, 1753 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1754 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1755 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1756 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1757 I40E_PHY_TYPE_XAUI = 0x5, 1758 I40E_PHY_TYPE_XFI = 0x6, 1759 I40E_PHY_TYPE_SFI = 0x7, 1760 I40E_PHY_TYPE_XLAUI = 0x8, 1761 I40E_PHY_TYPE_XLPPI = 0x9, 1762 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1763 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1764 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1765 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1766 I40E_PHY_TYPE_UNRECOGNIZED = 0xE, 1767 I40E_PHY_TYPE_UNSUPPORTED = 0xF, 1768 I40E_PHY_TYPE_100BASE_TX = 0x11, 1769 I40E_PHY_TYPE_1000BASE_T = 0x12, 1770 I40E_PHY_TYPE_10GBASE_T = 0x13, 1771 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1772 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1773 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1774 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1775 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1776 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1777 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1778 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1779 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1780 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1781 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1782 I40E_PHY_TYPE_25GBASE_KR = 0x1F, 1783 I40E_PHY_TYPE_25GBASE_CR = 0x20, 1784 I40E_PHY_TYPE_25GBASE_SR = 0x21, 1785 I40E_PHY_TYPE_25GBASE_LR = 0x22, 1786 I40E_PHY_TYPE_25GBASE_AOC = 0x23, 1787 I40E_PHY_TYPE_25GBASE_ACC = 0x24, 1788 I40E_PHY_TYPE_2_5GBASE_T = 0x30, 1789 I40E_PHY_TYPE_5GBASE_T = 0x31, 1790 I40E_PHY_TYPE_MAX, 1791 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD, 1792 I40E_PHY_TYPE_EMPTY = 0xFE, 1793 I40E_PHY_TYPE_DEFAULT = 0xFF, 1794}; 1795 1796#define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \ 1797 BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \ 1798 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \ 1799 BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \ 1800 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \ 1801 BIT_ULL(I40E_PHY_TYPE_XAUI) | \ 1802 BIT_ULL(I40E_PHY_TYPE_XFI) | \ 1803 BIT_ULL(I40E_PHY_TYPE_SFI) | \ 1804 BIT_ULL(I40E_PHY_TYPE_XLAUI) | \ 1805 BIT_ULL(I40E_PHY_TYPE_XLPPI) | \ 1806 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \ 1807 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \ 1808 BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \ 1809 BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \ 1810 BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \ 1811 BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \ 1812 BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \ 1813 BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \ 1814 BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \ 1815 BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \ 1816 BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \ 1817 BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \ 1818 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \ 1819 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \ 1820 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \ 1821 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \ 1822 BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \ 1823 BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \ 1824 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \ 1825 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \ 1826 BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \ 1827 BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \ 1828 BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \ 1829 BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \ 1830 BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \ 1831 BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \ 1832 BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \ 1833 BIT_ULL(I40E_PHY_TYPE_5GBASE_T)) 1834 1835#define I40E_LINK_SPEED_2_5GB_SHIFT 0x0 1836#define I40E_LINK_SPEED_100MB_SHIFT 0x1 1837#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1838#define I40E_LINK_SPEED_10GB_SHIFT 0x3 1839#define I40E_LINK_SPEED_40GB_SHIFT 0x4 1840#define I40E_LINK_SPEED_20GB_SHIFT 0x5 1841#define I40E_LINK_SPEED_25GB_SHIFT 0x6 1842#define I40E_LINK_SPEED_5GB_SHIFT 0x7 1843 1844enum i40e_aq_link_speed { 1845 I40E_LINK_SPEED_UNKNOWN = 0, 1846 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1847 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1848 I40E_LINK_SPEED_2_5GB = (1 << I40E_LINK_SPEED_2_5GB_SHIFT), 1849 I40E_LINK_SPEED_5GB = (1 << I40E_LINK_SPEED_5GB_SHIFT), 1850 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1851 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1852 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT), 1853 I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT), 1854}; 1855 1856struct i40e_aqc_module_desc { 1857 u8 oui[3]; 1858 u8 reserved1; 1859 u8 part_number[16]; 1860 u8 revision[4]; 1861 u8 reserved2[8]; 1862}; 1863 1864I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1865 1866struct i40e_aq_get_phy_abilities_resp { 1867 __le32 phy_type; /* bitmap using the above enum for offsets */ 1868 u8 link_speed; /* bitmap using the above enum bit patterns */ 1869 u8 abilities; 1870#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1871#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1872#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1873#define I40E_AQ_PHY_LINK_ENABLED 0x08 1874#define I40E_AQ_PHY_AN_ENABLED 0x10 1875#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1876#define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 1877#define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 1878 __le16 eee_capability; 1879#define I40E_AQ_EEE_AUTO 0x0001 1880#define I40E_AQ_EEE_100BASE_TX 0x0002 1881#define I40E_AQ_EEE_1000BASE_T 0x0004 1882#define I40E_AQ_EEE_10GBASE_T 0x0008 1883#define I40E_AQ_EEE_1000BASE_KX 0x0010 1884#define I40E_AQ_EEE_10GBASE_KX4 0x0020 1885#define I40E_AQ_EEE_10GBASE_KR 0x0040 1886#define I40E_AQ_EEE_2_5GBASE_T 0x0100 1887#define I40E_AQ_EEE_5GBASE_T 0x0200 1888 __le32 eeer_val; 1889 u8 d3_lpan; 1890#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1891 u8 phy_type_ext; 1892#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01 1893#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02 1894#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 1895#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 1896#define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10 1897#define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20 1898#define I40E_AQ_PHY_TYPE_EXT_2_5GBASE_T 0x40 1899#define I40E_AQ_PHY_TYPE_EXT_5GBASE_T 0x80 1900 u8 fec_cfg_curr_mod_ext_info; 1901#define I40E_AQ_ENABLE_FEC_KR 0x01 1902#define I40E_AQ_ENABLE_FEC_RS 0x02 1903#define I40E_AQ_REQUEST_FEC_KR 0x04 1904#define I40E_AQ_REQUEST_FEC_RS 0x08 1905#define I40E_AQ_ENABLE_FEC_AUTO 0x10 1906#define I40E_AQ_FEC 1907#define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 1908#define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5 1909 1910 u8 ext_comp_code; 1911 u8 phy_id[4]; 1912 u8 module_type[3]; 1913 u8 qualified_module_count; 1914#define I40E_AQ_PHY_MAX_QMS 16 1915 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1916}; 1917 1918I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1919 1920/* Set PHY Config (direct 0x0601) */ 1921struct i40e_aq_set_phy_config { /* same bits as above in all */ 1922 __le32 phy_type; 1923 u8 link_speed; 1924 u8 abilities; 1925/* bits 0-2 use the values from get_phy_abilities_resp */ 1926#define I40E_AQ_PHY_ENABLE_LINK 0x08 1927#define I40E_AQ_PHY_ENABLE_AN 0x10 1928#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1929 __le16 eee_capability; 1930 __le32 eeer; 1931 u8 low_power_ctrl; 1932 u8 phy_type_ext; 1933 u8 fec_config; 1934#define I40E_AQ_SET_FEC_ABILITY_KR BIT(0) 1935#define I40E_AQ_SET_FEC_ABILITY_RS BIT(1) 1936#define I40E_AQ_SET_FEC_REQUEST_KR BIT(2) 1937#define I40E_AQ_SET_FEC_REQUEST_RS BIT(3) 1938#define I40E_AQ_SET_FEC_AUTO BIT(4) 1939#define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0 1940#define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT) 1941 u8 reserved; 1942}; 1943 1944I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1945 1946/* Set MAC Config command data structure (direct 0x0603) */ 1947struct i40e_aq_set_mac_config { 1948 __le16 max_frame_size; 1949 u8 params; 1950#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1951#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1952#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1953#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1954#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1955#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1956#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1957#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1958#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1959#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1960#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1961#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1962#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1963#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1964 u8 tx_timer_priority; /* bitmap */ 1965 __le16 tx_timer_value; 1966 __le16 fc_refresh_threshold; 1967 u8 reserved[8]; 1968}; 1969 1970I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1971 1972/* Restart Auto-Negotiation (direct 0x605) */ 1973struct i40e_aqc_set_link_restart_an { 1974 u8 command; 1975#define I40E_AQ_PHY_RESTART_AN 0x02 1976#define I40E_AQ_PHY_LINK_ENABLE 0x04 1977 u8 reserved[15]; 1978}; 1979 1980I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1981 1982/* Get Link Status cmd & response data structure (direct 0x0607) */ 1983struct i40e_aqc_get_link_status { 1984 __le16 command_flags; /* only field set on command */ 1985#define I40E_AQ_LSE_MASK 0x3 1986#define I40E_AQ_LSE_NOP 0x0 1987#define I40E_AQ_LSE_DISABLE 0x2 1988#define I40E_AQ_LSE_ENABLE 0x3 1989/* only response uses this flag */ 1990#define I40E_AQ_LSE_IS_ENABLED 0x1 1991 u8 phy_type; /* i40e_aq_phy_type */ 1992 u8 link_speed; /* i40e_aq_link_speed */ 1993 u8 link_info; 1994#define I40E_AQ_LINK_UP 0x01 /* obsolete */ 1995#define I40E_AQ_LINK_UP_FUNCTION 0x01 1996#define I40E_AQ_LINK_FAULT 0x02 1997#define I40E_AQ_LINK_FAULT_TX 0x04 1998#define I40E_AQ_LINK_FAULT_RX 0x08 1999#define I40E_AQ_LINK_FAULT_REMOTE 0x10 2000#define I40E_AQ_LINK_UP_PORT 0x20 2001#define I40E_AQ_MEDIA_AVAILABLE 0x40 2002#define I40E_AQ_SIGNAL_DETECT 0x80 2003 u8 an_info; 2004#define I40E_AQ_AN_COMPLETED 0x01 2005#define I40E_AQ_LP_AN_ABILITY 0x02 2006#define I40E_AQ_PD_FAULT 0x04 2007#define I40E_AQ_FEC_EN 0x08 2008#define I40E_AQ_PHY_LOW_POWER 0x10 2009#define I40E_AQ_LINK_PAUSE_TX 0x20 2010#define I40E_AQ_LINK_PAUSE_RX 0x40 2011#define I40E_AQ_QUALIFIED_MODULE 0x80 2012 u8 ext_info; 2013#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 2014#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 2015#define I40E_AQ_LINK_TX_SHIFT 0x02 2016#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 2017#define I40E_AQ_LINK_TX_ACTIVE 0x00 2018#define I40E_AQ_LINK_TX_DRAINED 0x01 2019#define I40E_AQ_LINK_TX_FLUSHED 0x03 2020#define I40E_AQ_LINK_FORCED_40G 0x10 2021/* 25G Error Codes */ 2022#define I40E_AQ_25G_NO_ERR 0X00 2023#define I40E_AQ_25G_NOT_PRESENT 0X01 2024#define I40E_AQ_25G_NVM_CRC_ERR 0X02 2025#define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 2026#define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 2027#define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 2028 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 2029/* Since firmware API 1.7 loopback field keeps power class info as well */ 2030#define I40E_AQ_LOOPBACK_MASK 0x07 2031#define I40E_AQ_PWR_CLASS_SHIFT_LB 6 2032#define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB) 2033 __le16 max_frame_size; 2034 u8 config; 2035#define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 2036#define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 2037#define I40E_AQ_CONFIG_CRC_ENA 0x04 2038#define I40E_AQ_CONFIG_PACING_MASK 0x78 2039 union { 2040 struct { 2041 u8 power_desc; 2042#define I40E_AQ_LINK_POWER_CLASS_1 0x00 2043#define I40E_AQ_LINK_POWER_CLASS_2 0x01 2044#define I40E_AQ_LINK_POWER_CLASS_3 0x02 2045#define I40E_AQ_LINK_POWER_CLASS_4 0x03 2046#define I40E_AQ_PWR_CLASS_MASK 0x03 2047 u8 reserved[4]; 2048 }; 2049 struct { 2050 u8 link_type[4]; 2051 u8 link_type_ext; 2052 }; 2053 }; 2054}; 2055 2056I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 2057 2058/* Set event mask command (direct 0x613) */ 2059struct i40e_aqc_set_phy_int_mask { 2060 u8 reserved[8]; 2061 __le16 event_mask; 2062#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 2063#define I40E_AQ_EVENT_MEDIA_NA 0x0004 2064#define I40E_AQ_EVENT_LINK_FAULT 0x0008 2065#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 2066#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 2067#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 2068#define I40E_AQ_EVENT_AN_COMPLETED 0x0080 2069#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 2070#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 2071 u8 reserved1[6]; 2072}; 2073 2074I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 2075 2076/* Get Local AN advt register (direct 0x0614) 2077 * Set Local AN advt register (direct 0x0615) 2078 * Get Link Partner AN advt register (direct 0x0616) 2079 */ 2080struct i40e_aqc_an_advt_reg { 2081 __le32 local_an_reg0; 2082 __le16 local_an_reg1; 2083 u8 reserved[10]; 2084}; 2085 2086I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 2087 2088/* Set Loopback mode (0x0618) */ 2089struct i40e_aqc_set_lb_mode { 2090 u8 lb_level; 2091#define I40E_AQ_LB_NONE 0 2092#define I40E_AQ_LB_MAC 1 2093#define I40E_AQ_LB_SERDES 2 2094#define I40E_AQ_LB_PHY_INT 3 2095#define I40E_AQ_LB_PHY_EXT 4 2096#define I40E_AQ_LB_CPVL_PCS 5 2097#define I40E_AQ_LB_CPVL_EXT 6 2098#define I40E_AQ_LB_PHY_LOCAL 0x01 2099#define I40E_AQ_LB_PHY_REMOTE 0x02 2100#define I40E_AQ_LB_MAC_LOCAL 0x04 2101 u8 lb_type; 2102#define I40E_AQ_LB_LOCAL 0 2103#define I40E_AQ_LB_FAR 0x01 2104 u8 speed; 2105#define I40E_AQ_LB_SPEED_NONE 0 2106#define I40E_AQ_LB_SPEED_1G 1 2107#define I40E_AQ_LB_SPEED_10G 2 2108#define I40E_AQ_LB_SPEED_40G 3 2109#define I40E_AQ_LB_SPEED_20G 4 2110 u8 force_speed; 2111 u8 reserved[12]; 2112}; 2113 2114I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 2115 2116/* Set PHY Debug command (0x0622) */ 2117struct i40e_aqc_set_phy_debug { 2118 u8 command_flags; 2119#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 2120#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 2121#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 2122 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 2123#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 2124#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 2125#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 2126/* Disable link manageability on a single port */ 2127#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 2128/* Disable link manageability on all ports needs both bits 4 and 5 */ 2129#define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 2130 u8 reserved[15]; 2131}; 2132 2133I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 2134 2135enum i40e_aq_phy_reg_type { 2136 I40E_AQC_PHY_REG_INTERNAL = 0x1, 2137 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 2138 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 2139}; 2140 2141#pragma pack(1) 2142/* Run PHY Activity (0x0626) */ 2143struct i40e_aqc_run_phy_activity { 2144 u8 cmd_flags; 2145 __le16 activity_id; 2146#define I40E_AQ_RUN_PHY_ACTIVITY_ACTIVITY_ID_USER_DEFINED 0x10 2147 u8 reserved; 2148 union { 2149 struct { 2150 __le32 dnl_opcode; 2151#define I40E_AQ_RUN_PHY_ACTIVITY_DNL_OPCODE_GET_EEE_STATISTICS 0x801b 2152 __le32 data; 2153 u8 reserved2[4]; 2154 } cmd; 2155 struct { 2156 __le32 cmd_status; 2157#define I40E_AQ_RUN_PHY_ACTIVITY_CMD_STATUS_SUCCESS 0x4 2158 __le32 data0; 2159 __le32 data1; 2160 } resp; 2161 } params; 2162}; 2163#pragma pack() 2164 2165I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 2166 2167/* Set PHY Register command (0x0628) */ 2168/* Get PHY Register command (0x0629) */ 2169struct i40e_aqc_phy_register_access { 2170 u8 phy_interface; 2171#define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0 2172#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1 2173#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2 2174 u8 dev_addres; 2175 u8 cmd_flags; 2176#define I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE 1 2177 u8 reserved1; 2178 __le32 reg_address; 2179 __le32 reg_value; 2180 u8 reserved2[4]; 2181}; 2182 2183I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access); 2184 2185/* NVM Read command (indirect 0x0701) 2186 * NVM Erase commands (direct 0x0702) 2187 * NVM Update commands (indirect 0x0703) 2188 */ 2189struct i40e_aqc_nvm_update { 2190 u8 command_flags; 2191#define I40E_AQ_NVM_LAST_CMD 0x01 2192#define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20 2193#define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40 2194#define I40E_AQ_NVM_FLASH_ONLY 0x80 2195#define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1 2196#define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03 2197#define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03 2198#define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01 2199 u8 module_pointer; 2200 __le16 length; 2201 __le32 offset; 2202 __le32 addr_high; 2203 __le32 addr_low; 2204}; 2205 2206I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 2207 2208/* NVM Config Read (indirect 0x0704) */ 2209struct i40e_aqc_nvm_config_read { 2210 __le16 cmd_flags; 2211#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 2212#define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 2213#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 2214 __le16 element_count; 2215 __le16 element_id; /* Feature/field ID */ 2216 __le16 element_id_msw; /* MSWord of field ID */ 2217 __le32 address_high; 2218 __le32 address_low; 2219}; 2220 2221I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 2222 2223/* NVM Config Write (indirect 0x0705) */ 2224struct i40e_aqc_nvm_config_write { 2225 __le16 cmd_flags; 2226 __le16 element_count; 2227 u8 reserved[4]; 2228 __le32 address_high; 2229 __le32 address_low; 2230}; 2231 2232I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 2233 2234/* Used for 0x0704 as well as for 0x0705 commands */ 2235#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 2236#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 2237 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 2238#define I40E_AQ_ANVM_FEATURE 0 2239#define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 2240struct i40e_aqc_nvm_config_data_feature { 2241 __le16 feature_id; 2242#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 2243#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 2244#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 2245 __le16 feature_options; 2246 __le16 feature_selection; 2247}; 2248 2249I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 2250 2251struct i40e_aqc_nvm_config_data_immediate_field { 2252 __le32 field_id; 2253 __le32 field_value; 2254 __le16 field_options; 2255 __le16 reserved; 2256}; 2257 2258I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 2259 2260/* OEM Post Update (indirect 0x0720) 2261 * no command data struct used 2262 */ 2263struct i40e_aqc_nvm_oem_post_update { 2264#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 2265 u8 sel_data; 2266 u8 reserved[7]; 2267}; 2268 2269I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 2270 2271struct i40e_aqc_nvm_oem_post_update_buffer { 2272 u8 str_len; 2273 u8 dev_addr; 2274 __le16 eeprom_addr; 2275 u8 data[36]; 2276}; 2277 2278I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 2279 2280/* Thermal Sensor (indirect 0x0721) 2281 * read or set thermal sensor configs and values 2282 * takes a sensor and command specific data buffer, not detailed here 2283 */ 2284struct i40e_aqc_thermal_sensor { 2285 u8 sensor_action; 2286#define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 2287#define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 2288#define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 2289 u8 reserved[7]; 2290 __le32 addr_high; 2291 __le32 addr_low; 2292}; 2293 2294I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 2295 2296/* Send to PF command (indirect 0x0801) id is only used by PF 2297 * Send to VF command (indirect 0x0802) id is only used by PF 2298 * Send to Peer PF command (indirect 0x0803) 2299 */ 2300struct i40e_aqc_pf_vf_message { 2301 __le32 id; 2302 u8 reserved[4]; 2303 __le32 addr_high; 2304 __le32 addr_low; 2305}; 2306 2307I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 2308 2309/* Alternate structure */ 2310 2311/* Direct write (direct 0x0900) 2312 * Direct read (direct 0x0902) 2313 */ 2314struct i40e_aqc_alternate_write { 2315 __le32 address0; 2316 __le32 data0; 2317 __le32 address1; 2318 __le32 data1; 2319}; 2320 2321I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 2322 2323/* Indirect write (indirect 0x0901) 2324 * Indirect read (indirect 0x0903) 2325 */ 2326 2327struct i40e_aqc_alternate_ind_write { 2328 __le32 address; 2329 __le32 length; 2330 __le32 addr_high; 2331 __le32 addr_low; 2332}; 2333 2334I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 2335 2336/* Done alternate write (direct 0x0904) 2337 * uses i40e_aq_desc 2338 */ 2339struct i40e_aqc_alternate_write_done { 2340 __le16 cmd_flags; 2341#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 2342#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 2343#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 2344#define I40E_AQ_ALTERNATE_RESET_NEEDED 2 2345 u8 reserved[14]; 2346}; 2347 2348I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2349 2350/* Set OEM mode (direct 0x0905) */ 2351struct i40e_aqc_alternate_set_mode { 2352 __le32 mode; 2353#define I40E_AQ_ALTERNATE_MODE_NONE 0 2354#define I40E_AQ_ALTERNATE_MODE_OEM 1 2355 u8 reserved[12]; 2356}; 2357 2358I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2359 2360/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2361 2362/* async events 0x10xx */ 2363 2364/* Lan Queue Overflow Event (direct, 0x1001) */ 2365struct i40e_aqc_lan_overflow { 2366 __le32 prtdcb_rupto; 2367 __le32 otx_ctl; 2368 u8 reserved[8]; 2369}; 2370 2371I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2372 2373/* Get LLDP MIB (indirect 0x0A00) */ 2374struct i40e_aqc_lldp_get_mib { 2375 u8 type; 2376 u8 reserved1; 2377#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2378#define I40E_AQ_LLDP_MIB_LOCAL 0x0 2379#define I40E_AQ_LLDP_MIB_REMOTE 0x1 2380#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2381#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2382#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2383#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2384#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2385#define I40E_AQ_LLDP_TX_SHIFT 0x4 2386#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2387/* TX pause flags use I40E_AQ_LINK_TX_* above */ 2388 __le16 local_len; 2389 __le16 remote_len; 2390 u8 reserved2[2]; 2391 __le32 addr_high; 2392 __le32 addr_low; 2393}; 2394 2395I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2396 2397/* Configure LLDP MIB Change Event (direct 0x0A01) 2398 * also used for the event (with type in the command field) 2399 */ 2400struct i40e_aqc_lldp_update_mib { 2401 u8 command; 2402#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2403#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2404 u8 reserved[7]; 2405 __le32 addr_high; 2406 __le32 addr_low; 2407}; 2408 2409I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2410 2411/* Add LLDP TLV (indirect 0x0A02) 2412 * Delete LLDP TLV (indirect 0x0A04) 2413 */ 2414struct i40e_aqc_lldp_add_tlv { 2415 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2416 u8 reserved1[1]; 2417 __le16 len; 2418 u8 reserved2[4]; 2419 __le32 addr_high; 2420 __le32 addr_low; 2421}; 2422 2423I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2424 2425/* Update LLDP TLV (indirect 0x0A03) */ 2426struct i40e_aqc_lldp_update_tlv { 2427 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2428 u8 reserved; 2429 __le16 old_len; 2430 __le16 new_offset; 2431 __le16 new_len; 2432 __le32 addr_high; 2433 __le32 addr_low; 2434}; 2435 2436I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2437 2438/* Stop LLDP (direct 0x0A05) */ 2439struct i40e_aqc_lldp_stop { 2440 u8 command; 2441#define I40E_AQ_LLDP_AGENT_STOP 0x0 2442#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2443#define I40E_AQ_LLDP_AGENT_STOP_PERSIST 0x2 2444 u8 reserved[15]; 2445}; 2446 2447I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2448 2449/* Start LLDP (direct 0x0A06) */ 2450struct i40e_aqc_lldp_start { 2451 u8 command; 2452#define I40E_AQ_LLDP_AGENT_START 0x1 2453#define I40E_AQ_LLDP_AGENT_START_PERSIST 0x2 2454 u8 reserved[15]; 2455}; 2456 2457I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2458 2459/* Set DCB (direct 0x0303) */ 2460struct i40e_aqc_set_dcb_parameters { 2461 u8 command; 2462#define I40E_AQ_DCB_SET_AGENT 0x1 2463#define I40E_DCB_VALID 0x1 2464 u8 valid_flags; 2465 u8 reserved[14]; 2466}; 2467 2468I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters); 2469 2470/* Get CEE DCBX Oper Config (0x0A07) 2471 * uses the generic descriptor struct 2472 * returns below as indirect response 2473 */ 2474 2475#define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2476#define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2477#define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2478#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2479#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2480#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2481 2482#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2483#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2484#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2485#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2486#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2487#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2488#define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2489#define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2490#define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2491#define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2492#define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2493#define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2494 2495/* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2496 * word boundary layout issues, which the Linux compilers silently deal 2497 * with by adding padding, making the actual struct larger than designed. 2498 * However, the FW compiler for the NIC is less lenient and complains 2499 * about the struct. Hence, the struct defined here has an extra byte in 2500 * fields reserved3 and reserved4 to directly acknowledge that padding, 2501 * and the new length is used in the length check macro. 2502 */ 2503struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2504 u8 reserved1; 2505 u8 oper_num_tc; 2506 u8 oper_prio_tc[4]; 2507 u8 reserved2; 2508 u8 oper_tc_bw[8]; 2509 u8 oper_pfc_en; 2510 u8 reserved3[2]; 2511 __le16 oper_app_prio; 2512 u8 reserved4[2]; 2513 __le16 tlv_status; 2514}; 2515 2516I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2517 2518struct i40e_aqc_get_cee_dcb_cfg_resp { 2519 u8 oper_num_tc; 2520 u8 oper_prio_tc[4]; 2521 u8 oper_tc_bw[8]; 2522 u8 oper_pfc_en; 2523 __le16 oper_app_prio; 2524 __le32 tlv_status; 2525 u8 reserved[12]; 2526}; 2527 2528I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2529 2530/* Set Local LLDP MIB (indirect 0x0A08) 2531 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2532 */ 2533struct i40e_aqc_lldp_set_local_mib { 2534#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2535#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \ 2536 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2537#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2538#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2539#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \ 2540 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2541#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2542 u8 type; 2543 u8 reserved0; 2544 __le16 length; 2545 u8 reserved1[4]; 2546 __le32 address_high; 2547 __le32 address_low; 2548}; 2549 2550I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2551 2552struct i40e_aqc_lldp_set_local_mib_resp { 2553#define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01 2554 u8 status; 2555 u8 reserved[15]; 2556}; 2557 2558I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp); 2559 2560/* Stop/Start LLDP Agent (direct 0x0A09) 2561 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2562 */ 2563struct i40e_aqc_lldp_stop_start_specific_agent { 2564#define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2565#define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2566 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2567 u8 command; 2568 u8 reserved[15]; 2569}; 2570 2571I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2572 2573/* Restore LLDP Agent factory settings (direct 0x0A0A) */ 2574struct i40e_aqc_lldp_restore { 2575 u8 command; 2576#define I40E_AQ_LLDP_AGENT_RESTORE_NOT 0x0 2577#define I40E_AQ_LLDP_AGENT_RESTORE 0x1 2578 u8 reserved[15]; 2579}; 2580 2581I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_restore); 2582 2583/* Add Udp Tunnel command and completion (direct 0x0B00) */ 2584struct i40e_aqc_add_udp_tunnel { 2585 __le16 udp_port; 2586 u8 reserved0[3]; 2587 u8 protocol_type; 2588#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2589#define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2590#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2591#define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2592 u8 reserved1[10]; 2593}; 2594 2595I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2596 2597struct i40e_aqc_add_udp_tunnel_completion { 2598 __le16 udp_port; 2599 u8 filter_entry_index; 2600 u8 multiple_pfs; 2601#define I40E_AQC_SINGLE_PF 0x0 2602#define I40E_AQC_MULTIPLE_PFS 0x1 2603 u8 total_filters; 2604 u8 reserved[11]; 2605}; 2606 2607I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2608 2609/* remove UDP Tunnel command (0x0B01) */ 2610struct i40e_aqc_remove_udp_tunnel { 2611 u8 reserved[2]; 2612 u8 index; /* 0 to 15 */ 2613 u8 reserved2[13]; 2614}; 2615 2616I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2617 2618struct i40e_aqc_del_udp_tunnel_completion { 2619 __le16 udp_port; 2620 u8 index; /* 0 to 15 */ 2621 u8 multiple_pfs; 2622 u8 total_filters_used; 2623 u8 reserved1[11]; 2624}; 2625 2626I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2627 2628struct i40e_aqc_get_set_rss_key { 2629#define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15) 2630#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2631#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2632 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2633 __le16 vsi_id; 2634 u8 reserved[6]; 2635 __le32 addr_high; 2636 __le32 addr_low; 2637}; 2638 2639I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2640 2641struct i40e_aqc_get_set_rss_key_data { 2642 u8 standard_rss_key[0x28]; 2643 u8 extended_hash_key[0xc]; 2644}; 2645 2646I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2647 2648struct i40e_aqc_get_set_rss_lut { 2649#define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15) 2650#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2651#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2652 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2653 __le16 vsi_id; 2654#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2655#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \ 2656 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2657 2658#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2659#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2660 __le16 flags; 2661 u8 reserved[4]; 2662 __le32 addr_high; 2663 __le32 addr_low; 2664}; 2665 2666I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2667 2668/* tunnel key structure 0x0B10 */ 2669 2670struct i40e_aqc_tunnel_key_structure { 2671 u8 key1_off; 2672 u8 key2_off; 2673 u8 key1_len; /* 0 to 15 */ 2674 u8 key2_len; /* 0 to 15 */ 2675 u8 flags; 2676#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2677/* response flags */ 2678#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2679#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2680#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2681 u8 network_key_index; 2682#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2683#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2684#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2685#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2686 u8 reserved[10]; 2687}; 2688 2689I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2690 2691/* OEM mode commands (direct 0xFE0x) */ 2692struct i40e_aqc_oem_param_change { 2693 __le32 param_type; 2694#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2695#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2696#define I40E_AQ_OEM_PARAM_MAC 2 2697 __le32 param_value1; 2698 __le16 param_value2; 2699 u8 reserved[6]; 2700}; 2701 2702I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2703 2704struct i40e_aqc_oem_state_change { 2705 __le32 state; 2706#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2707#define I40E_AQ_OEM_STATE_LINK_UP 0x1 2708 u8 reserved[12]; 2709}; 2710 2711I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2712 2713/* Initialize OCSD (0xFE02, direct) */ 2714struct i40e_aqc_opc_oem_ocsd_initialize { 2715 u8 type_status; 2716 u8 reserved1[3]; 2717 __le32 ocsd_memory_block_addr_high; 2718 __le32 ocsd_memory_block_addr_low; 2719 __le32 requested_update_interval; 2720}; 2721 2722I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2723 2724/* Initialize OCBB (0xFE03, direct) */ 2725struct i40e_aqc_opc_oem_ocbb_initialize { 2726 u8 type_status; 2727 u8 reserved1[3]; 2728 __le32 ocbb_memory_block_addr_high; 2729 __le32 ocbb_memory_block_addr_low; 2730 u8 reserved2[4]; 2731}; 2732 2733I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2734 2735/* debug commands */ 2736 2737/* get device id (0xFF00) uses the generic structure */ 2738 2739/* set test more (0xFF01, internal) */ 2740 2741struct i40e_acq_set_test_mode { 2742 u8 mode; 2743#define I40E_AQ_TEST_PARTIAL 0 2744#define I40E_AQ_TEST_FULL 1 2745#define I40E_AQ_TEST_NVM 2 2746 u8 reserved[3]; 2747 u8 command; 2748#define I40E_AQ_TEST_OPEN 0 2749#define I40E_AQ_TEST_CLOSE 1 2750#define I40E_AQ_TEST_INC 2 2751 u8 reserved2[3]; 2752 __le32 address_high; 2753 __le32 address_low; 2754}; 2755 2756I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2757 2758/* Debug Read Register command (0xFF03) 2759 * Debug Write Register command (0xFF04) 2760 */ 2761struct i40e_aqc_debug_reg_read_write { 2762 __le32 reserved; 2763 __le32 address; 2764 __le32 value_high; 2765 __le32 value_low; 2766}; 2767 2768I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2769 2770/* Scatter/gather Reg Read (indirect 0xFF05) 2771 * Scatter/gather Reg Write (indirect 0xFF06) 2772 */ 2773 2774/* i40e_aq_desc is used for the command */ 2775struct i40e_aqc_debug_reg_sg_element_data { 2776 __le32 address; 2777 __le32 value; 2778}; 2779 2780/* Debug Modify register (direct 0xFF07) */ 2781struct i40e_aqc_debug_modify_reg { 2782 __le32 address; 2783 __le32 value; 2784 __le32 clear_mask; 2785 __le32 set_mask; 2786}; 2787 2788I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2789 2790/* dump internal data (0xFF08, indirect) */ 2791 2792#define I40E_AQ_CLUSTER_ID_AUX 0 2793#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2794#define I40E_AQ_CLUSTER_ID_TXSCHED 2 2795#define I40E_AQ_CLUSTER_ID_HMC 3 2796#define I40E_AQ_CLUSTER_ID_MAC0 4 2797#define I40E_AQ_CLUSTER_ID_MAC1 5 2798#define I40E_AQ_CLUSTER_ID_MAC2 6 2799#define I40E_AQ_CLUSTER_ID_MAC3 7 2800#define I40E_AQ_CLUSTER_ID_DCB 8 2801#define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2802#define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2803#define I40E_AQ_CLUSTER_ID_ALTRAM 11 2804 2805struct i40e_aqc_debug_dump_internals { 2806 u8 cluster_id; 2807 u8 table_id; 2808 __le16 data_size; 2809 __le32 idx; 2810 __le32 address_high; 2811 __le32 address_low; 2812}; 2813 2814I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2815 2816struct i40e_aqc_debug_modify_internals { 2817 u8 cluster_id; 2818 u8 cluster_specific_params[7]; 2819 __le32 address_high; 2820 __le32 address_low; 2821}; 2822 2823I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2824 2825#endif /* _I40E_ADMINQ_CMD_H_ */ 2826