i40e_adminq_cmd.h revision 333343
1266423Sjfv/****************************************************************************** 2266423Sjfv 3333343Serj Copyright (c) 2013-2017, Intel Corporation 4266423Sjfv All rights reserved. 5266423Sjfv 6266423Sjfv Redistribution and use in source and binary forms, with or without 7266423Sjfv modification, are permitted provided that the following conditions are met: 8266423Sjfv 9266423Sjfv 1. Redistributions of source code must retain the above copyright notice, 10266423Sjfv this list of conditions and the following disclaimer. 11266423Sjfv 12266423Sjfv 2. Redistributions in binary form must reproduce the above copyright 13266423Sjfv notice, this list of conditions and the following disclaimer in the 14266423Sjfv documentation and/or other materials provided with the distribution. 15266423Sjfv 16266423Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17266423Sjfv contributors may be used to endorse or promote products derived from 18266423Sjfv this software without specific prior written permission. 19266423Sjfv 20266423Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21266423Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22266423Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23266423Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24266423Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25266423Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26266423Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27266423Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28266423Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29266423Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30266423Sjfv POSSIBILITY OF SUCH DAMAGE. 31266423Sjfv 32266423Sjfv******************************************************************************/ 33266423Sjfv/*$FreeBSD: stable/11/sys/dev/ixl/i40e_adminq_cmd.h 333343 2018-05-07 23:23:11Z erj $*/ 34266423Sjfv 35266423Sjfv#ifndef _I40E_ADMINQ_CMD_H_ 36266423Sjfv#define _I40E_ADMINQ_CMD_H_ 37266423Sjfv 38266423Sjfv/* This header file defines the i40e Admin Queue commands and is shared between 39266423Sjfv * i40e Firmware and Software. 40266423Sjfv * 41266423Sjfv * This file needs to comply with the Linux Kernel coding style. 42266423Sjfv */ 43266423Sjfv 44333343Serj 45270346Sjfv#define I40E_FW_API_VERSION_MAJOR 0x0001 46333343Serj#define I40E_FW_API_VERSION_MINOR_X722 0x0005 47333343Serj#define I40E_FW_API_VERSION_MINOR_X710 0x0007 48266423Sjfv 49333343Serj#define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \ 50333343Serj I40E_FW_API_VERSION_MINOR_X710 : \ 51333343Serj I40E_FW_API_VERSION_MINOR_X722) 52333343Serj 53333343Serj/* API version 1.7 implements additional link and PHY-specific APIs */ 54333343Serj#define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007 55333343Serj 56266423Sjfvstruct i40e_aq_desc { 57266423Sjfv __le16 flags; 58266423Sjfv __le16 opcode; 59266423Sjfv __le16 datalen; 60266423Sjfv __le16 retval; 61266423Sjfv __le32 cookie_high; 62266423Sjfv __le32 cookie_low; 63266423Sjfv union { 64266423Sjfv struct { 65266423Sjfv __le32 param0; 66266423Sjfv __le32 param1; 67266423Sjfv __le32 param2; 68266423Sjfv __le32 param3; 69266423Sjfv } internal; 70266423Sjfv struct { 71266423Sjfv __le32 param0; 72266423Sjfv __le32 param1; 73266423Sjfv __le32 addr_high; 74266423Sjfv __le32 addr_low; 75266423Sjfv } external; 76266423Sjfv u8 raw[16]; 77266423Sjfv } params; 78266423Sjfv}; 79266423Sjfv 80266423Sjfv/* Flags sub-structure 81266423Sjfv * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 82266423Sjfv * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 83266423Sjfv */ 84266423Sjfv 85266423Sjfv/* command flags and offsets*/ 86270346Sjfv#define I40E_AQ_FLAG_DD_SHIFT 0 87270346Sjfv#define I40E_AQ_FLAG_CMP_SHIFT 1 88270346Sjfv#define I40E_AQ_FLAG_ERR_SHIFT 2 89270346Sjfv#define I40E_AQ_FLAG_VFE_SHIFT 3 90270346Sjfv#define I40E_AQ_FLAG_LB_SHIFT 9 91270346Sjfv#define I40E_AQ_FLAG_RD_SHIFT 10 92270346Sjfv#define I40E_AQ_FLAG_VFC_SHIFT 11 93270346Sjfv#define I40E_AQ_FLAG_BUF_SHIFT 12 94270346Sjfv#define I40E_AQ_FLAG_SI_SHIFT 13 95270346Sjfv#define I40E_AQ_FLAG_EI_SHIFT 14 96270346Sjfv#define I40E_AQ_FLAG_FE_SHIFT 15 97266423Sjfv 98270346Sjfv#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 99270346Sjfv#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 100270346Sjfv#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 101270346Sjfv#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 102270346Sjfv#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 103270346Sjfv#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 104270346Sjfv#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 105270346Sjfv#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 106270346Sjfv#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 107270346Sjfv#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 108270346Sjfv#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 109266423Sjfv 110266423Sjfv/* error codes */ 111266423Sjfvenum i40e_admin_queue_err { 112270346Sjfv I40E_AQ_RC_OK = 0, /* success */ 113270346Sjfv I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 114270346Sjfv I40E_AQ_RC_ENOENT = 2, /* No such element */ 115270346Sjfv I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 116270346Sjfv I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 117270346Sjfv I40E_AQ_RC_EIO = 5, /* I/O error */ 118270346Sjfv I40E_AQ_RC_ENXIO = 6, /* No such resource */ 119270346Sjfv I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 120270346Sjfv I40E_AQ_RC_EAGAIN = 8, /* Try again */ 121270346Sjfv I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 122270346Sjfv I40E_AQ_RC_EACCES = 10, /* Permission denied */ 123270346Sjfv I40E_AQ_RC_EFAULT = 11, /* Bad address */ 124270346Sjfv I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 125270346Sjfv I40E_AQ_RC_EEXIST = 13, /* object already exists */ 126270346Sjfv I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 127270346Sjfv I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 128270346Sjfv I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 129270346Sjfv I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 130270346Sjfv I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 131270346Sjfv I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 132270346Sjfv I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 133270346Sjfv I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 134270346Sjfv I40E_AQ_RC_EFBIG = 22, /* File too large */ 135266423Sjfv}; 136266423Sjfv 137266423Sjfv/* Admin Queue command opcodes */ 138266423Sjfvenum i40e_admin_queue_opc { 139266423Sjfv /* aq commands */ 140270346Sjfv i40e_aqc_opc_get_version = 0x0001, 141270346Sjfv i40e_aqc_opc_driver_version = 0x0002, 142270346Sjfv i40e_aqc_opc_queue_shutdown = 0x0003, 143270346Sjfv i40e_aqc_opc_set_pf_context = 0x0004, 144266423Sjfv 145266423Sjfv /* resource ownership */ 146270346Sjfv i40e_aqc_opc_request_resource = 0x0008, 147270346Sjfv i40e_aqc_opc_release_resource = 0x0009, 148266423Sjfv 149270346Sjfv i40e_aqc_opc_list_func_capabilities = 0x000A, 150270346Sjfv i40e_aqc_opc_list_dev_capabilities = 0x000B, 151266423Sjfv 152303967Ssbruno /* Proxy commands */ 153303967Ssbruno i40e_aqc_opc_set_proxy_config = 0x0104, 154303967Ssbruno i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, 155303967Ssbruno 156266423Sjfv /* LAA */ 157270346Sjfv i40e_aqc_opc_mac_address_read = 0x0107, 158270346Sjfv i40e_aqc_opc_mac_address_write = 0x0108, 159266423Sjfv 160266423Sjfv /* PXE */ 161270346Sjfv i40e_aqc_opc_clear_pxe_mode = 0x0110, 162266423Sjfv 163303967Ssbruno /* WoL commands */ 164303967Ssbruno i40e_aqc_opc_set_wol_filter = 0x0120, 165303967Ssbruno i40e_aqc_opc_get_wake_reason = 0x0121, 166318357Serj i40e_aqc_opc_clear_all_wol_filters = 0x025E, 167303967Ssbruno 168266423Sjfv /* internal switch commands */ 169270346Sjfv i40e_aqc_opc_get_switch_config = 0x0200, 170270346Sjfv i40e_aqc_opc_add_statistics = 0x0201, 171270346Sjfv i40e_aqc_opc_remove_statistics = 0x0202, 172270346Sjfv i40e_aqc_opc_set_port_parameters = 0x0203, 173270346Sjfv i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 174299549Serj i40e_aqc_opc_set_switch_config = 0x0205, 175299555Serj i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 176299555Serj i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 177266423Sjfv 178270346Sjfv i40e_aqc_opc_add_vsi = 0x0210, 179270346Sjfv i40e_aqc_opc_update_vsi_parameters = 0x0211, 180270346Sjfv i40e_aqc_opc_get_vsi_parameters = 0x0212, 181266423Sjfv 182270346Sjfv i40e_aqc_opc_add_pv = 0x0220, 183270346Sjfv i40e_aqc_opc_update_pv_parameters = 0x0221, 184270346Sjfv i40e_aqc_opc_get_pv_parameters = 0x0222, 185266423Sjfv 186270346Sjfv i40e_aqc_opc_add_veb = 0x0230, 187270346Sjfv i40e_aqc_opc_update_veb_parameters = 0x0231, 188270346Sjfv i40e_aqc_opc_get_veb_parameters = 0x0232, 189266423Sjfv 190270346Sjfv i40e_aqc_opc_delete_element = 0x0243, 191266423Sjfv 192270346Sjfv i40e_aqc_opc_add_macvlan = 0x0250, 193270346Sjfv i40e_aqc_opc_remove_macvlan = 0x0251, 194270346Sjfv i40e_aqc_opc_add_vlan = 0x0252, 195270346Sjfv i40e_aqc_opc_remove_vlan = 0x0253, 196270346Sjfv i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 197270346Sjfv i40e_aqc_opc_add_tag = 0x0255, 198270346Sjfv i40e_aqc_opc_remove_tag = 0x0256, 199270346Sjfv i40e_aqc_opc_add_multicast_etag = 0x0257, 200270346Sjfv i40e_aqc_opc_remove_multicast_etag = 0x0258, 201270346Sjfv i40e_aqc_opc_update_tag = 0x0259, 202270346Sjfv i40e_aqc_opc_add_control_packet_filter = 0x025A, 203270346Sjfv i40e_aqc_opc_remove_control_packet_filter = 0x025B, 204270346Sjfv i40e_aqc_opc_add_cloud_filters = 0x025C, 205270346Sjfv i40e_aqc_opc_remove_cloud_filters = 0x025D, 206303967Ssbruno i40e_aqc_opc_clear_wol_switch_filters = 0x025E, 207266423Sjfv 208270346Sjfv i40e_aqc_opc_add_mirror_rule = 0x0260, 209270346Sjfv i40e_aqc_opc_delete_mirror_rule = 0x0261, 210266423Sjfv 211266423Sjfv /* DCB commands */ 212270346Sjfv i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 213270346Sjfv i40e_aqc_opc_dcb_updated = 0x0302, 214333343Serj i40e_aqc_opc_set_dcb_parameters = 0x0303, 215266423Sjfv 216266423Sjfv /* TX scheduler */ 217270346Sjfv i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 218270346Sjfv i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 219270346Sjfv i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 220270346Sjfv i40e_aqc_opc_query_vsi_bw_config = 0x0408, 221270346Sjfv i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 222270346Sjfv i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 223266423Sjfv 224270346Sjfv i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 225270346Sjfv i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 226270346Sjfv i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 227270346Sjfv i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 228270346Sjfv i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 229270346Sjfv i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 230270346Sjfv i40e_aqc_opc_query_port_ets_config = 0x0419, 231270346Sjfv i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 232270346Sjfv i40e_aqc_opc_suspend_port_tx = 0x041B, 233270346Sjfv i40e_aqc_opc_resume_port_tx = 0x041C, 234270346Sjfv i40e_aqc_opc_configure_partition_bw = 0x041D, 235266423Sjfv /* hmc */ 236270346Sjfv i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 237270346Sjfv i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 238266423Sjfv 239266423Sjfv /* phy commands*/ 240270346Sjfv i40e_aqc_opc_get_phy_abilities = 0x0600, 241270346Sjfv i40e_aqc_opc_set_phy_config = 0x0601, 242270346Sjfv i40e_aqc_opc_set_mac_config = 0x0603, 243270346Sjfv i40e_aqc_opc_set_link_restart_an = 0x0605, 244270346Sjfv i40e_aqc_opc_get_link_status = 0x0607, 245270346Sjfv i40e_aqc_opc_set_phy_int_mask = 0x0613, 246270346Sjfv i40e_aqc_opc_get_local_advt_reg = 0x0614, 247270346Sjfv i40e_aqc_opc_set_local_advt_reg = 0x0615, 248270346Sjfv i40e_aqc_opc_get_partner_advt = 0x0616, 249270346Sjfv i40e_aqc_opc_set_lb_modes = 0x0618, 250270346Sjfv i40e_aqc_opc_get_phy_wol_caps = 0x0621, 251270346Sjfv i40e_aqc_opc_set_phy_debug = 0x0622, 252270346Sjfv i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 253299549Serj i40e_aqc_opc_run_phy_activity = 0x0626, 254333343Serj i40e_aqc_opc_set_phy_register = 0x0628, 255333343Serj i40e_aqc_opc_get_phy_register = 0x0629, 256266423Sjfv 257266423Sjfv /* NVM commands */ 258270346Sjfv i40e_aqc_opc_nvm_read = 0x0701, 259270346Sjfv i40e_aqc_opc_nvm_erase = 0x0702, 260270346Sjfv i40e_aqc_opc_nvm_update = 0x0703, 261270346Sjfv i40e_aqc_opc_nvm_config_read = 0x0704, 262270346Sjfv i40e_aqc_opc_nvm_config_write = 0x0705, 263333343Serj i40e_aqc_opc_nvm_progress = 0x0706, 264284049Sjfv i40e_aqc_opc_oem_post_update = 0x0720, 265299549Serj i40e_aqc_opc_thermal_sensor = 0x0721, 266266423Sjfv 267266423Sjfv /* virtualization commands */ 268270346Sjfv i40e_aqc_opc_send_msg_to_pf = 0x0801, 269270346Sjfv i40e_aqc_opc_send_msg_to_vf = 0x0802, 270270346Sjfv i40e_aqc_opc_send_msg_to_peer = 0x0803, 271266423Sjfv 272266423Sjfv /* alternate structure */ 273270346Sjfv i40e_aqc_opc_alternate_write = 0x0900, 274270346Sjfv i40e_aqc_opc_alternate_write_indirect = 0x0901, 275270346Sjfv i40e_aqc_opc_alternate_read = 0x0902, 276270346Sjfv i40e_aqc_opc_alternate_read_indirect = 0x0903, 277270346Sjfv i40e_aqc_opc_alternate_write_done = 0x0904, 278270346Sjfv i40e_aqc_opc_alternate_set_mode = 0x0905, 279270346Sjfv i40e_aqc_opc_alternate_clear_port = 0x0906, 280266423Sjfv 281266423Sjfv /* LLDP commands */ 282270346Sjfv i40e_aqc_opc_lldp_get_mib = 0x0A00, 283270346Sjfv i40e_aqc_opc_lldp_update_mib = 0x0A01, 284270346Sjfv i40e_aqc_opc_lldp_add_tlv = 0x0A02, 285270346Sjfv i40e_aqc_opc_lldp_update_tlv = 0x0A03, 286270346Sjfv i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 287270346Sjfv i40e_aqc_opc_lldp_stop = 0x0A05, 288270346Sjfv i40e_aqc_opc_lldp_start = 0x0A06, 289277082Sjfv i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 290277082Sjfv i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 291277082Sjfv i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 292266423Sjfv 293266423Sjfv /* Tunnel commands */ 294270346Sjfv i40e_aqc_opc_add_udp_tunnel = 0x0B00, 295270346Sjfv i40e_aqc_opc_del_udp_tunnel = 0x0B01, 296303967Ssbruno i40e_aqc_opc_set_rss_key = 0x0B02, 297303967Ssbruno i40e_aqc_opc_set_rss_lut = 0x0B03, 298303967Ssbruno i40e_aqc_opc_get_rss_key = 0x0B04, 299303967Ssbruno i40e_aqc_opc_get_rss_lut = 0x0B05, 300266423Sjfv 301266423Sjfv /* Async Events */ 302270346Sjfv i40e_aqc_opc_event_lan_overflow = 0x1001, 303266423Sjfv 304266423Sjfv /* OEM commands */ 305270346Sjfv i40e_aqc_opc_oem_parameter_change = 0xFE00, 306270346Sjfv i40e_aqc_opc_oem_device_status_change = 0xFE01, 307277082Sjfv i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 308277082Sjfv i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 309266423Sjfv 310266423Sjfv /* debug commands */ 311270346Sjfv i40e_aqc_opc_debug_read_reg = 0xFF03, 312270346Sjfv i40e_aqc_opc_debug_write_reg = 0xFF04, 313270346Sjfv i40e_aqc_opc_debug_modify_reg = 0xFF07, 314270346Sjfv i40e_aqc_opc_debug_dump_internals = 0xFF08, 315266423Sjfv}; 316266423Sjfv 317266423Sjfv/* command structures and indirect data structures */ 318266423Sjfv 319266423Sjfv/* Structure naming conventions: 320266423Sjfv * - no suffix for direct command descriptor structures 321266423Sjfv * - _data for indirect sent data 322266423Sjfv * - _resp for indirect return data (data which is both will use _data) 323266423Sjfv * - _completion for direct return data 324266423Sjfv * - _element_ for repeated elements (may also be _data or _resp) 325266423Sjfv * 326266423Sjfv * Command structures are expected to overlay the params.raw member of the basic 327266423Sjfv * descriptor, and as such cannot exceed 16 bytes in length. 328266423Sjfv */ 329266423Sjfv 330266423Sjfv/* This macro is used to generate a compilation error if a structure 331266423Sjfv * is not exactly the correct length. It gives a divide by zero error if the 332266423Sjfv * structure is not of the correct size, otherwise it creates an enum that is 333266423Sjfv * never used. 334266423Sjfv */ 335266423Sjfv#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 336266423Sjfv { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 337266423Sjfv 338266423Sjfv/* This macro is used extensively to ensure that command structures are 16 339266423Sjfv * bytes in length as they have to map to the raw array of that size. 340266423Sjfv */ 341270346Sjfv#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 342266423Sjfv 343266423Sjfv/* internal (0x00XX) commands */ 344266423Sjfv 345266423Sjfv/* Get version (direct 0x0001) */ 346266423Sjfvstruct i40e_aqc_get_version { 347266423Sjfv __le32 rom_ver; 348266423Sjfv __le32 fw_build; 349266423Sjfv __le16 fw_major; 350266423Sjfv __le16 fw_minor; 351266423Sjfv __le16 api_major; 352266423Sjfv __le16 api_minor; 353266423Sjfv}; 354266423Sjfv 355266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 356266423Sjfv 357266423Sjfv/* Send driver version (indirect 0x0002) */ 358266423Sjfvstruct i40e_aqc_driver_version { 359270346Sjfv u8 driver_major_ver; 360270346Sjfv u8 driver_minor_ver; 361270346Sjfv u8 driver_build_ver; 362270346Sjfv u8 driver_subbuild_ver; 363270346Sjfv u8 reserved[4]; 364270346Sjfv __le32 address_high; 365270346Sjfv __le32 address_low; 366266423Sjfv}; 367266423Sjfv 368266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 369266423Sjfv 370266423Sjfv/* Queue Shutdown (direct 0x0003) */ 371266423Sjfvstruct i40e_aqc_queue_shutdown { 372270346Sjfv __le32 driver_unloading; 373270346Sjfv#define I40E_AQ_DRIVER_UNLOADING 0x1 374270346Sjfv u8 reserved[12]; 375266423Sjfv}; 376266423Sjfv 377266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 378266423Sjfv 379266423Sjfv/* Set PF context (0x0004, direct) */ 380266423Sjfvstruct i40e_aqc_set_pf_context { 381266423Sjfv u8 pf_id; 382266423Sjfv u8 reserved[15]; 383266423Sjfv}; 384266423Sjfv 385266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 386266423Sjfv 387266423Sjfv/* Request resource ownership (direct 0x0008) 388266423Sjfv * Release resource ownership (direct 0x0009) 389266423Sjfv */ 390270346Sjfv#define I40E_AQ_RESOURCE_NVM 1 391270346Sjfv#define I40E_AQ_RESOURCE_SDP 2 392270346Sjfv#define I40E_AQ_RESOURCE_ACCESS_READ 1 393270346Sjfv#define I40E_AQ_RESOURCE_ACCESS_WRITE 2 394270346Sjfv#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 395270346Sjfv#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 396266423Sjfv 397266423Sjfvstruct i40e_aqc_request_resource { 398270346Sjfv __le16 resource_id; 399270346Sjfv __le16 access_type; 400270346Sjfv __le32 timeout; 401270346Sjfv __le32 resource_number; 402270346Sjfv u8 reserved[4]; 403266423Sjfv}; 404266423Sjfv 405266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 406266423Sjfv 407266423Sjfv/* Get function capabilities (indirect 0x000A) 408266423Sjfv * Get device capabilities (indirect 0x000B) 409266423Sjfv */ 410266423Sjfvstruct i40e_aqc_list_capabilites { 411266423Sjfv u8 command_flags; 412270346Sjfv#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 413266423Sjfv u8 pf_index; 414266423Sjfv u8 reserved[2]; 415266423Sjfv __le32 count; 416266423Sjfv __le32 addr_high; 417266423Sjfv __le32 addr_low; 418266423Sjfv}; 419266423Sjfv 420266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 421266423Sjfv 422266423Sjfvstruct i40e_aqc_list_capabilities_element_resp { 423270346Sjfv __le16 id; 424270346Sjfv u8 major_rev; 425270346Sjfv u8 minor_rev; 426270346Sjfv __le32 number; 427270346Sjfv __le32 logical_id; 428270346Sjfv __le32 phys_id; 429270346Sjfv u8 reserved[16]; 430266423Sjfv}; 431266423Sjfv 432266423Sjfv/* list of caps */ 433266423Sjfv 434270346Sjfv#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 435270346Sjfv#define I40E_AQ_CAP_ID_MNG_MODE 0x0002 436270346Sjfv#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 437270346Sjfv#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 438270346Sjfv#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 439270346Sjfv#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 440299548Serj#define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 441270346Sjfv#define I40E_AQ_CAP_ID_SRIOV 0x0012 442270346Sjfv#define I40E_AQ_CAP_ID_VF 0x0013 443270346Sjfv#define I40E_AQ_CAP_ID_VMDQ 0x0014 444270346Sjfv#define I40E_AQ_CAP_ID_8021QBG 0x0015 445270346Sjfv#define I40E_AQ_CAP_ID_8021QBR 0x0016 446270346Sjfv#define I40E_AQ_CAP_ID_VSI 0x0017 447270346Sjfv#define I40E_AQ_CAP_ID_DCB 0x0018 448270346Sjfv#define I40E_AQ_CAP_ID_FCOE 0x0021 449277082Sjfv#define I40E_AQ_CAP_ID_ISCSI 0x0022 450270346Sjfv#define I40E_AQ_CAP_ID_RSS 0x0040 451270346Sjfv#define I40E_AQ_CAP_ID_RXQ 0x0041 452270346Sjfv#define I40E_AQ_CAP_ID_TXQ 0x0042 453270346Sjfv#define I40E_AQ_CAP_ID_MSIX 0x0043 454270346Sjfv#define I40E_AQ_CAP_ID_VF_MSIX 0x0044 455270346Sjfv#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 456270346Sjfv#define I40E_AQ_CAP_ID_1588 0x0046 457270346Sjfv#define I40E_AQ_CAP_ID_IWARP 0x0051 458270346Sjfv#define I40E_AQ_CAP_ID_LED 0x0061 459270346Sjfv#define I40E_AQ_CAP_ID_SDP 0x0062 460270346Sjfv#define I40E_AQ_CAP_ID_MDIO 0x0063 461299548Serj#define I40E_AQ_CAP_ID_WSR_PROT 0x0064 462303967Ssbruno#define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 463270346Sjfv#define I40E_AQ_CAP_ID_FLEX10 0x00F1 464270346Sjfv#define I40E_AQ_CAP_ID_CEM 0x00F2 465266423Sjfv 466266423Sjfv/* Set CPPM Configuration (direct 0x0103) */ 467266423Sjfvstruct i40e_aqc_cppm_configuration { 468270346Sjfv __le16 command_flags; 469270346Sjfv#define I40E_AQ_CPPM_EN_LTRC 0x0800 470270346Sjfv#define I40E_AQ_CPPM_EN_DMCTH 0x1000 471270346Sjfv#define I40E_AQ_CPPM_EN_DMCTLX 0x2000 472270346Sjfv#define I40E_AQ_CPPM_EN_HPTC 0x4000 473270346Sjfv#define I40E_AQ_CPPM_EN_DMARC 0x8000 474270346Sjfv __le16 ttlx; 475270346Sjfv __le32 dmacr; 476270346Sjfv __le16 dmcth; 477270346Sjfv u8 hptc; 478270346Sjfv u8 reserved; 479270346Sjfv __le32 pfltrc; 480266423Sjfv}; 481266423Sjfv 482266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 483266423Sjfv 484266423Sjfv/* Set ARP Proxy command / response (indirect 0x0104) */ 485266423Sjfvstruct i40e_aqc_arp_proxy_data { 486270346Sjfv __le16 command_flags; 487303967Ssbruno#define I40E_AQ_ARP_INIT_IPV4 0x0800 488303967Ssbruno#define I40E_AQ_ARP_UNSUP_CTL 0x1000 489303967Ssbruno#define I40E_AQ_ARP_ENA 0x2000 490303967Ssbruno#define I40E_AQ_ARP_ADD_IPV4 0x4000 491303967Ssbruno#define I40E_AQ_ARP_DEL_IPV4 0x8000 492270346Sjfv __le16 table_id; 493303967Ssbruno __le32 enabled_offloads; 494303967Ssbruno#define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 495303967Ssbruno#define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 496270346Sjfv __le32 ip_addr; 497270346Sjfv u8 mac_addr[6]; 498277082Sjfv u8 reserved[2]; 499266423Sjfv}; 500266423Sjfv 501277082SjfvI40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 502277082Sjfv 503266423Sjfv/* Set NS Proxy Table Entry Command (indirect 0x0105) */ 504266423Sjfvstruct i40e_aqc_ns_proxy_data { 505270346Sjfv __le16 table_idx_mac_addr_0; 506270346Sjfv __le16 table_idx_mac_addr_1; 507270346Sjfv __le16 table_idx_ipv6_0; 508270346Sjfv __le16 table_idx_ipv6_1; 509270346Sjfv __le16 control; 510303967Ssbruno#define I40E_AQ_NS_PROXY_ADD_0 0x0001 511303967Ssbruno#define I40E_AQ_NS_PROXY_DEL_0 0x0002 512303967Ssbruno#define I40E_AQ_NS_PROXY_ADD_1 0x0004 513303967Ssbruno#define I40E_AQ_NS_PROXY_DEL_1 0x0008 514303967Ssbruno#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 515303967Ssbruno#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 516303967Ssbruno#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 517303967Ssbruno#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 518303967Ssbruno#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 519303967Ssbruno#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 520303967Ssbruno#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 521303967Ssbruno#define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 522303967Ssbruno#define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 523270346Sjfv u8 mac_addr_0[6]; 524270346Sjfv u8 mac_addr_1[6]; 525270346Sjfv u8 local_mac_addr[6]; 526270346Sjfv u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 527270346Sjfv u8 ipv6_addr_1[16]; 528266423Sjfv}; 529266423Sjfv 530277082SjfvI40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 531277082Sjfv 532266423Sjfv/* Manage LAA Command (0x0106) - obsolete */ 533266423Sjfvstruct i40e_aqc_mng_laa { 534266423Sjfv __le16 command_flags; 535270346Sjfv#define I40E_AQ_LAA_FLAG_WR 0x8000 536270346Sjfv u8 reserved[2]; 537270346Sjfv __le32 sal; 538270346Sjfv __le16 sah; 539270346Sjfv u8 reserved2[6]; 540266423Sjfv}; 541266423Sjfv 542277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 543277082Sjfv 544266423Sjfv/* Manage MAC Address Read Command (indirect 0x0107) */ 545266423Sjfvstruct i40e_aqc_mac_address_read { 546266423Sjfv __le16 command_flags; 547270346Sjfv#define I40E_AQC_LAN_ADDR_VALID 0x10 548270346Sjfv#define I40E_AQC_SAN_ADDR_VALID 0x20 549270346Sjfv#define I40E_AQC_PORT_ADDR_VALID 0x40 550270346Sjfv#define I40E_AQC_WOL_ADDR_VALID 0x80 551284049Sjfv#define I40E_AQC_MC_MAG_EN_VALID 0x100 552318357Serj#define I40E_AQC_WOL_PRESERVE_STATUS 0x200 553318357Serj#define I40E_AQC_ADDR_VALID_MASK 0x3F0 554270346Sjfv u8 reserved[6]; 555270346Sjfv __le32 addr_high; 556270346Sjfv __le32 addr_low; 557266423Sjfv}; 558266423Sjfv 559266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 560266423Sjfv 561266423Sjfvstruct i40e_aqc_mac_address_read_data { 562266423Sjfv u8 pf_lan_mac[6]; 563266423Sjfv u8 pf_san_mac[6]; 564266423Sjfv u8 port_mac[6]; 565266423Sjfv u8 pf_wol_mac[6]; 566266423Sjfv}; 567266423Sjfv 568266423SjfvI40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 569266423Sjfv 570266423Sjfv/* Manage MAC Address Write Command (0x0108) */ 571266423Sjfvstruct i40e_aqc_mac_address_write { 572270346Sjfv __le16 command_flags; 573303967Ssbruno#define I40E_AQC_MC_MAG_EN 0x0100 574318357Serj#define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200 575270346Sjfv#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 576270346Sjfv#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 577270346Sjfv#define I40E_AQC_WRITE_TYPE_PORT 0x8000 578284049Sjfv#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 579284049Sjfv#define I40E_AQC_WRITE_TYPE_MASK 0xC000 580284049Sjfv 581270346Sjfv __le16 mac_sah; 582270346Sjfv __le32 mac_sal; 583270346Sjfv u8 reserved[8]; 584266423Sjfv}; 585266423Sjfv 586266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 587266423Sjfv 588266423Sjfv/* PXE commands (0x011x) */ 589266423Sjfv 590266423Sjfv/* Clear PXE Command and response (direct 0x0110) */ 591266423Sjfvstruct i40e_aqc_clear_pxe { 592266423Sjfv u8 rx_cnt; 593266423Sjfv u8 reserved[15]; 594266423Sjfv}; 595266423Sjfv 596266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 597266423Sjfv 598303967Ssbruno/* Set WoL Filter (0x0120) */ 599303967Ssbruno 600303967Ssbrunostruct i40e_aqc_set_wol_filter { 601303967Ssbruno __le16 filter_index; 602303967Ssbruno#define I40E_AQC_MAX_NUM_WOL_FILTERS 8 603303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 604303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ 605303967Ssbruno I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) 606303967Ssbruno 607303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 608303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ 609303967Ssbruno I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) 610303967Ssbruno __le16 cmd_flags; 611303967Ssbruno#define I40E_AQC_SET_WOL_FILTER 0x8000 612303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 613318357Serj#define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000 614303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 615303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 616303967Ssbruno __le16 valid_flags; 617303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 618303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 619303967Ssbruno u8 reserved[2]; 620303967Ssbruno __le32 address_high; 621303967Ssbruno __le32 address_low; 622303967Ssbruno}; 623303967Ssbruno 624303967SsbrunoI40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); 625303967Ssbruno 626303967Ssbrunostruct i40e_aqc_set_wol_filter_data { 627303967Ssbruno u8 filter[128]; 628303967Ssbruno u8 mask[16]; 629303967Ssbruno}; 630303967Ssbruno 631303967SsbrunoI40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); 632303967Ssbruno 633303967Ssbruno/* Get Wake Reason (0x0121) */ 634303967Ssbruno 635303967Ssbrunostruct i40e_aqc_get_wake_reason_completion { 636303967Ssbruno u8 reserved_1[2]; 637303967Ssbruno __le16 wake_reason; 638303967Ssbruno#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 639303967Ssbruno#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ 640303967Ssbruno I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) 641303967Ssbruno#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 642303967Ssbruno#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ 643303967Ssbruno I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) 644303967Ssbruno u8 reserved_2[12]; 645303967Ssbruno}; 646303967Ssbruno 647303967SsbrunoI40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); 648303967Ssbruno 649266423Sjfv/* Switch configuration commands (0x02xx) */ 650266423Sjfv 651266423Sjfv/* Used by many indirect commands that only pass an seid and a buffer in the 652266423Sjfv * command 653266423Sjfv */ 654266423Sjfvstruct i40e_aqc_switch_seid { 655270346Sjfv __le16 seid; 656270346Sjfv u8 reserved[6]; 657270346Sjfv __le32 addr_high; 658270346Sjfv __le32 addr_low; 659266423Sjfv}; 660266423Sjfv 661266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 662266423Sjfv 663266423Sjfv/* Get Switch Configuration command (indirect 0x0200) 664266423Sjfv * uses i40e_aqc_switch_seid for the descriptor 665266423Sjfv */ 666266423Sjfvstruct i40e_aqc_get_switch_config_header_resp { 667270346Sjfv __le16 num_reported; 668270346Sjfv __le16 num_total; 669270346Sjfv u8 reserved[12]; 670266423Sjfv}; 671266423Sjfv 672277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 673277082Sjfv 674266423Sjfvstruct i40e_aqc_switch_config_element_resp { 675270346Sjfv u8 element_type; 676270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_MAC 1 677270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_PF 2 678270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_VF 3 679270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_EMP 4 680270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_BMC 5 681270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_PV 16 682270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_VEB 17 683270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_PA 18 684270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_VSI 19 685270346Sjfv u8 revision; 686270346Sjfv#define I40E_AQ_SW_ELEM_REV_1 1 687270346Sjfv __le16 seid; 688270346Sjfv __le16 uplink_seid; 689270346Sjfv __le16 downlink_seid; 690270346Sjfv u8 reserved[3]; 691270346Sjfv u8 connection_type; 692270346Sjfv#define I40E_AQ_CONN_TYPE_REGULAR 0x1 693270346Sjfv#define I40E_AQ_CONN_TYPE_DEFAULT 0x2 694270346Sjfv#define I40E_AQ_CONN_TYPE_CASCADED 0x3 695270346Sjfv __le16 scheduler_id; 696270346Sjfv __le16 element_info; 697266423Sjfv}; 698266423Sjfv 699277082SjfvI40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 700277082Sjfv 701266423Sjfv/* Get Switch Configuration (indirect 0x0200) 702266423Sjfv * an array of elements are returned in the response buffer 703266423Sjfv * the first in the array is the header, remainder are elements 704266423Sjfv */ 705266423Sjfvstruct i40e_aqc_get_switch_config_resp { 706270346Sjfv struct i40e_aqc_get_switch_config_header_resp header; 707270346Sjfv struct i40e_aqc_switch_config_element_resp element[1]; 708266423Sjfv}; 709266423Sjfv 710277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 711277082Sjfv 712266423Sjfv/* Add Statistics (direct 0x0201) 713266423Sjfv * Remove Statistics (direct 0x0202) 714266423Sjfv */ 715266423Sjfvstruct i40e_aqc_add_remove_statistics { 716270346Sjfv __le16 seid; 717270346Sjfv __le16 vlan; 718270346Sjfv __le16 stat_index; 719270346Sjfv u8 reserved[10]; 720266423Sjfv}; 721266423Sjfv 722266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 723266423Sjfv 724266423Sjfv/* Set Port Parameters command (direct 0x0203) */ 725266423Sjfvstruct i40e_aqc_set_port_parameters { 726270346Sjfv __le16 command_flags; 727270346Sjfv#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 728270346Sjfv#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 729270346Sjfv#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 730270346Sjfv __le16 bad_frame_vsi; 731303967Ssbruno#define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 732303967Ssbruno#define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF 733270346Sjfv __le16 default_seid; /* reserved for command */ 734270346Sjfv u8 reserved[10]; 735266423Sjfv}; 736266423Sjfv 737266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 738266423Sjfv 739266423Sjfv/* Get Switch Resource Allocation (indirect 0x0204) */ 740266423Sjfvstruct i40e_aqc_get_switch_resource_alloc { 741270346Sjfv u8 num_entries; /* reserved for command */ 742270346Sjfv u8 reserved[7]; 743270346Sjfv __le32 addr_high; 744270346Sjfv __le32 addr_low; 745266423Sjfv}; 746266423Sjfv 747266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 748266423Sjfv 749266423Sjfv/* expect an array of these structs in the response buffer */ 750266423Sjfvstruct i40e_aqc_switch_resource_alloc_element_resp { 751270346Sjfv u8 resource_type; 752270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VEB 0x0 753270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VSI 0x1 754270346Sjfv#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 755270346Sjfv#define I40E_AQ_RESOURCE_TYPE_STAG 0x3 756270346Sjfv#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 757270346Sjfv#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 758270346Sjfv#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 759270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 760270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 761270346Sjfv#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 762270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 763270346Sjfv#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 764270346Sjfv#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 765270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 766270346Sjfv#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 767270346Sjfv#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 768270346Sjfv#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 769270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 770270346Sjfv#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 771270346Sjfv u8 reserved1; 772270346Sjfv __le16 guaranteed; 773270346Sjfv __le16 total; 774270346Sjfv __le16 used; 775270346Sjfv __le16 total_unalloced; 776270346Sjfv u8 reserved2[6]; 777266423Sjfv}; 778266423Sjfv 779277082SjfvI40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 780277082Sjfv 781299549Serj/* Set Switch Configuration (direct 0x0205) */ 782299549Serjstruct i40e_aqc_set_switch_config { 783299549Serj __le16 flags; 784303967Ssbruno/* flags used for both fields below */ 785299549Serj#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 786299549Serj#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 787333343Serj#define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT 0x0004 788299549Serj __le16 valid_flags; 789333343Serj /* The ethertype in switch_tag is dropped on ingress and used 790333343Serj * internally by the switch. Set this to zero for the default 791333343Serj * of 0x88a8 (802.1ad). Should be zero for firmware API 792333343Serj * versions lower than 1.7. 793333343Serj */ 794333343Serj __le16 switch_tag; 795333343Serj /* The ethertypes in first_tag and second_tag are used to 796333343Serj * match the outer and inner VLAN tags (respectively) when HW 797333343Serj * double VLAN tagging is enabled via the set port parameters 798333343Serj * AQ command. Otherwise these are both ignored. Set them to 799333343Serj * zero for their defaults of 0x8100 (802.1Q). Should be zero 800333343Serj * for firmware API versions lower than 1.7. 801333343Serj */ 802333343Serj __le16 first_tag; 803333343Serj __le16 second_tag; 804333343Serj /* Next byte is split into following: 805333343Serj * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0 806333343Serj * Bit 6 : 0 : Destination Port, 1: source port 807333343Serj * Bit 5..4 : L4 type 808333343Serj * 0: rsvd 809333343Serj * 1: TCP 810333343Serj * 2: UDP 811333343Serj * 3: Both TCP and UDP 812333343Serj * Bits 3:0 Mode 813333343Serj * 0: default mode 814333343Serj * 1: L4 port only mode 815333343Serj * 2: non-tunneled mode 816333343Serj * 3: tunneled mode 817333343Serj */ 818333343Serj#define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80 819333343Serj 820333343Serj#define I40E_AQ_SET_SWITCH_L4_SRC_PORT 0x40 821333343Serj 822333343Serj#define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD 0x00 823333343Serj#define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10 824333343Serj#define I40E_AQ_SET_SWITCH_L4_TYPE_UDP 0x20 825333343Serj#define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH 0x30 826333343Serj 827333343Serj#define I40E_AQ_SET_SWITCH_MODE_DEFAULT 0x00 828333343Serj#define I40E_AQ_SET_SWITCH_MODE_L4_PORT 0x01 829333343Serj#define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02 830333343Serj#define I40E_AQ_SET_SWITCH_MODE_TUNNEL 0x03 831333343Serj u8 mode; 832333343Serj u8 rsvd5[5]; 833299549Serj}; 834299549Serj 835299549SerjI40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 836299549Serj 837299555Serj/* Read Receive control registers (direct 0x0206) 838299555Serj * Write Receive control registers (direct 0x0207) 839299555Serj * used for accessing Rx control registers that can be 840299555Serj * slow and need special handling when under high Rx load 841299555Serj */ 842299555Serjstruct i40e_aqc_rx_ctl_reg_read_write { 843299555Serj __le32 reserved1; 844299555Serj __le32 address; 845299555Serj __le32 reserved2; 846299555Serj __le32 value; 847299555Serj}; 848299555Serj 849299555SerjI40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 850299555Serj 851266423Sjfv/* Add VSI (indirect 0x0210) 852266423Sjfv * this indirect command uses struct i40e_aqc_vsi_properties_data 853266423Sjfv * as the indirect buffer (128 bytes) 854266423Sjfv * 855266423Sjfv * Update VSI (indirect 0x211) 856266423Sjfv * uses the same data structure as Add VSI 857266423Sjfv * 858266423Sjfv * Get VSI (indirect 0x0212) 859266423Sjfv * uses the same completion and data structure as Add VSI 860266423Sjfv */ 861266423Sjfvstruct i40e_aqc_add_get_update_vsi { 862270346Sjfv __le16 uplink_seid; 863270346Sjfv u8 connection_type; 864270346Sjfv#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 865270346Sjfv#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 866270346Sjfv#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 867270346Sjfv u8 reserved1; 868270346Sjfv u8 vf_id; 869270346Sjfv u8 reserved2; 870270346Sjfv __le16 vsi_flags; 871270346Sjfv#define I40E_AQ_VSI_TYPE_SHIFT 0x0 872270346Sjfv#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 873270346Sjfv#define I40E_AQ_VSI_TYPE_VF 0x0 874270346Sjfv#define I40E_AQ_VSI_TYPE_VMDQ2 0x1 875270346Sjfv#define I40E_AQ_VSI_TYPE_PF 0x2 876270346Sjfv#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 877270346Sjfv#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 878270346Sjfv __le32 addr_high; 879270346Sjfv __le32 addr_low; 880266423Sjfv}; 881266423Sjfv 882266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 883266423Sjfv 884266423Sjfvstruct i40e_aqc_add_get_update_vsi_completion { 885266423Sjfv __le16 seid; 886266423Sjfv __le16 vsi_number; 887266423Sjfv __le16 vsi_used; 888266423Sjfv __le16 vsi_free; 889266423Sjfv __le32 addr_high; 890266423Sjfv __le32 addr_low; 891266423Sjfv}; 892266423Sjfv 893266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 894266423Sjfv 895266423Sjfvstruct i40e_aqc_vsi_properties_data { 896266423Sjfv /* first 96 byte are written by SW */ 897270346Sjfv __le16 valid_sections; 898270346Sjfv#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 899270346Sjfv#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 900270346Sjfv#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 901270346Sjfv#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 902270346Sjfv#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 903270346Sjfv#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 904270346Sjfv#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 905270346Sjfv#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 906270346Sjfv#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 907270346Sjfv#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 908266423Sjfv /* switch section */ 909270346Sjfv __le16 switch_id; /* 12bit id combined with flags below */ 910270346Sjfv#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 911270346Sjfv#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 912270346Sjfv#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 913270346Sjfv#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 914270346Sjfv#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 915270346Sjfv u8 sw_reserved[2]; 916266423Sjfv /* security section */ 917270346Sjfv u8 sec_flags; 918270346Sjfv#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 919270346Sjfv#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 920270346Sjfv#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 921270346Sjfv u8 sec_reserved; 922266423Sjfv /* VLAN section */ 923270346Sjfv __le16 pvid; /* VLANS include priority bits */ 924270346Sjfv __le16 fcoe_pvid; 925270346Sjfv u8 port_vlan_flags; 926270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 927270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 928270346Sjfv I40E_AQ_VSI_PVLAN_MODE_SHIFT) 929270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 930270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 931270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 932270346Sjfv#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 933270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 934270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 935270346Sjfv I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 936270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 937270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 938270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 939270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 940270346Sjfv u8 pvlan_reserved[3]; 941266423Sjfv /* ingress egress up sections */ 942270346Sjfv __le32 ingress_table; /* bitmap, 3 bits per up */ 943270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 944270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 945270346Sjfv I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 946270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 947270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 948270346Sjfv I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 949270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 950270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 951270346Sjfv I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 952270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 953270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 954270346Sjfv I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 955270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 956270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 957270346Sjfv I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 958270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 959270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 960270346Sjfv I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 961270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 962270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 963270346Sjfv I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 964270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 965270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 966270346Sjfv I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 967270346Sjfv __le32 egress_table; /* same defines as for ingress table */ 968266423Sjfv /* cascaded PV section */ 969270346Sjfv __le16 cas_pv_tag; 970270346Sjfv u8 cas_pv_flags; 971270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 972270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 973270346Sjfv I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 974270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 975270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 976270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 977270346Sjfv#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 978270346Sjfv#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 979270346Sjfv#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 980270346Sjfv u8 cas_pv_reserved; 981266423Sjfv /* queue mapping section */ 982270346Sjfv __le16 mapping_flags; 983270346Sjfv#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 984270346Sjfv#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 985270346Sjfv __le16 queue_mapping[16]; 986270346Sjfv#define I40E_AQ_VSI_QUEUE_SHIFT 0x0 987270346Sjfv#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 988270346Sjfv __le16 tc_mapping[8]; 989270346Sjfv#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 990270346Sjfv#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 991270346Sjfv I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 992270346Sjfv#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 993270346Sjfv#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 994270346Sjfv I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 995266423Sjfv /* queueing option section */ 996270346Sjfv u8 queueing_opt_flags; 997303967Ssbruno#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 998303967Ssbruno#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 999270346Sjfv#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 1000270346Sjfv#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 1001303967Ssbruno#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 1002303967Ssbruno#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 1003270346Sjfv u8 queueing_opt_reserved[3]; 1004266423Sjfv /* scheduler section */ 1005270346Sjfv u8 up_enable_bits; 1006270346Sjfv u8 sched_reserved; 1007266423Sjfv /* outer up section */ 1008299555Serj __le32 outer_up_table; /* same structure and defines as ingress tbl */ 1009270346Sjfv u8 cmd_reserved[8]; 1010266423Sjfv /* last 32 bytes are written by FW */ 1011270346Sjfv __le16 qs_handle[8]; 1012266423Sjfv#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 1013270346Sjfv __le16 stat_counter_idx; 1014270346Sjfv __le16 sched_id; 1015270346Sjfv u8 resp_reserved[12]; 1016266423Sjfv}; 1017266423Sjfv 1018266423SjfvI40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 1019266423Sjfv 1020266423Sjfv/* Add Port Virtualizer (direct 0x0220) 1021266423Sjfv * also used for update PV (direct 0x0221) but only flags are used 1022266423Sjfv * (IS_CTRL_PORT only works on add PV) 1023266423Sjfv */ 1024266423Sjfvstruct i40e_aqc_add_update_pv { 1025270346Sjfv __le16 command_flags; 1026270346Sjfv#define I40E_AQC_PV_FLAG_PV_TYPE 0x1 1027270346Sjfv#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 1028270346Sjfv#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 1029270346Sjfv#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 1030270346Sjfv __le16 uplink_seid; 1031270346Sjfv __le16 connected_seid; 1032270346Sjfv u8 reserved[10]; 1033266423Sjfv}; 1034266423Sjfv 1035266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 1036266423Sjfv 1037266423Sjfvstruct i40e_aqc_add_update_pv_completion { 1038266423Sjfv /* reserved for update; for add also encodes error if rc == ENOSPC */ 1039270346Sjfv __le16 pv_seid; 1040270346Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 1041270346Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 1042270346Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 1043270346Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 1044270346Sjfv u8 reserved[14]; 1045266423Sjfv}; 1046266423Sjfv 1047266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 1048266423Sjfv 1049266423Sjfv/* Get PV Params (direct 0x0222) 1050266423Sjfv * uses i40e_aqc_switch_seid for the descriptor 1051266423Sjfv */ 1052266423Sjfv 1053266423Sjfvstruct i40e_aqc_get_pv_params_completion { 1054270346Sjfv __le16 seid; 1055270346Sjfv __le16 default_stag; 1056270346Sjfv __le16 pv_flags; /* same flags as add_pv */ 1057270346Sjfv#define I40E_AQC_GET_PV_PV_TYPE 0x1 1058270346Sjfv#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 1059270346Sjfv#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 1060270346Sjfv u8 reserved[8]; 1061270346Sjfv __le16 default_port_seid; 1062266423Sjfv}; 1063266423Sjfv 1064266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 1065266423Sjfv 1066266423Sjfv/* Add VEB (direct 0x0230) */ 1067266423Sjfvstruct i40e_aqc_add_veb { 1068270346Sjfv __le16 uplink_seid; 1069270346Sjfv __le16 downlink_seid; 1070270346Sjfv __le16 veb_flags; 1071270346Sjfv#define I40E_AQC_ADD_VEB_FLOATING 0x1 1072270346Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 1073270346Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 1074266423Sjfv I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 1075270346Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 1076270346Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 1077299549Serj#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 1078299549Serj#define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 1079270346Sjfv u8 enable_tcs; 1080270346Sjfv u8 reserved[9]; 1081266423Sjfv}; 1082266423Sjfv 1083266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 1084266423Sjfv 1085266423Sjfvstruct i40e_aqc_add_veb_completion { 1086270346Sjfv u8 reserved[6]; 1087270346Sjfv __le16 switch_seid; 1088266423Sjfv /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 1089270346Sjfv __le16 veb_seid; 1090270346Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 1091270346Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 1092270346Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 1093270346Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 1094270346Sjfv __le16 statistic_index; 1095270346Sjfv __le16 vebs_used; 1096270346Sjfv __le16 vebs_free; 1097266423Sjfv}; 1098266423Sjfv 1099266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 1100266423Sjfv 1101266423Sjfv/* Get VEB Parameters (direct 0x0232) 1102266423Sjfv * uses i40e_aqc_switch_seid for the descriptor 1103266423Sjfv */ 1104266423Sjfvstruct i40e_aqc_get_veb_parameters_completion { 1105270346Sjfv __le16 seid; 1106270346Sjfv __le16 switch_id; 1107270346Sjfv __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 1108270346Sjfv __le16 statistic_index; 1109270346Sjfv __le16 vebs_used; 1110270346Sjfv __le16 vebs_free; 1111270346Sjfv u8 reserved[4]; 1112266423Sjfv}; 1113266423Sjfv 1114266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 1115266423Sjfv 1116266423Sjfv/* Delete Element (direct 0x0243) 1117266423Sjfv * uses the generic i40e_aqc_switch_seid 1118266423Sjfv */ 1119266423Sjfv 1120266423Sjfv/* Add MAC-VLAN (indirect 0x0250) */ 1121266423Sjfv 1122266423Sjfv/* used for the command for most vlan commands */ 1123266423Sjfvstruct i40e_aqc_macvlan { 1124270346Sjfv __le16 num_addresses; 1125270346Sjfv __le16 seid[3]; 1126270346Sjfv#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 1127270346Sjfv#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 1128266423Sjfv I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1129270346Sjfv#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 1130270346Sjfv __le32 addr_high; 1131270346Sjfv __le32 addr_low; 1132266423Sjfv}; 1133266423Sjfv 1134266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 1135266423Sjfv 1136266423Sjfv/* indirect data for command and response */ 1137266423Sjfvstruct i40e_aqc_add_macvlan_element_data { 1138270346Sjfv u8 mac_addr[6]; 1139270346Sjfv __le16 vlan_tag; 1140270346Sjfv __le16 flags; 1141270346Sjfv#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 1142270346Sjfv#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 1143270346Sjfv#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 1144270346Sjfv#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 1145299549Serj#define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 1146270346Sjfv __le16 queue_number; 1147270346Sjfv#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 1148270346Sjfv#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 1149266423Sjfv I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1150266423Sjfv /* response section */ 1151270346Sjfv u8 match_method; 1152270346Sjfv#define I40E_AQC_MM_PERFECT_MATCH 0x01 1153270346Sjfv#define I40E_AQC_MM_HASH_MATCH 0x02 1154270346Sjfv#define I40E_AQC_MM_ERR_NO_RES 0xFF 1155270346Sjfv u8 reserved1[3]; 1156266423Sjfv}; 1157266423Sjfv 1158266423Sjfvstruct i40e_aqc_add_remove_macvlan_completion { 1159266423Sjfv __le16 perfect_mac_used; 1160266423Sjfv __le16 perfect_mac_free; 1161266423Sjfv __le16 unicast_hash_free; 1162266423Sjfv __le16 multicast_hash_free; 1163266423Sjfv __le32 addr_high; 1164266423Sjfv __le32 addr_low; 1165266423Sjfv}; 1166266423Sjfv 1167266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1168266423Sjfv 1169266423Sjfv/* Remove MAC-VLAN (indirect 0x0251) 1170266423Sjfv * uses i40e_aqc_macvlan for the descriptor 1171266423Sjfv * data points to an array of num_addresses of elements 1172266423Sjfv */ 1173266423Sjfv 1174266423Sjfvstruct i40e_aqc_remove_macvlan_element_data { 1175270346Sjfv u8 mac_addr[6]; 1176270346Sjfv __le16 vlan_tag; 1177270346Sjfv u8 flags; 1178270346Sjfv#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1179270346Sjfv#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1180270346Sjfv#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1181270346Sjfv#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1182270346Sjfv u8 reserved[3]; 1183266423Sjfv /* reply section */ 1184270346Sjfv u8 error_code; 1185270346Sjfv#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1186270346Sjfv#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1187270346Sjfv u8 reply_reserved[3]; 1188266423Sjfv}; 1189266423Sjfv 1190266423Sjfv/* Add VLAN (indirect 0x0252) 1191266423Sjfv * Remove VLAN (indirect 0x0253) 1192266423Sjfv * use the generic i40e_aqc_macvlan for the command 1193266423Sjfv */ 1194266423Sjfvstruct i40e_aqc_add_remove_vlan_element_data { 1195270346Sjfv __le16 vlan_tag; 1196270346Sjfv u8 vlan_flags; 1197266423Sjfv/* flags for add VLAN */ 1198270346Sjfv#define I40E_AQC_ADD_VLAN_LOCAL 0x1 1199270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1200270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1201270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1202270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1203270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1204270346Sjfv#define I40E_AQC_VLAN_PTYPE_SHIFT 3 1205270346Sjfv#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1206270346Sjfv#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1207270346Sjfv#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1208270346Sjfv#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1209270346Sjfv#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1210266423Sjfv/* flags for remove VLAN */ 1211270346Sjfv#define I40E_AQC_REMOVE_VLAN_ALL 0x1 1212270346Sjfv u8 reserved; 1213270346Sjfv u8 result; 1214266423Sjfv/* flags for add VLAN */ 1215270346Sjfv#define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1216270346Sjfv#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1217270346Sjfv#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1218266423Sjfv/* flags for remove VLAN */ 1219270346Sjfv#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1220270346Sjfv#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1221270346Sjfv u8 reserved1[3]; 1222266423Sjfv}; 1223266423Sjfv 1224266423Sjfvstruct i40e_aqc_add_remove_vlan_completion { 1225270346Sjfv u8 reserved[4]; 1226270346Sjfv __le16 vlans_used; 1227270346Sjfv __le16 vlans_free; 1228270346Sjfv __le32 addr_high; 1229270346Sjfv __le32 addr_low; 1230266423Sjfv}; 1231266423Sjfv 1232266423Sjfv/* Set VSI Promiscuous Modes (direct 0x0254) */ 1233266423Sjfvstruct i40e_aqc_set_vsi_promiscuous_modes { 1234270346Sjfv __le16 promiscuous_flags; 1235270346Sjfv __le16 valid_flags; 1236266423Sjfv/* flags used for both fields above */ 1237270346Sjfv#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1238270346Sjfv#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1239270346Sjfv#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1240270346Sjfv#define I40E_AQC_SET_VSI_DEFAULT 0x08 1241270346Sjfv#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1242299554Serj#define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 1243270346Sjfv __le16 seid; 1244270346Sjfv#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1245270346Sjfv __le16 vlan_tag; 1246284049Sjfv#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1247270346Sjfv#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1248270346Sjfv u8 reserved[8]; 1249266423Sjfv}; 1250266423Sjfv 1251266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1252266423Sjfv 1253266423Sjfv/* Add S/E-tag command (direct 0x0255) 1254266423Sjfv * Uses generic i40e_aqc_add_remove_tag_completion for completion 1255266423Sjfv */ 1256266423Sjfvstruct i40e_aqc_add_tag { 1257270346Sjfv __le16 flags; 1258270346Sjfv#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1259270346Sjfv __le16 seid; 1260270346Sjfv#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1261270346Sjfv#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1262266423Sjfv I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1263270346Sjfv __le16 tag; 1264270346Sjfv __le16 queue_number; 1265270346Sjfv u8 reserved[8]; 1266266423Sjfv}; 1267266423Sjfv 1268266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1269266423Sjfv 1270266423Sjfvstruct i40e_aqc_add_remove_tag_completion { 1271270346Sjfv u8 reserved[12]; 1272270346Sjfv __le16 tags_used; 1273270346Sjfv __le16 tags_free; 1274266423Sjfv}; 1275266423Sjfv 1276266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1277266423Sjfv 1278266423Sjfv/* Remove S/E-tag command (direct 0x0256) 1279266423Sjfv * Uses generic i40e_aqc_add_remove_tag_completion for completion 1280266423Sjfv */ 1281266423Sjfvstruct i40e_aqc_remove_tag { 1282270346Sjfv __le16 seid; 1283270346Sjfv#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1284270346Sjfv#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1285266423Sjfv I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1286270346Sjfv __le16 tag; 1287270346Sjfv u8 reserved[12]; 1288266423Sjfv}; 1289266423Sjfv 1290277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1291277082Sjfv 1292266423Sjfv/* Add multicast E-Tag (direct 0x0257) 1293266423Sjfv * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1294266423Sjfv * and no external data 1295266423Sjfv */ 1296266423Sjfvstruct i40e_aqc_add_remove_mcast_etag { 1297270346Sjfv __le16 pv_seid; 1298270346Sjfv __le16 etag; 1299270346Sjfv u8 num_unicast_etags; 1300270346Sjfv u8 reserved[3]; 1301270346Sjfv __le32 addr_high; /* address of array of 2-byte s-tags */ 1302270346Sjfv __le32 addr_low; 1303266423Sjfv}; 1304266423Sjfv 1305266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1306266423Sjfv 1307266423Sjfvstruct i40e_aqc_add_remove_mcast_etag_completion { 1308270346Sjfv u8 reserved[4]; 1309270346Sjfv __le16 mcast_etags_used; 1310270346Sjfv __le16 mcast_etags_free; 1311270346Sjfv __le32 addr_high; 1312270346Sjfv __le32 addr_low; 1313266423Sjfv 1314266423Sjfv}; 1315266423Sjfv 1316266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1317266423Sjfv 1318266423Sjfv/* Update S/E-Tag (direct 0x0259) */ 1319266423Sjfvstruct i40e_aqc_update_tag { 1320270346Sjfv __le16 seid; 1321270346Sjfv#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1322270346Sjfv#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1323266423Sjfv I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1324270346Sjfv __le16 old_tag; 1325270346Sjfv __le16 new_tag; 1326270346Sjfv u8 reserved[10]; 1327266423Sjfv}; 1328266423Sjfv 1329266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1330266423Sjfv 1331266423Sjfvstruct i40e_aqc_update_tag_completion { 1332270346Sjfv u8 reserved[12]; 1333270346Sjfv __le16 tags_used; 1334270346Sjfv __le16 tags_free; 1335266423Sjfv}; 1336266423Sjfv 1337266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1338266423Sjfv 1339266423Sjfv/* Add Control Packet filter (direct 0x025A) 1340266423Sjfv * Remove Control Packet filter (direct 0x025B) 1341266423Sjfv * uses the i40e_aqc_add_oveb_cloud, 1342266423Sjfv * and the generic direct completion structure 1343266423Sjfv */ 1344266423Sjfvstruct i40e_aqc_add_remove_control_packet_filter { 1345270346Sjfv u8 mac[6]; 1346270346Sjfv __le16 etype; 1347270346Sjfv __le16 flags; 1348270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1349270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1350270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1351270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1352270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1353270346Sjfv __le16 seid; 1354270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1355270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1356266423Sjfv I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1357270346Sjfv __le16 queue; 1358270346Sjfv u8 reserved[2]; 1359266423Sjfv}; 1360266423Sjfv 1361266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1362266423Sjfv 1363266423Sjfvstruct i40e_aqc_add_remove_control_packet_filter_completion { 1364270346Sjfv __le16 mac_etype_used; 1365270346Sjfv __le16 etype_used; 1366270346Sjfv __le16 mac_etype_free; 1367270346Sjfv __le16 etype_free; 1368270346Sjfv u8 reserved[8]; 1369266423Sjfv}; 1370266423Sjfv 1371266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1372266423Sjfv 1373266423Sjfv/* Add Cloud filters (indirect 0x025C) 1374266423Sjfv * Remove Cloud filters (indirect 0x025D) 1375266423Sjfv * uses the i40e_aqc_add_remove_cloud_filters, 1376266423Sjfv * and the generic indirect completion structure 1377266423Sjfv */ 1378266423Sjfvstruct i40e_aqc_add_remove_cloud_filters { 1379270346Sjfv u8 num_filters; 1380270346Sjfv u8 reserved; 1381270346Sjfv __le16 seid; 1382270346Sjfv#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1383270346Sjfv#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1384266423Sjfv I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1385270346Sjfv u8 reserved2[4]; 1386270346Sjfv __le32 addr_high; 1387270346Sjfv __le32 addr_low; 1388266423Sjfv}; 1389266423Sjfv 1390266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1391266423Sjfv 1392266423Sjfvstruct i40e_aqc_add_remove_cloud_filters_element_data { 1393270346Sjfv u8 outer_mac[6]; 1394270346Sjfv u8 inner_mac[6]; 1395270346Sjfv __le16 inner_vlan; 1396266423Sjfv union { 1397266423Sjfv struct { 1398266423Sjfv u8 reserved[12]; 1399266423Sjfv u8 data[4]; 1400266423Sjfv } v4; 1401266423Sjfv struct { 1402266423Sjfv u8 data[16]; 1403266423Sjfv } v6; 1404266423Sjfv } ipaddr; 1405270346Sjfv __le16 flags; 1406270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1407277082Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1408266423Sjfv I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1409266423Sjfv/* 0x0000 reserved */ 1410270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1411266423Sjfv/* 0x0002 reserved */ 1412270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1413270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1414266423Sjfv/* 0x0005 reserved */ 1415270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1416266423Sjfv/* 0x0007 reserved */ 1417266423Sjfv/* 0x0008 reserved */ 1418270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1419270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1420270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1421270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1422266423Sjfv 1423270346Sjfv#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1424270346Sjfv#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1425270346Sjfv#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1426270346Sjfv#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1427270346Sjfv#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1428266423Sjfv 1429270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1430270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1431299549Serj#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1432270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1433299549Serj#define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1434270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1435299549Serj#define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1436299549Serj#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1437266423Sjfv 1438299549Serj#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1439299549Serj#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1440299549Serj#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1441299549Serj 1442270346Sjfv __le32 tenant_id; 1443270346Sjfv u8 reserved[4]; 1444270346Sjfv __le16 queue_number; 1445270346Sjfv#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1446277082Sjfv#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1447270346Sjfv I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1448270346Sjfv u8 reserved2[14]; 1449266423Sjfv /* response section */ 1450270346Sjfv u8 allocation_result; 1451270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1452270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1453270346Sjfv u8 response_reserved[7]; 1454266423Sjfv}; 1455266423Sjfv 1456266423Sjfvstruct i40e_aqc_remove_cloud_filters_completion { 1457266423Sjfv __le16 perfect_ovlan_used; 1458266423Sjfv __le16 perfect_ovlan_free; 1459266423Sjfv __le16 vlan_used; 1460266423Sjfv __le16 vlan_free; 1461266423Sjfv __le32 addr_high; 1462266423Sjfv __le32 addr_low; 1463266423Sjfv}; 1464266423Sjfv 1465266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1466266423Sjfv 1467266423Sjfv/* Add Mirror Rule (indirect or direct 0x0260) 1468266423Sjfv * Delete Mirror Rule (indirect or direct 0x0261) 1469266423Sjfv * note: some rule types (4,5) do not use an external buffer. 1470266423Sjfv * take care to set the flags correctly. 1471266423Sjfv */ 1472266423Sjfvstruct i40e_aqc_add_delete_mirror_rule { 1473266423Sjfv __le16 seid; 1474266423Sjfv __le16 rule_type; 1475270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1476270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1477266423Sjfv I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1478270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1479270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1480270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1481270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1482270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1483266423Sjfv __le16 num_entries; 1484266423Sjfv __le16 destination; /* VSI for add, rule id for delete */ 1485266423Sjfv __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1486266423Sjfv __le32 addr_low; 1487266423Sjfv}; 1488266423Sjfv 1489266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1490266423Sjfv 1491266423Sjfvstruct i40e_aqc_add_delete_mirror_rule_completion { 1492270346Sjfv u8 reserved[2]; 1493270346Sjfv __le16 rule_id; /* only used on add */ 1494270346Sjfv __le16 mirror_rules_used; 1495270346Sjfv __le16 mirror_rules_free; 1496270346Sjfv __le32 addr_high; 1497270346Sjfv __le32 addr_low; 1498266423Sjfv}; 1499266423Sjfv 1500266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1501266423Sjfv 1502266423Sjfv/* DCB 0x03xx*/ 1503266423Sjfv 1504266423Sjfv/* PFC Ignore (direct 0x0301) 1505266423Sjfv * the command and response use the same descriptor structure 1506266423Sjfv */ 1507266423Sjfvstruct i40e_aqc_pfc_ignore { 1508270346Sjfv u8 tc_bitmap; 1509270346Sjfv u8 command_flags; /* unused on response */ 1510270346Sjfv#define I40E_AQC_PFC_IGNORE_SET 0x80 1511270346Sjfv#define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1512270346Sjfv u8 reserved[14]; 1513266423Sjfv}; 1514266423Sjfv 1515266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1516266423Sjfv 1517266423Sjfv/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1518266423Sjfv * with no parameters 1519266423Sjfv */ 1520266423Sjfv 1521266423Sjfv/* TX scheduler 0x04xx */ 1522266423Sjfv 1523266423Sjfv/* Almost all the indirect commands use 1524266423Sjfv * this generic struct to pass the SEID in param0 1525266423Sjfv */ 1526266423Sjfvstruct i40e_aqc_tx_sched_ind { 1527270346Sjfv __le16 vsi_seid; 1528270346Sjfv u8 reserved[6]; 1529270346Sjfv __le32 addr_high; 1530270346Sjfv __le32 addr_low; 1531266423Sjfv}; 1532266423Sjfv 1533266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1534266423Sjfv 1535266423Sjfv/* Several commands respond with a set of queue set handles */ 1536266423Sjfvstruct i40e_aqc_qs_handles_resp { 1537266423Sjfv __le16 qs_handles[8]; 1538266423Sjfv}; 1539266423Sjfv 1540266423Sjfv/* Configure VSI BW limits (direct 0x0400) */ 1541266423Sjfvstruct i40e_aqc_configure_vsi_bw_limit { 1542270346Sjfv __le16 vsi_seid; 1543270346Sjfv u8 reserved[2]; 1544270346Sjfv __le16 credit; 1545270346Sjfv u8 reserved1[2]; 1546270346Sjfv u8 max_credit; /* 0-3, limit = 2^max */ 1547270346Sjfv u8 reserved2[7]; 1548266423Sjfv}; 1549266423Sjfv 1550266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1551266423Sjfv 1552266423Sjfv/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1553266423Sjfv * responds with i40e_aqc_qs_handles_resp 1554266423Sjfv */ 1555266423Sjfvstruct i40e_aqc_configure_vsi_ets_sla_bw_data { 1556270346Sjfv u8 tc_valid_bits; 1557270346Sjfv u8 reserved[15]; 1558270346Sjfv __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1559266423Sjfv 1560266423Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1561270346Sjfv __le16 tc_bw_max[2]; 1562270346Sjfv u8 reserved1[28]; 1563266423Sjfv}; 1564266423Sjfv 1565277082SjfvI40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1566277082Sjfv 1567266423Sjfv/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1568266423Sjfv * responds with i40e_aqc_qs_handles_resp 1569266423Sjfv */ 1570266423Sjfvstruct i40e_aqc_configure_vsi_tc_bw_data { 1571270346Sjfv u8 tc_valid_bits; 1572270346Sjfv u8 reserved[3]; 1573270346Sjfv u8 tc_bw_credits[8]; 1574270346Sjfv u8 reserved1[4]; 1575270346Sjfv __le16 qs_handles[8]; 1576266423Sjfv}; 1577266423Sjfv 1578277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1579277082Sjfv 1580266423Sjfv/* Query vsi bw configuration (indirect 0x0408) */ 1581266423Sjfvstruct i40e_aqc_query_vsi_bw_config_resp { 1582270346Sjfv u8 tc_valid_bits; 1583270346Sjfv u8 tc_suspended_bits; 1584270346Sjfv u8 reserved[14]; 1585270346Sjfv __le16 qs_handles[8]; 1586270346Sjfv u8 reserved1[4]; 1587270346Sjfv __le16 port_bw_limit; 1588270346Sjfv u8 reserved2[2]; 1589270346Sjfv u8 max_bw; /* 0-3, limit = 2^max */ 1590270346Sjfv u8 reserved3[23]; 1591266423Sjfv}; 1592266423Sjfv 1593277082SjfvI40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1594277082Sjfv 1595266423Sjfv/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1596266423Sjfvstruct i40e_aqc_query_vsi_ets_sla_config_resp { 1597270346Sjfv u8 tc_valid_bits; 1598270346Sjfv u8 reserved[3]; 1599270346Sjfv u8 share_credits[8]; 1600270346Sjfv __le16 credits[8]; 1601266423Sjfv 1602266423Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1603270346Sjfv __le16 tc_bw_max[2]; 1604266423Sjfv}; 1605266423Sjfv 1606277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1607277082Sjfv 1608266423Sjfv/* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1609266423Sjfvstruct i40e_aqc_configure_switching_comp_bw_limit { 1610270346Sjfv __le16 seid; 1611270346Sjfv u8 reserved[2]; 1612270346Sjfv __le16 credit; 1613270346Sjfv u8 reserved1[2]; 1614270346Sjfv u8 max_bw; /* 0-3, limit = 2^max */ 1615270346Sjfv u8 reserved2[7]; 1616266423Sjfv}; 1617266423Sjfv 1618266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1619266423Sjfv 1620266423Sjfv/* Enable Physical Port ETS (indirect 0x0413) 1621266423Sjfv * Modify Physical Port ETS (indirect 0x0414) 1622266423Sjfv * Disable Physical Port ETS (indirect 0x0415) 1623266423Sjfv */ 1624266423Sjfvstruct i40e_aqc_configure_switching_comp_ets_data { 1625270346Sjfv u8 reserved[4]; 1626270346Sjfv u8 tc_valid_bits; 1627270346Sjfv u8 seepage; 1628270346Sjfv#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1629270346Sjfv u8 tc_strict_priority_flags; 1630270346Sjfv u8 reserved1[17]; 1631270346Sjfv u8 tc_bw_share_credits[8]; 1632270346Sjfv u8 reserved2[96]; 1633266423Sjfv}; 1634266423Sjfv 1635277082SjfvI40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1636277082Sjfv 1637266423Sjfv/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1638266423Sjfvstruct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1639270346Sjfv u8 tc_valid_bits; 1640270346Sjfv u8 reserved[15]; 1641270346Sjfv __le16 tc_bw_credit[8]; 1642266423Sjfv 1643266423Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1644270346Sjfv __le16 tc_bw_max[2]; 1645270346Sjfv u8 reserved1[28]; 1646266423Sjfv}; 1647266423Sjfv 1648299555SerjI40E_CHECK_STRUCT_LEN(0x40, 1649299555Serj i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1650277082Sjfv 1651266423Sjfv/* Configure Switching Component Bandwidth Allocation per Tc 1652266423Sjfv * (indirect 0x0417) 1653266423Sjfv */ 1654266423Sjfvstruct i40e_aqc_configure_switching_comp_bw_config_data { 1655270346Sjfv u8 tc_valid_bits; 1656270346Sjfv u8 reserved[2]; 1657270346Sjfv u8 absolute_credits; /* bool */ 1658270346Sjfv u8 tc_bw_share_credits[8]; 1659270346Sjfv u8 reserved1[20]; 1660266423Sjfv}; 1661266423Sjfv 1662277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1663277082Sjfv 1664266423Sjfv/* Query Switching Component Configuration (indirect 0x0418) */ 1665266423Sjfvstruct i40e_aqc_query_switching_comp_ets_config_resp { 1666270346Sjfv u8 tc_valid_bits; 1667270346Sjfv u8 reserved[35]; 1668270346Sjfv __le16 port_bw_limit; 1669270346Sjfv u8 reserved1[2]; 1670270346Sjfv u8 tc_bw_max; /* 0-3, limit = 2^max */ 1671270346Sjfv u8 reserved2[23]; 1672266423Sjfv}; 1673266423Sjfv 1674277082SjfvI40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1675277082Sjfv 1676266423Sjfv/* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1677266423Sjfvstruct i40e_aqc_query_port_ets_config_resp { 1678270346Sjfv u8 reserved[4]; 1679270346Sjfv u8 tc_valid_bits; 1680270346Sjfv u8 reserved1; 1681270346Sjfv u8 tc_strict_priority_bits; 1682270346Sjfv u8 reserved2; 1683270346Sjfv u8 tc_bw_share_credits[8]; 1684270346Sjfv __le16 tc_bw_limits[8]; 1685266423Sjfv 1686266423Sjfv /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1687270346Sjfv __le16 tc_bw_max[2]; 1688270346Sjfv u8 reserved3[32]; 1689266423Sjfv}; 1690266423Sjfv 1691277082SjfvI40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1692277082Sjfv 1693266423Sjfv/* Query Switching Component Bandwidth Allocation per Traffic Type 1694266423Sjfv * (indirect 0x041A) 1695266423Sjfv */ 1696266423Sjfvstruct i40e_aqc_query_switching_comp_bw_config_resp { 1697270346Sjfv u8 tc_valid_bits; 1698270346Sjfv u8 reserved[2]; 1699270346Sjfv u8 absolute_credits_enable; /* bool */ 1700270346Sjfv u8 tc_bw_share_credits[8]; 1701270346Sjfv __le16 tc_bw_limits[8]; 1702266423Sjfv 1703266423Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1704270346Sjfv __le16 tc_bw_max[2]; 1705266423Sjfv}; 1706266423Sjfv 1707277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1708277082Sjfv 1709266423Sjfv/* Suspend/resume port TX traffic 1710266423Sjfv * (direct 0x041B and 0x041C) uses the generic SEID struct 1711266423Sjfv */ 1712266423Sjfv 1713266423Sjfv/* Configure partition BW 1714266423Sjfv * (indirect 0x041D) 1715266423Sjfv */ 1716266423Sjfvstruct i40e_aqc_configure_partition_bw_data { 1717270346Sjfv __le16 pf_valid_bits; 1718270346Sjfv u8 min_bw[16]; /* guaranteed bandwidth */ 1719270346Sjfv u8 max_bw[16]; /* bandwidth limit */ 1720266423Sjfv}; 1721266423Sjfv 1722277082SjfvI40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1723277082Sjfv 1724266423Sjfv/* Get and set the active HMC resource profile and status. 1725266423Sjfv * (direct 0x0500) and (direct 0x0501) 1726266423Sjfv */ 1727266423Sjfvstruct i40e_aq_get_set_hmc_resource_profile { 1728270346Sjfv u8 pm_profile; 1729270346Sjfv u8 pe_vf_enabled; 1730270346Sjfv u8 reserved[14]; 1731266423Sjfv}; 1732266423Sjfv 1733266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1734266423Sjfv 1735266423Sjfvenum i40e_aq_hmc_profile { 1736303967Ssbruno /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1737270346Sjfv I40E_HMC_PROFILE_DEFAULT = 1, 1738270346Sjfv I40E_HMC_PROFILE_FAVOR_VF = 2, 1739270346Sjfv I40E_HMC_PROFILE_EQUAL = 3, 1740266423Sjfv}; 1741266423Sjfv 1742266423Sjfv/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1743266423Sjfv 1744266423Sjfv/* set in param0 for get phy abilities to report qualified modules */ 1745270346Sjfv#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1746270346Sjfv#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1747266423Sjfv 1748266423Sjfvenum i40e_aq_phy_type { 1749266423Sjfv I40E_PHY_TYPE_SGMII = 0x0, 1750266423Sjfv I40E_PHY_TYPE_1000BASE_KX = 0x1, 1751266423Sjfv I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1752266423Sjfv I40E_PHY_TYPE_10GBASE_KR = 0x3, 1753266423Sjfv I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1754266423Sjfv I40E_PHY_TYPE_XAUI = 0x5, 1755266423Sjfv I40E_PHY_TYPE_XFI = 0x6, 1756266423Sjfv I40E_PHY_TYPE_SFI = 0x7, 1757266423Sjfv I40E_PHY_TYPE_XLAUI = 0x8, 1758266423Sjfv I40E_PHY_TYPE_XLPPI = 0x9, 1759266423Sjfv I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1760266423Sjfv I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1761266423Sjfv I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1762266423Sjfv I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1763333343Serj I40E_PHY_TYPE_UNRECOGNIZED = 0xE, 1764333343Serj I40E_PHY_TYPE_UNSUPPORTED = 0xF, 1765266423Sjfv I40E_PHY_TYPE_100BASE_TX = 0x11, 1766266423Sjfv I40E_PHY_TYPE_1000BASE_T = 0x12, 1767266423Sjfv I40E_PHY_TYPE_10GBASE_T = 0x13, 1768266423Sjfv I40E_PHY_TYPE_10GBASE_SR = 0x14, 1769266423Sjfv I40E_PHY_TYPE_10GBASE_LR = 0x15, 1770266423Sjfv I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1771266423Sjfv I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1772266423Sjfv I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1773266423Sjfv I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1774266423Sjfv I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1775266423Sjfv I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1776266423Sjfv I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1777266423Sjfv I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1778266423Sjfv I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1779303967Ssbruno I40E_PHY_TYPE_25GBASE_KR = 0x1F, 1780303967Ssbruno I40E_PHY_TYPE_25GBASE_CR = 0x20, 1781303967Ssbruno I40E_PHY_TYPE_25GBASE_SR = 0x21, 1782303967Ssbruno I40E_PHY_TYPE_25GBASE_LR = 0x22, 1783333343Serj I40E_PHY_TYPE_25GBASE_AOC = 0x23, 1784333343Serj I40E_PHY_TYPE_25GBASE_ACC = 0x24, 1785333343Serj I40E_PHY_TYPE_MAX, 1786333343Serj I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD, 1787333343Serj I40E_PHY_TYPE_EMPTY = 0xFE, 1788333343Serj I40E_PHY_TYPE_DEFAULT = 0xFF, 1789266423Sjfv}; 1790266423Sjfv 1791333343Serj#define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \ 1792333343Serj BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \ 1793333343Serj BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \ 1794333343Serj BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \ 1795333343Serj BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \ 1796333343Serj BIT_ULL(I40E_PHY_TYPE_XAUI) | \ 1797333343Serj BIT_ULL(I40E_PHY_TYPE_XFI) | \ 1798333343Serj BIT_ULL(I40E_PHY_TYPE_SFI) | \ 1799333343Serj BIT_ULL(I40E_PHY_TYPE_XLAUI) | \ 1800333343Serj BIT_ULL(I40E_PHY_TYPE_XLPPI) | \ 1801333343Serj BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \ 1802333343Serj BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \ 1803333343Serj BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \ 1804333343Serj BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \ 1805333343Serj BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \ 1806333343Serj BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \ 1807333343Serj BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \ 1808333343Serj BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \ 1809333343Serj BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \ 1810333343Serj BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \ 1811333343Serj BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \ 1812333343Serj BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \ 1813333343Serj BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \ 1814333343Serj BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \ 1815333343Serj BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \ 1816333343Serj BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \ 1817333343Serj BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \ 1818333343Serj BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \ 1819333343Serj BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \ 1820333343Serj BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \ 1821333343Serj BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \ 1822333343Serj BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \ 1823333343Serj BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \ 1824333343Serj BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \ 1825333343Serj BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \ 1826333343Serj BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC)) 1827333343Serj 1828266423Sjfv#define I40E_LINK_SPEED_100MB_SHIFT 0x1 1829266423Sjfv#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1830266423Sjfv#define I40E_LINK_SPEED_10GB_SHIFT 0x3 1831266423Sjfv#define I40E_LINK_SPEED_40GB_SHIFT 0x4 1832266423Sjfv#define I40E_LINK_SPEED_20GB_SHIFT 0x5 1833303967Ssbruno#define I40E_LINK_SPEED_25GB_SHIFT 0x6 1834266423Sjfv 1835266423Sjfvenum i40e_aq_link_speed { 1836266423Sjfv I40E_LINK_SPEED_UNKNOWN = 0, 1837266423Sjfv I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1838266423Sjfv I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1839266423Sjfv I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1840266423Sjfv I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1841303967Ssbruno I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT), 1842303967Ssbruno I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT), 1843266423Sjfv}; 1844266423Sjfv 1845266423Sjfvstruct i40e_aqc_module_desc { 1846266423Sjfv u8 oui[3]; 1847266423Sjfv u8 reserved1; 1848266423Sjfv u8 part_number[16]; 1849266423Sjfv u8 revision[4]; 1850266423Sjfv u8 reserved2[8]; 1851266423Sjfv}; 1852266423Sjfv 1853277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1854277082Sjfv 1855266423Sjfvstruct i40e_aq_get_phy_abilities_resp { 1856270346Sjfv __le32 phy_type; /* bitmap using the above enum for offsets */ 1857270346Sjfv u8 link_speed; /* bitmap using the above enum bit patterns */ 1858270346Sjfv u8 abilities; 1859270346Sjfv#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1860270346Sjfv#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1861270346Sjfv#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1862270346Sjfv#define I40E_AQ_PHY_LINK_ENABLED 0x08 1863270346Sjfv#define I40E_AQ_PHY_AN_ENABLED 0x10 1864270346Sjfv#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1865318357Serj#define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 1866318357Serj#define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 1867270346Sjfv __le16 eee_capability; 1868270346Sjfv#define I40E_AQ_EEE_100BASE_TX 0x0002 1869270346Sjfv#define I40E_AQ_EEE_1000BASE_T 0x0004 1870270346Sjfv#define I40E_AQ_EEE_10GBASE_T 0x0008 1871270346Sjfv#define I40E_AQ_EEE_1000BASE_KX 0x0010 1872270346Sjfv#define I40E_AQ_EEE_10GBASE_KX4 0x0020 1873270346Sjfv#define I40E_AQ_EEE_10GBASE_KR 0x0040 1874270346Sjfv __le32 eeer_val; 1875270346Sjfv u8 d3_lpan; 1876270346Sjfv#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1877303967Ssbruno u8 phy_type_ext; 1878318357Serj#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01 1879318357Serj#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02 1880303967Ssbruno#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 1881303967Ssbruno#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 1882333343Serj#define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10 1883333343Serj#define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20 1884318357Serj u8 fec_cfg_curr_mod_ext_info; 1885318357Serj#define I40E_AQ_ENABLE_FEC_KR 0x01 1886318357Serj#define I40E_AQ_ENABLE_FEC_RS 0x02 1887318357Serj#define I40E_AQ_REQUEST_FEC_KR 0x04 1888318357Serj#define I40E_AQ_REQUEST_FEC_RS 0x08 1889318357Serj#define I40E_AQ_ENABLE_FEC_AUTO 0x10 1890318357Serj#define I40E_AQ_FEC 1891318357Serj#define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 1892318357Serj#define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5 1893318357Serj 1894303967Ssbruno u8 ext_comp_code; 1895270346Sjfv u8 phy_id[4]; 1896270346Sjfv u8 module_type[3]; 1897270346Sjfv u8 qualified_module_count; 1898270346Sjfv#define I40E_AQ_PHY_MAX_QMS 16 1899270346Sjfv struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1900266423Sjfv}; 1901266423Sjfv 1902277082SjfvI40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1903277082Sjfv 1904266423Sjfv/* Set PHY Config (direct 0x0601) */ 1905266423Sjfvstruct i40e_aq_set_phy_config { /* same bits as above in all */ 1906270346Sjfv __le32 phy_type; 1907270346Sjfv u8 link_speed; 1908270346Sjfv u8 abilities; 1909266423Sjfv/* bits 0-2 use the values from get_phy_abilities_resp */ 1910266423Sjfv#define I40E_AQ_PHY_ENABLE_LINK 0x08 1911266423Sjfv#define I40E_AQ_PHY_ENABLE_AN 0x10 1912266423Sjfv#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1913270346Sjfv __le16 eee_capability; 1914270346Sjfv __le32 eeer; 1915270346Sjfv u8 low_power_ctrl; 1916303967Ssbruno u8 phy_type_ext; 1917318357Serj u8 fec_config; 1918318357Serj#define I40E_AQ_SET_FEC_ABILITY_KR BIT(0) 1919318357Serj#define I40E_AQ_SET_FEC_ABILITY_RS BIT(1) 1920318357Serj#define I40E_AQ_SET_FEC_REQUEST_KR BIT(2) 1921318357Serj#define I40E_AQ_SET_FEC_REQUEST_RS BIT(3) 1922318357Serj#define I40E_AQ_SET_FEC_AUTO BIT(4) 1923318357Serj#define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0 1924318357Serj#define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT) 1925318357Serj u8 reserved; 1926266423Sjfv}; 1927266423Sjfv 1928266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1929266423Sjfv 1930266423Sjfv/* Set MAC Config command data structure (direct 0x0603) */ 1931266423Sjfvstruct i40e_aq_set_mac_config { 1932270346Sjfv __le16 max_frame_size; 1933270346Sjfv u8 params; 1934270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1935270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1936270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1937270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1938270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1939270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1940270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1941270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1942270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1943270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1944270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1945270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1946270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1947270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1948270346Sjfv u8 tx_timer_priority; /* bitmap */ 1949270346Sjfv __le16 tx_timer_value; 1950270346Sjfv __le16 fc_refresh_threshold; 1951270346Sjfv u8 reserved[8]; 1952266423Sjfv}; 1953266423Sjfv 1954266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1955266423Sjfv 1956266423Sjfv/* Restart Auto-Negotiation (direct 0x605) */ 1957266423Sjfvstruct i40e_aqc_set_link_restart_an { 1958270346Sjfv u8 command; 1959270346Sjfv#define I40E_AQ_PHY_RESTART_AN 0x02 1960270346Sjfv#define I40E_AQ_PHY_LINK_ENABLE 0x04 1961270346Sjfv u8 reserved[15]; 1962266423Sjfv}; 1963266423Sjfv 1964266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1965266423Sjfv 1966266423Sjfv/* Get Link Status cmd & response data structure (direct 0x0607) */ 1967266423Sjfvstruct i40e_aqc_get_link_status { 1968270346Sjfv __le16 command_flags; /* only field set on command */ 1969270346Sjfv#define I40E_AQ_LSE_MASK 0x3 1970270346Sjfv#define I40E_AQ_LSE_NOP 0x0 1971270346Sjfv#define I40E_AQ_LSE_DISABLE 0x2 1972270346Sjfv#define I40E_AQ_LSE_ENABLE 0x3 1973266423Sjfv/* only response uses this flag */ 1974270346Sjfv#define I40E_AQ_LSE_IS_ENABLED 0x1 1975270346Sjfv u8 phy_type; /* i40e_aq_phy_type */ 1976270346Sjfv u8 link_speed; /* i40e_aq_link_speed */ 1977270346Sjfv u8 link_info; 1978284049Sjfv#define I40E_AQ_LINK_UP 0x01 /* obsolete */ 1979284049Sjfv#define I40E_AQ_LINK_UP_FUNCTION 0x01 1980270346Sjfv#define I40E_AQ_LINK_FAULT 0x02 1981270346Sjfv#define I40E_AQ_LINK_FAULT_TX 0x04 1982270346Sjfv#define I40E_AQ_LINK_FAULT_RX 0x08 1983270346Sjfv#define I40E_AQ_LINK_FAULT_REMOTE 0x10 1984284049Sjfv#define I40E_AQ_LINK_UP_PORT 0x20 1985270346Sjfv#define I40E_AQ_MEDIA_AVAILABLE 0x40 1986270346Sjfv#define I40E_AQ_SIGNAL_DETECT 0x80 1987270346Sjfv u8 an_info; 1988270346Sjfv#define I40E_AQ_AN_COMPLETED 0x01 1989270346Sjfv#define I40E_AQ_LP_AN_ABILITY 0x02 1990270346Sjfv#define I40E_AQ_PD_FAULT 0x04 1991270346Sjfv#define I40E_AQ_FEC_EN 0x08 1992270346Sjfv#define I40E_AQ_PHY_LOW_POWER 0x10 1993270346Sjfv#define I40E_AQ_LINK_PAUSE_TX 0x20 1994270346Sjfv#define I40E_AQ_LINK_PAUSE_RX 0x40 1995270346Sjfv#define I40E_AQ_QUALIFIED_MODULE 0x80 1996270346Sjfv u8 ext_info; 1997270346Sjfv#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1998270346Sjfv#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1999270346Sjfv#define I40E_AQ_LINK_TX_SHIFT 0x02 2000270346Sjfv#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 2001270346Sjfv#define I40E_AQ_LINK_TX_ACTIVE 0x00 2002270346Sjfv#define I40E_AQ_LINK_TX_DRAINED 0x01 2003270346Sjfv#define I40E_AQ_LINK_TX_FLUSHED 0x03 2004270346Sjfv#define I40E_AQ_LINK_FORCED_40G 0x10 2005303967Ssbruno/* 25G Error Codes */ 2006303967Ssbruno#define I40E_AQ_25G_NO_ERR 0X00 2007303967Ssbruno#define I40E_AQ_25G_NOT_PRESENT 0X01 2008303967Ssbruno#define I40E_AQ_25G_NVM_CRC_ERR 0X02 2009303967Ssbruno#define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 2010303967Ssbruno#define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 2011303967Ssbruno#define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 2012270346Sjfv u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 2013333343Serj/* Since firmware API 1.7 loopback field keeps power class info as well */ 2014333343Serj#define I40E_AQ_LOOPBACK_MASK 0x07 2015333343Serj#define I40E_AQ_PWR_CLASS_SHIFT_LB 6 2016333343Serj#define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB) 2017270346Sjfv __le16 max_frame_size; 2018270346Sjfv u8 config; 2019318357Serj#define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 2020318357Serj#define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 2021270346Sjfv#define I40E_AQ_CONFIG_CRC_ENA 0x04 2022270346Sjfv#define I40E_AQ_CONFIG_PACING_MASK 0x78 2023333343Serj union { 2024333343Serj struct { 2025333343Serj u8 power_desc; 2026299549Serj#define I40E_AQ_LINK_POWER_CLASS_1 0x00 2027299549Serj#define I40E_AQ_LINK_POWER_CLASS_2 0x01 2028299549Serj#define I40E_AQ_LINK_POWER_CLASS_3 0x02 2029299549Serj#define I40E_AQ_LINK_POWER_CLASS_4 0x03 2030303967Ssbruno#define I40E_AQ_PWR_CLASS_MASK 0x03 2031333343Serj u8 reserved[4]; 2032333343Serj }; 2033333343Serj struct { 2034333343Serj u8 link_type[4]; 2035333343Serj u8 link_type_ext; 2036333343Serj }; 2037333343Serj }; 2038266423Sjfv}; 2039266423Sjfv 2040266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 2041266423Sjfv 2042266423Sjfv/* Set event mask command (direct 0x613) */ 2043266423Sjfvstruct i40e_aqc_set_phy_int_mask { 2044270346Sjfv u8 reserved[8]; 2045270346Sjfv __le16 event_mask; 2046270346Sjfv#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 2047270346Sjfv#define I40E_AQ_EVENT_MEDIA_NA 0x0004 2048270346Sjfv#define I40E_AQ_EVENT_LINK_FAULT 0x0008 2049270346Sjfv#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 2050270346Sjfv#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 2051270346Sjfv#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 2052270346Sjfv#define I40E_AQ_EVENT_AN_COMPLETED 0x0080 2053270346Sjfv#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 2054270346Sjfv#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 2055270346Sjfv u8 reserved1[6]; 2056266423Sjfv}; 2057266423Sjfv 2058266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 2059266423Sjfv 2060266423Sjfv/* Get Local AN advt register (direct 0x0614) 2061266423Sjfv * Set Local AN advt register (direct 0x0615) 2062266423Sjfv * Get Link Partner AN advt register (direct 0x0616) 2063266423Sjfv */ 2064266423Sjfvstruct i40e_aqc_an_advt_reg { 2065270346Sjfv __le32 local_an_reg0; 2066270346Sjfv __le16 local_an_reg1; 2067270346Sjfv u8 reserved[10]; 2068266423Sjfv}; 2069266423Sjfv 2070266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 2071266423Sjfv 2072266423Sjfv/* Set Loopback mode (0x0618) */ 2073266423Sjfvstruct i40e_aqc_set_lb_mode { 2074333343Serj u8 lb_level; 2075333343Serj#define I40E_AQ_LB_NONE 0 2076333343Serj#define I40E_AQ_LB_MAC 1 2077333343Serj#define I40E_AQ_LB_SERDES 2 2078333343Serj#define I40E_AQ_LB_PHY_INT 3 2079333343Serj#define I40E_AQ_LB_PHY_EXT 4 2080333343Serj#define I40E_AQ_LB_CPVL_PCS 5 2081333343Serj#define I40E_AQ_LB_CPVL_EXT 6 2082270346Sjfv#define I40E_AQ_LB_PHY_LOCAL 0x01 2083270346Sjfv#define I40E_AQ_LB_PHY_REMOTE 0x02 2084270346Sjfv#define I40E_AQ_LB_MAC_LOCAL 0x04 2085333343Serj u8 lb_type; 2086333343Serj#define I40E_AQ_LB_LOCAL 0 2087333343Serj#define I40E_AQ_LB_FAR 0x01 2088333343Serj u8 speed; 2089333343Serj#define I40E_AQ_LB_SPEED_NONE 0 2090333343Serj#define I40E_AQ_LB_SPEED_1G 1 2091333343Serj#define I40E_AQ_LB_SPEED_10G 2 2092333343Serj#define I40E_AQ_LB_SPEED_40G 3 2093333343Serj#define I40E_AQ_LB_SPEED_20G 4 2094333343Serj u8 force_speed; 2095333343Serj u8 reserved[12]; 2096266423Sjfv}; 2097266423Sjfv 2098266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 2099266423Sjfv 2100266423Sjfv/* Set PHY Debug command (0x0622) */ 2101266423Sjfvstruct i40e_aqc_set_phy_debug { 2102270346Sjfv u8 command_flags; 2103266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 2104266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 2105270346Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 2106270346Sjfv I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 2107266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 2108266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 2109266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 2110303967Ssbruno/* Disable link manageability on a single port */ 2111266423Sjfv#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 2112303967Ssbruno/* Disable link manageability on all ports needs both bits 4 and 5 */ 2113303967Ssbruno#define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 2114270346Sjfv u8 reserved[15]; 2115266423Sjfv}; 2116266423Sjfv 2117266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 2118266423Sjfv 2119266423Sjfvenum i40e_aq_phy_reg_type { 2120270346Sjfv I40E_AQC_PHY_REG_INTERNAL = 0x1, 2121270346Sjfv I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 2122270346Sjfv I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 2123266423Sjfv}; 2124266423Sjfv 2125299549Serj/* Run PHY Activity (0x0626) */ 2126299549Serjstruct i40e_aqc_run_phy_activity { 2127299549Serj __le16 activity_id; 2128299549Serj u8 flags; 2129299549Serj u8 reserved1; 2130299549Serj __le32 control; 2131299549Serj __le32 data; 2132299549Serj u8 reserved2[4]; 2133299549Serj}; 2134299549Serj 2135299549SerjI40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 2136299549Serj 2137333343Serj/* Set PHY Register command (0x0628) */ 2138333343Serj/* Get PHY Register command (0x0629) */ 2139333343Serjstruct i40e_aqc_phy_register_access { 2140333343Serj u8 phy_interface; 2141333343Serj#define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0 2142333343Serj#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1 2143333343Serj#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2 2144333343Serj u8 dev_addres; 2145333343Serj u8 reserved1[2]; 2146333343Serj __le32 reg_address; 2147333343Serj __le32 reg_value; 2148333343Serj u8 reserved2[4]; 2149333343Serj}; 2150333343Serj 2151333343SerjI40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access); 2152333343Serj 2153266423Sjfv/* NVM Read command (indirect 0x0701) 2154266423Sjfv * NVM Erase commands (direct 0x0702) 2155266423Sjfv * NVM Update commands (indirect 0x0703) 2156266423Sjfv */ 2157266423Sjfvstruct i40e_aqc_nvm_update { 2158270346Sjfv u8 command_flags; 2159333343Serj#define I40E_AQ_NVM_LAST_CMD 0x01 2160333343Serj#define I40E_AQ_NVM_FLASH_ONLY 0x80 2161333343Serj#define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1 2162333343Serj#define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03 2163333343Serj#define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03 2164333343Serj#define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01 2165270346Sjfv u8 module_pointer; 2166270346Sjfv __le16 length; 2167270346Sjfv __le32 offset; 2168270346Sjfv __le32 addr_high; 2169270346Sjfv __le32 addr_low; 2170266423Sjfv}; 2171266423Sjfv 2172266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 2173266423Sjfv 2174266423Sjfv/* NVM Config Read (indirect 0x0704) */ 2175266423Sjfvstruct i40e_aqc_nvm_config_read { 2176270346Sjfv __le16 cmd_flags; 2177277082Sjfv#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 2178277082Sjfv#define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 2179277082Sjfv#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 2180270346Sjfv __le16 element_count; 2181299555Serj __le16 element_id; /* Feature/field ID */ 2182277082Sjfv __le16 element_id_msw; /* MSWord of field ID */ 2183270346Sjfv __le32 address_high; 2184270346Sjfv __le32 address_low; 2185266423Sjfv}; 2186266423Sjfv 2187266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 2188266423Sjfv 2189266423Sjfv/* NVM Config Write (indirect 0x0705) */ 2190266423Sjfvstruct i40e_aqc_nvm_config_write { 2191270346Sjfv __le16 cmd_flags; 2192270346Sjfv __le16 element_count; 2193270346Sjfv u8 reserved[4]; 2194270346Sjfv __le32 address_high; 2195270346Sjfv __le32 address_low; 2196266423Sjfv}; 2197266423Sjfv 2198266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 2199266423Sjfv 2200277082Sjfv/* Used for 0x0704 as well as for 0x0705 commands */ 2201277082Sjfv#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 2202299555Serj#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 2203299555Serj (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 2204299555Serj#define I40E_AQ_ANVM_FEATURE 0 2205299555Serj#define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 2206266423Sjfvstruct i40e_aqc_nvm_config_data_feature { 2207266423Sjfv __le16 feature_id; 2208277082Sjfv#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 2209277082Sjfv#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 2210277082Sjfv#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 2211266423Sjfv __le16 feature_options; 2212266423Sjfv __le16 feature_selection; 2213266423Sjfv}; 2214266423Sjfv 2215277082SjfvI40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 2216277082Sjfv 2217266423Sjfvstruct i40e_aqc_nvm_config_data_immediate_field { 2218277082Sjfv __le32 field_id; 2219277082Sjfv __le32 field_value; 2220266423Sjfv __le16 field_options; 2221277082Sjfv __le16 reserved; 2222266423Sjfv}; 2223266423Sjfv 2224277082SjfvI40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 2225277082Sjfv 2226284049Sjfv/* OEM Post Update (indirect 0x0720) 2227284049Sjfv * no command data struct used 2228284049Sjfv */ 2229299555Serjstruct i40e_aqc_nvm_oem_post_update { 2230284049Sjfv#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 2231284049Sjfv u8 sel_data; 2232284049Sjfv u8 reserved[7]; 2233284049Sjfv}; 2234284049Sjfv 2235284049SjfvI40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 2236284049Sjfv 2237284049Sjfvstruct i40e_aqc_nvm_oem_post_update_buffer { 2238284049Sjfv u8 str_len; 2239284049Sjfv u8 dev_addr; 2240284049Sjfv __le16 eeprom_addr; 2241284049Sjfv u8 data[36]; 2242284049Sjfv}; 2243284049Sjfv 2244284049SjfvI40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 2245284049Sjfv 2246299549Serj/* Thermal Sensor (indirect 0x0721) 2247299549Serj * read or set thermal sensor configs and values 2248299549Serj * takes a sensor and command specific data buffer, not detailed here 2249299549Serj */ 2250299549Serjstruct i40e_aqc_thermal_sensor { 2251299549Serj u8 sensor_action; 2252299549Serj#define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 2253299549Serj#define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 2254299549Serj#define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 2255299549Serj u8 reserved[7]; 2256299549Serj __le32 addr_high; 2257299549Serj __le32 addr_low; 2258299549Serj}; 2259299549Serj 2260299549SerjI40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 2261299549Serj 2262266423Sjfv/* Send to PF command (indirect 0x0801) id is only used by PF 2263266423Sjfv * Send to VF command (indirect 0x0802) id is only used by PF 2264266423Sjfv * Send to Peer PF command (indirect 0x0803) 2265266423Sjfv */ 2266266423Sjfvstruct i40e_aqc_pf_vf_message { 2267270346Sjfv __le32 id; 2268270346Sjfv u8 reserved[4]; 2269270346Sjfv __le32 addr_high; 2270270346Sjfv __le32 addr_low; 2271266423Sjfv}; 2272266423Sjfv 2273266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 2274266423Sjfv 2275266423Sjfv/* Alternate structure */ 2276266423Sjfv 2277266423Sjfv/* Direct write (direct 0x0900) 2278266423Sjfv * Direct read (direct 0x0902) 2279266423Sjfv */ 2280266423Sjfvstruct i40e_aqc_alternate_write { 2281266423Sjfv __le32 address0; 2282266423Sjfv __le32 data0; 2283266423Sjfv __le32 address1; 2284266423Sjfv __le32 data1; 2285266423Sjfv}; 2286266423Sjfv 2287266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 2288266423Sjfv 2289266423Sjfv/* Indirect write (indirect 0x0901) 2290266423Sjfv * Indirect read (indirect 0x0903) 2291266423Sjfv */ 2292266423Sjfv 2293266423Sjfvstruct i40e_aqc_alternate_ind_write { 2294266423Sjfv __le32 address; 2295266423Sjfv __le32 length; 2296266423Sjfv __le32 addr_high; 2297266423Sjfv __le32 addr_low; 2298266423Sjfv}; 2299266423Sjfv 2300266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 2301266423Sjfv 2302266423Sjfv/* Done alternate write (direct 0x0904) 2303266423Sjfv * uses i40e_aq_desc 2304266423Sjfv */ 2305266423Sjfvstruct i40e_aqc_alternate_write_done { 2306270346Sjfv __le16 cmd_flags; 2307266423Sjfv#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 2308266423Sjfv#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 2309266423Sjfv#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 2310266423Sjfv#define I40E_AQ_ALTERNATE_RESET_NEEDED 2 2311270346Sjfv u8 reserved[14]; 2312266423Sjfv}; 2313266423Sjfv 2314266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2315266423Sjfv 2316266423Sjfv/* Set OEM mode (direct 0x0905) */ 2317266423Sjfvstruct i40e_aqc_alternate_set_mode { 2318270346Sjfv __le32 mode; 2319266423Sjfv#define I40E_AQ_ALTERNATE_MODE_NONE 0 2320266423Sjfv#define I40E_AQ_ALTERNATE_MODE_OEM 1 2321270346Sjfv u8 reserved[12]; 2322266423Sjfv}; 2323266423Sjfv 2324266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2325266423Sjfv 2326266423Sjfv/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2327266423Sjfv 2328266423Sjfv/* async events 0x10xx */ 2329266423Sjfv 2330266423Sjfv/* Lan Queue Overflow Event (direct, 0x1001) */ 2331266423Sjfvstruct i40e_aqc_lan_overflow { 2332270346Sjfv __le32 prtdcb_rupto; 2333270346Sjfv __le32 otx_ctl; 2334270346Sjfv u8 reserved[8]; 2335266423Sjfv}; 2336266423Sjfv 2337266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2338266423Sjfv 2339266423Sjfv/* Get LLDP MIB (indirect 0x0A00) */ 2340266423Sjfvstruct i40e_aqc_lldp_get_mib { 2341270346Sjfv u8 type; 2342270346Sjfv u8 reserved1; 2343270346Sjfv#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2344270346Sjfv#define I40E_AQ_LLDP_MIB_LOCAL 0x0 2345270346Sjfv#define I40E_AQ_LLDP_MIB_REMOTE 0x1 2346270346Sjfv#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2347270346Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2348270346Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2349270346Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2350270346Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2351270346Sjfv#define I40E_AQ_LLDP_TX_SHIFT 0x4 2352270346Sjfv#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2353266423Sjfv/* TX pause flags use I40E_AQ_LINK_TX_* above */ 2354270346Sjfv __le16 local_len; 2355270346Sjfv __le16 remote_len; 2356270346Sjfv u8 reserved2[2]; 2357270346Sjfv __le32 addr_high; 2358270346Sjfv __le32 addr_low; 2359266423Sjfv}; 2360266423Sjfv 2361266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2362266423Sjfv 2363266423Sjfv/* Configure LLDP MIB Change Event (direct 0x0A01) 2364266423Sjfv * also used for the event (with type in the command field) 2365266423Sjfv */ 2366266423Sjfvstruct i40e_aqc_lldp_update_mib { 2367270346Sjfv u8 command; 2368270346Sjfv#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2369270346Sjfv#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2370270346Sjfv u8 reserved[7]; 2371270346Sjfv __le32 addr_high; 2372270346Sjfv __le32 addr_low; 2373266423Sjfv}; 2374266423Sjfv 2375266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2376266423Sjfv 2377266423Sjfv/* Add LLDP TLV (indirect 0x0A02) 2378266423Sjfv * Delete LLDP TLV (indirect 0x0A04) 2379266423Sjfv */ 2380266423Sjfvstruct i40e_aqc_lldp_add_tlv { 2381270346Sjfv u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2382270346Sjfv u8 reserved1[1]; 2383270346Sjfv __le16 len; 2384270346Sjfv u8 reserved2[4]; 2385270346Sjfv __le32 addr_high; 2386270346Sjfv __le32 addr_low; 2387266423Sjfv}; 2388266423Sjfv 2389266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2390266423Sjfv 2391266423Sjfv/* Update LLDP TLV (indirect 0x0A03) */ 2392266423Sjfvstruct i40e_aqc_lldp_update_tlv { 2393270346Sjfv u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2394270346Sjfv u8 reserved; 2395270346Sjfv __le16 old_len; 2396270346Sjfv __le16 new_offset; 2397270346Sjfv __le16 new_len; 2398270346Sjfv __le32 addr_high; 2399270346Sjfv __le32 addr_low; 2400266423Sjfv}; 2401266423Sjfv 2402266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2403266423Sjfv 2404266423Sjfv/* Stop LLDP (direct 0x0A05) */ 2405266423Sjfvstruct i40e_aqc_lldp_stop { 2406270346Sjfv u8 command; 2407270346Sjfv#define I40E_AQ_LLDP_AGENT_STOP 0x0 2408270346Sjfv#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2409270346Sjfv u8 reserved[15]; 2410266423Sjfv}; 2411266423Sjfv 2412266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2413266423Sjfv 2414266423Sjfv/* Start LLDP (direct 0x0A06) */ 2415266423Sjfv 2416266423Sjfvstruct i40e_aqc_lldp_start { 2417270346Sjfv u8 command; 2418270346Sjfv#define I40E_AQ_LLDP_AGENT_START 0x1 2419270346Sjfv u8 reserved[15]; 2420266423Sjfv}; 2421266423Sjfv 2422266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2423266423Sjfv 2424333343Serj/* Set DCB (direct 0x0303) */ 2425333343Serjstruct i40e_aqc_set_dcb_parameters { 2426333343Serj u8 command; 2427333343Serj#define I40E_AQ_DCB_SET_AGENT 0x1 2428333343Serj#define I40E_DCB_VALID 0x1 2429333343Serj u8 valid_flags; 2430333343Serj u8 reserved[14]; 2431333343Serj}; 2432333343Serj 2433333343SerjI40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters); 2434333343Serj 2435277082Sjfv/* Get CEE DCBX Oper Config (0x0A07) 2436277082Sjfv * uses the generic descriptor struct 2437277082Sjfv * returns below as indirect response 2438266423Sjfv */ 2439266423Sjfv 2440277082Sjfv#define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2441277082Sjfv#define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2442277082Sjfv#define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2443277082Sjfv#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2444277082Sjfv#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2445277082Sjfv#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2446284049Sjfv 2447277082Sjfv#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2448277082Sjfv#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2449277082Sjfv#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2450277082Sjfv#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2451277082Sjfv#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2452277082Sjfv#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2453284049Sjfv#define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2454284049Sjfv#define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2455284049Sjfv#define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2456284049Sjfv#define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2457284049Sjfv#define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2458284049Sjfv#define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2459284049Sjfv 2460284049Sjfv/* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2461284049Sjfv * word boundary layout issues, which the Linux compilers silently deal 2462284049Sjfv * with by adding padding, making the actual struct larger than designed. 2463284049Sjfv * However, the FW compiler for the NIC is less lenient and complains 2464284049Sjfv * about the struct. Hence, the struct defined here has an extra byte in 2465284049Sjfv * fields reserved3 and reserved4 to directly acknowledge that padding, 2466284049Sjfv * and the new length is used in the length check macro. 2467284049Sjfv */ 2468277082Sjfvstruct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2469277082Sjfv u8 reserved1; 2470277082Sjfv u8 oper_num_tc; 2471277082Sjfv u8 oper_prio_tc[4]; 2472277082Sjfv u8 reserved2; 2473277082Sjfv u8 oper_tc_bw[8]; 2474277082Sjfv u8 oper_pfc_en; 2475284049Sjfv u8 reserved3[2]; 2476277082Sjfv __le16 oper_app_prio; 2477284049Sjfv u8 reserved4[2]; 2478277082Sjfv __le16 tlv_status; 2479277082Sjfv}; 2480277082Sjfv 2481277082SjfvI40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2482277082Sjfv 2483277082Sjfvstruct i40e_aqc_get_cee_dcb_cfg_resp { 2484277082Sjfv u8 oper_num_tc; 2485277082Sjfv u8 oper_prio_tc[4]; 2486277082Sjfv u8 oper_tc_bw[8]; 2487277082Sjfv u8 oper_pfc_en; 2488277082Sjfv __le16 oper_app_prio; 2489277082Sjfv __le32 tlv_status; 2490277082Sjfv u8 reserved[12]; 2491277082Sjfv}; 2492277082Sjfv 2493277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2494277082Sjfv 2495277082Sjfv/* Set Local LLDP MIB (indirect 0x0A08) 2496277082Sjfv * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2497277082Sjfv */ 2498277082Sjfvstruct i40e_aqc_lldp_set_local_mib { 2499277082Sjfv#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2500299545Serj#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \ 2501299545Serj SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2502299545Serj#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2503299545Serj#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2504299545Serj#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \ 2505299545Serj SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2506299545Serj#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2507277082Sjfv u8 type; 2508277082Sjfv u8 reserved0; 2509277082Sjfv __le16 length; 2510277082Sjfv u8 reserved1[4]; 2511277082Sjfv __le32 address_high; 2512277082Sjfv __le32 address_low; 2513277082Sjfv}; 2514277082Sjfv 2515277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2516277082Sjfv 2517299547Serjstruct i40e_aqc_lldp_set_local_mib_resp { 2518299547Serj#define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01 2519299547Serj u8 status; 2520299547Serj u8 reserved[15]; 2521299547Serj}; 2522299547Serj 2523299547SerjI40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp); 2524299547Serj 2525277082Sjfv/* Stop/Start LLDP Agent (direct 0x0A09) 2526277082Sjfv * Used for stopping/starting specific LLDP agent. e.g. DCBx 2527277082Sjfv */ 2528277082Sjfvstruct i40e_aqc_lldp_stop_start_specific_agent { 2529277082Sjfv#define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2530299555Serj#define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2531299555Serj (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2532277082Sjfv u8 command; 2533277082Sjfv u8 reserved[15]; 2534277082Sjfv}; 2535277082Sjfv 2536277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2537277082Sjfv 2538266423Sjfv/* Add Udp Tunnel command and completion (direct 0x0B00) */ 2539266423Sjfvstruct i40e_aqc_add_udp_tunnel { 2540270346Sjfv __le16 udp_port; 2541270346Sjfv u8 reserved0[3]; 2542270346Sjfv u8 protocol_type; 2543266423Sjfv#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2544266423Sjfv#define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2545266423Sjfv#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2546299549Serj#define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2547270346Sjfv u8 reserved1[10]; 2548266423Sjfv}; 2549266423Sjfv 2550266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2551266423Sjfv 2552266423Sjfvstruct i40e_aqc_add_udp_tunnel_completion { 2553299555Serj __le16 udp_port; 2554266423Sjfv u8 filter_entry_index; 2555266423Sjfv u8 multiple_pfs; 2556270346Sjfv#define I40E_AQC_SINGLE_PF 0x0 2557270346Sjfv#define I40E_AQC_MULTIPLE_PFS 0x1 2558266423Sjfv u8 total_filters; 2559266423Sjfv u8 reserved[11]; 2560266423Sjfv}; 2561266423Sjfv 2562266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2563266423Sjfv 2564266423Sjfv/* remove UDP Tunnel command (0x0B01) */ 2565266423Sjfvstruct i40e_aqc_remove_udp_tunnel { 2566270346Sjfv u8 reserved[2]; 2567270346Sjfv u8 index; /* 0 to 15 */ 2568270346Sjfv u8 reserved2[13]; 2569266423Sjfv}; 2570266423Sjfv 2571266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2572266423Sjfv 2573266423Sjfvstruct i40e_aqc_del_udp_tunnel_completion { 2574270346Sjfv __le16 udp_port; 2575270346Sjfv u8 index; /* 0 to 15 */ 2576270346Sjfv u8 multiple_pfs; 2577270346Sjfv u8 total_filters_used; 2578270346Sjfv u8 reserved1[11]; 2579266423Sjfv}; 2580266423Sjfv 2581266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2582266423Sjfv 2583303967Ssbrunostruct i40e_aqc_get_set_rss_key { 2584303967Ssbruno#define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15) 2585303967Ssbruno#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2586303967Ssbruno#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2587303967Ssbruno I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2588303967Ssbruno __le16 vsi_id; 2589303967Ssbruno u8 reserved[6]; 2590303967Ssbruno __le32 addr_high; 2591303967Ssbruno __le32 addr_low; 2592303967Ssbruno}; 2593303967Ssbruno 2594303967SsbrunoI40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2595303967Ssbruno 2596303967Ssbrunostruct i40e_aqc_get_set_rss_key_data { 2597303967Ssbruno u8 standard_rss_key[0x28]; 2598303967Ssbruno u8 extended_hash_key[0xc]; 2599303967Ssbruno}; 2600303967Ssbruno 2601303967SsbrunoI40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2602303967Ssbruno 2603303967Ssbrunostruct i40e_aqc_get_set_rss_lut { 2604303967Ssbruno#define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15) 2605303967Ssbruno#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2606303967Ssbruno#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2607303967Ssbruno I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2608303967Ssbruno __le16 vsi_id; 2609303967Ssbruno#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2610303967Ssbruno#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \ 2611303967Ssbruno I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2612303967Ssbruno 2613303967Ssbruno#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2614303967Ssbruno#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2615303967Ssbruno __le16 flags; 2616303967Ssbruno u8 reserved[4]; 2617303967Ssbruno __le32 addr_high; 2618303967Ssbruno __le32 addr_low; 2619303967Ssbruno}; 2620303967Ssbruno 2621303967SsbrunoI40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2622303967Ssbruno 2623266423Sjfv/* tunnel key structure 0x0B10 */ 2624266423Sjfv 2625266423Sjfvstruct i40e_aqc_tunnel_key_structure { 2626266423Sjfv u8 key1_off; 2627266423Sjfv u8 key2_off; 2628266423Sjfv u8 key1_len; /* 0 to 15 */ 2629266423Sjfv u8 key2_len; /* 0 to 15 */ 2630266423Sjfv u8 flags; 2631270346Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2632266423Sjfv/* response flags */ 2633270346Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2634270346Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2635270346Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2636266423Sjfv u8 network_key_index; 2637266423Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2638266423Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2639266423Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2640266423Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2641266423Sjfv u8 reserved[10]; 2642266423Sjfv}; 2643266423Sjfv 2644266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2645266423Sjfv 2646266423Sjfv/* OEM mode commands (direct 0xFE0x) */ 2647266423Sjfvstruct i40e_aqc_oem_param_change { 2648270346Sjfv __le32 param_type; 2649270346Sjfv#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2650270346Sjfv#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2651270346Sjfv#define I40E_AQ_OEM_PARAM_MAC 2 2652270346Sjfv __le32 param_value1; 2653277082Sjfv __le16 param_value2; 2654277082Sjfv u8 reserved[6]; 2655266423Sjfv}; 2656266423Sjfv 2657266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2658266423Sjfv 2659266423Sjfvstruct i40e_aqc_oem_state_change { 2660270346Sjfv __le32 state; 2661270346Sjfv#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2662270346Sjfv#define I40E_AQ_OEM_STATE_LINK_UP 0x1 2663270346Sjfv u8 reserved[12]; 2664266423Sjfv}; 2665266423Sjfv 2666266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2667266423Sjfv 2668277082Sjfv/* Initialize OCSD (0xFE02, direct) */ 2669277082Sjfvstruct i40e_aqc_opc_oem_ocsd_initialize { 2670277082Sjfv u8 type_status; 2671277082Sjfv u8 reserved1[3]; 2672277082Sjfv __le32 ocsd_memory_block_addr_high; 2673277082Sjfv __le32 ocsd_memory_block_addr_low; 2674277082Sjfv __le32 requested_update_interval; 2675277082Sjfv}; 2676277082Sjfv 2677277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2678277082Sjfv 2679277082Sjfv/* Initialize OCBB (0xFE03, direct) */ 2680277082Sjfvstruct i40e_aqc_opc_oem_ocbb_initialize { 2681277082Sjfv u8 type_status; 2682277082Sjfv u8 reserved1[3]; 2683277082Sjfv __le32 ocbb_memory_block_addr_high; 2684277082Sjfv __le32 ocbb_memory_block_addr_low; 2685277082Sjfv u8 reserved2[4]; 2686277082Sjfv}; 2687277082Sjfv 2688277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2689277082Sjfv 2690266423Sjfv/* debug commands */ 2691266423Sjfv 2692266423Sjfv/* get device id (0xFF00) uses the generic structure */ 2693266423Sjfv 2694266423Sjfv/* set test more (0xFF01, internal) */ 2695266423Sjfv 2696266423Sjfvstruct i40e_acq_set_test_mode { 2697270346Sjfv u8 mode; 2698270346Sjfv#define I40E_AQ_TEST_PARTIAL 0 2699270346Sjfv#define I40E_AQ_TEST_FULL 1 2700270346Sjfv#define I40E_AQ_TEST_NVM 2 2701270346Sjfv u8 reserved[3]; 2702270346Sjfv u8 command; 2703270346Sjfv#define I40E_AQ_TEST_OPEN 0 2704270346Sjfv#define I40E_AQ_TEST_CLOSE 1 2705270346Sjfv#define I40E_AQ_TEST_INC 2 2706270346Sjfv u8 reserved2[3]; 2707270346Sjfv __le32 address_high; 2708270346Sjfv __le32 address_low; 2709266423Sjfv}; 2710266423Sjfv 2711266423SjfvI40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2712266423Sjfv 2713266423Sjfv/* Debug Read Register command (0xFF03) 2714266423Sjfv * Debug Write Register command (0xFF04) 2715266423Sjfv */ 2716266423Sjfvstruct i40e_aqc_debug_reg_read_write { 2717266423Sjfv __le32 reserved; 2718266423Sjfv __le32 address; 2719266423Sjfv __le32 value_high; 2720266423Sjfv __le32 value_low; 2721266423Sjfv}; 2722266423Sjfv 2723266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2724266423Sjfv 2725266423Sjfv/* Scatter/gather Reg Read (indirect 0xFF05) 2726266423Sjfv * Scatter/gather Reg Write (indirect 0xFF06) 2727266423Sjfv */ 2728266423Sjfv 2729266423Sjfv/* i40e_aq_desc is used for the command */ 2730266423Sjfvstruct i40e_aqc_debug_reg_sg_element_data { 2731266423Sjfv __le32 address; 2732266423Sjfv __le32 value; 2733266423Sjfv}; 2734266423Sjfv 2735266423Sjfv/* Debug Modify register (direct 0xFF07) */ 2736266423Sjfvstruct i40e_aqc_debug_modify_reg { 2737266423Sjfv __le32 address; 2738266423Sjfv __le32 value; 2739266423Sjfv __le32 clear_mask; 2740266423Sjfv __le32 set_mask; 2741266423Sjfv}; 2742266423Sjfv 2743266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2744266423Sjfv 2745266423Sjfv/* dump internal data (0xFF08, indirect) */ 2746266423Sjfv 2747266423Sjfv#define I40E_AQ_CLUSTER_ID_AUX 0 2748266423Sjfv#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2749266423Sjfv#define I40E_AQ_CLUSTER_ID_TXSCHED 2 2750266423Sjfv#define I40E_AQ_CLUSTER_ID_HMC 3 2751266423Sjfv#define I40E_AQ_CLUSTER_ID_MAC0 4 2752266423Sjfv#define I40E_AQ_CLUSTER_ID_MAC1 5 2753266423Sjfv#define I40E_AQ_CLUSTER_ID_MAC2 6 2754266423Sjfv#define I40E_AQ_CLUSTER_ID_MAC3 7 2755266423Sjfv#define I40E_AQ_CLUSTER_ID_DCB 8 2756266423Sjfv#define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2757266423Sjfv#define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2758266423Sjfv#define I40E_AQ_CLUSTER_ID_ALTRAM 11 2759266423Sjfv 2760266423Sjfvstruct i40e_aqc_debug_dump_internals { 2761270346Sjfv u8 cluster_id; 2762270346Sjfv u8 table_id; 2763270346Sjfv __le16 data_size; 2764270346Sjfv __le32 idx; 2765270346Sjfv __le32 address_high; 2766270346Sjfv __le32 address_low; 2767266423Sjfv}; 2768266423Sjfv 2769266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2770266423Sjfv 2771266423Sjfvstruct i40e_aqc_debug_modify_internals { 2772270346Sjfv u8 cluster_id; 2773270346Sjfv u8 cluster_specific_params[7]; 2774270346Sjfv __le32 address_high; 2775270346Sjfv __le32 address_low; 2776266423Sjfv}; 2777266423Sjfv 2778266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2779266423Sjfv 2780299547Serj#endif /* _I40E_ADMINQ_CMD_H_ */ 2781