i40e_adminq_cmd.h revision 318357
1266423Sjfv/****************************************************************************** 2266423Sjfv 3279033Sjfv Copyright (c) 2013-2015, Intel Corporation 4266423Sjfv All rights reserved. 5266423Sjfv 6266423Sjfv Redistribution and use in source and binary forms, with or without 7266423Sjfv modification, are permitted provided that the following conditions are met: 8266423Sjfv 9266423Sjfv 1. Redistributions of source code must retain the above copyright notice, 10266423Sjfv this list of conditions and the following disclaimer. 11266423Sjfv 12266423Sjfv 2. Redistributions in binary form must reproduce the above copyright 13266423Sjfv notice, this list of conditions and the following disclaimer in the 14266423Sjfv documentation and/or other materials provided with the distribution. 15266423Sjfv 16266423Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17266423Sjfv contributors may be used to endorse or promote products derived from 18266423Sjfv this software without specific prior written permission. 19266423Sjfv 20266423Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21266423Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22266423Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23266423Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24266423Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25266423Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26266423Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27266423Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28266423Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29266423Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30266423Sjfv POSSIBILITY OF SUCH DAMAGE. 31266423Sjfv 32266423Sjfv******************************************************************************/ 33266423Sjfv/*$FreeBSD: stable/11/sys/dev/ixl/i40e_adminq_cmd.h 318357 2017-05-16 17:49:15Z erj $*/ 34266423Sjfv 35266423Sjfv#ifndef _I40E_ADMINQ_CMD_H_ 36266423Sjfv#define _I40E_ADMINQ_CMD_H_ 37266423Sjfv 38266423Sjfv/* This header file defines the i40e Admin Queue commands and is shared between 39266423Sjfv * i40e Firmware and Software. 40266423Sjfv * 41266423Sjfv * This file needs to comply with the Linux Kernel coding style. 42266423Sjfv */ 43266423Sjfv 44270346Sjfv#define I40E_FW_API_VERSION_MAJOR 0x0001 45299549Serj#define I40E_FW_API_VERSION_MINOR 0x0005 46266423Sjfv 47266423Sjfvstruct i40e_aq_desc { 48266423Sjfv __le16 flags; 49266423Sjfv __le16 opcode; 50266423Sjfv __le16 datalen; 51266423Sjfv __le16 retval; 52266423Sjfv __le32 cookie_high; 53266423Sjfv __le32 cookie_low; 54266423Sjfv union { 55266423Sjfv struct { 56266423Sjfv __le32 param0; 57266423Sjfv __le32 param1; 58266423Sjfv __le32 param2; 59266423Sjfv __le32 param3; 60266423Sjfv } internal; 61266423Sjfv struct { 62266423Sjfv __le32 param0; 63266423Sjfv __le32 param1; 64266423Sjfv __le32 addr_high; 65266423Sjfv __le32 addr_low; 66266423Sjfv } external; 67266423Sjfv u8 raw[16]; 68266423Sjfv } params; 69266423Sjfv}; 70266423Sjfv 71266423Sjfv/* Flags sub-structure 72266423Sjfv * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 73266423Sjfv * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 74266423Sjfv */ 75266423Sjfv 76266423Sjfv/* command flags and offsets*/ 77270346Sjfv#define I40E_AQ_FLAG_DD_SHIFT 0 78270346Sjfv#define I40E_AQ_FLAG_CMP_SHIFT 1 79270346Sjfv#define I40E_AQ_FLAG_ERR_SHIFT 2 80270346Sjfv#define I40E_AQ_FLAG_VFE_SHIFT 3 81270346Sjfv#define I40E_AQ_FLAG_LB_SHIFT 9 82270346Sjfv#define I40E_AQ_FLAG_RD_SHIFT 10 83270346Sjfv#define I40E_AQ_FLAG_VFC_SHIFT 11 84270346Sjfv#define I40E_AQ_FLAG_BUF_SHIFT 12 85270346Sjfv#define I40E_AQ_FLAG_SI_SHIFT 13 86270346Sjfv#define I40E_AQ_FLAG_EI_SHIFT 14 87270346Sjfv#define I40E_AQ_FLAG_FE_SHIFT 15 88266423Sjfv 89270346Sjfv#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 90270346Sjfv#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 91270346Sjfv#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 92270346Sjfv#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 93270346Sjfv#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 94270346Sjfv#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 95270346Sjfv#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 96270346Sjfv#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 97270346Sjfv#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 98270346Sjfv#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 99270346Sjfv#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 100266423Sjfv 101266423Sjfv/* error codes */ 102266423Sjfvenum i40e_admin_queue_err { 103270346Sjfv I40E_AQ_RC_OK = 0, /* success */ 104270346Sjfv I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 105270346Sjfv I40E_AQ_RC_ENOENT = 2, /* No such element */ 106270346Sjfv I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 107270346Sjfv I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 108270346Sjfv I40E_AQ_RC_EIO = 5, /* I/O error */ 109270346Sjfv I40E_AQ_RC_ENXIO = 6, /* No such resource */ 110270346Sjfv I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 111270346Sjfv I40E_AQ_RC_EAGAIN = 8, /* Try again */ 112270346Sjfv I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 113270346Sjfv I40E_AQ_RC_EACCES = 10, /* Permission denied */ 114270346Sjfv I40E_AQ_RC_EFAULT = 11, /* Bad address */ 115270346Sjfv I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 116270346Sjfv I40E_AQ_RC_EEXIST = 13, /* object already exists */ 117270346Sjfv I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 118270346Sjfv I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 119270346Sjfv I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 120270346Sjfv I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 121270346Sjfv I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 122270346Sjfv I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 123270346Sjfv I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 124270346Sjfv I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 125270346Sjfv I40E_AQ_RC_EFBIG = 22, /* File too large */ 126266423Sjfv}; 127266423Sjfv 128266423Sjfv/* Admin Queue command opcodes */ 129266423Sjfvenum i40e_admin_queue_opc { 130266423Sjfv /* aq commands */ 131270346Sjfv i40e_aqc_opc_get_version = 0x0001, 132270346Sjfv i40e_aqc_opc_driver_version = 0x0002, 133270346Sjfv i40e_aqc_opc_queue_shutdown = 0x0003, 134270346Sjfv i40e_aqc_opc_set_pf_context = 0x0004, 135266423Sjfv 136266423Sjfv /* resource ownership */ 137270346Sjfv i40e_aqc_opc_request_resource = 0x0008, 138270346Sjfv i40e_aqc_opc_release_resource = 0x0009, 139266423Sjfv 140270346Sjfv i40e_aqc_opc_list_func_capabilities = 0x000A, 141270346Sjfv i40e_aqc_opc_list_dev_capabilities = 0x000B, 142266423Sjfv 143303967Ssbruno /* Proxy commands */ 144303967Ssbruno i40e_aqc_opc_set_proxy_config = 0x0104, 145303967Ssbruno i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, 146303967Ssbruno 147266423Sjfv /* LAA */ 148270346Sjfv i40e_aqc_opc_mac_address_read = 0x0107, 149270346Sjfv i40e_aqc_opc_mac_address_write = 0x0108, 150266423Sjfv 151266423Sjfv /* PXE */ 152270346Sjfv i40e_aqc_opc_clear_pxe_mode = 0x0110, 153266423Sjfv 154303967Ssbruno /* WoL commands */ 155303967Ssbruno i40e_aqc_opc_set_wol_filter = 0x0120, 156303967Ssbruno i40e_aqc_opc_get_wake_reason = 0x0121, 157318357Serj i40e_aqc_opc_clear_all_wol_filters = 0x025E, 158303967Ssbruno 159266423Sjfv /* internal switch commands */ 160270346Sjfv i40e_aqc_opc_get_switch_config = 0x0200, 161270346Sjfv i40e_aqc_opc_add_statistics = 0x0201, 162270346Sjfv i40e_aqc_opc_remove_statistics = 0x0202, 163270346Sjfv i40e_aqc_opc_set_port_parameters = 0x0203, 164270346Sjfv i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 165299549Serj i40e_aqc_opc_set_switch_config = 0x0205, 166299555Serj i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 167299555Serj i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 168266423Sjfv 169270346Sjfv i40e_aqc_opc_add_vsi = 0x0210, 170270346Sjfv i40e_aqc_opc_update_vsi_parameters = 0x0211, 171270346Sjfv i40e_aqc_opc_get_vsi_parameters = 0x0212, 172266423Sjfv 173270346Sjfv i40e_aqc_opc_add_pv = 0x0220, 174270346Sjfv i40e_aqc_opc_update_pv_parameters = 0x0221, 175270346Sjfv i40e_aqc_opc_get_pv_parameters = 0x0222, 176266423Sjfv 177270346Sjfv i40e_aqc_opc_add_veb = 0x0230, 178270346Sjfv i40e_aqc_opc_update_veb_parameters = 0x0231, 179270346Sjfv i40e_aqc_opc_get_veb_parameters = 0x0232, 180266423Sjfv 181270346Sjfv i40e_aqc_opc_delete_element = 0x0243, 182266423Sjfv 183270346Sjfv i40e_aqc_opc_add_macvlan = 0x0250, 184270346Sjfv i40e_aqc_opc_remove_macvlan = 0x0251, 185270346Sjfv i40e_aqc_opc_add_vlan = 0x0252, 186270346Sjfv i40e_aqc_opc_remove_vlan = 0x0253, 187270346Sjfv i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 188270346Sjfv i40e_aqc_opc_add_tag = 0x0255, 189270346Sjfv i40e_aqc_opc_remove_tag = 0x0256, 190270346Sjfv i40e_aqc_opc_add_multicast_etag = 0x0257, 191270346Sjfv i40e_aqc_opc_remove_multicast_etag = 0x0258, 192270346Sjfv i40e_aqc_opc_update_tag = 0x0259, 193270346Sjfv i40e_aqc_opc_add_control_packet_filter = 0x025A, 194270346Sjfv i40e_aqc_opc_remove_control_packet_filter = 0x025B, 195270346Sjfv i40e_aqc_opc_add_cloud_filters = 0x025C, 196270346Sjfv i40e_aqc_opc_remove_cloud_filters = 0x025D, 197303967Ssbruno i40e_aqc_opc_clear_wol_switch_filters = 0x025E, 198266423Sjfv 199270346Sjfv i40e_aqc_opc_add_mirror_rule = 0x0260, 200270346Sjfv i40e_aqc_opc_delete_mirror_rule = 0x0261, 201266423Sjfv 202266423Sjfv /* DCB commands */ 203270346Sjfv i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 204270346Sjfv i40e_aqc_opc_dcb_updated = 0x0302, 205266423Sjfv 206266423Sjfv /* TX scheduler */ 207270346Sjfv i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 208270346Sjfv i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 209270346Sjfv i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 210270346Sjfv i40e_aqc_opc_query_vsi_bw_config = 0x0408, 211270346Sjfv i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 212270346Sjfv i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 213266423Sjfv 214270346Sjfv i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 215270346Sjfv i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 216270346Sjfv i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 217270346Sjfv i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 218270346Sjfv i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 219270346Sjfv i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 220270346Sjfv i40e_aqc_opc_query_port_ets_config = 0x0419, 221270346Sjfv i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 222270346Sjfv i40e_aqc_opc_suspend_port_tx = 0x041B, 223270346Sjfv i40e_aqc_opc_resume_port_tx = 0x041C, 224270346Sjfv i40e_aqc_opc_configure_partition_bw = 0x041D, 225266423Sjfv /* hmc */ 226270346Sjfv i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 227270346Sjfv i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 228266423Sjfv 229266423Sjfv /* phy commands*/ 230270346Sjfv i40e_aqc_opc_get_phy_abilities = 0x0600, 231270346Sjfv i40e_aqc_opc_set_phy_config = 0x0601, 232270346Sjfv i40e_aqc_opc_set_mac_config = 0x0603, 233270346Sjfv i40e_aqc_opc_set_link_restart_an = 0x0605, 234270346Sjfv i40e_aqc_opc_get_link_status = 0x0607, 235270346Sjfv i40e_aqc_opc_set_phy_int_mask = 0x0613, 236270346Sjfv i40e_aqc_opc_get_local_advt_reg = 0x0614, 237270346Sjfv i40e_aqc_opc_set_local_advt_reg = 0x0615, 238270346Sjfv i40e_aqc_opc_get_partner_advt = 0x0616, 239270346Sjfv i40e_aqc_opc_set_lb_modes = 0x0618, 240270346Sjfv i40e_aqc_opc_get_phy_wol_caps = 0x0621, 241270346Sjfv i40e_aqc_opc_set_phy_debug = 0x0622, 242270346Sjfv i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 243299549Serj i40e_aqc_opc_run_phy_activity = 0x0626, 244266423Sjfv 245266423Sjfv /* NVM commands */ 246270346Sjfv i40e_aqc_opc_nvm_read = 0x0701, 247270346Sjfv i40e_aqc_opc_nvm_erase = 0x0702, 248270346Sjfv i40e_aqc_opc_nvm_update = 0x0703, 249270346Sjfv i40e_aqc_opc_nvm_config_read = 0x0704, 250270346Sjfv i40e_aqc_opc_nvm_config_write = 0x0705, 251284049Sjfv i40e_aqc_opc_oem_post_update = 0x0720, 252299549Serj i40e_aqc_opc_thermal_sensor = 0x0721, 253266423Sjfv 254266423Sjfv /* virtualization commands */ 255270346Sjfv i40e_aqc_opc_send_msg_to_pf = 0x0801, 256270346Sjfv i40e_aqc_opc_send_msg_to_vf = 0x0802, 257270346Sjfv i40e_aqc_opc_send_msg_to_peer = 0x0803, 258266423Sjfv 259266423Sjfv /* alternate structure */ 260270346Sjfv i40e_aqc_opc_alternate_write = 0x0900, 261270346Sjfv i40e_aqc_opc_alternate_write_indirect = 0x0901, 262270346Sjfv i40e_aqc_opc_alternate_read = 0x0902, 263270346Sjfv i40e_aqc_opc_alternate_read_indirect = 0x0903, 264270346Sjfv i40e_aqc_opc_alternate_write_done = 0x0904, 265270346Sjfv i40e_aqc_opc_alternate_set_mode = 0x0905, 266270346Sjfv i40e_aqc_opc_alternate_clear_port = 0x0906, 267266423Sjfv 268266423Sjfv /* LLDP commands */ 269270346Sjfv i40e_aqc_opc_lldp_get_mib = 0x0A00, 270270346Sjfv i40e_aqc_opc_lldp_update_mib = 0x0A01, 271270346Sjfv i40e_aqc_opc_lldp_add_tlv = 0x0A02, 272270346Sjfv i40e_aqc_opc_lldp_update_tlv = 0x0A03, 273270346Sjfv i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 274270346Sjfv i40e_aqc_opc_lldp_stop = 0x0A05, 275270346Sjfv i40e_aqc_opc_lldp_start = 0x0A06, 276277082Sjfv i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 277277082Sjfv i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 278277082Sjfv i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 279266423Sjfv 280266423Sjfv /* Tunnel commands */ 281270346Sjfv i40e_aqc_opc_add_udp_tunnel = 0x0B00, 282270346Sjfv i40e_aqc_opc_del_udp_tunnel = 0x0B01, 283303967Ssbruno i40e_aqc_opc_set_rss_key = 0x0B02, 284303967Ssbruno i40e_aqc_opc_set_rss_lut = 0x0B03, 285303967Ssbruno i40e_aqc_opc_get_rss_key = 0x0B04, 286303967Ssbruno i40e_aqc_opc_get_rss_lut = 0x0B05, 287266423Sjfv 288266423Sjfv /* Async Events */ 289270346Sjfv i40e_aqc_opc_event_lan_overflow = 0x1001, 290266423Sjfv 291266423Sjfv /* OEM commands */ 292270346Sjfv i40e_aqc_opc_oem_parameter_change = 0xFE00, 293270346Sjfv i40e_aqc_opc_oem_device_status_change = 0xFE01, 294277082Sjfv i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 295277082Sjfv i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 296266423Sjfv 297266423Sjfv /* debug commands */ 298270346Sjfv i40e_aqc_opc_debug_read_reg = 0xFF03, 299270346Sjfv i40e_aqc_opc_debug_write_reg = 0xFF04, 300270346Sjfv i40e_aqc_opc_debug_modify_reg = 0xFF07, 301270346Sjfv i40e_aqc_opc_debug_dump_internals = 0xFF08, 302266423Sjfv}; 303266423Sjfv 304266423Sjfv/* command structures and indirect data structures */ 305266423Sjfv 306266423Sjfv/* Structure naming conventions: 307266423Sjfv * - no suffix for direct command descriptor structures 308266423Sjfv * - _data for indirect sent data 309266423Sjfv * - _resp for indirect return data (data which is both will use _data) 310266423Sjfv * - _completion for direct return data 311266423Sjfv * - _element_ for repeated elements (may also be _data or _resp) 312266423Sjfv * 313266423Sjfv * Command structures are expected to overlay the params.raw member of the basic 314266423Sjfv * descriptor, and as such cannot exceed 16 bytes in length. 315266423Sjfv */ 316266423Sjfv 317266423Sjfv/* This macro is used to generate a compilation error if a structure 318266423Sjfv * is not exactly the correct length. It gives a divide by zero error if the 319266423Sjfv * structure is not of the correct size, otherwise it creates an enum that is 320266423Sjfv * never used. 321266423Sjfv */ 322266423Sjfv#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 323266423Sjfv { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 324266423Sjfv 325266423Sjfv/* This macro is used extensively to ensure that command structures are 16 326266423Sjfv * bytes in length as they have to map to the raw array of that size. 327266423Sjfv */ 328270346Sjfv#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 329266423Sjfv 330266423Sjfv/* internal (0x00XX) commands */ 331266423Sjfv 332266423Sjfv/* Get version (direct 0x0001) */ 333266423Sjfvstruct i40e_aqc_get_version { 334266423Sjfv __le32 rom_ver; 335266423Sjfv __le32 fw_build; 336266423Sjfv __le16 fw_major; 337266423Sjfv __le16 fw_minor; 338266423Sjfv __le16 api_major; 339266423Sjfv __le16 api_minor; 340266423Sjfv}; 341266423Sjfv 342266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 343266423Sjfv 344266423Sjfv/* Send driver version (indirect 0x0002) */ 345266423Sjfvstruct i40e_aqc_driver_version { 346270346Sjfv u8 driver_major_ver; 347270346Sjfv u8 driver_minor_ver; 348270346Sjfv u8 driver_build_ver; 349270346Sjfv u8 driver_subbuild_ver; 350270346Sjfv u8 reserved[4]; 351270346Sjfv __le32 address_high; 352270346Sjfv __le32 address_low; 353266423Sjfv}; 354266423Sjfv 355266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 356266423Sjfv 357266423Sjfv/* Queue Shutdown (direct 0x0003) */ 358266423Sjfvstruct i40e_aqc_queue_shutdown { 359270346Sjfv __le32 driver_unloading; 360270346Sjfv#define I40E_AQ_DRIVER_UNLOADING 0x1 361270346Sjfv u8 reserved[12]; 362266423Sjfv}; 363266423Sjfv 364266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 365266423Sjfv 366266423Sjfv/* Set PF context (0x0004, direct) */ 367266423Sjfvstruct i40e_aqc_set_pf_context { 368266423Sjfv u8 pf_id; 369266423Sjfv u8 reserved[15]; 370266423Sjfv}; 371266423Sjfv 372266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 373266423Sjfv 374266423Sjfv/* Request resource ownership (direct 0x0008) 375266423Sjfv * Release resource ownership (direct 0x0009) 376266423Sjfv */ 377270346Sjfv#define I40E_AQ_RESOURCE_NVM 1 378270346Sjfv#define I40E_AQ_RESOURCE_SDP 2 379270346Sjfv#define I40E_AQ_RESOURCE_ACCESS_READ 1 380270346Sjfv#define I40E_AQ_RESOURCE_ACCESS_WRITE 2 381270346Sjfv#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 382270346Sjfv#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 383266423Sjfv 384266423Sjfvstruct i40e_aqc_request_resource { 385270346Sjfv __le16 resource_id; 386270346Sjfv __le16 access_type; 387270346Sjfv __le32 timeout; 388270346Sjfv __le32 resource_number; 389270346Sjfv u8 reserved[4]; 390266423Sjfv}; 391266423Sjfv 392266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 393266423Sjfv 394266423Sjfv/* Get function capabilities (indirect 0x000A) 395266423Sjfv * Get device capabilities (indirect 0x000B) 396266423Sjfv */ 397266423Sjfvstruct i40e_aqc_list_capabilites { 398266423Sjfv u8 command_flags; 399270346Sjfv#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 400266423Sjfv u8 pf_index; 401266423Sjfv u8 reserved[2]; 402266423Sjfv __le32 count; 403266423Sjfv __le32 addr_high; 404266423Sjfv __le32 addr_low; 405266423Sjfv}; 406266423Sjfv 407266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 408266423Sjfv 409266423Sjfvstruct i40e_aqc_list_capabilities_element_resp { 410270346Sjfv __le16 id; 411270346Sjfv u8 major_rev; 412270346Sjfv u8 minor_rev; 413270346Sjfv __le32 number; 414270346Sjfv __le32 logical_id; 415270346Sjfv __le32 phys_id; 416270346Sjfv u8 reserved[16]; 417266423Sjfv}; 418266423Sjfv 419266423Sjfv/* list of caps */ 420266423Sjfv 421270346Sjfv#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 422270346Sjfv#define I40E_AQ_CAP_ID_MNG_MODE 0x0002 423270346Sjfv#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 424270346Sjfv#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 425270346Sjfv#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 426270346Sjfv#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 427299548Serj#define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 428270346Sjfv#define I40E_AQ_CAP_ID_SRIOV 0x0012 429270346Sjfv#define I40E_AQ_CAP_ID_VF 0x0013 430270346Sjfv#define I40E_AQ_CAP_ID_VMDQ 0x0014 431270346Sjfv#define I40E_AQ_CAP_ID_8021QBG 0x0015 432270346Sjfv#define I40E_AQ_CAP_ID_8021QBR 0x0016 433270346Sjfv#define I40E_AQ_CAP_ID_VSI 0x0017 434270346Sjfv#define I40E_AQ_CAP_ID_DCB 0x0018 435270346Sjfv#define I40E_AQ_CAP_ID_FCOE 0x0021 436277082Sjfv#define I40E_AQ_CAP_ID_ISCSI 0x0022 437270346Sjfv#define I40E_AQ_CAP_ID_RSS 0x0040 438270346Sjfv#define I40E_AQ_CAP_ID_RXQ 0x0041 439270346Sjfv#define I40E_AQ_CAP_ID_TXQ 0x0042 440270346Sjfv#define I40E_AQ_CAP_ID_MSIX 0x0043 441270346Sjfv#define I40E_AQ_CAP_ID_VF_MSIX 0x0044 442270346Sjfv#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 443270346Sjfv#define I40E_AQ_CAP_ID_1588 0x0046 444270346Sjfv#define I40E_AQ_CAP_ID_IWARP 0x0051 445270346Sjfv#define I40E_AQ_CAP_ID_LED 0x0061 446270346Sjfv#define I40E_AQ_CAP_ID_SDP 0x0062 447270346Sjfv#define I40E_AQ_CAP_ID_MDIO 0x0063 448299548Serj#define I40E_AQ_CAP_ID_WSR_PROT 0x0064 449303967Ssbruno#define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 450270346Sjfv#define I40E_AQ_CAP_ID_FLEX10 0x00F1 451270346Sjfv#define I40E_AQ_CAP_ID_CEM 0x00F2 452266423Sjfv 453266423Sjfv/* Set CPPM Configuration (direct 0x0103) */ 454266423Sjfvstruct i40e_aqc_cppm_configuration { 455270346Sjfv __le16 command_flags; 456270346Sjfv#define I40E_AQ_CPPM_EN_LTRC 0x0800 457270346Sjfv#define I40E_AQ_CPPM_EN_DMCTH 0x1000 458270346Sjfv#define I40E_AQ_CPPM_EN_DMCTLX 0x2000 459270346Sjfv#define I40E_AQ_CPPM_EN_HPTC 0x4000 460270346Sjfv#define I40E_AQ_CPPM_EN_DMARC 0x8000 461270346Sjfv __le16 ttlx; 462270346Sjfv __le32 dmacr; 463270346Sjfv __le16 dmcth; 464270346Sjfv u8 hptc; 465270346Sjfv u8 reserved; 466270346Sjfv __le32 pfltrc; 467266423Sjfv}; 468266423Sjfv 469266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 470266423Sjfv 471266423Sjfv/* Set ARP Proxy command / response (indirect 0x0104) */ 472266423Sjfvstruct i40e_aqc_arp_proxy_data { 473270346Sjfv __le16 command_flags; 474303967Ssbruno#define I40E_AQ_ARP_INIT_IPV4 0x0800 475303967Ssbruno#define I40E_AQ_ARP_UNSUP_CTL 0x1000 476303967Ssbruno#define I40E_AQ_ARP_ENA 0x2000 477303967Ssbruno#define I40E_AQ_ARP_ADD_IPV4 0x4000 478303967Ssbruno#define I40E_AQ_ARP_DEL_IPV4 0x8000 479270346Sjfv __le16 table_id; 480303967Ssbruno __le32 enabled_offloads; 481303967Ssbruno#define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 482303967Ssbruno#define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 483270346Sjfv __le32 ip_addr; 484270346Sjfv u8 mac_addr[6]; 485277082Sjfv u8 reserved[2]; 486266423Sjfv}; 487266423Sjfv 488277082SjfvI40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 489277082Sjfv 490266423Sjfv/* Set NS Proxy Table Entry Command (indirect 0x0105) */ 491266423Sjfvstruct i40e_aqc_ns_proxy_data { 492270346Sjfv __le16 table_idx_mac_addr_0; 493270346Sjfv __le16 table_idx_mac_addr_1; 494270346Sjfv __le16 table_idx_ipv6_0; 495270346Sjfv __le16 table_idx_ipv6_1; 496270346Sjfv __le16 control; 497303967Ssbruno#define I40E_AQ_NS_PROXY_ADD_0 0x0001 498303967Ssbruno#define I40E_AQ_NS_PROXY_DEL_0 0x0002 499303967Ssbruno#define I40E_AQ_NS_PROXY_ADD_1 0x0004 500303967Ssbruno#define I40E_AQ_NS_PROXY_DEL_1 0x0008 501303967Ssbruno#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 502303967Ssbruno#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 503303967Ssbruno#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 504303967Ssbruno#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 505303967Ssbruno#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 506303967Ssbruno#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 507303967Ssbruno#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 508303967Ssbruno#define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 509303967Ssbruno#define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 510270346Sjfv u8 mac_addr_0[6]; 511270346Sjfv u8 mac_addr_1[6]; 512270346Sjfv u8 local_mac_addr[6]; 513270346Sjfv u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 514270346Sjfv u8 ipv6_addr_1[16]; 515266423Sjfv}; 516266423Sjfv 517277082SjfvI40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 518277082Sjfv 519266423Sjfv/* Manage LAA Command (0x0106) - obsolete */ 520266423Sjfvstruct i40e_aqc_mng_laa { 521266423Sjfv __le16 command_flags; 522270346Sjfv#define I40E_AQ_LAA_FLAG_WR 0x8000 523270346Sjfv u8 reserved[2]; 524270346Sjfv __le32 sal; 525270346Sjfv __le16 sah; 526270346Sjfv u8 reserved2[6]; 527266423Sjfv}; 528266423Sjfv 529277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 530277082Sjfv 531266423Sjfv/* Manage MAC Address Read Command (indirect 0x0107) */ 532266423Sjfvstruct i40e_aqc_mac_address_read { 533266423Sjfv __le16 command_flags; 534270346Sjfv#define I40E_AQC_LAN_ADDR_VALID 0x10 535270346Sjfv#define I40E_AQC_SAN_ADDR_VALID 0x20 536270346Sjfv#define I40E_AQC_PORT_ADDR_VALID 0x40 537270346Sjfv#define I40E_AQC_WOL_ADDR_VALID 0x80 538284049Sjfv#define I40E_AQC_MC_MAG_EN_VALID 0x100 539318357Serj#define I40E_AQC_WOL_PRESERVE_STATUS 0x200 540318357Serj#define I40E_AQC_ADDR_VALID_MASK 0x3F0 541270346Sjfv u8 reserved[6]; 542270346Sjfv __le32 addr_high; 543270346Sjfv __le32 addr_low; 544266423Sjfv}; 545266423Sjfv 546266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 547266423Sjfv 548266423Sjfvstruct i40e_aqc_mac_address_read_data { 549266423Sjfv u8 pf_lan_mac[6]; 550266423Sjfv u8 pf_san_mac[6]; 551266423Sjfv u8 port_mac[6]; 552266423Sjfv u8 pf_wol_mac[6]; 553266423Sjfv}; 554266423Sjfv 555266423SjfvI40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 556266423Sjfv 557266423Sjfv/* Manage MAC Address Write Command (0x0108) */ 558266423Sjfvstruct i40e_aqc_mac_address_write { 559270346Sjfv __le16 command_flags; 560303967Ssbruno#define I40E_AQC_MC_MAG_EN 0x0100 561318357Serj#define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200 562270346Sjfv#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 563270346Sjfv#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 564270346Sjfv#define I40E_AQC_WRITE_TYPE_PORT 0x8000 565284049Sjfv#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 566284049Sjfv#define I40E_AQC_WRITE_TYPE_MASK 0xC000 567284049Sjfv 568270346Sjfv __le16 mac_sah; 569270346Sjfv __le32 mac_sal; 570270346Sjfv u8 reserved[8]; 571266423Sjfv}; 572266423Sjfv 573266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 574266423Sjfv 575266423Sjfv/* PXE commands (0x011x) */ 576266423Sjfv 577266423Sjfv/* Clear PXE Command and response (direct 0x0110) */ 578266423Sjfvstruct i40e_aqc_clear_pxe { 579266423Sjfv u8 rx_cnt; 580266423Sjfv u8 reserved[15]; 581266423Sjfv}; 582266423Sjfv 583266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 584266423Sjfv 585303967Ssbruno/* Set WoL Filter (0x0120) */ 586303967Ssbruno 587303967Ssbrunostruct i40e_aqc_set_wol_filter { 588303967Ssbruno __le16 filter_index; 589303967Ssbruno#define I40E_AQC_MAX_NUM_WOL_FILTERS 8 590303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 591303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ 592303967Ssbruno I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) 593303967Ssbruno 594303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 595303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ 596303967Ssbruno I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) 597303967Ssbruno __le16 cmd_flags; 598303967Ssbruno#define I40E_AQC_SET_WOL_FILTER 0x8000 599303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 600318357Serj#define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000 601303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 602303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 603303967Ssbruno __le16 valid_flags; 604303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 605303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 606303967Ssbruno u8 reserved[2]; 607303967Ssbruno __le32 address_high; 608303967Ssbruno __le32 address_low; 609303967Ssbruno}; 610303967Ssbruno 611303967SsbrunoI40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); 612303967Ssbruno 613303967Ssbrunostruct i40e_aqc_set_wol_filter_data { 614303967Ssbruno u8 filter[128]; 615303967Ssbruno u8 mask[16]; 616303967Ssbruno}; 617303967Ssbruno 618303967SsbrunoI40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); 619303967Ssbruno 620303967Ssbruno/* Get Wake Reason (0x0121) */ 621303967Ssbruno 622303967Ssbrunostruct i40e_aqc_get_wake_reason_completion { 623303967Ssbruno u8 reserved_1[2]; 624303967Ssbruno __le16 wake_reason; 625303967Ssbruno#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 626303967Ssbruno#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ 627303967Ssbruno I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) 628303967Ssbruno#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 629303967Ssbruno#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ 630303967Ssbruno I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) 631303967Ssbruno u8 reserved_2[12]; 632303967Ssbruno}; 633303967Ssbruno 634303967SsbrunoI40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); 635303967Ssbruno 636266423Sjfv/* Switch configuration commands (0x02xx) */ 637266423Sjfv 638266423Sjfv/* Used by many indirect commands that only pass an seid and a buffer in the 639266423Sjfv * command 640266423Sjfv */ 641266423Sjfvstruct i40e_aqc_switch_seid { 642270346Sjfv __le16 seid; 643270346Sjfv u8 reserved[6]; 644270346Sjfv __le32 addr_high; 645270346Sjfv __le32 addr_low; 646266423Sjfv}; 647266423Sjfv 648266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 649266423Sjfv 650266423Sjfv/* Get Switch Configuration command (indirect 0x0200) 651266423Sjfv * uses i40e_aqc_switch_seid for the descriptor 652266423Sjfv */ 653266423Sjfvstruct i40e_aqc_get_switch_config_header_resp { 654270346Sjfv __le16 num_reported; 655270346Sjfv __le16 num_total; 656270346Sjfv u8 reserved[12]; 657266423Sjfv}; 658266423Sjfv 659277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 660277082Sjfv 661266423Sjfvstruct i40e_aqc_switch_config_element_resp { 662270346Sjfv u8 element_type; 663270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_MAC 1 664270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_PF 2 665270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_VF 3 666270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_EMP 4 667270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_BMC 5 668270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_PV 16 669270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_VEB 17 670270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_PA 18 671270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_VSI 19 672270346Sjfv u8 revision; 673270346Sjfv#define I40E_AQ_SW_ELEM_REV_1 1 674270346Sjfv __le16 seid; 675270346Sjfv __le16 uplink_seid; 676270346Sjfv __le16 downlink_seid; 677270346Sjfv u8 reserved[3]; 678270346Sjfv u8 connection_type; 679270346Sjfv#define I40E_AQ_CONN_TYPE_REGULAR 0x1 680270346Sjfv#define I40E_AQ_CONN_TYPE_DEFAULT 0x2 681270346Sjfv#define I40E_AQ_CONN_TYPE_CASCADED 0x3 682270346Sjfv __le16 scheduler_id; 683270346Sjfv __le16 element_info; 684266423Sjfv}; 685266423Sjfv 686277082SjfvI40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 687277082Sjfv 688266423Sjfv/* Get Switch Configuration (indirect 0x0200) 689266423Sjfv * an array of elements are returned in the response buffer 690266423Sjfv * the first in the array is the header, remainder are elements 691266423Sjfv */ 692266423Sjfvstruct i40e_aqc_get_switch_config_resp { 693270346Sjfv struct i40e_aqc_get_switch_config_header_resp header; 694270346Sjfv struct i40e_aqc_switch_config_element_resp element[1]; 695266423Sjfv}; 696266423Sjfv 697277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 698277082Sjfv 699266423Sjfv/* Add Statistics (direct 0x0201) 700266423Sjfv * Remove Statistics (direct 0x0202) 701266423Sjfv */ 702266423Sjfvstruct i40e_aqc_add_remove_statistics { 703270346Sjfv __le16 seid; 704270346Sjfv __le16 vlan; 705270346Sjfv __le16 stat_index; 706270346Sjfv u8 reserved[10]; 707266423Sjfv}; 708266423Sjfv 709266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 710266423Sjfv 711266423Sjfv/* Set Port Parameters command (direct 0x0203) */ 712266423Sjfvstruct i40e_aqc_set_port_parameters { 713270346Sjfv __le16 command_flags; 714270346Sjfv#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 715270346Sjfv#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 716270346Sjfv#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 717270346Sjfv __le16 bad_frame_vsi; 718303967Ssbruno#define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 719303967Ssbruno#define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF 720270346Sjfv __le16 default_seid; /* reserved for command */ 721270346Sjfv u8 reserved[10]; 722266423Sjfv}; 723266423Sjfv 724266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 725266423Sjfv 726266423Sjfv/* Get Switch Resource Allocation (indirect 0x0204) */ 727266423Sjfvstruct i40e_aqc_get_switch_resource_alloc { 728270346Sjfv u8 num_entries; /* reserved for command */ 729270346Sjfv u8 reserved[7]; 730270346Sjfv __le32 addr_high; 731270346Sjfv __le32 addr_low; 732266423Sjfv}; 733266423Sjfv 734266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 735266423Sjfv 736266423Sjfv/* expect an array of these structs in the response buffer */ 737266423Sjfvstruct i40e_aqc_switch_resource_alloc_element_resp { 738270346Sjfv u8 resource_type; 739270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VEB 0x0 740270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VSI 0x1 741270346Sjfv#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 742270346Sjfv#define I40E_AQ_RESOURCE_TYPE_STAG 0x3 743270346Sjfv#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 744270346Sjfv#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 745270346Sjfv#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 746270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 747270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 748270346Sjfv#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 749270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 750270346Sjfv#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 751270346Sjfv#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 752270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 753270346Sjfv#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 754270346Sjfv#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 755270346Sjfv#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 756270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 757270346Sjfv#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 758270346Sjfv u8 reserved1; 759270346Sjfv __le16 guaranteed; 760270346Sjfv __le16 total; 761270346Sjfv __le16 used; 762270346Sjfv __le16 total_unalloced; 763270346Sjfv u8 reserved2[6]; 764266423Sjfv}; 765266423Sjfv 766277082SjfvI40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 767277082Sjfv 768299549Serj/* Set Switch Configuration (direct 0x0205) */ 769299549Serjstruct i40e_aqc_set_switch_config { 770299549Serj __le16 flags; 771303967Ssbruno/* flags used for both fields below */ 772299549Serj#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 773299549Serj#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 774299549Serj __le16 valid_flags; 775299549Serj u8 reserved[12]; 776299549Serj}; 777299549Serj 778299549SerjI40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 779299549Serj 780299555Serj/* Read Receive control registers (direct 0x0206) 781299555Serj * Write Receive control registers (direct 0x0207) 782299555Serj * used for accessing Rx control registers that can be 783299555Serj * slow and need special handling when under high Rx load 784299555Serj */ 785299555Serjstruct i40e_aqc_rx_ctl_reg_read_write { 786299555Serj __le32 reserved1; 787299555Serj __le32 address; 788299555Serj __le32 reserved2; 789299555Serj __le32 value; 790299555Serj}; 791299555Serj 792299555SerjI40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 793299555Serj 794266423Sjfv/* Add VSI (indirect 0x0210) 795266423Sjfv * this indirect command uses struct i40e_aqc_vsi_properties_data 796266423Sjfv * as the indirect buffer (128 bytes) 797266423Sjfv * 798266423Sjfv * Update VSI (indirect 0x211) 799266423Sjfv * uses the same data structure as Add VSI 800266423Sjfv * 801266423Sjfv * Get VSI (indirect 0x0212) 802266423Sjfv * uses the same completion and data structure as Add VSI 803266423Sjfv */ 804266423Sjfvstruct i40e_aqc_add_get_update_vsi { 805270346Sjfv __le16 uplink_seid; 806270346Sjfv u8 connection_type; 807270346Sjfv#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 808270346Sjfv#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 809270346Sjfv#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 810270346Sjfv u8 reserved1; 811270346Sjfv u8 vf_id; 812270346Sjfv u8 reserved2; 813270346Sjfv __le16 vsi_flags; 814270346Sjfv#define I40E_AQ_VSI_TYPE_SHIFT 0x0 815270346Sjfv#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 816270346Sjfv#define I40E_AQ_VSI_TYPE_VF 0x0 817270346Sjfv#define I40E_AQ_VSI_TYPE_VMDQ2 0x1 818270346Sjfv#define I40E_AQ_VSI_TYPE_PF 0x2 819270346Sjfv#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 820270346Sjfv#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 821270346Sjfv __le32 addr_high; 822270346Sjfv __le32 addr_low; 823266423Sjfv}; 824266423Sjfv 825266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 826266423Sjfv 827266423Sjfvstruct i40e_aqc_add_get_update_vsi_completion { 828266423Sjfv __le16 seid; 829266423Sjfv __le16 vsi_number; 830266423Sjfv __le16 vsi_used; 831266423Sjfv __le16 vsi_free; 832266423Sjfv __le32 addr_high; 833266423Sjfv __le32 addr_low; 834266423Sjfv}; 835266423Sjfv 836266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 837266423Sjfv 838266423Sjfvstruct i40e_aqc_vsi_properties_data { 839266423Sjfv /* first 96 byte are written by SW */ 840270346Sjfv __le16 valid_sections; 841270346Sjfv#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 842270346Sjfv#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 843270346Sjfv#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 844270346Sjfv#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 845270346Sjfv#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 846270346Sjfv#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 847270346Sjfv#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 848270346Sjfv#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 849270346Sjfv#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 850270346Sjfv#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 851266423Sjfv /* switch section */ 852270346Sjfv __le16 switch_id; /* 12bit id combined with flags below */ 853270346Sjfv#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 854270346Sjfv#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 855270346Sjfv#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 856270346Sjfv#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 857270346Sjfv#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 858270346Sjfv u8 sw_reserved[2]; 859266423Sjfv /* security section */ 860270346Sjfv u8 sec_flags; 861270346Sjfv#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 862270346Sjfv#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 863270346Sjfv#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 864270346Sjfv u8 sec_reserved; 865266423Sjfv /* VLAN section */ 866270346Sjfv __le16 pvid; /* VLANS include priority bits */ 867270346Sjfv __le16 fcoe_pvid; 868270346Sjfv u8 port_vlan_flags; 869270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 870270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 871270346Sjfv I40E_AQ_VSI_PVLAN_MODE_SHIFT) 872270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 873270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 874270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 875270346Sjfv#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 876270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 877270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 878270346Sjfv I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 879270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 880270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 881270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 882270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 883270346Sjfv u8 pvlan_reserved[3]; 884266423Sjfv /* ingress egress up sections */ 885270346Sjfv __le32 ingress_table; /* bitmap, 3 bits per up */ 886270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 887270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 888270346Sjfv I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 889270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 890270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 891270346Sjfv I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 892270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 893270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 894270346Sjfv I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 895270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 896270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 897270346Sjfv I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 898270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 899270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 900270346Sjfv I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 901270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 902270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 903270346Sjfv I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 904270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 905270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 906270346Sjfv I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 907270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 908270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 909270346Sjfv I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 910270346Sjfv __le32 egress_table; /* same defines as for ingress table */ 911266423Sjfv /* cascaded PV section */ 912270346Sjfv __le16 cas_pv_tag; 913270346Sjfv u8 cas_pv_flags; 914270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 915270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 916270346Sjfv I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 917270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 918270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 919270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 920270346Sjfv#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 921270346Sjfv#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 922270346Sjfv#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 923270346Sjfv u8 cas_pv_reserved; 924266423Sjfv /* queue mapping section */ 925270346Sjfv __le16 mapping_flags; 926270346Sjfv#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 927270346Sjfv#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 928270346Sjfv __le16 queue_mapping[16]; 929270346Sjfv#define I40E_AQ_VSI_QUEUE_SHIFT 0x0 930270346Sjfv#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 931270346Sjfv __le16 tc_mapping[8]; 932270346Sjfv#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 933270346Sjfv#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 934270346Sjfv I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 935270346Sjfv#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 936270346Sjfv#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 937270346Sjfv I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 938266423Sjfv /* queueing option section */ 939270346Sjfv u8 queueing_opt_flags; 940303967Ssbruno#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 941303967Ssbruno#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 942270346Sjfv#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 943270346Sjfv#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 944303967Ssbruno#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 945303967Ssbruno#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 946270346Sjfv u8 queueing_opt_reserved[3]; 947266423Sjfv /* scheduler section */ 948270346Sjfv u8 up_enable_bits; 949270346Sjfv u8 sched_reserved; 950266423Sjfv /* outer up section */ 951299555Serj __le32 outer_up_table; /* same structure and defines as ingress tbl */ 952270346Sjfv u8 cmd_reserved[8]; 953266423Sjfv /* last 32 bytes are written by FW */ 954270346Sjfv __le16 qs_handle[8]; 955266423Sjfv#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 956270346Sjfv __le16 stat_counter_idx; 957270346Sjfv __le16 sched_id; 958270346Sjfv u8 resp_reserved[12]; 959266423Sjfv}; 960266423Sjfv 961266423SjfvI40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 962266423Sjfv 963266423Sjfv/* Add Port Virtualizer (direct 0x0220) 964266423Sjfv * also used for update PV (direct 0x0221) but only flags are used 965266423Sjfv * (IS_CTRL_PORT only works on add PV) 966266423Sjfv */ 967266423Sjfvstruct i40e_aqc_add_update_pv { 968270346Sjfv __le16 command_flags; 969270346Sjfv#define I40E_AQC_PV_FLAG_PV_TYPE 0x1 970270346Sjfv#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 971270346Sjfv#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 972270346Sjfv#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 973270346Sjfv __le16 uplink_seid; 974270346Sjfv __le16 connected_seid; 975270346Sjfv u8 reserved[10]; 976266423Sjfv}; 977266423Sjfv 978266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 979266423Sjfv 980266423Sjfvstruct i40e_aqc_add_update_pv_completion { 981266423Sjfv /* reserved for update; for add also encodes error if rc == ENOSPC */ 982270346Sjfv __le16 pv_seid; 983270346Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 984270346Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 985270346Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 986270346Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 987270346Sjfv u8 reserved[14]; 988266423Sjfv}; 989266423Sjfv 990266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 991266423Sjfv 992266423Sjfv/* Get PV Params (direct 0x0222) 993266423Sjfv * uses i40e_aqc_switch_seid for the descriptor 994266423Sjfv */ 995266423Sjfv 996266423Sjfvstruct i40e_aqc_get_pv_params_completion { 997270346Sjfv __le16 seid; 998270346Sjfv __le16 default_stag; 999270346Sjfv __le16 pv_flags; /* same flags as add_pv */ 1000270346Sjfv#define I40E_AQC_GET_PV_PV_TYPE 0x1 1001270346Sjfv#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 1002270346Sjfv#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 1003270346Sjfv u8 reserved[8]; 1004270346Sjfv __le16 default_port_seid; 1005266423Sjfv}; 1006266423Sjfv 1007266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 1008266423Sjfv 1009266423Sjfv/* Add VEB (direct 0x0230) */ 1010266423Sjfvstruct i40e_aqc_add_veb { 1011270346Sjfv __le16 uplink_seid; 1012270346Sjfv __le16 downlink_seid; 1013270346Sjfv __le16 veb_flags; 1014270346Sjfv#define I40E_AQC_ADD_VEB_FLOATING 0x1 1015270346Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 1016270346Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 1017266423Sjfv I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 1018270346Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 1019270346Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 1020299549Serj#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 1021299549Serj#define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 1022270346Sjfv u8 enable_tcs; 1023270346Sjfv u8 reserved[9]; 1024266423Sjfv}; 1025266423Sjfv 1026266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 1027266423Sjfv 1028266423Sjfvstruct i40e_aqc_add_veb_completion { 1029270346Sjfv u8 reserved[6]; 1030270346Sjfv __le16 switch_seid; 1031266423Sjfv /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 1032270346Sjfv __le16 veb_seid; 1033270346Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 1034270346Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 1035270346Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 1036270346Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 1037270346Sjfv __le16 statistic_index; 1038270346Sjfv __le16 vebs_used; 1039270346Sjfv __le16 vebs_free; 1040266423Sjfv}; 1041266423Sjfv 1042266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 1043266423Sjfv 1044266423Sjfv/* Get VEB Parameters (direct 0x0232) 1045266423Sjfv * uses i40e_aqc_switch_seid for the descriptor 1046266423Sjfv */ 1047266423Sjfvstruct i40e_aqc_get_veb_parameters_completion { 1048270346Sjfv __le16 seid; 1049270346Sjfv __le16 switch_id; 1050270346Sjfv __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 1051270346Sjfv __le16 statistic_index; 1052270346Sjfv __le16 vebs_used; 1053270346Sjfv __le16 vebs_free; 1054270346Sjfv u8 reserved[4]; 1055266423Sjfv}; 1056266423Sjfv 1057266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 1058266423Sjfv 1059266423Sjfv/* Delete Element (direct 0x0243) 1060266423Sjfv * uses the generic i40e_aqc_switch_seid 1061266423Sjfv */ 1062266423Sjfv 1063266423Sjfv/* Add MAC-VLAN (indirect 0x0250) */ 1064266423Sjfv 1065266423Sjfv/* used for the command for most vlan commands */ 1066266423Sjfvstruct i40e_aqc_macvlan { 1067270346Sjfv __le16 num_addresses; 1068270346Sjfv __le16 seid[3]; 1069270346Sjfv#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 1070270346Sjfv#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 1071266423Sjfv I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1072270346Sjfv#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 1073270346Sjfv __le32 addr_high; 1074270346Sjfv __le32 addr_low; 1075266423Sjfv}; 1076266423Sjfv 1077266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 1078266423Sjfv 1079266423Sjfv/* indirect data for command and response */ 1080266423Sjfvstruct i40e_aqc_add_macvlan_element_data { 1081270346Sjfv u8 mac_addr[6]; 1082270346Sjfv __le16 vlan_tag; 1083270346Sjfv __le16 flags; 1084270346Sjfv#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 1085270346Sjfv#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 1086270346Sjfv#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 1087270346Sjfv#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 1088299549Serj#define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 1089270346Sjfv __le16 queue_number; 1090270346Sjfv#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 1091270346Sjfv#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 1092266423Sjfv I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1093266423Sjfv /* response section */ 1094270346Sjfv u8 match_method; 1095270346Sjfv#define I40E_AQC_MM_PERFECT_MATCH 0x01 1096270346Sjfv#define I40E_AQC_MM_HASH_MATCH 0x02 1097270346Sjfv#define I40E_AQC_MM_ERR_NO_RES 0xFF 1098270346Sjfv u8 reserved1[3]; 1099266423Sjfv}; 1100266423Sjfv 1101266423Sjfvstruct i40e_aqc_add_remove_macvlan_completion { 1102266423Sjfv __le16 perfect_mac_used; 1103266423Sjfv __le16 perfect_mac_free; 1104266423Sjfv __le16 unicast_hash_free; 1105266423Sjfv __le16 multicast_hash_free; 1106266423Sjfv __le32 addr_high; 1107266423Sjfv __le32 addr_low; 1108266423Sjfv}; 1109266423Sjfv 1110266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1111266423Sjfv 1112266423Sjfv/* Remove MAC-VLAN (indirect 0x0251) 1113266423Sjfv * uses i40e_aqc_macvlan for the descriptor 1114266423Sjfv * data points to an array of num_addresses of elements 1115266423Sjfv */ 1116266423Sjfv 1117266423Sjfvstruct i40e_aqc_remove_macvlan_element_data { 1118270346Sjfv u8 mac_addr[6]; 1119270346Sjfv __le16 vlan_tag; 1120270346Sjfv u8 flags; 1121270346Sjfv#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1122270346Sjfv#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1123270346Sjfv#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1124270346Sjfv#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1125270346Sjfv u8 reserved[3]; 1126266423Sjfv /* reply section */ 1127270346Sjfv u8 error_code; 1128270346Sjfv#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1129270346Sjfv#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1130270346Sjfv u8 reply_reserved[3]; 1131266423Sjfv}; 1132266423Sjfv 1133266423Sjfv/* Add VLAN (indirect 0x0252) 1134266423Sjfv * Remove VLAN (indirect 0x0253) 1135266423Sjfv * use the generic i40e_aqc_macvlan for the command 1136266423Sjfv */ 1137266423Sjfvstruct i40e_aqc_add_remove_vlan_element_data { 1138270346Sjfv __le16 vlan_tag; 1139270346Sjfv u8 vlan_flags; 1140266423Sjfv/* flags for add VLAN */ 1141270346Sjfv#define I40E_AQC_ADD_VLAN_LOCAL 0x1 1142270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1143270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1144270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1145270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1146270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1147270346Sjfv#define I40E_AQC_VLAN_PTYPE_SHIFT 3 1148270346Sjfv#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1149270346Sjfv#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1150270346Sjfv#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1151270346Sjfv#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1152270346Sjfv#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1153266423Sjfv/* flags for remove VLAN */ 1154270346Sjfv#define I40E_AQC_REMOVE_VLAN_ALL 0x1 1155270346Sjfv u8 reserved; 1156270346Sjfv u8 result; 1157266423Sjfv/* flags for add VLAN */ 1158270346Sjfv#define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1159270346Sjfv#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1160270346Sjfv#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1161266423Sjfv/* flags for remove VLAN */ 1162270346Sjfv#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1163270346Sjfv#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1164270346Sjfv u8 reserved1[3]; 1165266423Sjfv}; 1166266423Sjfv 1167266423Sjfvstruct i40e_aqc_add_remove_vlan_completion { 1168270346Sjfv u8 reserved[4]; 1169270346Sjfv __le16 vlans_used; 1170270346Sjfv __le16 vlans_free; 1171270346Sjfv __le32 addr_high; 1172270346Sjfv __le32 addr_low; 1173266423Sjfv}; 1174266423Sjfv 1175266423Sjfv/* Set VSI Promiscuous Modes (direct 0x0254) */ 1176266423Sjfvstruct i40e_aqc_set_vsi_promiscuous_modes { 1177270346Sjfv __le16 promiscuous_flags; 1178270346Sjfv __le16 valid_flags; 1179266423Sjfv/* flags used for both fields above */ 1180270346Sjfv#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1181270346Sjfv#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1182270346Sjfv#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1183270346Sjfv#define I40E_AQC_SET_VSI_DEFAULT 0x08 1184270346Sjfv#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1185299554Serj#define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 1186270346Sjfv __le16 seid; 1187270346Sjfv#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1188270346Sjfv __le16 vlan_tag; 1189284049Sjfv#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1190270346Sjfv#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1191270346Sjfv u8 reserved[8]; 1192266423Sjfv}; 1193266423Sjfv 1194266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1195266423Sjfv 1196266423Sjfv/* Add S/E-tag command (direct 0x0255) 1197266423Sjfv * Uses generic i40e_aqc_add_remove_tag_completion for completion 1198266423Sjfv */ 1199266423Sjfvstruct i40e_aqc_add_tag { 1200270346Sjfv __le16 flags; 1201270346Sjfv#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1202270346Sjfv __le16 seid; 1203270346Sjfv#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1204270346Sjfv#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1205266423Sjfv I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1206270346Sjfv __le16 tag; 1207270346Sjfv __le16 queue_number; 1208270346Sjfv u8 reserved[8]; 1209266423Sjfv}; 1210266423Sjfv 1211266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1212266423Sjfv 1213266423Sjfvstruct i40e_aqc_add_remove_tag_completion { 1214270346Sjfv u8 reserved[12]; 1215270346Sjfv __le16 tags_used; 1216270346Sjfv __le16 tags_free; 1217266423Sjfv}; 1218266423Sjfv 1219266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1220266423Sjfv 1221266423Sjfv/* Remove S/E-tag command (direct 0x0256) 1222266423Sjfv * Uses generic i40e_aqc_add_remove_tag_completion for completion 1223266423Sjfv */ 1224266423Sjfvstruct i40e_aqc_remove_tag { 1225270346Sjfv __le16 seid; 1226270346Sjfv#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1227270346Sjfv#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1228266423Sjfv I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1229270346Sjfv __le16 tag; 1230270346Sjfv u8 reserved[12]; 1231266423Sjfv}; 1232266423Sjfv 1233277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1234277082Sjfv 1235266423Sjfv/* Add multicast E-Tag (direct 0x0257) 1236266423Sjfv * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1237266423Sjfv * and no external data 1238266423Sjfv */ 1239266423Sjfvstruct i40e_aqc_add_remove_mcast_etag { 1240270346Sjfv __le16 pv_seid; 1241270346Sjfv __le16 etag; 1242270346Sjfv u8 num_unicast_etags; 1243270346Sjfv u8 reserved[3]; 1244270346Sjfv __le32 addr_high; /* address of array of 2-byte s-tags */ 1245270346Sjfv __le32 addr_low; 1246266423Sjfv}; 1247266423Sjfv 1248266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1249266423Sjfv 1250266423Sjfvstruct i40e_aqc_add_remove_mcast_etag_completion { 1251270346Sjfv u8 reserved[4]; 1252270346Sjfv __le16 mcast_etags_used; 1253270346Sjfv __le16 mcast_etags_free; 1254270346Sjfv __le32 addr_high; 1255270346Sjfv __le32 addr_low; 1256266423Sjfv 1257266423Sjfv}; 1258266423Sjfv 1259266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1260266423Sjfv 1261266423Sjfv/* Update S/E-Tag (direct 0x0259) */ 1262266423Sjfvstruct i40e_aqc_update_tag { 1263270346Sjfv __le16 seid; 1264270346Sjfv#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1265270346Sjfv#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1266266423Sjfv I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1267270346Sjfv __le16 old_tag; 1268270346Sjfv __le16 new_tag; 1269270346Sjfv u8 reserved[10]; 1270266423Sjfv}; 1271266423Sjfv 1272266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1273266423Sjfv 1274266423Sjfvstruct i40e_aqc_update_tag_completion { 1275270346Sjfv u8 reserved[12]; 1276270346Sjfv __le16 tags_used; 1277270346Sjfv __le16 tags_free; 1278266423Sjfv}; 1279266423Sjfv 1280266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1281266423Sjfv 1282266423Sjfv/* Add Control Packet filter (direct 0x025A) 1283266423Sjfv * Remove Control Packet filter (direct 0x025B) 1284266423Sjfv * uses the i40e_aqc_add_oveb_cloud, 1285266423Sjfv * and the generic direct completion structure 1286266423Sjfv */ 1287266423Sjfvstruct i40e_aqc_add_remove_control_packet_filter { 1288270346Sjfv u8 mac[6]; 1289270346Sjfv __le16 etype; 1290270346Sjfv __le16 flags; 1291270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1292270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1293270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1294270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1295270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1296270346Sjfv __le16 seid; 1297270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1298270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1299266423Sjfv I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1300270346Sjfv __le16 queue; 1301270346Sjfv u8 reserved[2]; 1302266423Sjfv}; 1303266423Sjfv 1304266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1305266423Sjfv 1306266423Sjfvstruct i40e_aqc_add_remove_control_packet_filter_completion { 1307270346Sjfv __le16 mac_etype_used; 1308270346Sjfv __le16 etype_used; 1309270346Sjfv __le16 mac_etype_free; 1310270346Sjfv __le16 etype_free; 1311270346Sjfv u8 reserved[8]; 1312266423Sjfv}; 1313266423Sjfv 1314266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1315266423Sjfv 1316266423Sjfv/* Add Cloud filters (indirect 0x025C) 1317266423Sjfv * Remove Cloud filters (indirect 0x025D) 1318266423Sjfv * uses the i40e_aqc_add_remove_cloud_filters, 1319266423Sjfv * and the generic indirect completion structure 1320266423Sjfv */ 1321266423Sjfvstruct i40e_aqc_add_remove_cloud_filters { 1322270346Sjfv u8 num_filters; 1323270346Sjfv u8 reserved; 1324270346Sjfv __le16 seid; 1325270346Sjfv#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1326270346Sjfv#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1327266423Sjfv I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1328270346Sjfv u8 reserved2[4]; 1329270346Sjfv __le32 addr_high; 1330270346Sjfv __le32 addr_low; 1331266423Sjfv}; 1332266423Sjfv 1333266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1334266423Sjfv 1335266423Sjfvstruct i40e_aqc_add_remove_cloud_filters_element_data { 1336270346Sjfv u8 outer_mac[6]; 1337270346Sjfv u8 inner_mac[6]; 1338270346Sjfv __le16 inner_vlan; 1339266423Sjfv union { 1340266423Sjfv struct { 1341266423Sjfv u8 reserved[12]; 1342266423Sjfv u8 data[4]; 1343266423Sjfv } v4; 1344266423Sjfv struct { 1345266423Sjfv u8 data[16]; 1346266423Sjfv } v6; 1347266423Sjfv } ipaddr; 1348270346Sjfv __le16 flags; 1349270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1350277082Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1351266423Sjfv I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1352266423Sjfv/* 0x0000 reserved */ 1353270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1354266423Sjfv/* 0x0002 reserved */ 1355270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1356270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1357266423Sjfv/* 0x0005 reserved */ 1358270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1359266423Sjfv/* 0x0007 reserved */ 1360266423Sjfv/* 0x0008 reserved */ 1361270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1362270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1363270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1364270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1365266423Sjfv 1366270346Sjfv#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1367270346Sjfv#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1368270346Sjfv#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1369270346Sjfv#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1370270346Sjfv#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1371266423Sjfv 1372270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1373270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1374299549Serj#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1375270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1376299549Serj#define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1377270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1378299549Serj#define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1379299549Serj#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1380266423Sjfv 1381299549Serj#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1382299549Serj#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1383299549Serj#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1384299549Serj 1385270346Sjfv __le32 tenant_id; 1386270346Sjfv u8 reserved[4]; 1387270346Sjfv __le16 queue_number; 1388270346Sjfv#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1389277082Sjfv#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1390270346Sjfv I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1391270346Sjfv u8 reserved2[14]; 1392266423Sjfv /* response section */ 1393270346Sjfv u8 allocation_result; 1394270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1395270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1396270346Sjfv u8 response_reserved[7]; 1397266423Sjfv}; 1398266423Sjfv 1399266423Sjfvstruct i40e_aqc_remove_cloud_filters_completion { 1400266423Sjfv __le16 perfect_ovlan_used; 1401266423Sjfv __le16 perfect_ovlan_free; 1402266423Sjfv __le16 vlan_used; 1403266423Sjfv __le16 vlan_free; 1404266423Sjfv __le32 addr_high; 1405266423Sjfv __le32 addr_low; 1406266423Sjfv}; 1407266423Sjfv 1408266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1409266423Sjfv 1410266423Sjfv/* Add Mirror Rule (indirect or direct 0x0260) 1411266423Sjfv * Delete Mirror Rule (indirect or direct 0x0261) 1412266423Sjfv * note: some rule types (4,5) do not use an external buffer. 1413266423Sjfv * take care to set the flags correctly. 1414266423Sjfv */ 1415266423Sjfvstruct i40e_aqc_add_delete_mirror_rule { 1416266423Sjfv __le16 seid; 1417266423Sjfv __le16 rule_type; 1418270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1419270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1420266423Sjfv I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1421270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1422270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1423270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1424270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1425270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1426266423Sjfv __le16 num_entries; 1427266423Sjfv __le16 destination; /* VSI for add, rule id for delete */ 1428266423Sjfv __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1429266423Sjfv __le32 addr_low; 1430266423Sjfv}; 1431266423Sjfv 1432266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1433266423Sjfv 1434266423Sjfvstruct i40e_aqc_add_delete_mirror_rule_completion { 1435270346Sjfv u8 reserved[2]; 1436270346Sjfv __le16 rule_id; /* only used on add */ 1437270346Sjfv __le16 mirror_rules_used; 1438270346Sjfv __le16 mirror_rules_free; 1439270346Sjfv __le32 addr_high; 1440270346Sjfv __le32 addr_low; 1441266423Sjfv}; 1442266423Sjfv 1443266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1444266423Sjfv 1445266423Sjfv/* DCB 0x03xx*/ 1446266423Sjfv 1447266423Sjfv/* PFC Ignore (direct 0x0301) 1448266423Sjfv * the command and response use the same descriptor structure 1449266423Sjfv */ 1450266423Sjfvstruct i40e_aqc_pfc_ignore { 1451270346Sjfv u8 tc_bitmap; 1452270346Sjfv u8 command_flags; /* unused on response */ 1453270346Sjfv#define I40E_AQC_PFC_IGNORE_SET 0x80 1454270346Sjfv#define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1455270346Sjfv u8 reserved[14]; 1456266423Sjfv}; 1457266423Sjfv 1458266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1459266423Sjfv 1460266423Sjfv/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1461266423Sjfv * with no parameters 1462266423Sjfv */ 1463266423Sjfv 1464266423Sjfv/* TX scheduler 0x04xx */ 1465266423Sjfv 1466266423Sjfv/* Almost all the indirect commands use 1467266423Sjfv * this generic struct to pass the SEID in param0 1468266423Sjfv */ 1469266423Sjfvstruct i40e_aqc_tx_sched_ind { 1470270346Sjfv __le16 vsi_seid; 1471270346Sjfv u8 reserved[6]; 1472270346Sjfv __le32 addr_high; 1473270346Sjfv __le32 addr_low; 1474266423Sjfv}; 1475266423Sjfv 1476266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1477266423Sjfv 1478266423Sjfv/* Several commands respond with a set of queue set handles */ 1479266423Sjfvstruct i40e_aqc_qs_handles_resp { 1480266423Sjfv __le16 qs_handles[8]; 1481266423Sjfv}; 1482266423Sjfv 1483266423Sjfv/* Configure VSI BW limits (direct 0x0400) */ 1484266423Sjfvstruct i40e_aqc_configure_vsi_bw_limit { 1485270346Sjfv __le16 vsi_seid; 1486270346Sjfv u8 reserved[2]; 1487270346Sjfv __le16 credit; 1488270346Sjfv u8 reserved1[2]; 1489270346Sjfv u8 max_credit; /* 0-3, limit = 2^max */ 1490270346Sjfv u8 reserved2[7]; 1491266423Sjfv}; 1492266423Sjfv 1493266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1494266423Sjfv 1495266423Sjfv/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1496266423Sjfv * responds with i40e_aqc_qs_handles_resp 1497266423Sjfv */ 1498266423Sjfvstruct i40e_aqc_configure_vsi_ets_sla_bw_data { 1499270346Sjfv u8 tc_valid_bits; 1500270346Sjfv u8 reserved[15]; 1501270346Sjfv __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1502266423Sjfv 1503266423Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1504270346Sjfv __le16 tc_bw_max[2]; 1505270346Sjfv u8 reserved1[28]; 1506266423Sjfv}; 1507266423Sjfv 1508277082SjfvI40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1509277082Sjfv 1510266423Sjfv/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1511266423Sjfv * responds with i40e_aqc_qs_handles_resp 1512266423Sjfv */ 1513266423Sjfvstruct i40e_aqc_configure_vsi_tc_bw_data { 1514270346Sjfv u8 tc_valid_bits; 1515270346Sjfv u8 reserved[3]; 1516270346Sjfv u8 tc_bw_credits[8]; 1517270346Sjfv u8 reserved1[4]; 1518270346Sjfv __le16 qs_handles[8]; 1519266423Sjfv}; 1520266423Sjfv 1521277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1522277082Sjfv 1523266423Sjfv/* Query vsi bw configuration (indirect 0x0408) */ 1524266423Sjfvstruct i40e_aqc_query_vsi_bw_config_resp { 1525270346Sjfv u8 tc_valid_bits; 1526270346Sjfv u8 tc_suspended_bits; 1527270346Sjfv u8 reserved[14]; 1528270346Sjfv __le16 qs_handles[8]; 1529270346Sjfv u8 reserved1[4]; 1530270346Sjfv __le16 port_bw_limit; 1531270346Sjfv u8 reserved2[2]; 1532270346Sjfv u8 max_bw; /* 0-3, limit = 2^max */ 1533270346Sjfv u8 reserved3[23]; 1534266423Sjfv}; 1535266423Sjfv 1536277082SjfvI40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1537277082Sjfv 1538266423Sjfv/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1539266423Sjfvstruct i40e_aqc_query_vsi_ets_sla_config_resp { 1540270346Sjfv u8 tc_valid_bits; 1541270346Sjfv u8 reserved[3]; 1542270346Sjfv u8 share_credits[8]; 1543270346Sjfv __le16 credits[8]; 1544266423Sjfv 1545266423Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1546270346Sjfv __le16 tc_bw_max[2]; 1547266423Sjfv}; 1548266423Sjfv 1549277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1550277082Sjfv 1551266423Sjfv/* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1552266423Sjfvstruct i40e_aqc_configure_switching_comp_bw_limit { 1553270346Sjfv __le16 seid; 1554270346Sjfv u8 reserved[2]; 1555270346Sjfv __le16 credit; 1556270346Sjfv u8 reserved1[2]; 1557270346Sjfv u8 max_bw; /* 0-3, limit = 2^max */ 1558270346Sjfv u8 reserved2[7]; 1559266423Sjfv}; 1560266423Sjfv 1561266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1562266423Sjfv 1563266423Sjfv/* Enable Physical Port ETS (indirect 0x0413) 1564266423Sjfv * Modify Physical Port ETS (indirect 0x0414) 1565266423Sjfv * Disable Physical Port ETS (indirect 0x0415) 1566266423Sjfv */ 1567266423Sjfvstruct i40e_aqc_configure_switching_comp_ets_data { 1568270346Sjfv u8 reserved[4]; 1569270346Sjfv u8 tc_valid_bits; 1570270346Sjfv u8 seepage; 1571270346Sjfv#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1572270346Sjfv u8 tc_strict_priority_flags; 1573270346Sjfv u8 reserved1[17]; 1574270346Sjfv u8 tc_bw_share_credits[8]; 1575270346Sjfv u8 reserved2[96]; 1576266423Sjfv}; 1577266423Sjfv 1578277082SjfvI40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1579277082Sjfv 1580266423Sjfv/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1581266423Sjfvstruct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1582270346Sjfv u8 tc_valid_bits; 1583270346Sjfv u8 reserved[15]; 1584270346Sjfv __le16 tc_bw_credit[8]; 1585266423Sjfv 1586266423Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1587270346Sjfv __le16 tc_bw_max[2]; 1588270346Sjfv u8 reserved1[28]; 1589266423Sjfv}; 1590266423Sjfv 1591299555SerjI40E_CHECK_STRUCT_LEN(0x40, 1592299555Serj i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1593277082Sjfv 1594266423Sjfv/* Configure Switching Component Bandwidth Allocation per Tc 1595266423Sjfv * (indirect 0x0417) 1596266423Sjfv */ 1597266423Sjfvstruct i40e_aqc_configure_switching_comp_bw_config_data { 1598270346Sjfv u8 tc_valid_bits; 1599270346Sjfv u8 reserved[2]; 1600270346Sjfv u8 absolute_credits; /* bool */ 1601270346Sjfv u8 tc_bw_share_credits[8]; 1602270346Sjfv u8 reserved1[20]; 1603266423Sjfv}; 1604266423Sjfv 1605277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1606277082Sjfv 1607266423Sjfv/* Query Switching Component Configuration (indirect 0x0418) */ 1608266423Sjfvstruct i40e_aqc_query_switching_comp_ets_config_resp { 1609270346Sjfv u8 tc_valid_bits; 1610270346Sjfv u8 reserved[35]; 1611270346Sjfv __le16 port_bw_limit; 1612270346Sjfv u8 reserved1[2]; 1613270346Sjfv u8 tc_bw_max; /* 0-3, limit = 2^max */ 1614270346Sjfv u8 reserved2[23]; 1615266423Sjfv}; 1616266423Sjfv 1617277082SjfvI40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1618277082Sjfv 1619266423Sjfv/* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1620266423Sjfvstruct i40e_aqc_query_port_ets_config_resp { 1621270346Sjfv u8 reserved[4]; 1622270346Sjfv u8 tc_valid_bits; 1623270346Sjfv u8 reserved1; 1624270346Sjfv u8 tc_strict_priority_bits; 1625270346Sjfv u8 reserved2; 1626270346Sjfv u8 tc_bw_share_credits[8]; 1627270346Sjfv __le16 tc_bw_limits[8]; 1628266423Sjfv 1629266423Sjfv /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1630270346Sjfv __le16 tc_bw_max[2]; 1631270346Sjfv u8 reserved3[32]; 1632266423Sjfv}; 1633266423Sjfv 1634277082SjfvI40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1635277082Sjfv 1636266423Sjfv/* Query Switching Component Bandwidth Allocation per Traffic Type 1637266423Sjfv * (indirect 0x041A) 1638266423Sjfv */ 1639266423Sjfvstruct i40e_aqc_query_switching_comp_bw_config_resp { 1640270346Sjfv u8 tc_valid_bits; 1641270346Sjfv u8 reserved[2]; 1642270346Sjfv u8 absolute_credits_enable; /* bool */ 1643270346Sjfv u8 tc_bw_share_credits[8]; 1644270346Sjfv __le16 tc_bw_limits[8]; 1645266423Sjfv 1646266423Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1647270346Sjfv __le16 tc_bw_max[2]; 1648266423Sjfv}; 1649266423Sjfv 1650277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1651277082Sjfv 1652266423Sjfv/* Suspend/resume port TX traffic 1653266423Sjfv * (direct 0x041B and 0x041C) uses the generic SEID struct 1654266423Sjfv */ 1655266423Sjfv 1656266423Sjfv/* Configure partition BW 1657266423Sjfv * (indirect 0x041D) 1658266423Sjfv */ 1659266423Sjfvstruct i40e_aqc_configure_partition_bw_data { 1660270346Sjfv __le16 pf_valid_bits; 1661270346Sjfv u8 min_bw[16]; /* guaranteed bandwidth */ 1662270346Sjfv u8 max_bw[16]; /* bandwidth limit */ 1663266423Sjfv}; 1664266423Sjfv 1665277082SjfvI40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1666277082Sjfv 1667266423Sjfv/* Get and set the active HMC resource profile and status. 1668266423Sjfv * (direct 0x0500) and (direct 0x0501) 1669266423Sjfv */ 1670266423Sjfvstruct i40e_aq_get_set_hmc_resource_profile { 1671270346Sjfv u8 pm_profile; 1672270346Sjfv u8 pe_vf_enabled; 1673270346Sjfv u8 reserved[14]; 1674266423Sjfv}; 1675266423Sjfv 1676266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1677266423Sjfv 1678266423Sjfvenum i40e_aq_hmc_profile { 1679303967Ssbruno /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1680270346Sjfv I40E_HMC_PROFILE_DEFAULT = 1, 1681270346Sjfv I40E_HMC_PROFILE_FAVOR_VF = 2, 1682270346Sjfv I40E_HMC_PROFILE_EQUAL = 3, 1683266423Sjfv}; 1684266423Sjfv 1685266423Sjfv/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1686266423Sjfv 1687266423Sjfv/* set in param0 for get phy abilities to report qualified modules */ 1688270346Sjfv#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1689270346Sjfv#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1690266423Sjfv 1691266423Sjfvenum i40e_aq_phy_type { 1692266423Sjfv I40E_PHY_TYPE_SGMII = 0x0, 1693266423Sjfv I40E_PHY_TYPE_1000BASE_KX = 0x1, 1694266423Sjfv I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1695266423Sjfv I40E_PHY_TYPE_10GBASE_KR = 0x3, 1696266423Sjfv I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1697266423Sjfv I40E_PHY_TYPE_XAUI = 0x5, 1698266423Sjfv I40E_PHY_TYPE_XFI = 0x6, 1699266423Sjfv I40E_PHY_TYPE_SFI = 0x7, 1700266423Sjfv I40E_PHY_TYPE_XLAUI = 0x8, 1701266423Sjfv I40E_PHY_TYPE_XLPPI = 0x9, 1702266423Sjfv I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1703266423Sjfv I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1704266423Sjfv I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1705266423Sjfv I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1706266423Sjfv I40E_PHY_TYPE_100BASE_TX = 0x11, 1707266423Sjfv I40E_PHY_TYPE_1000BASE_T = 0x12, 1708266423Sjfv I40E_PHY_TYPE_10GBASE_T = 0x13, 1709266423Sjfv I40E_PHY_TYPE_10GBASE_SR = 0x14, 1710266423Sjfv I40E_PHY_TYPE_10GBASE_LR = 0x15, 1711266423Sjfv I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1712266423Sjfv I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1713266423Sjfv I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1714266423Sjfv I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1715266423Sjfv I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1716266423Sjfv I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1717266423Sjfv I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1718266423Sjfv I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1719266423Sjfv I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1720303967Ssbruno I40E_PHY_TYPE_25GBASE_KR = 0x1F, 1721303967Ssbruno I40E_PHY_TYPE_25GBASE_CR = 0x20, 1722303967Ssbruno I40E_PHY_TYPE_25GBASE_SR = 0x21, 1723303967Ssbruno I40E_PHY_TYPE_25GBASE_LR = 0x22, 1724266423Sjfv I40E_PHY_TYPE_MAX 1725266423Sjfv}; 1726266423Sjfv 1727266423Sjfv#define I40E_LINK_SPEED_100MB_SHIFT 0x1 1728266423Sjfv#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1729266423Sjfv#define I40E_LINK_SPEED_10GB_SHIFT 0x3 1730266423Sjfv#define I40E_LINK_SPEED_40GB_SHIFT 0x4 1731266423Sjfv#define I40E_LINK_SPEED_20GB_SHIFT 0x5 1732303967Ssbruno#define I40E_LINK_SPEED_25GB_SHIFT 0x6 1733266423Sjfv 1734266423Sjfvenum i40e_aq_link_speed { 1735266423Sjfv I40E_LINK_SPEED_UNKNOWN = 0, 1736266423Sjfv I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1737266423Sjfv I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1738266423Sjfv I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1739266423Sjfv I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1740303967Ssbruno I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT), 1741303967Ssbruno I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT), 1742266423Sjfv}; 1743266423Sjfv 1744266423Sjfvstruct i40e_aqc_module_desc { 1745266423Sjfv u8 oui[3]; 1746266423Sjfv u8 reserved1; 1747266423Sjfv u8 part_number[16]; 1748266423Sjfv u8 revision[4]; 1749266423Sjfv u8 reserved2[8]; 1750266423Sjfv}; 1751266423Sjfv 1752277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1753277082Sjfv 1754266423Sjfvstruct i40e_aq_get_phy_abilities_resp { 1755270346Sjfv __le32 phy_type; /* bitmap using the above enum for offsets */ 1756270346Sjfv u8 link_speed; /* bitmap using the above enum bit patterns */ 1757270346Sjfv u8 abilities; 1758270346Sjfv#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1759270346Sjfv#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1760270346Sjfv#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1761270346Sjfv#define I40E_AQ_PHY_LINK_ENABLED 0x08 1762270346Sjfv#define I40E_AQ_PHY_AN_ENABLED 0x10 1763270346Sjfv#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1764318357Serj#define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 1765318357Serj#define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 1766270346Sjfv __le16 eee_capability; 1767270346Sjfv#define I40E_AQ_EEE_100BASE_TX 0x0002 1768270346Sjfv#define I40E_AQ_EEE_1000BASE_T 0x0004 1769270346Sjfv#define I40E_AQ_EEE_10GBASE_T 0x0008 1770270346Sjfv#define I40E_AQ_EEE_1000BASE_KX 0x0010 1771270346Sjfv#define I40E_AQ_EEE_10GBASE_KX4 0x0020 1772270346Sjfv#define I40E_AQ_EEE_10GBASE_KR 0x0040 1773270346Sjfv __le32 eeer_val; 1774270346Sjfv u8 d3_lpan; 1775270346Sjfv#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1776303967Ssbruno u8 phy_type_ext; 1777318357Serj#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01 1778318357Serj#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02 1779303967Ssbruno#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 1780303967Ssbruno#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 1781318357Serj u8 fec_cfg_curr_mod_ext_info; 1782318357Serj#define I40E_AQ_ENABLE_FEC_KR 0x01 1783318357Serj#define I40E_AQ_ENABLE_FEC_RS 0x02 1784318357Serj#define I40E_AQ_REQUEST_FEC_KR 0x04 1785318357Serj#define I40E_AQ_REQUEST_FEC_RS 0x08 1786318357Serj#define I40E_AQ_ENABLE_FEC_AUTO 0x10 1787318357Serj#define I40E_AQ_FEC 1788318357Serj#define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 1789318357Serj#define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5 1790318357Serj 1791303967Ssbruno u8 ext_comp_code; 1792270346Sjfv u8 phy_id[4]; 1793270346Sjfv u8 module_type[3]; 1794270346Sjfv u8 qualified_module_count; 1795270346Sjfv#define I40E_AQ_PHY_MAX_QMS 16 1796270346Sjfv struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1797266423Sjfv}; 1798266423Sjfv 1799277082SjfvI40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1800277082Sjfv 1801266423Sjfv/* Set PHY Config (direct 0x0601) */ 1802266423Sjfvstruct i40e_aq_set_phy_config { /* same bits as above in all */ 1803270346Sjfv __le32 phy_type; 1804270346Sjfv u8 link_speed; 1805270346Sjfv u8 abilities; 1806266423Sjfv/* bits 0-2 use the values from get_phy_abilities_resp */ 1807266423Sjfv#define I40E_AQ_PHY_ENABLE_LINK 0x08 1808266423Sjfv#define I40E_AQ_PHY_ENABLE_AN 0x10 1809266423Sjfv#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1810270346Sjfv __le16 eee_capability; 1811270346Sjfv __le32 eeer; 1812270346Sjfv u8 low_power_ctrl; 1813303967Ssbruno u8 phy_type_ext; 1814318357Serj u8 fec_config; 1815318357Serj#define I40E_AQ_SET_FEC_ABILITY_KR BIT(0) 1816318357Serj#define I40E_AQ_SET_FEC_ABILITY_RS BIT(1) 1817318357Serj#define I40E_AQ_SET_FEC_REQUEST_KR BIT(2) 1818318357Serj#define I40E_AQ_SET_FEC_REQUEST_RS BIT(3) 1819318357Serj#define I40E_AQ_SET_FEC_AUTO BIT(4) 1820318357Serj#define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0 1821318357Serj#define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT) 1822318357Serj u8 reserved; 1823266423Sjfv}; 1824266423Sjfv 1825266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1826266423Sjfv 1827266423Sjfv/* Set MAC Config command data structure (direct 0x0603) */ 1828266423Sjfvstruct i40e_aq_set_mac_config { 1829270346Sjfv __le16 max_frame_size; 1830270346Sjfv u8 params; 1831270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1832270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1833270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1834270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1835270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1836270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1837270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1838270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1839270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1840270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1841270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1842270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1843270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1844270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1845270346Sjfv u8 tx_timer_priority; /* bitmap */ 1846270346Sjfv __le16 tx_timer_value; 1847270346Sjfv __le16 fc_refresh_threshold; 1848270346Sjfv u8 reserved[8]; 1849266423Sjfv}; 1850266423Sjfv 1851266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1852266423Sjfv 1853266423Sjfv/* Restart Auto-Negotiation (direct 0x605) */ 1854266423Sjfvstruct i40e_aqc_set_link_restart_an { 1855270346Sjfv u8 command; 1856270346Sjfv#define I40E_AQ_PHY_RESTART_AN 0x02 1857270346Sjfv#define I40E_AQ_PHY_LINK_ENABLE 0x04 1858270346Sjfv u8 reserved[15]; 1859266423Sjfv}; 1860266423Sjfv 1861266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1862266423Sjfv 1863266423Sjfv/* Get Link Status cmd & response data structure (direct 0x0607) */ 1864266423Sjfvstruct i40e_aqc_get_link_status { 1865270346Sjfv __le16 command_flags; /* only field set on command */ 1866270346Sjfv#define I40E_AQ_LSE_MASK 0x3 1867270346Sjfv#define I40E_AQ_LSE_NOP 0x0 1868270346Sjfv#define I40E_AQ_LSE_DISABLE 0x2 1869270346Sjfv#define I40E_AQ_LSE_ENABLE 0x3 1870266423Sjfv/* only response uses this flag */ 1871270346Sjfv#define I40E_AQ_LSE_IS_ENABLED 0x1 1872270346Sjfv u8 phy_type; /* i40e_aq_phy_type */ 1873270346Sjfv u8 link_speed; /* i40e_aq_link_speed */ 1874270346Sjfv u8 link_info; 1875284049Sjfv#define I40E_AQ_LINK_UP 0x01 /* obsolete */ 1876284049Sjfv#define I40E_AQ_LINK_UP_FUNCTION 0x01 1877270346Sjfv#define I40E_AQ_LINK_FAULT 0x02 1878270346Sjfv#define I40E_AQ_LINK_FAULT_TX 0x04 1879270346Sjfv#define I40E_AQ_LINK_FAULT_RX 0x08 1880270346Sjfv#define I40E_AQ_LINK_FAULT_REMOTE 0x10 1881284049Sjfv#define I40E_AQ_LINK_UP_PORT 0x20 1882270346Sjfv#define I40E_AQ_MEDIA_AVAILABLE 0x40 1883270346Sjfv#define I40E_AQ_SIGNAL_DETECT 0x80 1884270346Sjfv u8 an_info; 1885270346Sjfv#define I40E_AQ_AN_COMPLETED 0x01 1886270346Sjfv#define I40E_AQ_LP_AN_ABILITY 0x02 1887270346Sjfv#define I40E_AQ_PD_FAULT 0x04 1888270346Sjfv#define I40E_AQ_FEC_EN 0x08 1889270346Sjfv#define I40E_AQ_PHY_LOW_POWER 0x10 1890270346Sjfv#define I40E_AQ_LINK_PAUSE_TX 0x20 1891270346Sjfv#define I40E_AQ_LINK_PAUSE_RX 0x40 1892270346Sjfv#define I40E_AQ_QUALIFIED_MODULE 0x80 1893270346Sjfv u8 ext_info; 1894270346Sjfv#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1895270346Sjfv#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1896270346Sjfv#define I40E_AQ_LINK_TX_SHIFT 0x02 1897270346Sjfv#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1898270346Sjfv#define I40E_AQ_LINK_TX_ACTIVE 0x00 1899270346Sjfv#define I40E_AQ_LINK_TX_DRAINED 0x01 1900270346Sjfv#define I40E_AQ_LINK_TX_FLUSHED 0x03 1901270346Sjfv#define I40E_AQ_LINK_FORCED_40G 0x10 1902303967Ssbruno/* 25G Error Codes */ 1903303967Ssbruno#define I40E_AQ_25G_NO_ERR 0X00 1904303967Ssbruno#define I40E_AQ_25G_NOT_PRESENT 0X01 1905303967Ssbruno#define I40E_AQ_25G_NVM_CRC_ERR 0X02 1906303967Ssbruno#define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 1907303967Ssbruno#define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 1908303967Ssbruno#define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 1909270346Sjfv u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1910270346Sjfv __le16 max_frame_size; 1911270346Sjfv u8 config; 1912318357Serj#define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 1913318357Serj#define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 1914270346Sjfv#define I40E_AQ_CONFIG_CRC_ENA 0x04 1915270346Sjfv#define I40E_AQ_CONFIG_PACING_MASK 0x78 1916303967Ssbruno u8 power_desc; 1917299549Serj#define I40E_AQ_LINK_POWER_CLASS_1 0x00 1918299549Serj#define I40E_AQ_LINK_POWER_CLASS_2 0x01 1919299549Serj#define I40E_AQ_LINK_POWER_CLASS_3 0x02 1920299549Serj#define I40E_AQ_LINK_POWER_CLASS_4 0x03 1921303967Ssbruno#define I40E_AQ_PWR_CLASS_MASK 0x03 1922299549Serj u8 reserved[4]; 1923266423Sjfv}; 1924266423Sjfv 1925266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1926266423Sjfv 1927266423Sjfv/* Set event mask command (direct 0x613) */ 1928266423Sjfvstruct i40e_aqc_set_phy_int_mask { 1929270346Sjfv u8 reserved[8]; 1930270346Sjfv __le16 event_mask; 1931270346Sjfv#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1932270346Sjfv#define I40E_AQ_EVENT_MEDIA_NA 0x0004 1933270346Sjfv#define I40E_AQ_EVENT_LINK_FAULT 0x0008 1934270346Sjfv#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1935270346Sjfv#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1936270346Sjfv#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1937270346Sjfv#define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1938270346Sjfv#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1939270346Sjfv#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1940270346Sjfv u8 reserved1[6]; 1941266423Sjfv}; 1942266423Sjfv 1943266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1944266423Sjfv 1945266423Sjfv/* Get Local AN advt register (direct 0x0614) 1946266423Sjfv * Set Local AN advt register (direct 0x0615) 1947266423Sjfv * Get Link Partner AN advt register (direct 0x0616) 1948266423Sjfv */ 1949266423Sjfvstruct i40e_aqc_an_advt_reg { 1950270346Sjfv __le32 local_an_reg0; 1951270346Sjfv __le16 local_an_reg1; 1952270346Sjfv u8 reserved[10]; 1953266423Sjfv}; 1954266423Sjfv 1955266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1956266423Sjfv 1957266423Sjfv/* Set Loopback mode (0x0618) */ 1958266423Sjfvstruct i40e_aqc_set_lb_mode { 1959270346Sjfv __le16 lb_mode; 1960270346Sjfv#define I40E_AQ_LB_PHY_LOCAL 0x01 1961270346Sjfv#define I40E_AQ_LB_PHY_REMOTE 0x02 1962270346Sjfv#define I40E_AQ_LB_MAC_LOCAL 0x04 1963270346Sjfv u8 reserved[14]; 1964266423Sjfv}; 1965266423Sjfv 1966266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1967266423Sjfv 1968266423Sjfv/* Set PHY Debug command (0x0622) */ 1969266423Sjfvstruct i40e_aqc_set_phy_debug { 1970270346Sjfv u8 command_flags; 1971266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1972266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1973270346Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1974270346Sjfv I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1975266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1976266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1977266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1978303967Ssbruno/* Disable link manageability on a single port */ 1979266423Sjfv#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1980303967Ssbruno/* Disable link manageability on all ports needs both bits 4 and 5 */ 1981303967Ssbruno#define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 1982270346Sjfv u8 reserved[15]; 1983266423Sjfv}; 1984266423Sjfv 1985266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1986266423Sjfv 1987266423Sjfvenum i40e_aq_phy_reg_type { 1988270346Sjfv I40E_AQC_PHY_REG_INTERNAL = 0x1, 1989270346Sjfv I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1990270346Sjfv I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1991266423Sjfv}; 1992266423Sjfv 1993299549Serj/* Run PHY Activity (0x0626) */ 1994299549Serjstruct i40e_aqc_run_phy_activity { 1995299549Serj __le16 activity_id; 1996299549Serj u8 flags; 1997299549Serj u8 reserved1; 1998299549Serj __le32 control; 1999299549Serj __le32 data; 2000299549Serj u8 reserved2[4]; 2001299549Serj}; 2002299549Serj 2003299549SerjI40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 2004299549Serj 2005266423Sjfv/* NVM Read command (indirect 0x0701) 2006266423Sjfv * NVM Erase commands (direct 0x0702) 2007266423Sjfv * NVM Update commands (indirect 0x0703) 2008266423Sjfv */ 2009266423Sjfvstruct i40e_aqc_nvm_update { 2010270346Sjfv u8 command_flags; 2011270346Sjfv#define I40E_AQ_NVM_LAST_CMD 0x01 2012270346Sjfv#define I40E_AQ_NVM_FLASH_ONLY 0x80 2013270346Sjfv u8 module_pointer; 2014270346Sjfv __le16 length; 2015270346Sjfv __le32 offset; 2016270346Sjfv __le32 addr_high; 2017270346Sjfv __le32 addr_low; 2018266423Sjfv}; 2019266423Sjfv 2020266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 2021266423Sjfv 2022266423Sjfv/* NVM Config Read (indirect 0x0704) */ 2023266423Sjfvstruct i40e_aqc_nvm_config_read { 2024270346Sjfv __le16 cmd_flags; 2025277082Sjfv#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 2026277082Sjfv#define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 2027277082Sjfv#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 2028270346Sjfv __le16 element_count; 2029299555Serj __le16 element_id; /* Feature/field ID */ 2030277082Sjfv __le16 element_id_msw; /* MSWord of field ID */ 2031270346Sjfv __le32 address_high; 2032270346Sjfv __le32 address_low; 2033266423Sjfv}; 2034266423Sjfv 2035266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 2036266423Sjfv 2037266423Sjfv/* NVM Config Write (indirect 0x0705) */ 2038266423Sjfvstruct i40e_aqc_nvm_config_write { 2039270346Sjfv __le16 cmd_flags; 2040270346Sjfv __le16 element_count; 2041270346Sjfv u8 reserved[4]; 2042270346Sjfv __le32 address_high; 2043270346Sjfv __le32 address_low; 2044266423Sjfv}; 2045266423Sjfv 2046266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 2047266423Sjfv 2048277082Sjfv/* Used for 0x0704 as well as for 0x0705 commands */ 2049277082Sjfv#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 2050299555Serj#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 2051299555Serj (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 2052299555Serj#define I40E_AQ_ANVM_FEATURE 0 2053299555Serj#define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 2054266423Sjfvstruct i40e_aqc_nvm_config_data_feature { 2055266423Sjfv __le16 feature_id; 2056277082Sjfv#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 2057277082Sjfv#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 2058277082Sjfv#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 2059266423Sjfv __le16 feature_options; 2060266423Sjfv __le16 feature_selection; 2061266423Sjfv}; 2062266423Sjfv 2063277082SjfvI40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 2064277082Sjfv 2065266423Sjfvstruct i40e_aqc_nvm_config_data_immediate_field { 2066277082Sjfv __le32 field_id; 2067277082Sjfv __le32 field_value; 2068266423Sjfv __le16 field_options; 2069277082Sjfv __le16 reserved; 2070266423Sjfv}; 2071266423Sjfv 2072277082SjfvI40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 2073277082Sjfv 2074284049Sjfv/* OEM Post Update (indirect 0x0720) 2075284049Sjfv * no command data struct used 2076284049Sjfv */ 2077299555Serjstruct i40e_aqc_nvm_oem_post_update { 2078284049Sjfv#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 2079284049Sjfv u8 sel_data; 2080284049Sjfv u8 reserved[7]; 2081284049Sjfv}; 2082284049Sjfv 2083284049SjfvI40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 2084284049Sjfv 2085284049Sjfvstruct i40e_aqc_nvm_oem_post_update_buffer { 2086284049Sjfv u8 str_len; 2087284049Sjfv u8 dev_addr; 2088284049Sjfv __le16 eeprom_addr; 2089284049Sjfv u8 data[36]; 2090284049Sjfv}; 2091284049Sjfv 2092284049SjfvI40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 2093284049Sjfv 2094299549Serj/* Thermal Sensor (indirect 0x0721) 2095299549Serj * read or set thermal sensor configs and values 2096299549Serj * takes a sensor and command specific data buffer, not detailed here 2097299549Serj */ 2098299549Serjstruct i40e_aqc_thermal_sensor { 2099299549Serj u8 sensor_action; 2100299549Serj#define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 2101299549Serj#define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 2102299549Serj#define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 2103299549Serj u8 reserved[7]; 2104299549Serj __le32 addr_high; 2105299549Serj __le32 addr_low; 2106299549Serj}; 2107299549Serj 2108299549SerjI40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 2109299549Serj 2110266423Sjfv/* Send to PF command (indirect 0x0801) id is only used by PF 2111266423Sjfv * Send to VF command (indirect 0x0802) id is only used by PF 2112266423Sjfv * Send to Peer PF command (indirect 0x0803) 2113266423Sjfv */ 2114266423Sjfvstruct i40e_aqc_pf_vf_message { 2115270346Sjfv __le32 id; 2116270346Sjfv u8 reserved[4]; 2117270346Sjfv __le32 addr_high; 2118270346Sjfv __le32 addr_low; 2119266423Sjfv}; 2120266423Sjfv 2121266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 2122266423Sjfv 2123266423Sjfv/* Alternate structure */ 2124266423Sjfv 2125266423Sjfv/* Direct write (direct 0x0900) 2126266423Sjfv * Direct read (direct 0x0902) 2127266423Sjfv */ 2128266423Sjfvstruct i40e_aqc_alternate_write { 2129266423Sjfv __le32 address0; 2130266423Sjfv __le32 data0; 2131266423Sjfv __le32 address1; 2132266423Sjfv __le32 data1; 2133266423Sjfv}; 2134266423Sjfv 2135266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 2136266423Sjfv 2137266423Sjfv/* Indirect write (indirect 0x0901) 2138266423Sjfv * Indirect read (indirect 0x0903) 2139266423Sjfv */ 2140266423Sjfv 2141266423Sjfvstruct i40e_aqc_alternate_ind_write { 2142266423Sjfv __le32 address; 2143266423Sjfv __le32 length; 2144266423Sjfv __le32 addr_high; 2145266423Sjfv __le32 addr_low; 2146266423Sjfv}; 2147266423Sjfv 2148266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 2149266423Sjfv 2150266423Sjfv/* Done alternate write (direct 0x0904) 2151266423Sjfv * uses i40e_aq_desc 2152266423Sjfv */ 2153266423Sjfvstruct i40e_aqc_alternate_write_done { 2154270346Sjfv __le16 cmd_flags; 2155266423Sjfv#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 2156266423Sjfv#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 2157266423Sjfv#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 2158266423Sjfv#define I40E_AQ_ALTERNATE_RESET_NEEDED 2 2159270346Sjfv u8 reserved[14]; 2160266423Sjfv}; 2161266423Sjfv 2162266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2163266423Sjfv 2164266423Sjfv/* Set OEM mode (direct 0x0905) */ 2165266423Sjfvstruct i40e_aqc_alternate_set_mode { 2166270346Sjfv __le32 mode; 2167266423Sjfv#define I40E_AQ_ALTERNATE_MODE_NONE 0 2168266423Sjfv#define I40E_AQ_ALTERNATE_MODE_OEM 1 2169270346Sjfv u8 reserved[12]; 2170266423Sjfv}; 2171266423Sjfv 2172266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2173266423Sjfv 2174266423Sjfv/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2175266423Sjfv 2176266423Sjfv/* async events 0x10xx */ 2177266423Sjfv 2178266423Sjfv/* Lan Queue Overflow Event (direct, 0x1001) */ 2179266423Sjfvstruct i40e_aqc_lan_overflow { 2180270346Sjfv __le32 prtdcb_rupto; 2181270346Sjfv __le32 otx_ctl; 2182270346Sjfv u8 reserved[8]; 2183266423Sjfv}; 2184266423Sjfv 2185266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2186266423Sjfv 2187266423Sjfv/* Get LLDP MIB (indirect 0x0A00) */ 2188266423Sjfvstruct i40e_aqc_lldp_get_mib { 2189270346Sjfv u8 type; 2190270346Sjfv u8 reserved1; 2191270346Sjfv#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2192270346Sjfv#define I40E_AQ_LLDP_MIB_LOCAL 0x0 2193270346Sjfv#define I40E_AQ_LLDP_MIB_REMOTE 0x1 2194270346Sjfv#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2195270346Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2196270346Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2197270346Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2198270346Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2199270346Sjfv#define I40E_AQ_LLDP_TX_SHIFT 0x4 2200270346Sjfv#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2201266423Sjfv/* TX pause flags use I40E_AQ_LINK_TX_* above */ 2202270346Sjfv __le16 local_len; 2203270346Sjfv __le16 remote_len; 2204270346Sjfv u8 reserved2[2]; 2205270346Sjfv __le32 addr_high; 2206270346Sjfv __le32 addr_low; 2207266423Sjfv}; 2208266423Sjfv 2209266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2210266423Sjfv 2211266423Sjfv/* Configure LLDP MIB Change Event (direct 0x0A01) 2212266423Sjfv * also used for the event (with type in the command field) 2213266423Sjfv */ 2214266423Sjfvstruct i40e_aqc_lldp_update_mib { 2215270346Sjfv u8 command; 2216270346Sjfv#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2217270346Sjfv#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2218270346Sjfv u8 reserved[7]; 2219270346Sjfv __le32 addr_high; 2220270346Sjfv __le32 addr_low; 2221266423Sjfv}; 2222266423Sjfv 2223266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2224266423Sjfv 2225266423Sjfv/* Add LLDP TLV (indirect 0x0A02) 2226266423Sjfv * Delete LLDP TLV (indirect 0x0A04) 2227266423Sjfv */ 2228266423Sjfvstruct i40e_aqc_lldp_add_tlv { 2229270346Sjfv u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2230270346Sjfv u8 reserved1[1]; 2231270346Sjfv __le16 len; 2232270346Sjfv u8 reserved2[4]; 2233270346Sjfv __le32 addr_high; 2234270346Sjfv __le32 addr_low; 2235266423Sjfv}; 2236266423Sjfv 2237266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2238266423Sjfv 2239266423Sjfv/* Update LLDP TLV (indirect 0x0A03) */ 2240266423Sjfvstruct i40e_aqc_lldp_update_tlv { 2241270346Sjfv u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2242270346Sjfv u8 reserved; 2243270346Sjfv __le16 old_len; 2244270346Sjfv __le16 new_offset; 2245270346Sjfv __le16 new_len; 2246270346Sjfv __le32 addr_high; 2247270346Sjfv __le32 addr_low; 2248266423Sjfv}; 2249266423Sjfv 2250266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2251266423Sjfv 2252266423Sjfv/* Stop LLDP (direct 0x0A05) */ 2253266423Sjfvstruct i40e_aqc_lldp_stop { 2254270346Sjfv u8 command; 2255270346Sjfv#define I40E_AQ_LLDP_AGENT_STOP 0x0 2256270346Sjfv#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2257270346Sjfv u8 reserved[15]; 2258266423Sjfv}; 2259266423Sjfv 2260266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2261266423Sjfv 2262266423Sjfv/* Start LLDP (direct 0x0A06) */ 2263266423Sjfv 2264266423Sjfvstruct i40e_aqc_lldp_start { 2265270346Sjfv u8 command; 2266270346Sjfv#define I40E_AQ_LLDP_AGENT_START 0x1 2267270346Sjfv u8 reserved[15]; 2268266423Sjfv}; 2269266423Sjfv 2270266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2271266423Sjfv 2272277082Sjfv/* Get CEE DCBX Oper Config (0x0A07) 2273277082Sjfv * uses the generic descriptor struct 2274277082Sjfv * returns below as indirect response 2275266423Sjfv */ 2276266423Sjfv 2277277082Sjfv#define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2278277082Sjfv#define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2279277082Sjfv#define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2280277082Sjfv#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2281277082Sjfv#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2282277082Sjfv#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2283284049Sjfv 2284277082Sjfv#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2285277082Sjfv#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2286277082Sjfv#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2287277082Sjfv#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2288277082Sjfv#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2289277082Sjfv#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2290284049Sjfv#define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2291284049Sjfv#define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2292284049Sjfv#define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2293284049Sjfv#define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2294284049Sjfv#define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2295284049Sjfv#define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2296284049Sjfv 2297284049Sjfv/* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2298284049Sjfv * word boundary layout issues, which the Linux compilers silently deal 2299284049Sjfv * with by adding padding, making the actual struct larger than designed. 2300284049Sjfv * However, the FW compiler for the NIC is less lenient and complains 2301284049Sjfv * about the struct. Hence, the struct defined here has an extra byte in 2302284049Sjfv * fields reserved3 and reserved4 to directly acknowledge that padding, 2303284049Sjfv * and the new length is used in the length check macro. 2304284049Sjfv */ 2305277082Sjfvstruct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2306277082Sjfv u8 reserved1; 2307277082Sjfv u8 oper_num_tc; 2308277082Sjfv u8 oper_prio_tc[4]; 2309277082Sjfv u8 reserved2; 2310277082Sjfv u8 oper_tc_bw[8]; 2311277082Sjfv u8 oper_pfc_en; 2312284049Sjfv u8 reserved3[2]; 2313277082Sjfv __le16 oper_app_prio; 2314284049Sjfv u8 reserved4[2]; 2315277082Sjfv __le16 tlv_status; 2316277082Sjfv}; 2317277082Sjfv 2318277082SjfvI40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2319277082Sjfv 2320277082Sjfvstruct i40e_aqc_get_cee_dcb_cfg_resp { 2321277082Sjfv u8 oper_num_tc; 2322277082Sjfv u8 oper_prio_tc[4]; 2323277082Sjfv u8 oper_tc_bw[8]; 2324277082Sjfv u8 oper_pfc_en; 2325277082Sjfv __le16 oper_app_prio; 2326277082Sjfv __le32 tlv_status; 2327277082Sjfv u8 reserved[12]; 2328277082Sjfv}; 2329277082Sjfv 2330277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2331277082Sjfv 2332277082Sjfv/* Set Local LLDP MIB (indirect 0x0A08) 2333277082Sjfv * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2334277082Sjfv */ 2335277082Sjfvstruct i40e_aqc_lldp_set_local_mib { 2336277082Sjfv#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2337299545Serj#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \ 2338299545Serj SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2339299545Serj#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2340299545Serj#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2341299545Serj#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \ 2342299545Serj SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2343299545Serj#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2344277082Sjfv u8 type; 2345277082Sjfv u8 reserved0; 2346277082Sjfv __le16 length; 2347277082Sjfv u8 reserved1[4]; 2348277082Sjfv __le32 address_high; 2349277082Sjfv __le32 address_low; 2350277082Sjfv}; 2351277082Sjfv 2352277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2353277082Sjfv 2354299547Serjstruct i40e_aqc_lldp_set_local_mib_resp { 2355299547Serj#define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01 2356299547Serj u8 status; 2357299547Serj u8 reserved[15]; 2358299547Serj}; 2359299547Serj 2360299547SerjI40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp); 2361299547Serj 2362277082Sjfv/* Stop/Start LLDP Agent (direct 0x0A09) 2363277082Sjfv * Used for stopping/starting specific LLDP agent. e.g. DCBx 2364277082Sjfv */ 2365277082Sjfvstruct i40e_aqc_lldp_stop_start_specific_agent { 2366277082Sjfv#define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2367299555Serj#define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2368299555Serj (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2369277082Sjfv u8 command; 2370277082Sjfv u8 reserved[15]; 2371277082Sjfv}; 2372277082Sjfv 2373277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2374277082Sjfv 2375266423Sjfv/* Add Udp Tunnel command and completion (direct 0x0B00) */ 2376266423Sjfvstruct i40e_aqc_add_udp_tunnel { 2377270346Sjfv __le16 udp_port; 2378270346Sjfv u8 reserved0[3]; 2379270346Sjfv u8 protocol_type; 2380266423Sjfv#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2381266423Sjfv#define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2382266423Sjfv#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2383299549Serj#define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2384270346Sjfv u8 reserved1[10]; 2385266423Sjfv}; 2386266423Sjfv 2387266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2388266423Sjfv 2389266423Sjfvstruct i40e_aqc_add_udp_tunnel_completion { 2390299555Serj __le16 udp_port; 2391266423Sjfv u8 filter_entry_index; 2392266423Sjfv u8 multiple_pfs; 2393270346Sjfv#define I40E_AQC_SINGLE_PF 0x0 2394270346Sjfv#define I40E_AQC_MULTIPLE_PFS 0x1 2395266423Sjfv u8 total_filters; 2396266423Sjfv u8 reserved[11]; 2397266423Sjfv}; 2398266423Sjfv 2399266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2400266423Sjfv 2401266423Sjfv/* remove UDP Tunnel command (0x0B01) */ 2402266423Sjfvstruct i40e_aqc_remove_udp_tunnel { 2403270346Sjfv u8 reserved[2]; 2404270346Sjfv u8 index; /* 0 to 15 */ 2405270346Sjfv u8 reserved2[13]; 2406266423Sjfv}; 2407266423Sjfv 2408266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2409266423Sjfv 2410266423Sjfvstruct i40e_aqc_del_udp_tunnel_completion { 2411270346Sjfv __le16 udp_port; 2412270346Sjfv u8 index; /* 0 to 15 */ 2413270346Sjfv u8 multiple_pfs; 2414270346Sjfv u8 total_filters_used; 2415270346Sjfv u8 reserved1[11]; 2416266423Sjfv}; 2417266423Sjfv 2418266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2419266423Sjfv 2420303967Ssbrunostruct i40e_aqc_get_set_rss_key { 2421303967Ssbruno#define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15) 2422303967Ssbruno#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2423303967Ssbruno#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2424303967Ssbruno I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2425303967Ssbruno __le16 vsi_id; 2426303967Ssbruno u8 reserved[6]; 2427303967Ssbruno __le32 addr_high; 2428303967Ssbruno __le32 addr_low; 2429303967Ssbruno}; 2430303967Ssbruno 2431303967SsbrunoI40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2432303967Ssbruno 2433303967Ssbrunostruct i40e_aqc_get_set_rss_key_data { 2434303967Ssbruno u8 standard_rss_key[0x28]; 2435303967Ssbruno u8 extended_hash_key[0xc]; 2436303967Ssbruno}; 2437303967Ssbruno 2438303967SsbrunoI40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2439303967Ssbruno 2440303967Ssbrunostruct i40e_aqc_get_set_rss_lut { 2441303967Ssbruno#define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15) 2442303967Ssbruno#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2443303967Ssbruno#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2444303967Ssbruno I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2445303967Ssbruno __le16 vsi_id; 2446303967Ssbruno#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2447303967Ssbruno#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \ 2448303967Ssbruno I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2449303967Ssbruno 2450303967Ssbruno#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2451303967Ssbruno#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2452303967Ssbruno __le16 flags; 2453303967Ssbruno u8 reserved[4]; 2454303967Ssbruno __le32 addr_high; 2455303967Ssbruno __le32 addr_low; 2456303967Ssbruno}; 2457303967Ssbruno 2458303967SsbrunoI40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2459303967Ssbruno 2460266423Sjfv/* tunnel key structure 0x0B10 */ 2461266423Sjfv 2462266423Sjfvstruct i40e_aqc_tunnel_key_structure { 2463266423Sjfv u8 key1_off; 2464266423Sjfv u8 key2_off; 2465266423Sjfv u8 key1_len; /* 0 to 15 */ 2466266423Sjfv u8 key2_len; /* 0 to 15 */ 2467266423Sjfv u8 flags; 2468270346Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2469266423Sjfv/* response flags */ 2470270346Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2471270346Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2472270346Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2473266423Sjfv u8 network_key_index; 2474266423Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2475266423Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2476266423Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2477266423Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2478266423Sjfv u8 reserved[10]; 2479266423Sjfv}; 2480266423Sjfv 2481266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2482266423Sjfv 2483266423Sjfv/* OEM mode commands (direct 0xFE0x) */ 2484266423Sjfvstruct i40e_aqc_oem_param_change { 2485270346Sjfv __le32 param_type; 2486270346Sjfv#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2487270346Sjfv#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2488270346Sjfv#define I40E_AQ_OEM_PARAM_MAC 2 2489270346Sjfv __le32 param_value1; 2490277082Sjfv __le16 param_value2; 2491277082Sjfv u8 reserved[6]; 2492266423Sjfv}; 2493266423Sjfv 2494266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2495266423Sjfv 2496266423Sjfvstruct i40e_aqc_oem_state_change { 2497270346Sjfv __le32 state; 2498270346Sjfv#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2499270346Sjfv#define I40E_AQ_OEM_STATE_LINK_UP 0x1 2500270346Sjfv u8 reserved[12]; 2501266423Sjfv}; 2502266423Sjfv 2503266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2504266423Sjfv 2505277082Sjfv/* Initialize OCSD (0xFE02, direct) */ 2506277082Sjfvstruct i40e_aqc_opc_oem_ocsd_initialize { 2507277082Sjfv u8 type_status; 2508277082Sjfv u8 reserved1[3]; 2509277082Sjfv __le32 ocsd_memory_block_addr_high; 2510277082Sjfv __le32 ocsd_memory_block_addr_low; 2511277082Sjfv __le32 requested_update_interval; 2512277082Sjfv}; 2513277082Sjfv 2514277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2515277082Sjfv 2516277082Sjfv/* Initialize OCBB (0xFE03, direct) */ 2517277082Sjfvstruct i40e_aqc_opc_oem_ocbb_initialize { 2518277082Sjfv u8 type_status; 2519277082Sjfv u8 reserved1[3]; 2520277082Sjfv __le32 ocbb_memory_block_addr_high; 2521277082Sjfv __le32 ocbb_memory_block_addr_low; 2522277082Sjfv u8 reserved2[4]; 2523277082Sjfv}; 2524277082Sjfv 2525277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2526277082Sjfv 2527266423Sjfv/* debug commands */ 2528266423Sjfv 2529266423Sjfv/* get device id (0xFF00) uses the generic structure */ 2530266423Sjfv 2531266423Sjfv/* set test more (0xFF01, internal) */ 2532266423Sjfv 2533266423Sjfvstruct i40e_acq_set_test_mode { 2534270346Sjfv u8 mode; 2535270346Sjfv#define I40E_AQ_TEST_PARTIAL 0 2536270346Sjfv#define I40E_AQ_TEST_FULL 1 2537270346Sjfv#define I40E_AQ_TEST_NVM 2 2538270346Sjfv u8 reserved[3]; 2539270346Sjfv u8 command; 2540270346Sjfv#define I40E_AQ_TEST_OPEN 0 2541270346Sjfv#define I40E_AQ_TEST_CLOSE 1 2542270346Sjfv#define I40E_AQ_TEST_INC 2 2543270346Sjfv u8 reserved2[3]; 2544270346Sjfv __le32 address_high; 2545270346Sjfv __le32 address_low; 2546266423Sjfv}; 2547266423Sjfv 2548266423SjfvI40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2549266423Sjfv 2550266423Sjfv/* Debug Read Register command (0xFF03) 2551266423Sjfv * Debug Write Register command (0xFF04) 2552266423Sjfv */ 2553266423Sjfvstruct i40e_aqc_debug_reg_read_write { 2554266423Sjfv __le32 reserved; 2555266423Sjfv __le32 address; 2556266423Sjfv __le32 value_high; 2557266423Sjfv __le32 value_low; 2558266423Sjfv}; 2559266423Sjfv 2560266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2561266423Sjfv 2562266423Sjfv/* Scatter/gather Reg Read (indirect 0xFF05) 2563266423Sjfv * Scatter/gather Reg Write (indirect 0xFF06) 2564266423Sjfv */ 2565266423Sjfv 2566266423Sjfv/* i40e_aq_desc is used for the command */ 2567266423Sjfvstruct i40e_aqc_debug_reg_sg_element_data { 2568266423Sjfv __le32 address; 2569266423Sjfv __le32 value; 2570266423Sjfv}; 2571266423Sjfv 2572266423Sjfv/* Debug Modify register (direct 0xFF07) */ 2573266423Sjfvstruct i40e_aqc_debug_modify_reg { 2574266423Sjfv __le32 address; 2575266423Sjfv __le32 value; 2576266423Sjfv __le32 clear_mask; 2577266423Sjfv __le32 set_mask; 2578266423Sjfv}; 2579266423Sjfv 2580266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2581266423Sjfv 2582266423Sjfv/* dump internal data (0xFF08, indirect) */ 2583266423Sjfv 2584266423Sjfv#define I40E_AQ_CLUSTER_ID_AUX 0 2585266423Sjfv#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2586266423Sjfv#define I40E_AQ_CLUSTER_ID_TXSCHED 2 2587266423Sjfv#define I40E_AQ_CLUSTER_ID_HMC 3 2588266423Sjfv#define I40E_AQ_CLUSTER_ID_MAC0 4 2589266423Sjfv#define I40E_AQ_CLUSTER_ID_MAC1 5 2590266423Sjfv#define I40E_AQ_CLUSTER_ID_MAC2 6 2591266423Sjfv#define I40E_AQ_CLUSTER_ID_MAC3 7 2592266423Sjfv#define I40E_AQ_CLUSTER_ID_DCB 8 2593266423Sjfv#define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2594266423Sjfv#define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2595266423Sjfv#define I40E_AQ_CLUSTER_ID_ALTRAM 11 2596266423Sjfv 2597266423Sjfvstruct i40e_aqc_debug_dump_internals { 2598270346Sjfv u8 cluster_id; 2599270346Sjfv u8 table_id; 2600270346Sjfv __le16 data_size; 2601270346Sjfv __le32 idx; 2602270346Sjfv __le32 address_high; 2603270346Sjfv __le32 address_low; 2604266423Sjfv}; 2605266423Sjfv 2606266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2607266423Sjfv 2608266423Sjfvstruct i40e_aqc_debug_modify_internals { 2609270346Sjfv u8 cluster_id; 2610270346Sjfv u8 cluster_specific_params[7]; 2611270346Sjfv __le32 address_high; 2612270346Sjfv __le32 address_low; 2613266423Sjfv}; 2614266423Sjfv 2615266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2616266423Sjfv 2617299547Serj#endif /* _I40E_ADMINQ_CMD_H_ */ 2618