i40e_adminq_cmd.h revision 303967
1/****************************************************************************** 2 3 Copyright (c) 2013-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: stable/11/sys/dev/ixl/i40e_adminq_cmd.h 303967 2016-08-11 19:13:30Z sbruno $*/ 34 35#ifndef _I40E_ADMINQ_CMD_H_ 36#define _I40E_ADMINQ_CMD_H_ 37 38/* This header file defines the i40e Admin Queue commands and is shared between 39 * i40e Firmware and Software. 40 * 41 * This file needs to comply with the Linux Kernel coding style. 42 */ 43 44#define I40E_FW_API_VERSION_MAJOR 0x0001 45#define I40E_FW_API_VERSION_MINOR 0x0005 46 47struct i40e_aq_desc { 48 __le16 flags; 49 __le16 opcode; 50 __le16 datalen; 51 __le16 retval; 52 __le32 cookie_high; 53 __le32 cookie_low; 54 union { 55 struct { 56 __le32 param0; 57 __le32 param1; 58 __le32 param2; 59 __le32 param3; 60 } internal; 61 struct { 62 __le32 param0; 63 __le32 param1; 64 __le32 addr_high; 65 __le32 addr_low; 66 } external; 67 u8 raw[16]; 68 } params; 69}; 70 71/* Flags sub-structure 72 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 73 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 74 */ 75 76/* command flags and offsets*/ 77#define I40E_AQ_FLAG_DD_SHIFT 0 78#define I40E_AQ_FLAG_CMP_SHIFT 1 79#define I40E_AQ_FLAG_ERR_SHIFT 2 80#define I40E_AQ_FLAG_VFE_SHIFT 3 81#define I40E_AQ_FLAG_LB_SHIFT 9 82#define I40E_AQ_FLAG_RD_SHIFT 10 83#define I40E_AQ_FLAG_VFC_SHIFT 11 84#define I40E_AQ_FLAG_BUF_SHIFT 12 85#define I40E_AQ_FLAG_SI_SHIFT 13 86#define I40E_AQ_FLAG_EI_SHIFT 14 87#define I40E_AQ_FLAG_FE_SHIFT 15 88 89#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 90#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 91#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 92#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 93#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 94#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 95#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 96#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 97#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 98#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 99#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 100 101/* error codes */ 102enum i40e_admin_queue_err { 103 I40E_AQ_RC_OK = 0, /* success */ 104 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 105 I40E_AQ_RC_ENOENT = 2, /* No such element */ 106 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 107 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 108 I40E_AQ_RC_EIO = 5, /* I/O error */ 109 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 110 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 111 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 112 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 113 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 114 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 115 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 116 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 117 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 118 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 119 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 120 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 121 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 122 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 123 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 124 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 125 I40E_AQ_RC_EFBIG = 22, /* File too large */ 126}; 127 128/* Admin Queue command opcodes */ 129enum i40e_admin_queue_opc { 130 /* aq commands */ 131 i40e_aqc_opc_get_version = 0x0001, 132 i40e_aqc_opc_driver_version = 0x0002, 133 i40e_aqc_opc_queue_shutdown = 0x0003, 134 i40e_aqc_opc_set_pf_context = 0x0004, 135 136 /* resource ownership */ 137 i40e_aqc_opc_request_resource = 0x0008, 138 i40e_aqc_opc_release_resource = 0x0009, 139 140 i40e_aqc_opc_list_func_capabilities = 0x000A, 141 i40e_aqc_opc_list_dev_capabilities = 0x000B, 142 143 /* Proxy commands */ 144 i40e_aqc_opc_set_proxy_config = 0x0104, 145 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, 146 147 /* LAA */ 148 i40e_aqc_opc_mac_address_read = 0x0107, 149 i40e_aqc_opc_mac_address_write = 0x0108, 150 151 /* PXE */ 152 i40e_aqc_opc_clear_pxe_mode = 0x0110, 153 154 /* WoL commands */ 155 i40e_aqc_opc_set_wol_filter = 0x0120, 156 i40e_aqc_opc_get_wake_reason = 0x0121, 157 158 /* internal switch commands */ 159 i40e_aqc_opc_get_switch_config = 0x0200, 160 i40e_aqc_opc_add_statistics = 0x0201, 161 i40e_aqc_opc_remove_statistics = 0x0202, 162 i40e_aqc_opc_set_port_parameters = 0x0203, 163 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 164 i40e_aqc_opc_set_switch_config = 0x0205, 165 i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 166 i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 167 168 i40e_aqc_opc_add_vsi = 0x0210, 169 i40e_aqc_opc_update_vsi_parameters = 0x0211, 170 i40e_aqc_opc_get_vsi_parameters = 0x0212, 171 172 i40e_aqc_opc_add_pv = 0x0220, 173 i40e_aqc_opc_update_pv_parameters = 0x0221, 174 i40e_aqc_opc_get_pv_parameters = 0x0222, 175 176 i40e_aqc_opc_add_veb = 0x0230, 177 i40e_aqc_opc_update_veb_parameters = 0x0231, 178 i40e_aqc_opc_get_veb_parameters = 0x0232, 179 180 i40e_aqc_opc_delete_element = 0x0243, 181 182 i40e_aqc_opc_add_macvlan = 0x0250, 183 i40e_aqc_opc_remove_macvlan = 0x0251, 184 i40e_aqc_opc_add_vlan = 0x0252, 185 i40e_aqc_opc_remove_vlan = 0x0253, 186 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 187 i40e_aqc_opc_add_tag = 0x0255, 188 i40e_aqc_opc_remove_tag = 0x0256, 189 i40e_aqc_opc_add_multicast_etag = 0x0257, 190 i40e_aqc_opc_remove_multicast_etag = 0x0258, 191 i40e_aqc_opc_update_tag = 0x0259, 192 i40e_aqc_opc_add_control_packet_filter = 0x025A, 193 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 194 i40e_aqc_opc_add_cloud_filters = 0x025C, 195 i40e_aqc_opc_remove_cloud_filters = 0x025D, 196 i40e_aqc_opc_clear_wol_switch_filters = 0x025E, 197 198 i40e_aqc_opc_add_mirror_rule = 0x0260, 199 i40e_aqc_opc_delete_mirror_rule = 0x0261, 200 201 /* DCB commands */ 202 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 203 i40e_aqc_opc_dcb_updated = 0x0302, 204 205 /* TX scheduler */ 206 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 207 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 208 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 209 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 210 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 211 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 212 213 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 214 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 215 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 216 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 217 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 218 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 219 i40e_aqc_opc_query_port_ets_config = 0x0419, 220 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 221 i40e_aqc_opc_suspend_port_tx = 0x041B, 222 i40e_aqc_opc_resume_port_tx = 0x041C, 223 i40e_aqc_opc_configure_partition_bw = 0x041D, 224 /* hmc */ 225 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 226 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 227 228 /* phy commands*/ 229 i40e_aqc_opc_get_phy_abilities = 0x0600, 230 i40e_aqc_opc_set_phy_config = 0x0601, 231 i40e_aqc_opc_set_mac_config = 0x0603, 232 i40e_aqc_opc_set_link_restart_an = 0x0605, 233 i40e_aqc_opc_get_link_status = 0x0607, 234 i40e_aqc_opc_set_phy_int_mask = 0x0613, 235 i40e_aqc_opc_get_local_advt_reg = 0x0614, 236 i40e_aqc_opc_set_local_advt_reg = 0x0615, 237 i40e_aqc_opc_get_partner_advt = 0x0616, 238 i40e_aqc_opc_set_lb_modes = 0x0618, 239 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 240 i40e_aqc_opc_set_phy_debug = 0x0622, 241 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 242 i40e_aqc_opc_run_phy_activity = 0x0626, 243 244 /* NVM commands */ 245 i40e_aqc_opc_nvm_read = 0x0701, 246 i40e_aqc_opc_nvm_erase = 0x0702, 247 i40e_aqc_opc_nvm_update = 0x0703, 248 i40e_aqc_opc_nvm_config_read = 0x0704, 249 i40e_aqc_opc_nvm_config_write = 0x0705, 250 i40e_aqc_opc_oem_post_update = 0x0720, 251 i40e_aqc_opc_thermal_sensor = 0x0721, 252 253 /* virtualization commands */ 254 i40e_aqc_opc_send_msg_to_pf = 0x0801, 255 i40e_aqc_opc_send_msg_to_vf = 0x0802, 256 i40e_aqc_opc_send_msg_to_peer = 0x0803, 257 258 /* alternate structure */ 259 i40e_aqc_opc_alternate_write = 0x0900, 260 i40e_aqc_opc_alternate_write_indirect = 0x0901, 261 i40e_aqc_opc_alternate_read = 0x0902, 262 i40e_aqc_opc_alternate_read_indirect = 0x0903, 263 i40e_aqc_opc_alternate_write_done = 0x0904, 264 i40e_aqc_opc_alternate_set_mode = 0x0905, 265 i40e_aqc_opc_alternate_clear_port = 0x0906, 266 267 /* LLDP commands */ 268 i40e_aqc_opc_lldp_get_mib = 0x0A00, 269 i40e_aqc_opc_lldp_update_mib = 0x0A01, 270 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 271 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 272 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 273 i40e_aqc_opc_lldp_stop = 0x0A05, 274 i40e_aqc_opc_lldp_start = 0x0A06, 275 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 276 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 277 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 278 279 /* Tunnel commands */ 280 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 281 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 282 i40e_aqc_opc_set_rss_key = 0x0B02, 283 i40e_aqc_opc_set_rss_lut = 0x0B03, 284 i40e_aqc_opc_get_rss_key = 0x0B04, 285 i40e_aqc_opc_get_rss_lut = 0x0B05, 286 287 /* Async Events */ 288 i40e_aqc_opc_event_lan_overflow = 0x1001, 289 290 /* OEM commands */ 291 i40e_aqc_opc_oem_parameter_change = 0xFE00, 292 i40e_aqc_opc_oem_device_status_change = 0xFE01, 293 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 294 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 295 296 /* debug commands */ 297 i40e_aqc_opc_debug_read_reg = 0xFF03, 298 i40e_aqc_opc_debug_write_reg = 0xFF04, 299 i40e_aqc_opc_debug_modify_reg = 0xFF07, 300 i40e_aqc_opc_debug_dump_internals = 0xFF08, 301}; 302 303/* command structures and indirect data structures */ 304 305/* Structure naming conventions: 306 * - no suffix for direct command descriptor structures 307 * - _data for indirect sent data 308 * - _resp for indirect return data (data which is both will use _data) 309 * - _completion for direct return data 310 * - _element_ for repeated elements (may also be _data or _resp) 311 * 312 * Command structures are expected to overlay the params.raw member of the basic 313 * descriptor, and as such cannot exceed 16 bytes in length. 314 */ 315 316/* This macro is used to generate a compilation error if a structure 317 * is not exactly the correct length. It gives a divide by zero error if the 318 * structure is not of the correct size, otherwise it creates an enum that is 319 * never used. 320 */ 321#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 322 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 323 324/* This macro is used extensively to ensure that command structures are 16 325 * bytes in length as they have to map to the raw array of that size. 326 */ 327#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 328 329/* internal (0x00XX) commands */ 330 331/* Get version (direct 0x0001) */ 332struct i40e_aqc_get_version { 333 __le32 rom_ver; 334 __le32 fw_build; 335 __le16 fw_major; 336 __le16 fw_minor; 337 __le16 api_major; 338 __le16 api_minor; 339}; 340 341I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 342 343/* Send driver version (indirect 0x0002) */ 344struct i40e_aqc_driver_version { 345 u8 driver_major_ver; 346 u8 driver_minor_ver; 347 u8 driver_build_ver; 348 u8 driver_subbuild_ver; 349 u8 reserved[4]; 350 __le32 address_high; 351 __le32 address_low; 352}; 353 354I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 355 356/* Queue Shutdown (direct 0x0003) */ 357struct i40e_aqc_queue_shutdown { 358 __le32 driver_unloading; 359#define I40E_AQ_DRIVER_UNLOADING 0x1 360 u8 reserved[12]; 361}; 362 363I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 364 365/* Set PF context (0x0004, direct) */ 366struct i40e_aqc_set_pf_context { 367 u8 pf_id; 368 u8 reserved[15]; 369}; 370 371I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 372 373/* Request resource ownership (direct 0x0008) 374 * Release resource ownership (direct 0x0009) 375 */ 376#define I40E_AQ_RESOURCE_NVM 1 377#define I40E_AQ_RESOURCE_SDP 2 378#define I40E_AQ_RESOURCE_ACCESS_READ 1 379#define I40E_AQ_RESOURCE_ACCESS_WRITE 2 380#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 381#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 382 383struct i40e_aqc_request_resource { 384 __le16 resource_id; 385 __le16 access_type; 386 __le32 timeout; 387 __le32 resource_number; 388 u8 reserved[4]; 389}; 390 391I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 392 393/* Get function capabilities (indirect 0x000A) 394 * Get device capabilities (indirect 0x000B) 395 */ 396struct i40e_aqc_list_capabilites { 397 u8 command_flags; 398#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 399 u8 pf_index; 400 u8 reserved[2]; 401 __le32 count; 402 __le32 addr_high; 403 __le32 addr_low; 404}; 405 406I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 407 408struct i40e_aqc_list_capabilities_element_resp { 409 __le16 id; 410 u8 major_rev; 411 u8 minor_rev; 412 __le32 number; 413 __le32 logical_id; 414 __le32 phys_id; 415 u8 reserved[16]; 416}; 417 418/* list of caps */ 419 420#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 421#define I40E_AQ_CAP_ID_MNG_MODE 0x0002 422#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 423#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 424#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 425#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 426#define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 427#define I40E_AQ_CAP_ID_SRIOV 0x0012 428#define I40E_AQ_CAP_ID_VF 0x0013 429#define I40E_AQ_CAP_ID_VMDQ 0x0014 430#define I40E_AQ_CAP_ID_8021QBG 0x0015 431#define I40E_AQ_CAP_ID_8021QBR 0x0016 432#define I40E_AQ_CAP_ID_VSI 0x0017 433#define I40E_AQ_CAP_ID_DCB 0x0018 434#define I40E_AQ_CAP_ID_FCOE 0x0021 435#define I40E_AQ_CAP_ID_ISCSI 0x0022 436#define I40E_AQ_CAP_ID_RSS 0x0040 437#define I40E_AQ_CAP_ID_RXQ 0x0041 438#define I40E_AQ_CAP_ID_TXQ 0x0042 439#define I40E_AQ_CAP_ID_MSIX 0x0043 440#define I40E_AQ_CAP_ID_VF_MSIX 0x0044 441#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 442#define I40E_AQ_CAP_ID_1588 0x0046 443#define I40E_AQ_CAP_ID_IWARP 0x0051 444#define I40E_AQ_CAP_ID_LED 0x0061 445#define I40E_AQ_CAP_ID_SDP 0x0062 446#define I40E_AQ_CAP_ID_MDIO 0x0063 447#define I40E_AQ_CAP_ID_WSR_PROT 0x0064 448#define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 449#define I40E_AQ_CAP_ID_FLEX10 0x00F1 450#define I40E_AQ_CAP_ID_CEM 0x00F2 451 452/* Set CPPM Configuration (direct 0x0103) */ 453struct i40e_aqc_cppm_configuration { 454 __le16 command_flags; 455#define I40E_AQ_CPPM_EN_LTRC 0x0800 456#define I40E_AQ_CPPM_EN_DMCTH 0x1000 457#define I40E_AQ_CPPM_EN_DMCTLX 0x2000 458#define I40E_AQ_CPPM_EN_HPTC 0x4000 459#define I40E_AQ_CPPM_EN_DMARC 0x8000 460 __le16 ttlx; 461 __le32 dmacr; 462 __le16 dmcth; 463 u8 hptc; 464 u8 reserved; 465 __le32 pfltrc; 466}; 467 468I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 469 470/* Set ARP Proxy command / response (indirect 0x0104) */ 471struct i40e_aqc_arp_proxy_data { 472 __le16 command_flags; 473#define I40E_AQ_ARP_INIT_IPV4 0x0800 474#define I40E_AQ_ARP_UNSUP_CTL 0x1000 475#define I40E_AQ_ARP_ENA 0x2000 476#define I40E_AQ_ARP_ADD_IPV4 0x4000 477#define I40E_AQ_ARP_DEL_IPV4 0x8000 478 __le16 table_id; 479 __le32 enabled_offloads; 480#define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 481#define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 482 __le32 ip_addr; 483 u8 mac_addr[6]; 484 u8 reserved[2]; 485}; 486 487I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 488 489/* Set NS Proxy Table Entry Command (indirect 0x0105) */ 490struct i40e_aqc_ns_proxy_data { 491 __le16 table_idx_mac_addr_0; 492 __le16 table_idx_mac_addr_1; 493 __le16 table_idx_ipv6_0; 494 __le16 table_idx_ipv6_1; 495 __le16 control; 496#define I40E_AQ_NS_PROXY_ADD_0 0x0001 497#define I40E_AQ_NS_PROXY_DEL_0 0x0002 498#define I40E_AQ_NS_PROXY_ADD_1 0x0004 499#define I40E_AQ_NS_PROXY_DEL_1 0x0008 500#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 501#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 502#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 503#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 504#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 505#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 506#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 507#define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 508#define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 509 u8 mac_addr_0[6]; 510 u8 mac_addr_1[6]; 511 u8 local_mac_addr[6]; 512 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 513 u8 ipv6_addr_1[16]; 514}; 515 516I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 517 518/* Manage LAA Command (0x0106) - obsolete */ 519struct i40e_aqc_mng_laa { 520 __le16 command_flags; 521#define I40E_AQ_LAA_FLAG_WR 0x8000 522 u8 reserved[2]; 523 __le32 sal; 524 __le16 sah; 525 u8 reserved2[6]; 526}; 527 528I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 529 530/* Manage MAC Address Read Command (indirect 0x0107) */ 531struct i40e_aqc_mac_address_read { 532 __le16 command_flags; 533#define I40E_AQC_LAN_ADDR_VALID 0x10 534#define I40E_AQC_SAN_ADDR_VALID 0x20 535#define I40E_AQC_PORT_ADDR_VALID 0x40 536#define I40E_AQC_WOL_ADDR_VALID 0x80 537#define I40E_AQC_MC_MAG_EN_VALID 0x100 538#define I40E_AQC_ADDR_VALID_MASK 0x1F0 539 u8 reserved[6]; 540 __le32 addr_high; 541 __le32 addr_low; 542}; 543 544I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 545 546struct i40e_aqc_mac_address_read_data { 547 u8 pf_lan_mac[6]; 548 u8 pf_san_mac[6]; 549 u8 port_mac[6]; 550 u8 pf_wol_mac[6]; 551}; 552 553I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 554 555/* Manage MAC Address Write Command (0x0108) */ 556struct i40e_aqc_mac_address_write { 557 __le16 command_flags; 558#define I40E_AQC_MC_MAG_EN 0x0100 559#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 560#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 561#define I40E_AQC_WRITE_TYPE_PORT 0x8000 562#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 563#define I40E_AQC_WRITE_TYPE_MASK 0xC000 564 565 __le16 mac_sah; 566 __le32 mac_sal; 567 u8 reserved[8]; 568}; 569 570I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 571 572/* PXE commands (0x011x) */ 573 574/* Clear PXE Command and response (direct 0x0110) */ 575struct i40e_aqc_clear_pxe { 576 u8 rx_cnt; 577 u8 reserved[15]; 578}; 579 580I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 581 582/* Set WoL Filter (0x0120) */ 583 584struct i40e_aqc_set_wol_filter { 585 __le16 filter_index; 586#define I40E_AQC_MAX_NUM_WOL_FILTERS 8 587#define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 588#define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ 589 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) 590 591#define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 592#define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ 593 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) 594 __le16 cmd_flags; 595#define I40E_AQC_SET_WOL_FILTER 0x8000 596#define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 597#define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 598#define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 599 __le16 valid_flags; 600#define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 601#define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 602 u8 reserved[2]; 603 __le32 address_high; 604 __le32 address_low; 605}; 606 607I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); 608 609struct i40e_aqc_set_wol_filter_data { 610 u8 filter[128]; 611 u8 mask[16]; 612}; 613 614I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); 615 616/* Get Wake Reason (0x0121) */ 617 618struct i40e_aqc_get_wake_reason_completion { 619 u8 reserved_1[2]; 620 __le16 wake_reason; 621#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 622#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ 623 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) 624#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 625#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ 626 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) 627 u8 reserved_2[12]; 628}; 629 630I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); 631 632/* Switch configuration commands (0x02xx) */ 633 634/* Used by many indirect commands that only pass an seid and a buffer in the 635 * command 636 */ 637struct i40e_aqc_switch_seid { 638 __le16 seid; 639 u8 reserved[6]; 640 __le32 addr_high; 641 __le32 addr_low; 642}; 643 644I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 645 646/* Get Switch Configuration command (indirect 0x0200) 647 * uses i40e_aqc_switch_seid for the descriptor 648 */ 649struct i40e_aqc_get_switch_config_header_resp { 650 __le16 num_reported; 651 __le16 num_total; 652 u8 reserved[12]; 653}; 654 655I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 656 657struct i40e_aqc_switch_config_element_resp { 658 u8 element_type; 659#define I40E_AQ_SW_ELEM_TYPE_MAC 1 660#define I40E_AQ_SW_ELEM_TYPE_PF 2 661#define I40E_AQ_SW_ELEM_TYPE_VF 3 662#define I40E_AQ_SW_ELEM_TYPE_EMP 4 663#define I40E_AQ_SW_ELEM_TYPE_BMC 5 664#define I40E_AQ_SW_ELEM_TYPE_PV 16 665#define I40E_AQ_SW_ELEM_TYPE_VEB 17 666#define I40E_AQ_SW_ELEM_TYPE_PA 18 667#define I40E_AQ_SW_ELEM_TYPE_VSI 19 668 u8 revision; 669#define I40E_AQ_SW_ELEM_REV_1 1 670 __le16 seid; 671 __le16 uplink_seid; 672 __le16 downlink_seid; 673 u8 reserved[3]; 674 u8 connection_type; 675#define I40E_AQ_CONN_TYPE_REGULAR 0x1 676#define I40E_AQ_CONN_TYPE_DEFAULT 0x2 677#define I40E_AQ_CONN_TYPE_CASCADED 0x3 678 __le16 scheduler_id; 679 __le16 element_info; 680}; 681 682I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 683 684/* Get Switch Configuration (indirect 0x0200) 685 * an array of elements are returned in the response buffer 686 * the first in the array is the header, remainder are elements 687 */ 688struct i40e_aqc_get_switch_config_resp { 689 struct i40e_aqc_get_switch_config_header_resp header; 690 struct i40e_aqc_switch_config_element_resp element[1]; 691}; 692 693I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 694 695/* Add Statistics (direct 0x0201) 696 * Remove Statistics (direct 0x0202) 697 */ 698struct i40e_aqc_add_remove_statistics { 699 __le16 seid; 700 __le16 vlan; 701 __le16 stat_index; 702 u8 reserved[10]; 703}; 704 705I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 706 707/* Set Port Parameters command (direct 0x0203) */ 708struct i40e_aqc_set_port_parameters { 709 __le16 command_flags; 710#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 711#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 712#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 713 __le16 bad_frame_vsi; 714#define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 715#define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF 716 __le16 default_seid; /* reserved for command */ 717 u8 reserved[10]; 718}; 719 720I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 721 722/* Get Switch Resource Allocation (indirect 0x0204) */ 723struct i40e_aqc_get_switch_resource_alloc { 724 u8 num_entries; /* reserved for command */ 725 u8 reserved[7]; 726 __le32 addr_high; 727 __le32 addr_low; 728}; 729 730I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 731 732/* expect an array of these structs in the response buffer */ 733struct i40e_aqc_switch_resource_alloc_element_resp { 734 u8 resource_type; 735#define I40E_AQ_RESOURCE_TYPE_VEB 0x0 736#define I40E_AQ_RESOURCE_TYPE_VSI 0x1 737#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 738#define I40E_AQ_RESOURCE_TYPE_STAG 0x3 739#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 740#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 741#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 742#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 743#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 744#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 745#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 746#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 747#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 748#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 749#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 750#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 751#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 752#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 753#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 754 u8 reserved1; 755 __le16 guaranteed; 756 __le16 total; 757 __le16 used; 758 __le16 total_unalloced; 759 u8 reserved2[6]; 760}; 761 762I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 763 764/* Set Switch Configuration (direct 0x0205) */ 765struct i40e_aqc_set_switch_config { 766 __le16 flags; 767/* flags used for both fields below */ 768#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 769#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 770 __le16 valid_flags; 771 u8 reserved[12]; 772}; 773 774I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 775 776/* Read Receive control registers (direct 0x0206) 777 * Write Receive control registers (direct 0x0207) 778 * used for accessing Rx control registers that can be 779 * slow and need special handling when under high Rx load 780 */ 781struct i40e_aqc_rx_ctl_reg_read_write { 782 __le32 reserved1; 783 __le32 address; 784 __le32 reserved2; 785 __le32 value; 786}; 787 788I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 789 790/* Add VSI (indirect 0x0210) 791 * this indirect command uses struct i40e_aqc_vsi_properties_data 792 * as the indirect buffer (128 bytes) 793 * 794 * Update VSI (indirect 0x211) 795 * uses the same data structure as Add VSI 796 * 797 * Get VSI (indirect 0x0212) 798 * uses the same completion and data structure as Add VSI 799 */ 800struct i40e_aqc_add_get_update_vsi { 801 __le16 uplink_seid; 802 u8 connection_type; 803#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 804#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 805#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 806 u8 reserved1; 807 u8 vf_id; 808 u8 reserved2; 809 __le16 vsi_flags; 810#define I40E_AQ_VSI_TYPE_SHIFT 0x0 811#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 812#define I40E_AQ_VSI_TYPE_VF 0x0 813#define I40E_AQ_VSI_TYPE_VMDQ2 0x1 814#define I40E_AQ_VSI_TYPE_PF 0x2 815#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 816#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 817 __le32 addr_high; 818 __le32 addr_low; 819}; 820 821I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 822 823struct i40e_aqc_add_get_update_vsi_completion { 824 __le16 seid; 825 __le16 vsi_number; 826 __le16 vsi_used; 827 __le16 vsi_free; 828 __le32 addr_high; 829 __le32 addr_low; 830}; 831 832I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 833 834struct i40e_aqc_vsi_properties_data { 835 /* first 96 byte are written by SW */ 836 __le16 valid_sections; 837#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 838#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 839#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 840#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 841#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 842#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 843#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 844#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 845#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 846#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 847 /* switch section */ 848 __le16 switch_id; /* 12bit id combined with flags below */ 849#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 850#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 851#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 852#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 853#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 854 u8 sw_reserved[2]; 855 /* security section */ 856 u8 sec_flags; 857#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 858#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 859#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 860 u8 sec_reserved; 861 /* VLAN section */ 862 __le16 pvid; /* VLANS include priority bits */ 863 __le16 fcoe_pvid; 864 u8 port_vlan_flags; 865#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 866#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 867 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 868#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 869#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 870#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 871#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 872#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 873#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 874 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 875#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 876#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 877#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 878#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 879 u8 pvlan_reserved[3]; 880 /* ingress egress up sections */ 881 __le32 ingress_table; /* bitmap, 3 bits per up */ 882#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 883#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 884 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 885#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 886#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 887 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 888#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 889#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 890 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 891#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 892#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 893 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 894#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 895#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 896 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 897#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 898#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 899 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 900#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 901#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 902 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 903#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 904#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 905 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 906 __le32 egress_table; /* same defines as for ingress table */ 907 /* cascaded PV section */ 908 __le16 cas_pv_tag; 909 u8 cas_pv_flags; 910#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 911#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 912 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 913#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 914#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 915#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 916#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 917#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 918#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 919 u8 cas_pv_reserved; 920 /* queue mapping section */ 921 __le16 mapping_flags; 922#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 923#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 924 __le16 queue_mapping[16]; 925#define I40E_AQ_VSI_QUEUE_SHIFT 0x0 926#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 927 __le16 tc_mapping[8]; 928#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 929#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 930 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 931#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 932#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 933 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 934 /* queueing option section */ 935 u8 queueing_opt_flags; 936#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 937#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 938#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 939#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 940#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 941#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 942 u8 queueing_opt_reserved[3]; 943 /* scheduler section */ 944 u8 up_enable_bits; 945 u8 sched_reserved; 946 /* outer up section */ 947 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 948 u8 cmd_reserved[8]; 949 /* last 32 bytes are written by FW */ 950 __le16 qs_handle[8]; 951#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 952 __le16 stat_counter_idx; 953 __le16 sched_id; 954 u8 resp_reserved[12]; 955}; 956 957I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 958 959/* Add Port Virtualizer (direct 0x0220) 960 * also used for update PV (direct 0x0221) but only flags are used 961 * (IS_CTRL_PORT only works on add PV) 962 */ 963struct i40e_aqc_add_update_pv { 964 __le16 command_flags; 965#define I40E_AQC_PV_FLAG_PV_TYPE 0x1 966#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 967#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 968#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 969 __le16 uplink_seid; 970 __le16 connected_seid; 971 u8 reserved[10]; 972}; 973 974I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 975 976struct i40e_aqc_add_update_pv_completion { 977 /* reserved for update; for add also encodes error if rc == ENOSPC */ 978 __le16 pv_seid; 979#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 980#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 981#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 982#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 983 u8 reserved[14]; 984}; 985 986I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 987 988/* Get PV Params (direct 0x0222) 989 * uses i40e_aqc_switch_seid for the descriptor 990 */ 991 992struct i40e_aqc_get_pv_params_completion { 993 __le16 seid; 994 __le16 default_stag; 995 __le16 pv_flags; /* same flags as add_pv */ 996#define I40E_AQC_GET_PV_PV_TYPE 0x1 997#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 998#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 999 u8 reserved[8]; 1000 __le16 default_port_seid; 1001}; 1002 1003I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 1004 1005/* Add VEB (direct 0x0230) */ 1006struct i40e_aqc_add_veb { 1007 __le16 uplink_seid; 1008 __le16 downlink_seid; 1009 __le16 veb_flags; 1010#define I40E_AQC_ADD_VEB_FLOATING 0x1 1011#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 1012#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 1013 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 1014#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 1015#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 1016#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 1017#define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 1018 u8 enable_tcs; 1019 u8 reserved[9]; 1020}; 1021 1022I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 1023 1024struct i40e_aqc_add_veb_completion { 1025 u8 reserved[6]; 1026 __le16 switch_seid; 1027 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 1028 __le16 veb_seid; 1029#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 1030#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 1031#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 1032#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 1033 __le16 statistic_index; 1034 __le16 vebs_used; 1035 __le16 vebs_free; 1036}; 1037 1038I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 1039 1040/* Get VEB Parameters (direct 0x0232) 1041 * uses i40e_aqc_switch_seid for the descriptor 1042 */ 1043struct i40e_aqc_get_veb_parameters_completion { 1044 __le16 seid; 1045 __le16 switch_id; 1046 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 1047 __le16 statistic_index; 1048 __le16 vebs_used; 1049 __le16 vebs_free; 1050 u8 reserved[4]; 1051}; 1052 1053I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 1054 1055/* Delete Element (direct 0x0243) 1056 * uses the generic i40e_aqc_switch_seid 1057 */ 1058 1059/* Add MAC-VLAN (indirect 0x0250) */ 1060 1061/* used for the command for most vlan commands */ 1062struct i40e_aqc_macvlan { 1063 __le16 num_addresses; 1064 __le16 seid[3]; 1065#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 1066#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 1067 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1068#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 1069 __le32 addr_high; 1070 __le32 addr_low; 1071}; 1072 1073I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 1074 1075/* indirect data for command and response */ 1076struct i40e_aqc_add_macvlan_element_data { 1077 u8 mac_addr[6]; 1078 __le16 vlan_tag; 1079 __le16 flags; 1080#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 1081#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 1082#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 1083#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 1084#define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 1085 __le16 queue_number; 1086#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 1087#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 1088 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1089 /* response section */ 1090 u8 match_method; 1091#define I40E_AQC_MM_PERFECT_MATCH 0x01 1092#define I40E_AQC_MM_HASH_MATCH 0x02 1093#define I40E_AQC_MM_ERR_NO_RES 0xFF 1094 u8 reserved1[3]; 1095}; 1096 1097struct i40e_aqc_add_remove_macvlan_completion { 1098 __le16 perfect_mac_used; 1099 __le16 perfect_mac_free; 1100 __le16 unicast_hash_free; 1101 __le16 multicast_hash_free; 1102 __le32 addr_high; 1103 __le32 addr_low; 1104}; 1105 1106I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1107 1108/* Remove MAC-VLAN (indirect 0x0251) 1109 * uses i40e_aqc_macvlan for the descriptor 1110 * data points to an array of num_addresses of elements 1111 */ 1112 1113struct i40e_aqc_remove_macvlan_element_data { 1114 u8 mac_addr[6]; 1115 __le16 vlan_tag; 1116 u8 flags; 1117#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1118#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1119#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1120#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1121 u8 reserved[3]; 1122 /* reply section */ 1123 u8 error_code; 1124#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1125#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1126 u8 reply_reserved[3]; 1127}; 1128 1129/* Add VLAN (indirect 0x0252) 1130 * Remove VLAN (indirect 0x0253) 1131 * use the generic i40e_aqc_macvlan for the command 1132 */ 1133struct i40e_aqc_add_remove_vlan_element_data { 1134 __le16 vlan_tag; 1135 u8 vlan_flags; 1136/* flags for add VLAN */ 1137#define I40E_AQC_ADD_VLAN_LOCAL 0x1 1138#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1139#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1140#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1141#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1142#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1143#define I40E_AQC_VLAN_PTYPE_SHIFT 3 1144#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1145#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1146#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1147#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1148#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1149/* flags for remove VLAN */ 1150#define I40E_AQC_REMOVE_VLAN_ALL 0x1 1151 u8 reserved; 1152 u8 result; 1153/* flags for add VLAN */ 1154#define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1155#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1156#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1157/* flags for remove VLAN */ 1158#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1159#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1160 u8 reserved1[3]; 1161}; 1162 1163struct i40e_aqc_add_remove_vlan_completion { 1164 u8 reserved[4]; 1165 __le16 vlans_used; 1166 __le16 vlans_free; 1167 __le32 addr_high; 1168 __le32 addr_low; 1169}; 1170 1171/* Set VSI Promiscuous Modes (direct 0x0254) */ 1172struct i40e_aqc_set_vsi_promiscuous_modes { 1173 __le16 promiscuous_flags; 1174 __le16 valid_flags; 1175/* flags used for both fields above */ 1176#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1177#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1178#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1179#define I40E_AQC_SET_VSI_DEFAULT 0x08 1180#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1181#define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 1182 __le16 seid; 1183#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1184 __le16 vlan_tag; 1185#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1186#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1187 u8 reserved[8]; 1188}; 1189 1190I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1191 1192/* Add S/E-tag command (direct 0x0255) 1193 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1194 */ 1195struct i40e_aqc_add_tag { 1196 __le16 flags; 1197#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1198 __le16 seid; 1199#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1200#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1201 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1202 __le16 tag; 1203 __le16 queue_number; 1204 u8 reserved[8]; 1205}; 1206 1207I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1208 1209struct i40e_aqc_add_remove_tag_completion { 1210 u8 reserved[12]; 1211 __le16 tags_used; 1212 __le16 tags_free; 1213}; 1214 1215I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1216 1217/* Remove S/E-tag command (direct 0x0256) 1218 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1219 */ 1220struct i40e_aqc_remove_tag { 1221 __le16 seid; 1222#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1223#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1224 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1225 __le16 tag; 1226 u8 reserved[12]; 1227}; 1228 1229I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1230 1231/* Add multicast E-Tag (direct 0x0257) 1232 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1233 * and no external data 1234 */ 1235struct i40e_aqc_add_remove_mcast_etag { 1236 __le16 pv_seid; 1237 __le16 etag; 1238 u8 num_unicast_etags; 1239 u8 reserved[3]; 1240 __le32 addr_high; /* address of array of 2-byte s-tags */ 1241 __le32 addr_low; 1242}; 1243 1244I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1245 1246struct i40e_aqc_add_remove_mcast_etag_completion { 1247 u8 reserved[4]; 1248 __le16 mcast_etags_used; 1249 __le16 mcast_etags_free; 1250 __le32 addr_high; 1251 __le32 addr_low; 1252 1253}; 1254 1255I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1256 1257/* Update S/E-Tag (direct 0x0259) */ 1258struct i40e_aqc_update_tag { 1259 __le16 seid; 1260#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1261#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1262 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1263 __le16 old_tag; 1264 __le16 new_tag; 1265 u8 reserved[10]; 1266}; 1267 1268I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1269 1270struct i40e_aqc_update_tag_completion { 1271 u8 reserved[12]; 1272 __le16 tags_used; 1273 __le16 tags_free; 1274}; 1275 1276I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1277 1278/* Add Control Packet filter (direct 0x025A) 1279 * Remove Control Packet filter (direct 0x025B) 1280 * uses the i40e_aqc_add_oveb_cloud, 1281 * and the generic direct completion structure 1282 */ 1283struct i40e_aqc_add_remove_control_packet_filter { 1284 u8 mac[6]; 1285 __le16 etype; 1286 __le16 flags; 1287#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1288#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1289#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1290#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1291#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1292 __le16 seid; 1293#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1294#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1295 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1296 __le16 queue; 1297 u8 reserved[2]; 1298}; 1299 1300I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1301 1302struct i40e_aqc_add_remove_control_packet_filter_completion { 1303 __le16 mac_etype_used; 1304 __le16 etype_used; 1305 __le16 mac_etype_free; 1306 __le16 etype_free; 1307 u8 reserved[8]; 1308}; 1309 1310I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1311 1312/* Add Cloud filters (indirect 0x025C) 1313 * Remove Cloud filters (indirect 0x025D) 1314 * uses the i40e_aqc_add_remove_cloud_filters, 1315 * and the generic indirect completion structure 1316 */ 1317struct i40e_aqc_add_remove_cloud_filters { 1318 u8 num_filters; 1319 u8 reserved; 1320 __le16 seid; 1321#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1322#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1323 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1324 u8 reserved2[4]; 1325 __le32 addr_high; 1326 __le32 addr_low; 1327}; 1328 1329I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1330 1331struct i40e_aqc_add_remove_cloud_filters_element_data { 1332 u8 outer_mac[6]; 1333 u8 inner_mac[6]; 1334 __le16 inner_vlan; 1335 union { 1336 struct { 1337 u8 reserved[12]; 1338 u8 data[4]; 1339 } v4; 1340 struct { 1341 u8 data[16]; 1342 } v6; 1343 } ipaddr; 1344 __le16 flags; 1345#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1346#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1347 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1348/* 0x0000 reserved */ 1349#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1350/* 0x0002 reserved */ 1351#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1352#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1353/* 0x0005 reserved */ 1354#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1355/* 0x0007 reserved */ 1356/* 0x0008 reserved */ 1357#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1358#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1359#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1360#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1361 1362#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1363#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1364#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1365#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1366#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1367 1368#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1369#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1370#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1371#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1372#define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1373#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1374#define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1375#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1376 1377#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1378#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1379#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1380 1381 __le32 tenant_id; 1382 u8 reserved[4]; 1383 __le16 queue_number; 1384#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1385#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1386 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1387 u8 reserved2[14]; 1388 /* response section */ 1389 u8 allocation_result; 1390#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1391#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1392 u8 response_reserved[7]; 1393}; 1394 1395struct i40e_aqc_remove_cloud_filters_completion { 1396 __le16 perfect_ovlan_used; 1397 __le16 perfect_ovlan_free; 1398 __le16 vlan_used; 1399 __le16 vlan_free; 1400 __le32 addr_high; 1401 __le32 addr_low; 1402}; 1403 1404I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1405 1406/* Add Mirror Rule (indirect or direct 0x0260) 1407 * Delete Mirror Rule (indirect or direct 0x0261) 1408 * note: some rule types (4,5) do not use an external buffer. 1409 * take care to set the flags correctly. 1410 */ 1411struct i40e_aqc_add_delete_mirror_rule { 1412 __le16 seid; 1413 __le16 rule_type; 1414#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1415#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1416 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1417#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1418#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1419#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1420#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1421#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1422 __le16 num_entries; 1423 __le16 destination; /* VSI for add, rule id for delete */ 1424 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1425 __le32 addr_low; 1426}; 1427 1428I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1429 1430struct i40e_aqc_add_delete_mirror_rule_completion { 1431 u8 reserved[2]; 1432 __le16 rule_id; /* only used on add */ 1433 __le16 mirror_rules_used; 1434 __le16 mirror_rules_free; 1435 __le32 addr_high; 1436 __le32 addr_low; 1437}; 1438 1439I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1440 1441/* DCB 0x03xx*/ 1442 1443/* PFC Ignore (direct 0x0301) 1444 * the command and response use the same descriptor structure 1445 */ 1446struct i40e_aqc_pfc_ignore { 1447 u8 tc_bitmap; 1448 u8 command_flags; /* unused on response */ 1449#define I40E_AQC_PFC_IGNORE_SET 0x80 1450#define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1451 u8 reserved[14]; 1452}; 1453 1454I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1455 1456/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1457 * with no parameters 1458 */ 1459 1460/* TX scheduler 0x04xx */ 1461 1462/* Almost all the indirect commands use 1463 * this generic struct to pass the SEID in param0 1464 */ 1465struct i40e_aqc_tx_sched_ind { 1466 __le16 vsi_seid; 1467 u8 reserved[6]; 1468 __le32 addr_high; 1469 __le32 addr_low; 1470}; 1471 1472I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1473 1474/* Several commands respond with a set of queue set handles */ 1475struct i40e_aqc_qs_handles_resp { 1476 __le16 qs_handles[8]; 1477}; 1478 1479/* Configure VSI BW limits (direct 0x0400) */ 1480struct i40e_aqc_configure_vsi_bw_limit { 1481 __le16 vsi_seid; 1482 u8 reserved[2]; 1483 __le16 credit; 1484 u8 reserved1[2]; 1485 u8 max_credit; /* 0-3, limit = 2^max */ 1486 u8 reserved2[7]; 1487}; 1488 1489I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1490 1491/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1492 * responds with i40e_aqc_qs_handles_resp 1493 */ 1494struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1495 u8 tc_valid_bits; 1496 u8 reserved[15]; 1497 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1498 1499 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1500 __le16 tc_bw_max[2]; 1501 u8 reserved1[28]; 1502}; 1503 1504I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1505 1506/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1507 * responds with i40e_aqc_qs_handles_resp 1508 */ 1509struct i40e_aqc_configure_vsi_tc_bw_data { 1510 u8 tc_valid_bits; 1511 u8 reserved[3]; 1512 u8 tc_bw_credits[8]; 1513 u8 reserved1[4]; 1514 __le16 qs_handles[8]; 1515}; 1516 1517I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1518 1519/* Query vsi bw configuration (indirect 0x0408) */ 1520struct i40e_aqc_query_vsi_bw_config_resp { 1521 u8 tc_valid_bits; 1522 u8 tc_suspended_bits; 1523 u8 reserved[14]; 1524 __le16 qs_handles[8]; 1525 u8 reserved1[4]; 1526 __le16 port_bw_limit; 1527 u8 reserved2[2]; 1528 u8 max_bw; /* 0-3, limit = 2^max */ 1529 u8 reserved3[23]; 1530}; 1531 1532I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1533 1534/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1535struct i40e_aqc_query_vsi_ets_sla_config_resp { 1536 u8 tc_valid_bits; 1537 u8 reserved[3]; 1538 u8 share_credits[8]; 1539 __le16 credits[8]; 1540 1541 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1542 __le16 tc_bw_max[2]; 1543}; 1544 1545I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1546 1547/* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1548struct i40e_aqc_configure_switching_comp_bw_limit { 1549 __le16 seid; 1550 u8 reserved[2]; 1551 __le16 credit; 1552 u8 reserved1[2]; 1553 u8 max_bw; /* 0-3, limit = 2^max */ 1554 u8 reserved2[7]; 1555}; 1556 1557I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1558 1559/* Enable Physical Port ETS (indirect 0x0413) 1560 * Modify Physical Port ETS (indirect 0x0414) 1561 * Disable Physical Port ETS (indirect 0x0415) 1562 */ 1563struct i40e_aqc_configure_switching_comp_ets_data { 1564 u8 reserved[4]; 1565 u8 tc_valid_bits; 1566 u8 seepage; 1567#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1568 u8 tc_strict_priority_flags; 1569 u8 reserved1[17]; 1570 u8 tc_bw_share_credits[8]; 1571 u8 reserved2[96]; 1572}; 1573 1574I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1575 1576/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1577struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1578 u8 tc_valid_bits; 1579 u8 reserved[15]; 1580 __le16 tc_bw_credit[8]; 1581 1582 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1583 __le16 tc_bw_max[2]; 1584 u8 reserved1[28]; 1585}; 1586 1587I40E_CHECK_STRUCT_LEN(0x40, 1588 i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1589 1590/* Configure Switching Component Bandwidth Allocation per Tc 1591 * (indirect 0x0417) 1592 */ 1593struct i40e_aqc_configure_switching_comp_bw_config_data { 1594 u8 tc_valid_bits; 1595 u8 reserved[2]; 1596 u8 absolute_credits; /* bool */ 1597 u8 tc_bw_share_credits[8]; 1598 u8 reserved1[20]; 1599}; 1600 1601I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1602 1603/* Query Switching Component Configuration (indirect 0x0418) */ 1604struct i40e_aqc_query_switching_comp_ets_config_resp { 1605 u8 tc_valid_bits; 1606 u8 reserved[35]; 1607 __le16 port_bw_limit; 1608 u8 reserved1[2]; 1609 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1610 u8 reserved2[23]; 1611}; 1612 1613I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1614 1615/* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1616struct i40e_aqc_query_port_ets_config_resp { 1617 u8 reserved[4]; 1618 u8 tc_valid_bits; 1619 u8 reserved1; 1620 u8 tc_strict_priority_bits; 1621 u8 reserved2; 1622 u8 tc_bw_share_credits[8]; 1623 __le16 tc_bw_limits[8]; 1624 1625 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1626 __le16 tc_bw_max[2]; 1627 u8 reserved3[32]; 1628}; 1629 1630I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1631 1632/* Query Switching Component Bandwidth Allocation per Traffic Type 1633 * (indirect 0x041A) 1634 */ 1635struct i40e_aqc_query_switching_comp_bw_config_resp { 1636 u8 tc_valid_bits; 1637 u8 reserved[2]; 1638 u8 absolute_credits_enable; /* bool */ 1639 u8 tc_bw_share_credits[8]; 1640 __le16 tc_bw_limits[8]; 1641 1642 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1643 __le16 tc_bw_max[2]; 1644}; 1645 1646I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1647 1648/* Suspend/resume port TX traffic 1649 * (direct 0x041B and 0x041C) uses the generic SEID struct 1650 */ 1651 1652/* Configure partition BW 1653 * (indirect 0x041D) 1654 */ 1655struct i40e_aqc_configure_partition_bw_data { 1656 __le16 pf_valid_bits; 1657 u8 min_bw[16]; /* guaranteed bandwidth */ 1658 u8 max_bw[16]; /* bandwidth limit */ 1659}; 1660 1661I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1662 1663/* Get and set the active HMC resource profile and status. 1664 * (direct 0x0500) and (direct 0x0501) 1665 */ 1666struct i40e_aq_get_set_hmc_resource_profile { 1667 u8 pm_profile; 1668 u8 pe_vf_enabled; 1669 u8 reserved[14]; 1670}; 1671 1672I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1673 1674enum i40e_aq_hmc_profile { 1675 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1676 I40E_HMC_PROFILE_DEFAULT = 1, 1677 I40E_HMC_PROFILE_FAVOR_VF = 2, 1678 I40E_HMC_PROFILE_EQUAL = 3, 1679}; 1680 1681/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1682 1683/* set in param0 for get phy abilities to report qualified modules */ 1684#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1685#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1686 1687enum i40e_aq_phy_type { 1688 I40E_PHY_TYPE_SGMII = 0x0, 1689 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1690 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1691 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1692 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1693 I40E_PHY_TYPE_XAUI = 0x5, 1694 I40E_PHY_TYPE_XFI = 0x6, 1695 I40E_PHY_TYPE_SFI = 0x7, 1696 I40E_PHY_TYPE_XLAUI = 0x8, 1697 I40E_PHY_TYPE_XLPPI = 0x9, 1698 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1699 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1700 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1701 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1702 I40E_PHY_TYPE_100BASE_TX = 0x11, 1703 I40E_PHY_TYPE_1000BASE_T = 0x12, 1704 I40E_PHY_TYPE_10GBASE_T = 0x13, 1705 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1706 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1707 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1708 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1709 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1710 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1711 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1712 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1713 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1714 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1715 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1716 I40E_PHY_TYPE_25GBASE_KR = 0x1F, 1717 I40E_PHY_TYPE_25GBASE_CR = 0x20, 1718 I40E_PHY_TYPE_25GBASE_SR = 0x21, 1719 I40E_PHY_TYPE_25GBASE_LR = 0x22, 1720 I40E_PHY_TYPE_MAX 1721}; 1722 1723#define I40E_LINK_SPEED_100MB_SHIFT 0x1 1724#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1725#define I40E_LINK_SPEED_10GB_SHIFT 0x3 1726#define I40E_LINK_SPEED_40GB_SHIFT 0x4 1727#define I40E_LINK_SPEED_20GB_SHIFT 0x5 1728#define I40E_LINK_SPEED_25GB_SHIFT 0x6 1729 1730enum i40e_aq_link_speed { 1731 I40E_LINK_SPEED_UNKNOWN = 0, 1732 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1733 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1734 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1735 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1736 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT), 1737 I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT), 1738}; 1739 1740struct i40e_aqc_module_desc { 1741 u8 oui[3]; 1742 u8 reserved1; 1743 u8 part_number[16]; 1744 u8 revision[4]; 1745 u8 reserved2[8]; 1746}; 1747 1748I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1749 1750struct i40e_aq_get_phy_abilities_resp { 1751 __le32 phy_type; /* bitmap using the above enum for offsets */ 1752 u8 link_speed; /* bitmap using the above enum bit patterns */ 1753 u8 abilities; 1754#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1755#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1756#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1757#define I40E_AQ_PHY_LINK_ENABLED 0x08 1758#define I40E_AQ_PHY_AN_ENABLED 0x10 1759#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1760 __le16 eee_capability; 1761#define I40E_AQ_EEE_100BASE_TX 0x0002 1762#define I40E_AQ_EEE_1000BASE_T 0x0004 1763#define I40E_AQ_EEE_10GBASE_T 0x0008 1764#define I40E_AQ_EEE_1000BASE_KX 0x0010 1765#define I40E_AQ_EEE_10GBASE_KX4 0x0020 1766#define I40E_AQ_EEE_10GBASE_KR 0x0040 1767 __le32 eeer_val; 1768 u8 d3_lpan; 1769#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1770 u8 phy_type_ext; 1771#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 1772#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 1773#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 1774#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 1775 u8 mod_type_ext; 1776 u8 ext_comp_code; 1777 u8 phy_id[4]; 1778 u8 module_type[3]; 1779 u8 qualified_module_count; 1780#define I40E_AQ_PHY_MAX_QMS 16 1781 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1782}; 1783 1784I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1785 1786/* Set PHY Config (direct 0x0601) */ 1787struct i40e_aq_set_phy_config { /* same bits as above in all */ 1788 __le32 phy_type; 1789 u8 link_speed; 1790 u8 abilities; 1791/* bits 0-2 use the values from get_phy_abilities_resp */ 1792#define I40E_AQ_PHY_ENABLE_LINK 0x08 1793#define I40E_AQ_PHY_ENABLE_AN 0x10 1794#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1795 __le16 eee_capability; 1796 __le32 eeer; 1797 u8 low_power_ctrl; 1798 u8 phy_type_ext; 1799#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 1800#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 1801#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 1802#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 1803 u8 reserved[2]; 1804}; 1805 1806I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1807 1808/* Set MAC Config command data structure (direct 0x0603) */ 1809struct i40e_aq_set_mac_config { 1810 __le16 max_frame_size; 1811 u8 params; 1812#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1813#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1814#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1815#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1816#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1817#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1818#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1819#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1820#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1821#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1822#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1823#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1824#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1825#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1826 u8 tx_timer_priority; /* bitmap */ 1827 __le16 tx_timer_value; 1828 __le16 fc_refresh_threshold; 1829 u8 reserved[8]; 1830}; 1831 1832I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1833 1834/* Restart Auto-Negotiation (direct 0x605) */ 1835struct i40e_aqc_set_link_restart_an { 1836 u8 command; 1837#define I40E_AQ_PHY_RESTART_AN 0x02 1838#define I40E_AQ_PHY_LINK_ENABLE 0x04 1839 u8 reserved[15]; 1840}; 1841 1842I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1843 1844/* Get Link Status cmd & response data structure (direct 0x0607) */ 1845struct i40e_aqc_get_link_status { 1846 __le16 command_flags; /* only field set on command */ 1847#define I40E_AQ_LSE_MASK 0x3 1848#define I40E_AQ_LSE_NOP 0x0 1849#define I40E_AQ_LSE_DISABLE 0x2 1850#define I40E_AQ_LSE_ENABLE 0x3 1851/* only response uses this flag */ 1852#define I40E_AQ_LSE_IS_ENABLED 0x1 1853 u8 phy_type; /* i40e_aq_phy_type */ 1854 u8 link_speed; /* i40e_aq_link_speed */ 1855 u8 link_info; 1856#define I40E_AQ_LINK_UP 0x01 /* obsolete */ 1857#define I40E_AQ_LINK_UP_FUNCTION 0x01 1858#define I40E_AQ_LINK_FAULT 0x02 1859#define I40E_AQ_LINK_FAULT_TX 0x04 1860#define I40E_AQ_LINK_FAULT_RX 0x08 1861#define I40E_AQ_LINK_FAULT_REMOTE 0x10 1862#define I40E_AQ_LINK_UP_PORT 0x20 1863#define I40E_AQ_MEDIA_AVAILABLE 0x40 1864#define I40E_AQ_SIGNAL_DETECT 0x80 1865 u8 an_info; 1866#define I40E_AQ_AN_COMPLETED 0x01 1867#define I40E_AQ_LP_AN_ABILITY 0x02 1868#define I40E_AQ_PD_FAULT 0x04 1869#define I40E_AQ_FEC_EN 0x08 1870#define I40E_AQ_PHY_LOW_POWER 0x10 1871#define I40E_AQ_LINK_PAUSE_TX 0x20 1872#define I40E_AQ_LINK_PAUSE_RX 0x40 1873#define I40E_AQ_QUALIFIED_MODULE 0x80 1874 u8 ext_info; 1875#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1876#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1877#define I40E_AQ_LINK_TX_SHIFT 0x02 1878#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1879#define I40E_AQ_LINK_TX_ACTIVE 0x00 1880#define I40E_AQ_LINK_TX_DRAINED 0x01 1881#define I40E_AQ_LINK_TX_FLUSHED 0x03 1882#define I40E_AQ_LINK_FORCED_40G 0x10 1883/* 25G Error Codes */ 1884#define I40E_AQ_25G_NO_ERR 0X00 1885#define I40E_AQ_25G_NOT_PRESENT 0X01 1886#define I40E_AQ_25G_NVM_CRC_ERR 0X02 1887#define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 1888#define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 1889#define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 1890 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1891 __le16 max_frame_size; 1892 u8 config; 1893#define I40E_AQ_CONFIG_CRC_ENA 0x04 1894#define I40E_AQ_CONFIG_PACING_MASK 0x78 1895 u8 power_desc; 1896#define I40E_AQ_LINK_POWER_CLASS_1 0x00 1897#define I40E_AQ_LINK_POWER_CLASS_2 0x01 1898#define I40E_AQ_LINK_POWER_CLASS_3 0x02 1899#define I40E_AQ_LINK_POWER_CLASS_4 0x03 1900#define I40E_AQ_PWR_CLASS_MASK 0x03 1901 u8 reserved[4]; 1902}; 1903 1904I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1905 1906/* Set event mask command (direct 0x613) */ 1907struct i40e_aqc_set_phy_int_mask { 1908 u8 reserved[8]; 1909 __le16 event_mask; 1910#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1911#define I40E_AQ_EVENT_MEDIA_NA 0x0004 1912#define I40E_AQ_EVENT_LINK_FAULT 0x0008 1913#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1914#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1915#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1916#define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1917#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1918#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1919 u8 reserved1[6]; 1920}; 1921 1922I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1923 1924/* Get Local AN advt register (direct 0x0614) 1925 * Set Local AN advt register (direct 0x0615) 1926 * Get Link Partner AN advt register (direct 0x0616) 1927 */ 1928struct i40e_aqc_an_advt_reg { 1929 __le32 local_an_reg0; 1930 __le16 local_an_reg1; 1931 u8 reserved[10]; 1932}; 1933 1934I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1935 1936/* Set Loopback mode (0x0618) */ 1937struct i40e_aqc_set_lb_mode { 1938 __le16 lb_mode; 1939#define I40E_AQ_LB_PHY_LOCAL 0x01 1940#define I40E_AQ_LB_PHY_REMOTE 0x02 1941#define I40E_AQ_LB_MAC_LOCAL 0x04 1942 u8 reserved[14]; 1943}; 1944 1945I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1946 1947/* Set PHY Debug command (0x0622) */ 1948struct i40e_aqc_set_phy_debug { 1949 u8 command_flags; 1950#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1951#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1952#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1953 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1954#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1955#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1956#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1957/* Disable link manageability on a single port */ 1958#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1959/* Disable link manageability on all ports needs both bits 4 and 5 */ 1960#define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 1961 u8 reserved[15]; 1962}; 1963 1964I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1965 1966enum i40e_aq_phy_reg_type { 1967 I40E_AQC_PHY_REG_INTERNAL = 0x1, 1968 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1969 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1970}; 1971 1972/* Run PHY Activity (0x0626) */ 1973struct i40e_aqc_run_phy_activity { 1974 __le16 activity_id; 1975 u8 flags; 1976 u8 reserved1; 1977 __le32 control; 1978 __le32 data; 1979 u8 reserved2[4]; 1980}; 1981 1982I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 1983 1984/* NVM Read command (indirect 0x0701) 1985 * NVM Erase commands (direct 0x0702) 1986 * NVM Update commands (indirect 0x0703) 1987 */ 1988struct i40e_aqc_nvm_update { 1989 u8 command_flags; 1990#define I40E_AQ_NVM_LAST_CMD 0x01 1991#define I40E_AQ_NVM_FLASH_ONLY 0x80 1992 u8 module_pointer; 1993 __le16 length; 1994 __le32 offset; 1995 __le32 addr_high; 1996 __le32 addr_low; 1997}; 1998 1999I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 2000 2001/* NVM Config Read (indirect 0x0704) */ 2002struct i40e_aqc_nvm_config_read { 2003 __le16 cmd_flags; 2004#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 2005#define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 2006#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 2007 __le16 element_count; 2008 __le16 element_id; /* Feature/field ID */ 2009 __le16 element_id_msw; /* MSWord of field ID */ 2010 __le32 address_high; 2011 __le32 address_low; 2012}; 2013 2014I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 2015 2016/* NVM Config Write (indirect 0x0705) */ 2017struct i40e_aqc_nvm_config_write { 2018 __le16 cmd_flags; 2019 __le16 element_count; 2020 u8 reserved[4]; 2021 __le32 address_high; 2022 __le32 address_low; 2023}; 2024 2025I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 2026 2027/* Used for 0x0704 as well as for 0x0705 commands */ 2028#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 2029#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 2030 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 2031#define I40E_AQ_ANVM_FEATURE 0 2032#define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 2033struct i40e_aqc_nvm_config_data_feature { 2034 __le16 feature_id; 2035#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 2036#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 2037#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 2038 __le16 feature_options; 2039 __le16 feature_selection; 2040}; 2041 2042I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 2043 2044struct i40e_aqc_nvm_config_data_immediate_field { 2045 __le32 field_id; 2046 __le32 field_value; 2047 __le16 field_options; 2048 __le16 reserved; 2049}; 2050 2051I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 2052 2053/* OEM Post Update (indirect 0x0720) 2054 * no command data struct used 2055 */ 2056struct i40e_aqc_nvm_oem_post_update { 2057#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 2058 u8 sel_data; 2059 u8 reserved[7]; 2060}; 2061 2062I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 2063 2064struct i40e_aqc_nvm_oem_post_update_buffer { 2065 u8 str_len; 2066 u8 dev_addr; 2067 __le16 eeprom_addr; 2068 u8 data[36]; 2069}; 2070 2071I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 2072 2073/* Thermal Sensor (indirect 0x0721) 2074 * read or set thermal sensor configs and values 2075 * takes a sensor and command specific data buffer, not detailed here 2076 */ 2077struct i40e_aqc_thermal_sensor { 2078 u8 sensor_action; 2079#define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 2080#define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 2081#define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 2082 u8 reserved[7]; 2083 __le32 addr_high; 2084 __le32 addr_low; 2085}; 2086 2087I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 2088 2089/* Send to PF command (indirect 0x0801) id is only used by PF 2090 * Send to VF command (indirect 0x0802) id is only used by PF 2091 * Send to Peer PF command (indirect 0x0803) 2092 */ 2093struct i40e_aqc_pf_vf_message { 2094 __le32 id; 2095 u8 reserved[4]; 2096 __le32 addr_high; 2097 __le32 addr_low; 2098}; 2099 2100I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 2101 2102/* Alternate structure */ 2103 2104/* Direct write (direct 0x0900) 2105 * Direct read (direct 0x0902) 2106 */ 2107struct i40e_aqc_alternate_write { 2108 __le32 address0; 2109 __le32 data0; 2110 __le32 address1; 2111 __le32 data1; 2112}; 2113 2114I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 2115 2116/* Indirect write (indirect 0x0901) 2117 * Indirect read (indirect 0x0903) 2118 */ 2119 2120struct i40e_aqc_alternate_ind_write { 2121 __le32 address; 2122 __le32 length; 2123 __le32 addr_high; 2124 __le32 addr_low; 2125}; 2126 2127I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 2128 2129/* Done alternate write (direct 0x0904) 2130 * uses i40e_aq_desc 2131 */ 2132struct i40e_aqc_alternate_write_done { 2133 __le16 cmd_flags; 2134#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 2135#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 2136#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 2137#define I40E_AQ_ALTERNATE_RESET_NEEDED 2 2138 u8 reserved[14]; 2139}; 2140 2141I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2142 2143/* Set OEM mode (direct 0x0905) */ 2144struct i40e_aqc_alternate_set_mode { 2145 __le32 mode; 2146#define I40E_AQ_ALTERNATE_MODE_NONE 0 2147#define I40E_AQ_ALTERNATE_MODE_OEM 1 2148 u8 reserved[12]; 2149}; 2150 2151I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2152 2153/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2154 2155/* async events 0x10xx */ 2156 2157/* Lan Queue Overflow Event (direct, 0x1001) */ 2158struct i40e_aqc_lan_overflow { 2159 __le32 prtdcb_rupto; 2160 __le32 otx_ctl; 2161 u8 reserved[8]; 2162}; 2163 2164I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2165 2166/* Get LLDP MIB (indirect 0x0A00) */ 2167struct i40e_aqc_lldp_get_mib { 2168 u8 type; 2169 u8 reserved1; 2170#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2171#define I40E_AQ_LLDP_MIB_LOCAL 0x0 2172#define I40E_AQ_LLDP_MIB_REMOTE 0x1 2173#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2174#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2175#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2176#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2177#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2178#define I40E_AQ_LLDP_TX_SHIFT 0x4 2179#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2180/* TX pause flags use I40E_AQ_LINK_TX_* above */ 2181 __le16 local_len; 2182 __le16 remote_len; 2183 u8 reserved2[2]; 2184 __le32 addr_high; 2185 __le32 addr_low; 2186}; 2187 2188I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2189 2190/* Configure LLDP MIB Change Event (direct 0x0A01) 2191 * also used for the event (with type in the command field) 2192 */ 2193struct i40e_aqc_lldp_update_mib { 2194 u8 command; 2195#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2196#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2197 u8 reserved[7]; 2198 __le32 addr_high; 2199 __le32 addr_low; 2200}; 2201 2202I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2203 2204/* Add LLDP TLV (indirect 0x0A02) 2205 * Delete LLDP TLV (indirect 0x0A04) 2206 */ 2207struct i40e_aqc_lldp_add_tlv { 2208 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2209 u8 reserved1[1]; 2210 __le16 len; 2211 u8 reserved2[4]; 2212 __le32 addr_high; 2213 __le32 addr_low; 2214}; 2215 2216I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2217 2218/* Update LLDP TLV (indirect 0x0A03) */ 2219struct i40e_aqc_lldp_update_tlv { 2220 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2221 u8 reserved; 2222 __le16 old_len; 2223 __le16 new_offset; 2224 __le16 new_len; 2225 __le32 addr_high; 2226 __le32 addr_low; 2227}; 2228 2229I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2230 2231/* Stop LLDP (direct 0x0A05) */ 2232struct i40e_aqc_lldp_stop { 2233 u8 command; 2234#define I40E_AQ_LLDP_AGENT_STOP 0x0 2235#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2236 u8 reserved[15]; 2237}; 2238 2239I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2240 2241/* Start LLDP (direct 0x0A06) */ 2242 2243struct i40e_aqc_lldp_start { 2244 u8 command; 2245#define I40E_AQ_LLDP_AGENT_START 0x1 2246 u8 reserved[15]; 2247}; 2248 2249I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2250 2251/* Get CEE DCBX Oper Config (0x0A07) 2252 * uses the generic descriptor struct 2253 * returns below as indirect response 2254 */ 2255 2256#define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2257#define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2258#define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2259#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2260#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2261#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2262 2263#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2264#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2265#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2266#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2267#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2268#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2269#define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2270#define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2271#define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2272#define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2273#define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2274#define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2275 2276/* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2277 * word boundary layout issues, which the Linux compilers silently deal 2278 * with by adding padding, making the actual struct larger than designed. 2279 * However, the FW compiler for the NIC is less lenient and complains 2280 * about the struct. Hence, the struct defined here has an extra byte in 2281 * fields reserved3 and reserved4 to directly acknowledge that padding, 2282 * and the new length is used in the length check macro. 2283 */ 2284struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2285 u8 reserved1; 2286 u8 oper_num_tc; 2287 u8 oper_prio_tc[4]; 2288 u8 reserved2; 2289 u8 oper_tc_bw[8]; 2290 u8 oper_pfc_en; 2291 u8 reserved3[2]; 2292 __le16 oper_app_prio; 2293 u8 reserved4[2]; 2294 __le16 tlv_status; 2295}; 2296 2297I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2298 2299struct i40e_aqc_get_cee_dcb_cfg_resp { 2300 u8 oper_num_tc; 2301 u8 oper_prio_tc[4]; 2302 u8 oper_tc_bw[8]; 2303 u8 oper_pfc_en; 2304 __le16 oper_app_prio; 2305 __le32 tlv_status; 2306 u8 reserved[12]; 2307}; 2308 2309I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2310 2311/* Set Local LLDP MIB (indirect 0x0A08) 2312 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2313 */ 2314struct i40e_aqc_lldp_set_local_mib { 2315#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2316#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \ 2317 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2318#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2319#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2320#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \ 2321 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2322#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2323 u8 type; 2324 u8 reserved0; 2325 __le16 length; 2326 u8 reserved1[4]; 2327 __le32 address_high; 2328 __le32 address_low; 2329}; 2330 2331I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2332 2333struct i40e_aqc_lldp_set_local_mib_resp { 2334#define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01 2335 u8 status; 2336 u8 reserved[15]; 2337}; 2338 2339I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp); 2340 2341/* Stop/Start LLDP Agent (direct 0x0A09) 2342 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2343 */ 2344struct i40e_aqc_lldp_stop_start_specific_agent { 2345#define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2346#define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2347 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2348 u8 command; 2349 u8 reserved[15]; 2350}; 2351 2352I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2353 2354/* Add Udp Tunnel command and completion (direct 0x0B00) */ 2355struct i40e_aqc_add_udp_tunnel { 2356 __le16 udp_port; 2357 u8 reserved0[3]; 2358 u8 protocol_type; 2359#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2360#define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2361#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2362#define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2363 u8 reserved1[10]; 2364}; 2365 2366I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2367 2368struct i40e_aqc_add_udp_tunnel_completion { 2369 __le16 udp_port; 2370 u8 filter_entry_index; 2371 u8 multiple_pfs; 2372#define I40E_AQC_SINGLE_PF 0x0 2373#define I40E_AQC_MULTIPLE_PFS 0x1 2374 u8 total_filters; 2375 u8 reserved[11]; 2376}; 2377 2378I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2379 2380/* remove UDP Tunnel command (0x0B01) */ 2381struct i40e_aqc_remove_udp_tunnel { 2382 u8 reserved[2]; 2383 u8 index; /* 0 to 15 */ 2384 u8 reserved2[13]; 2385}; 2386 2387I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2388 2389struct i40e_aqc_del_udp_tunnel_completion { 2390 __le16 udp_port; 2391 u8 index; /* 0 to 15 */ 2392 u8 multiple_pfs; 2393 u8 total_filters_used; 2394 u8 reserved1[11]; 2395}; 2396 2397I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2398 2399struct i40e_aqc_get_set_rss_key { 2400#define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15) 2401#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2402#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2403 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2404 __le16 vsi_id; 2405 u8 reserved[6]; 2406 __le32 addr_high; 2407 __le32 addr_low; 2408}; 2409 2410I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2411 2412struct i40e_aqc_get_set_rss_key_data { 2413 u8 standard_rss_key[0x28]; 2414 u8 extended_hash_key[0xc]; 2415}; 2416 2417I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2418 2419struct i40e_aqc_get_set_rss_lut { 2420#define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15) 2421#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2422#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2423 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2424 __le16 vsi_id; 2425#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2426#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \ 2427 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2428 2429#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2430#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2431 __le16 flags; 2432 u8 reserved[4]; 2433 __le32 addr_high; 2434 __le32 addr_low; 2435}; 2436 2437I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2438 2439/* tunnel key structure 0x0B10 */ 2440 2441struct i40e_aqc_tunnel_key_structure { 2442 u8 key1_off; 2443 u8 key2_off; 2444 u8 key1_len; /* 0 to 15 */ 2445 u8 key2_len; /* 0 to 15 */ 2446 u8 flags; 2447#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2448/* response flags */ 2449#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2450#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2451#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2452 u8 network_key_index; 2453#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2454#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2455#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2456#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2457 u8 reserved[10]; 2458}; 2459 2460I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2461 2462/* OEM mode commands (direct 0xFE0x) */ 2463struct i40e_aqc_oem_param_change { 2464 __le32 param_type; 2465#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2466#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2467#define I40E_AQ_OEM_PARAM_MAC 2 2468 __le32 param_value1; 2469 __le16 param_value2; 2470 u8 reserved[6]; 2471}; 2472 2473I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2474 2475struct i40e_aqc_oem_state_change { 2476 __le32 state; 2477#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2478#define I40E_AQ_OEM_STATE_LINK_UP 0x1 2479 u8 reserved[12]; 2480}; 2481 2482I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2483 2484/* Initialize OCSD (0xFE02, direct) */ 2485struct i40e_aqc_opc_oem_ocsd_initialize { 2486 u8 type_status; 2487 u8 reserved1[3]; 2488 __le32 ocsd_memory_block_addr_high; 2489 __le32 ocsd_memory_block_addr_low; 2490 __le32 requested_update_interval; 2491}; 2492 2493I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2494 2495/* Initialize OCBB (0xFE03, direct) */ 2496struct i40e_aqc_opc_oem_ocbb_initialize { 2497 u8 type_status; 2498 u8 reserved1[3]; 2499 __le32 ocbb_memory_block_addr_high; 2500 __le32 ocbb_memory_block_addr_low; 2501 u8 reserved2[4]; 2502}; 2503 2504I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2505 2506/* debug commands */ 2507 2508/* get device id (0xFF00) uses the generic structure */ 2509 2510/* set test more (0xFF01, internal) */ 2511 2512struct i40e_acq_set_test_mode { 2513 u8 mode; 2514#define I40E_AQ_TEST_PARTIAL 0 2515#define I40E_AQ_TEST_FULL 1 2516#define I40E_AQ_TEST_NVM 2 2517 u8 reserved[3]; 2518 u8 command; 2519#define I40E_AQ_TEST_OPEN 0 2520#define I40E_AQ_TEST_CLOSE 1 2521#define I40E_AQ_TEST_INC 2 2522 u8 reserved2[3]; 2523 __le32 address_high; 2524 __le32 address_low; 2525}; 2526 2527I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2528 2529/* Debug Read Register command (0xFF03) 2530 * Debug Write Register command (0xFF04) 2531 */ 2532struct i40e_aqc_debug_reg_read_write { 2533 __le32 reserved; 2534 __le32 address; 2535 __le32 value_high; 2536 __le32 value_low; 2537}; 2538 2539I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2540 2541/* Scatter/gather Reg Read (indirect 0xFF05) 2542 * Scatter/gather Reg Write (indirect 0xFF06) 2543 */ 2544 2545/* i40e_aq_desc is used for the command */ 2546struct i40e_aqc_debug_reg_sg_element_data { 2547 __le32 address; 2548 __le32 value; 2549}; 2550 2551/* Debug Modify register (direct 0xFF07) */ 2552struct i40e_aqc_debug_modify_reg { 2553 __le32 address; 2554 __le32 value; 2555 __le32 clear_mask; 2556 __le32 set_mask; 2557}; 2558 2559I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2560 2561/* dump internal data (0xFF08, indirect) */ 2562 2563#define I40E_AQ_CLUSTER_ID_AUX 0 2564#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2565#define I40E_AQ_CLUSTER_ID_TXSCHED 2 2566#define I40E_AQ_CLUSTER_ID_HMC 3 2567#define I40E_AQ_CLUSTER_ID_MAC0 4 2568#define I40E_AQ_CLUSTER_ID_MAC1 5 2569#define I40E_AQ_CLUSTER_ID_MAC2 6 2570#define I40E_AQ_CLUSTER_ID_MAC3 7 2571#define I40E_AQ_CLUSTER_ID_DCB 8 2572#define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2573#define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2574#define I40E_AQ_CLUSTER_ID_ALTRAM 11 2575 2576struct i40e_aqc_debug_dump_internals { 2577 u8 cluster_id; 2578 u8 table_id; 2579 __le16 data_size; 2580 __le32 idx; 2581 __le32 address_high; 2582 __le32 address_low; 2583}; 2584 2585I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2586 2587struct i40e_aqc_debug_modify_internals { 2588 u8 cluster_id; 2589 u8 cluster_specific_params[7]; 2590 __le32 address_high; 2591 __le32 address_low; 2592}; 2593 2594I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2595 2596#endif /* _I40E_ADMINQ_CMD_H_ */ 2597