i40e_adminq_cmd.h revision 299555
1/****************************************************************************** 2 3 Copyright (c) 2013-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/ixl/i40e_adminq_cmd.h 299555 2016-05-12 18:22:12Z erj $*/ 34 35#ifndef _I40E_ADMINQ_CMD_H_ 36#define _I40E_ADMINQ_CMD_H_ 37 38/* This header file defines the i40e Admin Queue commands and is shared between 39 * i40e Firmware and Software. 40 * 41 * This file needs to comply with the Linux Kernel coding style. 42 */ 43 44#define I40E_FW_API_VERSION_MAJOR 0x0001 45#define I40E_FW_API_VERSION_MINOR 0x0005 46 47struct i40e_aq_desc { 48 __le16 flags; 49 __le16 opcode; 50 __le16 datalen; 51 __le16 retval; 52 __le32 cookie_high; 53 __le32 cookie_low; 54 union { 55 struct { 56 __le32 param0; 57 __le32 param1; 58 __le32 param2; 59 __le32 param3; 60 } internal; 61 struct { 62 __le32 param0; 63 __le32 param1; 64 __le32 addr_high; 65 __le32 addr_low; 66 } external; 67 u8 raw[16]; 68 } params; 69}; 70 71/* Flags sub-structure 72 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 73 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 74 */ 75 76/* command flags and offsets*/ 77#define I40E_AQ_FLAG_DD_SHIFT 0 78#define I40E_AQ_FLAG_CMP_SHIFT 1 79#define I40E_AQ_FLAG_ERR_SHIFT 2 80#define I40E_AQ_FLAG_VFE_SHIFT 3 81#define I40E_AQ_FLAG_LB_SHIFT 9 82#define I40E_AQ_FLAG_RD_SHIFT 10 83#define I40E_AQ_FLAG_VFC_SHIFT 11 84#define I40E_AQ_FLAG_BUF_SHIFT 12 85#define I40E_AQ_FLAG_SI_SHIFT 13 86#define I40E_AQ_FLAG_EI_SHIFT 14 87#define I40E_AQ_FLAG_FE_SHIFT 15 88 89#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 90#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 91#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 92#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 93#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 94#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 95#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 96#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 97#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 98#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 99#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 100 101/* error codes */ 102enum i40e_admin_queue_err { 103 I40E_AQ_RC_OK = 0, /* success */ 104 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 105 I40E_AQ_RC_ENOENT = 2, /* No such element */ 106 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 107 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 108 I40E_AQ_RC_EIO = 5, /* I/O error */ 109 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 110 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 111 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 112 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 113 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 114 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 115 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 116 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 117 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 118 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 119 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 120 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 121 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 122 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 123 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 124 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 125 I40E_AQ_RC_EFBIG = 22, /* File too large */ 126}; 127 128/* Admin Queue command opcodes */ 129enum i40e_admin_queue_opc { 130 /* aq commands */ 131 i40e_aqc_opc_get_version = 0x0001, 132 i40e_aqc_opc_driver_version = 0x0002, 133 i40e_aqc_opc_queue_shutdown = 0x0003, 134 i40e_aqc_opc_set_pf_context = 0x0004, 135 136 /* resource ownership */ 137 i40e_aqc_opc_request_resource = 0x0008, 138 i40e_aqc_opc_release_resource = 0x0009, 139 140 i40e_aqc_opc_list_func_capabilities = 0x000A, 141 i40e_aqc_opc_list_dev_capabilities = 0x000B, 142 143 /* LAA */ 144 i40e_aqc_opc_mac_address_read = 0x0107, 145 i40e_aqc_opc_mac_address_write = 0x0108, 146 147 /* PXE */ 148 i40e_aqc_opc_clear_pxe_mode = 0x0110, 149 150 /* internal switch commands */ 151 i40e_aqc_opc_get_switch_config = 0x0200, 152 i40e_aqc_opc_add_statistics = 0x0201, 153 i40e_aqc_opc_remove_statistics = 0x0202, 154 i40e_aqc_opc_set_port_parameters = 0x0203, 155 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 156 i40e_aqc_opc_set_switch_config = 0x0205, 157 i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 158 i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 159 160 i40e_aqc_opc_add_vsi = 0x0210, 161 i40e_aqc_opc_update_vsi_parameters = 0x0211, 162 i40e_aqc_opc_get_vsi_parameters = 0x0212, 163 164 i40e_aqc_opc_add_pv = 0x0220, 165 i40e_aqc_opc_update_pv_parameters = 0x0221, 166 i40e_aqc_opc_get_pv_parameters = 0x0222, 167 168 i40e_aqc_opc_add_veb = 0x0230, 169 i40e_aqc_opc_update_veb_parameters = 0x0231, 170 i40e_aqc_opc_get_veb_parameters = 0x0232, 171 172 i40e_aqc_opc_delete_element = 0x0243, 173 174 i40e_aqc_opc_add_macvlan = 0x0250, 175 i40e_aqc_opc_remove_macvlan = 0x0251, 176 i40e_aqc_opc_add_vlan = 0x0252, 177 i40e_aqc_opc_remove_vlan = 0x0253, 178 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 179 i40e_aqc_opc_add_tag = 0x0255, 180 i40e_aqc_opc_remove_tag = 0x0256, 181 i40e_aqc_opc_add_multicast_etag = 0x0257, 182 i40e_aqc_opc_remove_multicast_etag = 0x0258, 183 i40e_aqc_opc_update_tag = 0x0259, 184 i40e_aqc_opc_add_control_packet_filter = 0x025A, 185 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 186 i40e_aqc_opc_add_cloud_filters = 0x025C, 187 i40e_aqc_opc_remove_cloud_filters = 0x025D, 188 189 i40e_aqc_opc_add_mirror_rule = 0x0260, 190 i40e_aqc_opc_delete_mirror_rule = 0x0261, 191 192 /* DCB commands */ 193 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 194 i40e_aqc_opc_dcb_updated = 0x0302, 195 196 /* TX scheduler */ 197 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 198 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 199 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 200 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 201 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 202 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 203 204 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 205 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 206 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 207 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 208 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 209 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 210 i40e_aqc_opc_query_port_ets_config = 0x0419, 211 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 212 i40e_aqc_opc_suspend_port_tx = 0x041B, 213 i40e_aqc_opc_resume_port_tx = 0x041C, 214 i40e_aqc_opc_configure_partition_bw = 0x041D, 215 216 /* hmc */ 217 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 218 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 219 220 /* phy commands*/ 221 i40e_aqc_opc_get_phy_abilities = 0x0600, 222 i40e_aqc_opc_set_phy_config = 0x0601, 223 i40e_aqc_opc_set_mac_config = 0x0603, 224 i40e_aqc_opc_set_link_restart_an = 0x0605, 225 i40e_aqc_opc_get_link_status = 0x0607, 226 i40e_aqc_opc_set_phy_int_mask = 0x0613, 227 i40e_aqc_opc_get_local_advt_reg = 0x0614, 228 i40e_aqc_opc_set_local_advt_reg = 0x0615, 229 i40e_aqc_opc_get_partner_advt = 0x0616, 230 i40e_aqc_opc_set_lb_modes = 0x0618, 231 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 232 i40e_aqc_opc_set_phy_debug = 0x0622, 233 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 234 i40e_aqc_opc_run_phy_activity = 0x0626, 235 236 /* NVM commands */ 237 i40e_aqc_opc_nvm_read = 0x0701, 238 i40e_aqc_opc_nvm_erase = 0x0702, 239 i40e_aqc_opc_nvm_update = 0x0703, 240 i40e_aqc_opc_nvm_config_read = 0x0704, 241 i40e_aqc_opc_nvm_config_write = 0x0705, 242 i40e_aqc_opc_oem_post_update = 0x0720, 243 i40e_aqc_opc_thermal_sensor = 0x0721, 244 245 /* virtualization commands */ 246 i40e_aqc_opc_send_msg_to_pf = 0x0801, 247 i40e_aqc_opc_send_msg_to_vf = 0x0802, 248 i40e_aqc_opc_send_msg_to_peer = 0x0803, 249 250 /* alternate structure */ 251 i40e_aqc_opc_alternate_write = 0x0900, 252 i40e_aqc_opc_alternate_write_indirect = 0x0901, 253 i40e_aqc_opc_alternate_read = 0x0902, 254 i40e_aqc_opc_alternate_read_indirect = 0x0903, 255 i40e_aqc_opc_alternate_write_done = 0x0904, 256 i40e_aqc_opc_alternate_set_mode = 0x0905, 257 i40e_aqc_opc_alternate_clear_port = 0x0906, 258 259 /* LLDP commands */ 260 i40e_aqc_opc_lldp_get_mib = 0x0A00, 261 i40e_aqc_opc_lldp_update_mib = 0x0A01, 262 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 263 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 264 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 265 i40e_aqc_opc_lldp_stop = 0x0A05, 266 i40e_aqc_opc_lldp_start = 0x0A06, 267 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 268 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 269 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 270 271 /* Tunnel commands */ 272 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 273 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 274 275 /* Async Events */ 276 i40e_aqc_opc_event_lan_overflow = 0x1001, 277 278 /* OEM commands */ 279 i40e_aqc_opc_oem_parameter_change = 0xFE00, 280 i40e_aqc_opc_oem_device_status_change = 0xFE01, 281 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 282 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 283 284 /* debug commands */ 285 i40e_aqc_opc_debug_read_reg = 0xFF03, 286 i40e_aqc_opc_debug_write_reg = 0xFF04, 287 i40e_aqc_opc_debug_modify_reg = 0xFF07, 288 i40e_aqc_opc_debug_dump_internals = 0xFF08, 289}; 290 291/* command structures and indirect data structures */ 292 293/* Structure naming conventions: 294 * - no suffix for direct command descriptor structures 295 * - _data for indirect sent data 296 * - _resp for indirect return data (data which is both will use _data) 297 * - _completion for direct return data 298 * - _element_ for repeated elements (may also be _data or _resp) 299 * 300 * Command structures are expected to overlay the params.raw member of the basic 301 * descriptor, and as such cannot exceed 16 bytes in length. 302 */ 303 304/* This macro is used to generate a compilation error if a structure 305 * is not exactly the correct length. It gives a divide by zero error if the 306 * structure is not of the correct size, otherwise it creates an enum that is 307 * never used. 308 */ 309#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 310 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 311 312/* This macro is used extensively to ensure that command structures are 16 313 * bytes in length as they have to map to the raw array of that size. 314 */ 315#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 316 317/* internal (0x00XX) commands */ 318 319/* Get version (direct 0x0001) */ 320struct i40e_aqc_get_version { 321 __le32 rom_ver; 322 __le32 fw_build; 323 __le16 fw_major; 324 __le16 fw_minor; 325 __le16 api_major; 326 __le16 api_minor; 327}; 328 329I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 330 331/* Send driver version (indirect 0x0002) */ 332struct i40e_aqc_driver_version { 333 u8 driver_major_ver; 334 u8 driver_minor_ver; 335 u8 driver_build_ver; 336 u8 driver_subbuild_ver; 337 u8 reserved[4]; 338 __le32 address_high; 339 __le32 address_low; 340}; 341 342I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 343 344/* Queue Shutdown (direct 0x0003) */ 345struct i40e_aqc_queue_shutdown { 346 __le32 driver_unloading; 347#define I40E_AQ_DRIVER_UNLOADING 0x1 348 u8 reserved[12]; 349}; 350 351I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 352 353/* Set PF context (0x0004, direct) */ 354struct i40e_aqc_set_pf_context { 355 u8 pf_id; 356 u8 reserved[15]; 357}; 358 359I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 360 361/* Request resource ownership (direct 0x0008) 362 * Release resource ownership (direct 0x0009) 363 */ 364#define I40E_AQ_RESOURCE_NVM 1 365#define I40E_AQ_RESOURCE_SDP 2 366#define I40E_AQ_RESOURCE_ACCESS_READ 1 367#define I40E_AQ_RESOURCE_ACCESS_WRITE 2 368#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 369#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 370 371struct i40e_aqc_request_resource { 372 __le16 resource_id; 373 __le16 access_type; 374 __le32 timeout; 375 __le32 resource_number; 376 u8 reserved[4]; 377}; 378 379I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 380 381/* Get function capabilities (indirect 0x000A) 382 * Get device capabilities (indirect 0x000B) 383 */ 384struct i40e_aqc_list_capabilites { 385 u8 command_flags; 386#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 387 u8 pf_index; 388 u8 reserved[2]; 389 __le32 count; 390 __le32 addr_high; 391 __le32 addr_low; 392}; 393 394I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 395 396struct i40e_aqc_list_capabilities_element_resp { 397 __le16 id; 398 u8 major_rev; 399 u8 minor_rev; 400 __le32 number; 401 __le32 logical_id; 402 __le32 phys_id; 403 u8 reserved[16]; 404}; 405 406/* list of caps */ 407 408#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 409#define I40E_AQ_CAP_ID_MNG_MODE 0x0002 410#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 411#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 412#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 413#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 414#define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 415#define I40E_AQ_CAP_ID_SRIOV 0x0012 416#define I40E_AQ_CAP_ID_VF 0x0013 417#define I40E_AQ_CAP_ID_VMDQ 0x0014 418#define I40E_AQ_CAP_ID_8021QBG 0x0015 419#define I40E_AQ_CAP_ID_8021QBR 0x0016 420#define I40E_AQ_CAP_ID_VSI 0x0017 421#define I40E_AQ_CAP_ID_DCB 0x0018 422#define I40E_AQ_CAP_ID_FCOE 0x0021 423#define I40E_AQ_CAP_ID_ISCSI 0x0022 424#define I40E_AQ_CAP_ID_RSS 0x0040 425#define I40E_AQ_CAP_ID_RXQ 0x0041 426#define I40E_AQ_CAP_ID_TXQ 0x0042 427#define I40E_AQ_CAP_ID_MSIX 0x0043 428#define I40E_AQ_CAP_ID_VF_MSIX 0x0044 429#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 430#define I40E_AQ_CAP_ID_1588 0x0046 431#define I40E_AQ_CAP_ID_IWARP 0x0051 432#define I40E_AQ_CAP_ID_LED 0x0061 433#define I40E_AQ_CAP_ID_SDP 0x0062 434#define I40E_AQ_CAP_ID_MDIO 0x0063 435#define I40E_AQ_CAP_ID_WSR_PROT 0x0064 436#define I40E_AQ_CAP_ID_FLEX10 0x00F1 437#define I40E_AQ_CAP_ID_CEM 0x00F2 438 439/* Set CPPM Configuration (direct 0x0103) */ 440struct i40e_aqc_cppm_configuration { 441 __le16 command_flags; 442#define I40E_AQ_CPPM_EN_LTRC 0x0800 443#define I40E_AQ_CPPM_EN_DMCTH 0x1000 444#define I40E_AQ_CPPM_EN_DMCTLX 0x2000 445#define I40E_AQ_CPPM_EN_HPTC 0x4000 446#define I40E_AQ_CPPM_EN_DMARC 0x8000 447 __le16 ttlx; 448 __le32 dmacr; 449 __le16 dmcth; 450 u8 hptc; 451 u8 reserved; 452 __le32 pfltrc; 453}; 454 455I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 456 457/* Set ARP Proxy command / response (indirect 0x0104) */ 458struct i40e_aqc_arp_proxy_data { 459 __le16 command_flags; 460#define I40E_AQ_ARP_INIT_IPV4 0x0008 461#define I40E_AQ_ARP_UNSUP_CTL 0x0010 462#define I40E_AQ_ARP_ENA 0x0020 463#define I40E_AQ_ARP_ADD_IPV4 0x0040 464#define I40E_AQ_ARP_DEL_IPV4 0x0080 465 __le16 table_id; 466 __le32 pfpm_proxyfc; 467 __le32 ip_addr; 468 u8 mac_addr[6]; 469 u8 reserved[2]; 470}; 471 472I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 473 474/* Set NS Proxy Table Entry Command (indirect 0x0105) */ 475struct i40e_aqc_ns_proxy_data { 476 __le16 table_idx_mac_addr_0; 477 __le16 table_idx_mac_addr_1; 478 __le16 table_idx_ipv6_0; 479 __le16 table_idx_ipv6_1; 480 __le16 control; 481#define I40E_AQ_NS_PROXY_ADD_0 0x0100 482#define I40E_AQ_NS_PROXY_DEL_0 0x0200 483#define I40E_AQ_NS_PROXY_ADD_1 0x0400 484#define I40E_AQ_NS_PROXY_DEL_1 0x0800 485#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 486#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 487#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 488#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 489#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 490#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 491#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 492 u8 mac_addr_0[6]; 493 u8 mac_addr_1[6]; 494 u8 local_mac_addr[6]; 495 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 496 u8 ipv6_addr_1[16]; 497}; 498 499I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 500 501/* Manage LAA Command (0x0106) - obsolete */ 502struct i40e_aqc_mng_laa { 503 __le16 command_flags; 504#define I40E_AQ_LAA_FLAG_WR 0x8000 505 u8 reserved[2]; 506 __le32 sal; 507 __le16 sah; 508 u8 reserved2[6]; 509}; 510 511I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 512 513/* Manage MAC Address Read Command (indirect 0x0107) */ 514struct i40e_aqc_mac_address_read { 515 __le16 command_flags; 516#define I40E_AQC_LAN_ADDR_VALID 0x10 517#define I40E_AQC_SAN_ADDR_VALID 0x20 518#define I40E_AQC_PORT_ADDR_VALID 0x40 519#define I40E_AQC_WOL_ADDR_VALID 0x80 520#define I40E_AQC_MC_MAG_EN_VALID 0x100 521#define I40E_AQC_ADDR_VALID_MASK 0x1F0 522 u8 reserved[6]; 523 __le32 addr_high; 524 __le32 addr_low; 525}; 526 527I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 528 529struct i40e_aqc_mac_address_read_data { 530 u8 pf_lan_mac[6]; 531 u8 pf_san_mac[6]; 532 u8 port_mac[6]; 533 u8 pf_wol_mac[6]; 534}; 535 536I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 537 538/* Manage MAC Address Write Command (0x0108) */ 539struct i40e_aqc_mac_address_write { 540 __le16 command_flags; 541#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 542#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 543#define I40E_AQC_WRITE_TYPE_PORT 0x8000 544#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 545#define I40E_AQC_WRITE_TYPE_MASK 0xC000 546 547 __le16 mac_sah; 548 __le32 mac_sal; 549 u8 reserved[8]; 550}; 551 552I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 553 554/* PXE commands (0x011x) */ 555 556/* Clear PXE Command and response (direct 0x0110) */ 557struct i40e_aqc_clear_pxe { 558 u8 rx_cnt; 559 u8 reserved[15]; 560}; 561 562I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 563 564/* Switch configuration commands (0x02xx) */ 565 566/* Used by many indirect commands that only pass an seid and a buffer in the 567 * command 568 */ 569struct i40e_aqc_switch_seid { 570 __le16 seid; 571 u8 reserved[6]; 572 __le32 addr_high; 573 __le32 addr_low; 574}; 575 576I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 577 578/* Get Switch Configuration command (indirect 0x0200) 579 * uses i40e_aqc_switch_seid for the descriptor 580 */ 581struct i40e_aqc_get_switch_config_header_resp { 582 __le16 num_reported; 583 __le16 num_total; 584 u8 reserved[12]; 585}; 586 587I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 588 589struct i40e_aqc_switch_config_element_resp { 590 u8 element_type; 591#define I40E_AQ_SW_ELEM_TYPE_MAC 1 592#define I40E_AQ_SW_ELEM_TYPE_PF 2 593#define I40E_AQ_SW_ELEM_TYPE_VF 3 594#define I40E_AQ_SW_ELEM_TYPE_EMP 4 595#define I40E_AQ_SW_ELEM_TYPE_BMC 5 596#define I40E_AQ_SW_ELEM_TYPE_PV 16 597#define I40E_AQ_SW_ELEM_TYPE_VEB 17 598#define I40E_AQ_SW_ELEM_TYPE_PA 18 599#define I40E_AQ_SW_ELEM_TYPE_VSI 19 600 u8 revision; 601#define I40E_AQ_SW_ELEM_REV_1 1 602 __le16 seid; 603 __le16 uplink_seid; 604 __le16 downlink_seid; 605 u8 reserved[3]; 606 u8 connection_type; 607#define I40E_AQ_CONN_TYPE_REGULAR 0x1 608#define I40E_AQ_CONN_TYPE_DEFAULT 0x2 609#define I40E_AQ_CONN_TYPE_CASCADED 0x3 610 __le16 scheduler_id; 611 __le16 element_info; 612}; 613 614I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 615 616/* Get Switch Configuration (indirect 0x0200) 617 * an array of elements are returned in the response buffer 618 * the first in the array is the header, remainder are elements 619 */ 620struct i40e_aqc_get_switch_config_resp { 621 struct i40e_aqc_get_switch_config_header_resp header; 622 struct i40e_aqc_switch_config_element_resp element[1]; 623}; 624 625I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 626 627/* Add Statistics (direct 0x0201) 628 * Remove Statistics (direct 0x0202) 629 */ 630struct i40e_aqc_add_remove_statistics { 631 __le16 seid; 632 __le16 vlan; 633 __le16 stat_index; 634 u8 reserved[10]; 635}; 636 637I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 638 639/* Set Port Parameters command (direct 0x0203) */ 640struct i40e_aqc_set_port_parameters { 641 __le16 command_flags; 642#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 643#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 644#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 645 __le16 bad_frame_vsi; 646 __le16 default_seid; /* reserved for command */ 647 u8 reserved[10]; 648}; 649 650I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 651 652/* Get Switch Resource Allocation (indirect 0x0204) */ 653struct i40e_aqc_get_switch_resource_alloc { 654 u8 num_entries; /* reserved for command */ 655 u8 reserved[7]; 656 __le32 addr_high; 657 __le32 addr_low; 658}; 659 660I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 661 662/* expect an array of these structs in the response buffer */ 663struct i40e_aqc_switch_resource_alloc_element_resp { 664 u8 resource_type; 665#define I40E_AQ_RESOURCE_TYPE_VEB 0x0 666#define I40E_AQ_RESOURCE_TYPE_VSI 0x1 667#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 668#define I40E_AQ_RESOURCE_TYPE_STAG 0x3 669#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 670#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 671#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 672#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 673#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 674#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 675#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 676#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 677#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 678#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 679#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 680#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 681#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 682#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 683#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 684 u8 reserved1; 685 __le16 guaranteed; 686 __le16 total; 687 __le16 used; 688 __le16 total_unalloced; 689 u8 reserved2[6]; 690}; 691 692I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 693 694/* Set Switch Configuration (direct 0x0205) */ 695struct i40e_aqc_set_switch_config { 696 __le16 flags; 697#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 698#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 699 __le16 valid_flags; 700 u8 reserved[12]; 701}; 702 703I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 704 705/* Read Receive control registers (direct 0x0206) 706 * Write Receive control registers (direct 0x0207) 707 * used for accessing Rx control registers that can be 708 * slow and need special handling when under high Rx load 709 */ 710struct i40e_aqc_rx_ctl_reg_read_write { 711 __le32 reserved1; 712 __le32 address; 713 __le32 reserved2; 714 __le32 value; 715}; 716 717I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 718 719/* Add VSI (indirect 0x0210) 720 * this indirect command uses struct i40e_aqc_vsi_properties_data 721 * as the indirect buffer (128 bytes) 722 * 723 * Update VSI (indirect 0x211) 724 * uses the same data structure as Add VSI 725 * 726 * Get VSI (indirect 0x0212) 727 * uses the same completion and data structure as Add VSI 728 */ 729struct i40e_aqc_add_get_update_vsi { 730 __le16 uplink_seid; 731 u8 connection_type; 732#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 733#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 734#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 735 u8 reserved1; 736 u8 vf_id; 737 u8 reserved2; 738 __le16 vsi_flags; 739#define I40E_AQ_VSI_TYPE_SHIFT 0x0 740#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 741#define I40E_AQ_VSI_TYPE_VF 0x0 742#define I40E_AQ_VSI_TYPE_VMDQ2 0x1 743#define I40E_AQ_VSI_TYPE_PF 0x2 744#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 745#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 746 __le32 addr_high; 747 __le32 addr_low; 748}; 749 750I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 751 752struct i40e_aqc_add_get_update_vsi_completion { 753 __le16 seid; 754 __le16 vsi_number; 755 __le16 vsi_used; 756 __le16 vsi_free; 757 __le32 addr_high; 758 __le32 addr_low; 759}; 760 761I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 762 763struct i40e_aqc_vsi_properties_data { 764 /* first 96 byte are written by SW */ 765 __le16 valid_sections; 766#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 767#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 768#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 769#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 770#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 771#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 772#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 773#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 774#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 775#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 776 /* switch section */ 777 __le16 switch_id; /* 12bit id combined with flags below */ 778#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 779#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 780#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 781#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 782#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 783 u8 sw_reserved[2]; 784 /* security section */ 785 u8 sec_flags; 786#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 787#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 788#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 789 u8 sec_reserved; 790 /* VLAN section */ 791 __le16 pvid; /* VLANS include priority bits */ 792 __le16 fcoe_pvid; 793 u8 port_vlan_flags; 794#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 795#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 796 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 797#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 798#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 799#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 800#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 801#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 802#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 803 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 804#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 805#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 806#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 807#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 808 u8 pvlan_reserved[3]; 809 /* ingress egress up sections */ 810 __le32 ingress_table; /* bitmap, 3 bits per up */ 811#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 812#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 813 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 814#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 815#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 816 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 817#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 818#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 819 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 820#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 821#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 822 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 823#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 824#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 825 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 826#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 827#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 828 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 829#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 830#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 831 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 832#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 833#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 834 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 835 __le32 egress_table; /* same defines as for ingress table */ 836 /* cascaded PV section */ 837 __le16 cas_pv_tag; 838 u8 cas_pv_flags; 839#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 840#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 841 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 842#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 843#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 844#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 845#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 846#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 847#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 848 u8 cas_pv_reserved; 849 /* queue mapping section */ 850 __le16 mapping_flags; 851#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 852#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 853 __le16 queue_mapping[16]; 854#define I40E_AQ_VSI_QUEUE_SHIFT 0x0 855#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 856 __le16 tc_mapping[8]; 857#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 858#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 859 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 860#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 861#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 862 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 863 /* queueing option section */ 864 u8 queueing_opt_flags; 865#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 866#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 867 u8 queueing_opt_reserved[3]; 868 /* scheduler section */ 869 u8 up_enable_bits; 870 u8 sched_reserved; 871 /* outer up section */ 872 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 873 u8 cmd_reserved[8]; 874 /* last 32 bytes are written by FW */ 875 __le16 qs_handle[8]; 876#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 877 __le16 stat_counter_idx; 878 __le16 sched_id; 879 u8 resp_reserved[12]; 880}; 881 882I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 883 884/* Add Port Virtualizer (direct 0x0220) 885 * also used for update PV (direct 0x0221) but only flags are used 886 * (IS_CTRL_PORT only works on add PV) 887 */ 888struct i40e_aqc_add_update_pv { 889 __le16 command_flags; 890#define I40E_AQC_PV_FLAG_PV_TYPE 0x1 891#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 892#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 893#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 894 __le16 uplink_seid; 895 __le16 connected_seid; 896 u8 reserved[10]; 897}; 898 899I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 900 901struct i40e_aqc_add_update_pv_completion { 902 /* reserved for update; for add also encodes error if rc == ENOSPC */ 903 __le16 pv_seid; 904#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 905#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 906#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 907#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 908 u8 reserved[14]; 909}; 910 911I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 912 913/* Get PV Params (direct 0x0222) 914 * uses i40e_aqc_switch_seid for the descriptor 915 */ 916 917struct i40e_aqc_get_pv_params_completion { 918 __le16 seid; 919 __le16 default_stag; 920 __le16 pv_flags; /* same flags as add_pv */ 921#define I40E_AQC_GET_PV_PV_TYPE 0x1 922#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 923#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 924 u8 reserved[8]; 925 __le16 default_port_seid; 926}; 927 928I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 929 930/* Add VEB (direct 0x0230) */ 931struct i40e_aqc_add_veb { 932 __le16 uplink_seid; 933 __le16 downlink_seid; 934 __le16 veb_flags; 935#define I40E_AQC_ADD_VEB_FLOATING 0x1 936#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 937#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 938 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 939#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 940#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 941#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 942#define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 943 u8 enable_tcs; 944 u8 reserved[9]; 945}; 946 947I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 948 949struct i40e_aqc_add_veb_completion { 950 u8 reserved[6]; 951 __le16 switch_seid; 952 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 953 __le16 veb_seid; 954#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 955#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 956#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 957#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 958 __le16 statistic_index; 959 __le16 vebs_used; 960 __le16 vebs_free; 961}; 962 963I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 964 965/* Get VEB Parameters (direct 0x0232) 966 * uses i40e_aqc_switch_seid for the descriptor 967 */ 968struct i40e_aqc_get_veb_parameters_completion { 969 __le16 seid; 970 __le16 switch_id; 971 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 972 __le16 statistic_index; 973 __le16 vebs_used; 974 __le16 vebs_free; 975 u8 reserved[4]; 976}; 977 978I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 979 980/* Delete Element (direct 0x0243) 981 * uses the generic i40e_aqc_switch_seid 982 */ 983 984/* Add MAC-VLAN (indirect 0x0250) */ 985 986/* used for the command for most vlan commands */ 987struct i40e_aqc_macvlan { 988 __le16 num_addresses; 989 __le16 seid[3]; 990#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 991#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 992 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 993#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 994 __le32 addr_high; 995 __le32 addr_low; 996}; 997 998I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 999 1000/* indirect data for command and response */ 1001struct i40e_aqc_add_macvlan_element_data { 1002 u8 mac_addr[6]; 1003 __le16 vlan_tag; 1004 __le16 flags; 1005#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 1006#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 1007#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 1008#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 1009#define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 1010 __le16 queue_number; 1011#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 1012#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 1013 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1014 /* response section */ 1015 u8 match_method; 1016#define I40E_AQC_MM_PERFECT_MATCH 0x01 1017#define I40E_AQC_MM_HASH_MATCH 0x02 1018#define I40E_AQC_MM_ERR_NO_RES 0xFF 1019 u8 reserved1[3]; 1020}; 1021 1022struct i40e_aqc_add_remove_macvlan_completion { 1023 __le16 perfect_mac_used; 1024 __le16 perfect_mac_free; 1025 __le16 unicast_hash_free; 1026 __le16 multicast_hash_free; 1027 __le32 addr_high; 1028 __le32 addr_low; 1029}; 1030 1031I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1032 1033/* Remove MAC-VLAN (indirect 0x0251) 1034 * uses i40e_aqc_macvlan for the descriptor 1035 * data points to an array of num_addresses of elements 1036 */ 1037 1038struct i40e_aqc_remove_macvlan_element_data { 1039 u8 mac_addr[6]; 1040 __le16 vlan_tag; 1041 u8 flags; 1042#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1043#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1044#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1045#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1046 u8 reserved[3]; 1047 /* reply section */ 1048 u8 error_code; 1049#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1050#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1051 u8 reply_reserved[3]; 1052}; 1053 1054/* Add VLAN (indirect 0x0252) 1055 * Remove VLAN (indirect 0x0253) 1056 * use the generic i40e_aqc_macvlan for the command 1057 */ 1058struct i40e_aqc_add_remove_vlan_element_data { 1059 __le16 vlan_tag; 1060 u8 vlan_flags; 1061/* flags for add VLAN */ 1062#define I40E_AQC_ADD_VLAN_LOCAL 0x1 1063#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1064#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1065#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1066#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1067#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1068#define I40E_AQC_VLAN_PTYPE_SHIFT 3 1069#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1070#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1071#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1072#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1073#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1074/* flags for remove VLAN */ 1075#define I40E_AQC_REMOVE_VLAN_ALL 0x1 1076 u8 reserved; 1077 u8 result; 1078/* flags for add VLAN */ 1079#define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1080#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1081#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1082/* flags for remove VLAN */ 1083#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1084#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1085 u8 reserved1[3]; 1086}; 1087 1088struct i40e_aqc_add_remove_vlan_completion { 1089 u8 reserved[4]; 1090 __le16 vlans_used; 1091 __le16 vlans_free; 1092 __le32 addr_high; 1093 __le32 addr_low; 1094}; 1095 1096/* Set VSI Promiscuous Modes (direct 0x0254) */ 1097struct i40e_aqc_set_vsi_promiscuous_modes { 1098 __le16 promiscuous_flags; 1099 __le16 valid_flags; 1100/* flags used for both fields above */ 1101#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1102#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1103#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1104#define I40E_AQC_SET_VSI_DEFAULT 0x08 1105#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1106#define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 1107 __le16 seid; 1108#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1109 __le16 vlan_tag; 1110#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1111#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1112 u8 reserved[8]; 1113}; 1114 1115I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1116 1117/* Add S/E-tag command (direct 0x0255) 1118 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1119 */ 1120struct i40e_aqc_add_tag { 1121 __le16 flags; 1122#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1123 __le16 seid; 1124#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1125#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1126 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1127 __le16 tag; 1128 __le16 queue_number; 1129 u8 reserved[8]; 1130}; 1131 1132I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1133 1134struct i40e_aqc_add_remove_tag_completion { 1135 u8 reserved[12]; 1136 __le16 tags_used; 1137 __le16 tags_free; 1138}; 1139 1140I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1141 1142/* Remove S/E-tag command (direct 0x0256) 1143 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1144 */ 1145struct i40e_aqc_remove_tag { 1146 __le16 seid; 1147#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1148#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1149 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1150 __le16 tag; 1151 u8 reserved[12]; 1152}; 1153 1154I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1155 1156/* Add multicast E-Tag (direct 0x0257) 1157 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1158 * and no external data 1159 */ 1160struct i40e_aqc_add_remove_mcast_etag { 1161 __le16 pv_seid; 1162 __le16 etag; 1163 u8 num_unicast_etags; 1164 u8 reserved[3]; 1165 __le32 addr_high; /* address of array of 2-byte s-tags */ 1166 __le32 addr_low; 1167}; 1168 1169I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1170 1171struct i40e_aqc_add_remove_mcast_etag_completion { 1172 u8 reserved[4]; 1173 __le16 mcast_etags_used; 1174 __le16 mcast_etags_free; 1175 __le32 addr_high; 1176 __le32 addr_low; 1177 1178}; 1179 1180I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1181 1182/* Update S/E-Tag (direct 0x0259) */ 1183struct i40e_aqc_update_tag { 1184 __le16 seid; 1185#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1186#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1187 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1188 __le16 old_tag; 1189 __le16 new_tag; 1190 u8 reserved[10]; 1191}; 1192 1193I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1194 1195struct i40e_aqc_update_tag_completion { 1196 u8 reserved[12]; 1197 __le16 tags_used; 1198 __le16 tags_free; 1199}; 1200 1201I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1202 1203/* Add Control Packet filter (direct 0x025A) 1204 * Remove Control Packet filter (direct 0x025B) 1205 * uses the i40e_aqc_add_oveb_cloud, 1206 * and the generic direct completion structure 1207 */ 1208struct i40e_aqc_add_remove_control_packet_filter { 1209 u8 mac[6]; 1210 __le16 etype; 1211 __le16 flags; 1212#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1213#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1214#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1215#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1216#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1217 __le16 seid; 1218#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1219#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1220 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1221 __le16 queue; 1222 u8 reserved[2]; 1223}; 1224 1225I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1226 1227struct i40e_aqc_add_remove_control_packet_filter_completion { 1228 __le16 mac_etype_used; 1229 __le16 etype_used; 1230 __le16 mac_etype_free; 1231 __le16 etype_free; 1232 u8 reserved[8]; 1233}; 1234 1235I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1236 1237/* Add Cloud filters (indirect 0x025C) 1238 * Remove Cloud filters (indirect 0x025D) 1239 * uses the i40e_aqc_add_remove_cloud_filters, 1240 * and the generic indirect completion structure 1241 */ 1242struct i40e_aqc_add_remove_cloud_filters { 1243 u8 num_filters; 1244 u8 reserved; 1245 __le16 seid; 1246#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1247#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1248 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1249 u8 reserved2[4]; 1250 __le32 addr_high; 1251 __le32 addr_low; 1252}; 1253 1254I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1255 1256struct i40e_aqc_add_remove_cloud_filters_element_data { 1257 u8 outer_mac[6]; 1258 u8 inner_mac[6]; 1259 __le16 inner_vlan; 1260 union { 1261 struct { 1262 u8 reserved[12]; 1263 u8 data[4]; 1264 } v4; 1265 struct { 1266 u8 data[16]; 1267 } v6; 1268 } ipaddr; 1269 __le16 flags; 1270#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1271#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1272 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1273/* 0x0000 reserved */ 1274#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1275/* 0x0002 reserved */ 1276#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1277#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1278/* 0x0005 reserved */ 1279#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1280/* 0x0007 reserved */ 1281/* 0x0008 reserved */ 1282#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1283#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1284#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1285#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1286 1287#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1288#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1289#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1290#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1291#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1292 1293#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1294#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1295#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1296#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1297#define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1298#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1299#define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1300#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1301 1302#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1303#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1304#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1305 1306 __le32 tenant_id; 1307 u8 reserved[4]; 1308 __le16 queue_number; 1309#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1310#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1311 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1312 u8 reserved2[14]; 1313 /* response section */ 1314 u8 allocation_result; 1315#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1316#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1317 u8 response_reserved[7]; 1318}; 1319 1320struct i40e_aqc_remove_cloud_filters_completion { 1321 __le16 perfect_ovlan_used; 1322 __le16 perfect_ovlan_free; 1323 __le16 vlan_used; 1324 __le16 vlan_free; 1325 __le32 addr_high; 1326 __le32 addr_low; 1327}; 1328 1329I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1330 1331/* Add Mirror Rule (indirect or direct 0x0260) 1332 * Delete Mirror Rule (indirect or direct 0x0261) 1333 * note: some rule types (4,5) do not use an external buffer. 1334 * take care to set the flags correctly. 1335 */ 1336struct i40e_aqc_add_delete_mirror_rule { 1337 __le16 seid; 1338 __le16 rule_type; 1339#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1340#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1341 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1342#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1343#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1344#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1345#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1346#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1347 __le16 num_entries; 1348 __le16 destination; /* VSI for add, rule id for delete */ 1349 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1350 __le32 addr_low; 1351}; 1352 1353I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1354 1355struct i40e_aqc_add_delete_mirror_rule_completion { 1356 u8 reserved[2]; 1357 __le16 rule_id; /* only used on add */ 1358 __le16 mirror_rules_used; 1359 __le16 mirror_rules_free; 1360 __le32 addr_high; 1361 __le32 addr_low; 1362}; 1363 1364I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1365 1366/* DCB 0x03xx*/ 1367 1368/* PFC Ignore (direct 0x0301) 1369 * the command and response use the same descriptor structure 1370 */ 1371struct i40e_aqc_pfc_ignore { 1372 u8 tc_bitmap; 1373 u8 command_flags; /* unused on response */ 1374#define I40E_AQC_PFC_IGNORE_SET 0x80 1375#define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1376 u8 reserved[14]; 1377}; 1378 1379I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1380 1381/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1382 * with no parameters 1383 */ 1384 1385/* TX scheduler 0x04xx */ 1386 1387/* Almost all the indirect commands use 1388 * this generic struct to pass the SEID in param0 1389 */ 1390struct i40e_aqc_tx_sched_ind { 1391 __le16 vsi_seid; 1392 u8 reserved[6]; 1393 __le32 addr_high; 1394 __le32 addr_low; 1395}; 1396 1397I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1398 1399/* Several commands respond with a set of queue set handles */ 1400struct i40e_aqc_qs_handles_resp { 1401 __le16 qs_handles[8]; 1402}; 1403 1404/* Configure VSI BW limits (direct 0x0400) */ 1405struct i40e_aqc_configure_vsi_bw_limit { 1406 __le16 vsi_seid; 1407 u8 reserved[2]; 1408 __le16 credit; 1409 u8 reserved1[2]; 1410 u8 max_credit; /* 0-3, limit = 2^max */ 1411 u8 reserved2[7]; 1412}; 1413 1414I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1415 1416/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1417 * responds with i40e_aqc_qs_handles_resp 1418 */ 1419struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1420 u8 tc_valid_bits; 1421 u8 reserved[15]; 1422 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1423 1424 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1425 __le16 tc_bw_max[2]; 1426 u8 reserved1[28]; 1427}; 1428 1429I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1430 1431/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1432 * responds with i40e_aqc_qs_handles_resp 1433 */ 1434struct i40e_aqc_configure_vsi_tc_bw_data { 1435 u8 tc_valid_bits; 1436 u8 reserved[3]; 1437 u8 tc_bw_credits[8]; 1438 u8 reserved1[4]; 1439 __le16 qs_handles[8]; 1440}; 1441 1442I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1443 1444/* Query vsi bw configuration (indirect 0x0408) */ 1445struct i40e_aqc_query_vsi_bw_config_resp { 1446 u8 tc_valid_bits; 1447 u8 tc_suspended_bits; 1448 u8 reserved[14]; 1449 __le16 qs_handles[8]; 1450 u8 reserved1[4]; 1451 __le16 port_bw_limit; 1452 u8 reserved2[2]; 1453 u8 max_bw; /* 0-3, limit = 2^max */ 1454 u8 reserved3[23]; 1455}; 1456 1457I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1458 1459/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1460struct i40e_aqc_query_vsi_ets_sla_config_resp { 1461 u8 tc_valid_bits; 1462 u8 reserved[3]; 1463 u8 share_credits[8]; 1464 __le16 credits[8]; 1465 1466 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1467 __le16 tc_bw_max[2]; 1468}; 1469 1470I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1471 1472/* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1473struct i40e_aqc_configure_switching_comp_bw_limit { 1474 __le16 seid; 1475 u8 reserved[2]; 1476 __le16 credit; 1477 u8 reserved1[2]; 1478 u8 max_bw; /* 0-3, limit = 2^max */ 1479 u8 reserved2[7]; 1480}; 1481 1482I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1483 1484/* Enable Physical Port ETS (indirect 0x0413) 1485 * Modify Physical Port ETS (indirect 0x0414) 1486 * Disable Physical Port ETS (indirect 0x0415) 1487 */ 1488struct i40e_aqc_configure_switching_comp_ets_data { 1489 u8 reserved[4]; 1490 u8 tc_valid_bits; 1491 u8 seepage; 1492#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1493 u8 tc_strict_priority_flags; 1494 u8 reserved1[17]; 1495 u8 tc_bw_share_credits[8]; 1496 u8 reserved2[96]; 1497}; 1498 1499I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1500 1501/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1502struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1503 u8 tc_valid_bits; 1504 u8 reserved[15]; 1505 __le16 tc_bw_credit[8]; 1506 1507 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1508 __le16 tc_bw_max[2]; 1509 u8 reserved1[28]; 1510}; 1511 1512I40E_CHECK_STRUCT_LEN(0x40, 1513 i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1514 1515/* Configure Switching Component Bandwidth Allocation per Tc 1516 * (indirect 0x0417) 1517 */ 1518struct i40e_aqc_configure_switching_comp_bw_config_data { 1519 u8 tc_valid_bits; 1520 u8 reserved[2]; 1521 u8 absolute_credits; /* bool */ 1522 u8 tc_bw_share_credits[8]; 1523 u8 reserved1[20]; 1524}; 1525 1526I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1527 1528/* Query Switching Component Configuration (indirect 0x0418) */ 1529struct i40e_aqc_query_switching_comp_ets_config_resp { 1530 u8 tc_valid_bits; 1531 u8 reserved[35]; 1532 __le16 port_bw_limit; 1533 u8 reserved1[2]; 1534 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1535 u8 reserved2[23]; 1536}; 1537 1538I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1539 1540/* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1541struct i40e_aqc_query_port_ets_config_resp { 1542 u8 reserved[4]; 1543 u8 tc_valid_bits; 1544 u8 reserved1; 1545 u8 tc_strict_priority_bits; 1546 u8 reserved2; 1547 u8 tc_bw_share_credits[8]; 1548 __le16 tc_bw_limits[8]; 1549 1550 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1551 __le16 tc_bw_max[2]; 1552 u8 reserved3[32]; 1553}; 1554 1555I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1556 1557/* Query Switching Component Bandwidth Allocation per Traffic Type 1558 * (indirect 0x041A) 1559 */ 1560struct i40e_aqc_query_switching_comp_bw_config_resp { 1561 u8 tc_valid_bits; 1562 u8 reserved[2]; 1563 u8 absolute_credits_enable; /* bool */ 1564 u8 tc_bw_share_credits[8]; 1565 __le16 tc_bw_limits[8]; 1566 1567 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1568 __le16 tc_bw_max[2]; 1569}; 1570 1571I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1572 1573/* Suspend/resume port TX traffic 1574 * (direct 0x041B and 0x041C) uses the generic SEID struct 1575 */ 1576 1577/* Configure partition BW 1578 * (indirect 0x041D) 1579 */ 1580struct i40e_aqc_configure_partition_bw_data { 1581 __le16 pf_valid_bits; 1582 u8 min_bw[16]; /* guaranteed bandwidth */ 1583 u8 max_bw[16]; /* bandwidth limit */ 1584}; 1585 1586I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1587 1588/* Get and set the active HMC resource profile and status. 1589 * (direct 0x0500) and (direct 0x0501) 1590 */ 1591struct i40e_aq_get_set_hmc_resource_profile { 1592 u8 pm_profile; 1593 u8 pe_vf_enabled; 1594 u8 reserved[14]; 1595}; 1596 1597I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1598 1599enum i40e_aq_hmc_profile { 1600 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1601 I40E_HMC_PROFILE_DEFAULT = 1, 1602 I40E_HMC_PROFILE_FAVOR_VF = 2, 1603 I40E_HMC_PROFILE_EQUAL = 3, 1604}; 1605 1606#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF 1607#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F 1608 1609/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1610 1611/* set in param0 for get phy abilities to report qualified modules */ 1612#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1613#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1614 1615enum i40e_aq_phy_type { 1616 I40E_PHY_TYPE_SGMII = 0x0, 1617 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1618 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1619 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1620 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1621 I40E_PHY_TYPE_XAUI = 0x5, 1622 I40E_PHY_TYPE_XFI = 0x6, 1623 I40E_PHY_TYPE_SFI = 0x7, 1624 I40E_PHY_TYPE_XLAUI = 0x8, 1625 I40E_PHY_TYPE_XLPPI = 0x9, 1626 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1627 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1628 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1629 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1630 I40E_PHY_TYPE_100BASE_TX = 0x11, 1631 I40E_PHY_TYPE_1000BASE_T = 0x12, 1632 I40E_PHY_TYPE_10GBASE_T = 0x13, 1633 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1634 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1635 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1636 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1637 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1638 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1639 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1640 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1641 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1642 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1643 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1644 I40E_PHY_TYPE_MAX 1645}; 1646 1647#define I40E_LINK_SPEED_100MB_SHIFT 0x1 1648#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1649#define I40E_LINK_SPEED_10GB_SHIFT 0x3 1650#define I40E_LINK_SPEED_40GB_SHIFT 0x4 1651#define I40E_LINK_SPEED_20GB_SHIFT 0x5 1652 1653enum i40e_aq_link_speed { 1654 I40E_LINK_SPEED_UNKNOWN = 0, 1655 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1656 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1657 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1658 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1659 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) 1660}; 1661 1662struct i40e_aqc_module_desc { 1663 u8 oui[3]; 1664 u8 reserved1; 1665 u8 part_number[16]; 1666 u8 revision[4]; 1667 u8 reserved2[8]; 1668}; 1669 1670I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1671 1672struct i40e_aq_get_phy_abilities_resp { 1673 __le32 phy_type; /* bitmap using the above enum for offsets */ 1674 u8 link_speed; /* bitmap using the above enum bit patterns */ 1675 u8 abilities; 1676#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1677#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1678#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1679#define I40E_AQ_PHY_LINK_ENABLED 0x08 1680#define I40E_AQ_PHY_AN_ENABLED 0x10 1681#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1682 __le16 eee_capability; 1683#define I40E_AQ_EEE_100BASE_TX 0x0002 1684#define I40E_AQ_EEE_1000BASE_T 0x0004 1685#define I40E_AQ_EEE_10GBASE_T 0x0008 1686#define I40E_AQ_EEE_1000BASE_KX 0x0010 1687#define I40E_AQ_EEE_10GBASE_KX4 0x0020 1688#define I40E_AQ_EEE_10GBASE_KR 0x0040 1689 __le32 eeer_val; 1690 u8 d3_lpan; 1691#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1692 u8 reserved[3]; 1693 u8 phy_id[4]; 1694 u8 module_type[3]; 1695 u8 qualified_module_count; 1696#define I40E_AQ_PHY_MAX_QMS 16 1697 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1698}; 1699 1700I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1701 1702/* Set PHY Config (direct 0x0601) */ 1703struct i40e_aq_set_phy_config { /* same bits as above in all */ 1704 __le32 phy_type; 1705 u8 link_speed; 1706 u8 abilities; 1707/* bits 0-2 use the values from get_phy_abilities_resp */ 1708#define I40E_AQ_PHY_ENABLE_LINK 0x08 1709#define I40E_AQ_PHY_ENABLE_AN 0x10 1710#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1711 __le16 eee_capability; 1712 __le32 eeer; 1713 u8 low_power_ctrl; 1714 u8 reserved[3]; 1715}; 1716 1717I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1718 1719/* Set MAC Config command data structure (direct 0x0603) */ 1720struct i40e_aq_set_mac_config { 1721 __le16 max_frame_size; 1722 u8 params; 1723#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1724#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1725#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1726#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1727#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1728#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1729#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1730#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1731#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1732#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1733#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1734#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1735#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1736#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1737 u8 tx_timer_priority; /* bitmap */ 1738 __le16 tx_timer_value; 1739 __le16 fc_refresh_threshold; 1740 u8 reserved[8]; 1741}; 1742 1743I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1744 1745/* Restart Auto-Negotiation (direct 0x605) */ 1746struct i40e_aqc_set_link_restart_an { 1747 u8 command; 1748#define I40E_AQ_PHY_RESTART_AN 0x02 1749#define I40E_AQ_PHY_LINK_ENABLE 0x04 1750 u8 reserved[15]; 1751}; 1752 1753I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1754 1755/* Get Link Status cmd & response data structure (direct 0x0607) */ 1756struct i40e_aqc_get_link_status { 1757 __le16 command_flags; /* only field set on command */ 1758#define I40E_AQ_LSE_MASK 0x3 1759#define I40E_AQ_LSE_NOP 0x0 1760#define I40E_AQ_LSE_DISABLE 0x2 1761#define I40E_AQ_LSE_ENABLE 0x3 1762/* only response uses this flag */ 1763#define I40E_AQ_LSE_IS_ENABLED 0x1 1764 u8 phy_type; /* i40e_aq_phy_type */ 1765 u8 link_speed; /* i40e_aq_link_speed */ 1766 u8 link_info; 1767#define I40E_AQ_LINK_UP 0x01 /* obsolete */ 1768#define I40E_AQ_LINK_UP_FUNCTION 0x01 1769#define I40E_AQ_LINK_FAULT 0x02 1770#define I40E_AQ_LINK_FAULT_TX 0x04 1771#define I40E_AQ_LINK_FAULT_RX 0x08 1772#define I40E_AQ_LINK_FAULT_REMOTE 0x10 1773#define I40E_AQ_LINK_UP_PORT 0x20 1774#define I40E_AQ_MEDIA_AVAILABLE 0x40 1775#define I40E_AQ_SIGNAL_DETECT 0x80 1776 u8 an_info; 1777#define I40E_AQ_AN_COMPLETED 0x01 1778#define I40E_AQ_LP_AN_ABILITY 0x02 1779#define I40E_AQ_PD_FAULT 0x04 1780#define I40E_AQ_FEC_EN 0x08 1781#define I40E_AQ_PHY_LOW_POWER 0x10 1782#define I40E_AQ_LINK_PAUSE_TX 0x20 1783#define I40E_AQ_LINK_PAUSE_RX 0x40 1784#define I40E_AQ_QUALIFIED_MODULE 0x80 1785 u8 ext_info; 1786#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1787#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1788#define I40E_AQ_LINK_TX_SHIFT 0x02 1789#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1790#define I40E_AQ_LINK_TX_ACTIVE 0x00 1791#define I40E_AQ_LINK_TX_DRAINED 0x01 1792#define I40E_AQ_LINK_TX_FLUSHED 0x03 1793#define I40E_AQ_LINK_FORCED_40G 0x10 1794 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1795 __le16 max_frame_size; 1796 u8 config; 1797#define I40E_AQ_CONFIG_CRC_ENA 0x04 1798#define I40E_AQ_CONFIG_PACING_MASK 0x78 1799 u8 external_power_ability; 1800#define I40E_AQ_LINK_POWER_CLASS_1 0x00 1801#define I40E_AQ_LINK_POWER_CLASS_2 0x01 1802#define I40E_AQ_LINK_POWER_CLASS_3 0x02 1803#define I40E_AQ_LINK_POWER_CLASS_4 0x03 1804 u8 reserved[4]; 1805}; 1806 1807I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1808 1809/* Set event mask command (direct 0x613) */ 1810struct i40e_aqc_set_phy_int_mask { 1811 u8 reserved[8]; 1812 __le16 event_mask; 1813#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1814#define I40E_AQ_EVENT_MEDIA_NA 0x0004 1815#define I40E_AQ_EVENT_LINK_FAULT 0x0008 1816#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1817#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1818#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1819#define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1820#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1821#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1822 u8 reserved1[6]; 1823}; 1824 1825I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1826 1827/* Get Local AN advt register (direct 0x0614) 1828 * Set Local AN advt register (direct 0x0615) 1829 * Get Link Partner AN advt register (direct 0x0616) 1830 */ 1831struct i40e_aqc_an_advt_reg { 1832 __le32 local_an_reg0; 1833 __le16 local_an_reg1; 1834 u8 reserved[10]; 1835}; 1836 1837I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1838 1839/* Set Loopback mode (0x0618) */ 1840struct i40e_aqc_set_lb_mode { 1841 __le16 lb_mode; 1842#define I40E_AQ_LB_PHY_LOCAL 0x01 1843#define I40E_AQ_LB_PHY_REMOTE 0x02 1844#define I40E_AQ_LB_MAC_LOCAL 0x04 1845 u8 reserved[14]; 1846}; 1847 1848I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1849 1850/* Set PHY Debug command (0x0622) */ 1851struct i40e_aqc_set_phy_debug { 1852 u8 command_flags; 1853#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1854#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1855#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1856 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1857#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1858#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1859#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1860#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1861 u8 reserved[15]; 1862}; 1863 1864I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1865 1866enum i40e_aq_phy_reg_type { 1867 I40E_AQC_PHY_REG_INTERNAL = 0x1, 1868 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1869 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1870}; 1871 1872/* Run PHY Activity (0x0626) */ 1873struct i40e_aqc_run_phy_activity { 1874 __le16 activity_id; 1875 u8 flags; 1876 u8 reserved1; 1877 __le32 control; 1878 __le32 data; 1879 u8 reserved2[4]; 1880}; 1881 1882I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 1883 1884/* NVM Read command (indirect 0x0701) 1885 * NVM Erase commands (direct 0x0702) 1886 * NVM Update commands (indirect 0x0703) 1887 */ 1888struct i40e_aqc_nvm_update { 1889 u8 command_flags; 1890#define I40E_AQ_NVM_LAST_CMD 0x01 1891#define I40E_AQ_NVM_FLASH_ONLY 0x80 1892 u8 module_pointer; 1893 __le16 length; 1894 __le32 offset; 1895 __le32 addr_high; 1896 __le32 addr_low; 1897}; 1898 1899I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 1900 1901/* NVM Config Read (indirect 0x0704) */ 1902struct i40e_aqc_nvm_config_read { 1903 __le16 cmd_flags; 1904#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 1905#define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 1906#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 1907 __le16 element_count; 1908 __le16 element_id; /* Feature/field ID */ 1909 __le16 element_id_msw; /* MSWord of field ID */ 1910 __le32 address_high; 1911 __le32 address_low; 1912}; 1913 1914I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 1915 1916/* NVM Config Write (indirect 0x0705) */ 1917struct i40e_aqc_nvm_config_write { 1918 __le16 cmd_flags; 1919 __le16 element_count; 1920 u8 reserved[4]; 1921 __le32 address_high; 1922 __le32 address_low; 1923}; 1924 1925I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 1926 1927/* Used for 0x0704 as well as for 0x0705 commands */ 1928#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 1929#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 1930 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 1931#define I40E_AQ_ANVM_FEATURE 0 1932#define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 1933struct i40e_aqc_nvm_config_data_feature { 1934 __le16 feature_id; 1935#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 1936#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 1937#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 1938 __le16 feature_options; 1939 __le16 feature_selection; 1940}; 1941 1942I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 1943 1944struct i40e_aqc_nvm_config_data_immediate_field { 1945 __le32 field_id; 1946 __le32 field_value; 1947 __le16 field_options; 1948 __le16 reserved; 1949}; 1950 1951I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 1952 1953/* OEM Post Update (indirect 0x0720) 1954 * no command data struct used 1955 */ 1956struct i40e_aqc_nvm_oem_post_update { 1957#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 1958 u8 sel_data; 1959 u8 reserved[7]; 1960}; 1961 1962I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 1963 1964struct i40e_aqc_nvm_oem_post_update_buffer { 1965 u8 str_len; 1966 u8 dev_addr; 1967 __le16 eeprom_addr; 1968 u8 data[36]; 1969}; 1970 1971I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 1972 1973/* Thermal Sensor (indirect 0x0721) 1974 * read or set thermal sensor configs and values 1975 * takes a sensor and command specific data buffer, not detailed here 1976 */ 1977struct i40e_aqc_thermal_sensor { 1978 u8 sensor_action; 1979#define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 1980#define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 1981#define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 1982 u8 reserved[7]; 1983 __le32 addr_high; 1984 __le32 addr_low; 1985}; 1986 1987I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 1988 1989/* Send to PF command (indirect 0x0801) id is only used by PF 1990 * Send to VF command (indirect 0x0802) id is only used by PF 1991 * Send to Peer PF command (indirect 0x0803) 1992 */ 1993struct i40e_aqc_pf_vf_message { 1994 __le32 id; 1995 u8 reserved[4]; 1996 __le32 addr_high; 1997 __le32 addr_low; 1998}; 1999 2000I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 2001 2002/* Alternate structure */ 2003 2004/* Direct write (direct 0x0900) 2005 * Direct read (direct 0x0902) 2006 */ 2007struct i40e_aqc_alternate_write { 2008 __le32 address0; 2009 __le32 data0; 2010 __le32 address1; 2011 __le32 data1; 2012}; 2013 2014I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 2015 2016/* Indirect write (indirect 0x0901) 2017 * Indirect read (indirect 0x0903) 2018 */ 2019 2020struct i40e_aqc_alternate_ind_write { 2021 __le32 address; 2022 __le32 length; 2023 __le32 addr_high; 2024 __le32 addr_low; 2025}; 2026 2027I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 2028 2029/* Done alternate write (direct 0x0904) 2030 * uses i40e_aq_desc 2031 */ 2032struct i40e_aqc_alternate_write_done { 2033 __le16 cmd_flags; 2034#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 2035#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 2036#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 2037#define I40E_AQ_ALTERNATE_RESET_NEEDED 2 2038 u8 reserved[14]; 2039}; 2040 2041I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2042 2043/* Set OEM mode (direct 0x0905) */ 2044struct i40e_aqc_alternate_set_mode { 2045 __le32 mode; 2046#define I40E_AQ_ALTERNATE_MODE_NONE 0 2047#define I40E_AQ_ALTERNATE_MODE_OEM 1 2048 u8 reserved[12]; 2049}; 2050 2051I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2052 2053/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2054 2055/* async events 0x10xx */ 2056 2057/* Lan Queue Overflow Event (direct, 0x1001) */ 2058struct i40e_aqc_lan_overflow { 2059 __le32 prtdcb_rupto; 2060 __le32 otx_ctl; 2061 u8 reserved[8]; 2062}; 2063 2064I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2065 2066/* Get LLDP MIB (indirect 0x0A00) */ 2067struct i40e_aqc_lldp_get_mib { 2068 u8 type; 2069 u8 reserved1; 2070#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2071#define I40E_AQ_LLDP_MIB_LOCAL 0x0 2072#define I40E_AQ_LLDP_MIB_REMOTE 0x1 2073#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2074#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2075#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2076#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2077#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2078#define I40E_AQ_LLDP_TX_SHIFT 0x4 2079#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2080/* TX pause flags use I40E_AQ_LINK_TX_* above */ 2081 __le16 local_len; 2082 __le16 remote_len; 2083 u8 reserved2[2]; 2084 __le32 addr_high; 2085 __le32 addr_low; 2086}; 2087 2088I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2089 2090/* Configure LLDP MIB Change Event (direct 0x0A01) 2091 * also used for the event (with type in the command field) 2092 */ 2093struct i40e_aqc_lldp_update_mib { 2094 u8 command; 2095#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2096#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2097 u8 reserved[7]; 2098 __le32 addr_high; 2099 __le32 addr_low; 2100}; 2101 2102I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2103 2104/* Add LLDP TLV (indirect 0x0A02) 2105 * Delete LLDP TLV (indirect 0x0A04) 2106 */ 2107struct i40e_aqc_lldp_add_tlv { 2108 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2109 u8 reserved1[1]; 2110 __le16 len; 2111 u8 reserved2[4]; 2112 __le32 addr_high; 2113 __le32 addr_low; 2114}; 2115 2116I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2117 2118/* Update LLDP TLV (indirect 0x0A03) */ 2119struct i40e_aqc_lldp_update_tlv { 2120 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2121 u8 reserved; 2122 __le16 old_len; 2123 __le16 new_offset; 2124 __le16 new_len; 2125 __le32 addr_high; 2126 __le32 addr_low; 2127}; 2128 2129I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2130 2131/* Stop LLDP (direct 0x0A05) */ 2132struct i40e_aqc_lldp_stop { 2133 u8 command; 2134#define I40E_AQ_LLDP_AGENT_STOP 0x0 2135#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2136 u8 reserved[15]; 2137}; 2138 2139I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2140 2141/* Start LLDP (direct 0x0A06) */ 2142 2143struct i40e_aqc_lldp_start { 2144 u8 command; 2145#define I40E_AQ_LLDP_AGENT_START 0x1 2146 u8 reserved[15]; 2147}; 2148 2149I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2150 2151/* Get CEE DCBX Oper Config (0x0A07) 2152 * uses the generic descriptor struct 2153 * returns below as indirect response 2154 */ 2155 2156#define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2157#define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2158#define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2159#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2160#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2161#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2162 2163#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2164#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2165#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2166#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2167#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2168#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2169#define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2170#define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2171#define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2172#define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2173#define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2174#define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2175 2176/* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2177 * word boundary layout issues, which the Linux compilers silently deal 2178 * with by adding padding, making the actual struct larger than designed. 2179 * However, the FW compiler for the NIC is less lenient and complains 2180 * about the struct. Hence, the struct defined here has an extra byte in 2181 * fields reserved3 and reserved4 to directly acknowledge that padding, 2182 * and the new length is used in the length check macro. 2183 */ 2184struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2185 u8 reserved1; 2186 u8 oper_num_tc; 2187 u8 oper_prio_tc[4]; 2188 u8 reserved2; 2189 u8 oper_tc_bw[8]; 2190 u8 oper_pfc_en; 2191 u8 reserved3[2]; 2192 __le16 oper_app_prio; 2193 u8 reserved4[2]; 2194 __le16 tlv_status; 2195}; 2196 2197I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2198 2199struct i40e_aqc_get_cee_dcb_cfg_resp { 2200 u8 oper_num_tc; 2201 u8 oper_prio_tc[4]; 2202 u8 oper_tc_bw[8]; 2203 u8 oper_pfc_en; 2204 __le16 oper_app_prio; 2205 __le32 tlv_status; 2206 u8 reserved[12]; 2207}; 2208 2209I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2210 2211/* Set Local LLDP MIB (indirect 0x0A08) 2212 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2213 */ 2214struct i40e_aqc_lldp_set_local_mib { 2215#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2216#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \ 2217 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2218#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2219#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2220#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \ 2221 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2222#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2223 u8 type; 2224 u8 reserved0; 2225 __le16 length; 2226 u8 reserved1[4]; 2227 __le32 address_high; 2228 __le32 address_low; 2229}; 2230 2231I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2232 2233struct i40e_aqc_lldp_set_local_mib_resp { 2234#define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01 2235 u8 status; 2236 u8 reserved[15]; 2237}; 2238 2239I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp); 2240 2241/* Stop/Start LLDP Agent (direct 0x0A09) 2242 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2243 */ 2244struct i40e_aqc_lldp_stop_start_specific_agent { 2245#define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2246#define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2247 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2248 u8 command; 2249 u8 reserved[15]; 2250}; 2251 2252I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2253 2254/* Add Udp Tunnel command and completion (direct 0x0B00) */ 2255struct i40e_aqc_add_udp_tunnel { 2256 __le16 udp_port; 2257 u8 reserved0[3]; 2258 u8 protocol_type; 2259#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2260#define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2261#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2262#define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2263 u8 reserved1[10]; 2264}; 2265 2266I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2267 2268struct i40e_aqc_add_udp_tunnel_completion { 2269 __le16 udp_port; 2270 u8 filter_entry_index; 2271 u8 multiple_pfs; 2272#define I40E_AQC_SINGLE_PF 0x0 2273#define I40E_AQC_MULTIPLE_PFS 0x1 2274 u8 total_filters; 2275 u8 reserved[11]; 2276}; 2277 2278I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2279 2280/* remove UDP Tunnel command (0x0B01) */ 2281struct i40e_aqc_remove_udp_tunnel { 2282 u8 reserved[2]; 2283 u8 index; /* 0 to 15 */ 2284 u8 reserved2[13]; 2285}; 2286 2287I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2288 2289struct i40e_aqc_del_udp_tunnel_completion { 2290 __le16 udp_port; 2291 u8 index; /* 0 to 15 */ 2292 u8 multiple_pfs; 2293 u8 total_filters_used; 2294 u8 reserved1[11]; 2295}; 2296 2297I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2298 2299/* tunnel key structure 0x0B10 */ 2300 2301struct i40e_aqc_tunnel_key_structure { 2302 u8 key1_off; 2303 u8 key2_off; 2304 u8 key1_len; /* 0 to 15 */ 2305 u8 key2_len; /* 0 to 15 */ 2306 u8 flags; 2307#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2308/* response flags */ 2309#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2310#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2311#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2312 u8 network_key_index; 2313#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2314#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2315#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2316#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2317 u8 reserved[10]; 2318}; 2319 2320I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2321 2322/* OEM mode commands (direct 0xFE0x) */ 2323struct i40e_aqc_oem_param_change { 2324 __le32 param_type; 2325#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2326#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2327#define I40E_AQ_OEM_PARAM_MAC 2 2328 __le32 param_value1; 2329 __le16 param_value2; 2330 u8 reserved[6]; 2331}; 2332 2333I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2334 2335struct i40e_aqc_oem_state_change { 2336 __le32 state; 2337#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2338#define I40E_AQ_OEM_STATE_LINK_UP 0x1 2339 u8 reserved[12]; 2340}; 2341 2342I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2343 2344/* Initialize OCSD (0xFE02, direct) */ 2345struct i40e_aqc_opc_oem_ocsd_initialize { 2346 u8 type_status; 2347 u8 reserved1[3]; 2348 __le32 ocsd_memory_block_addr_high; 2349 __le32 ocsd_memory_block_addr_low; 2350 __le32 requested_update_interval; 2351}; 2352 2353I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2354 2355/* Initialize OCBB (0xFE03, direct) */ 2356struct i40e_aqc_opc_oem_ocbb_initialize { 2357 u8 type_status; 2358 u8 reserved1[3]; 2359 __le32 ocbb_memory_block_addr_high; 2360 __le32 ocbb_memory_block_addr_low; 2361 u8 reserved2[4]; 2362}; 2363 2364I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2365 2366/* debug commands */ 2367 2368/* get device id (0xFF00) uses the generic structure */ 2369 2370/* set test more (0xFF01, internal) */ 2371 2372struct i40e_acq_set_test_mode { 2373 u8 mode; 2374#define I40E_AQ_TEST_PARTIAL 0 2375#define I40E_AQ_TEST_FULL 1 2376#define I40E_AQ_TEST_NVM 2 2377 u8 reserved[3]; 2378 u8 command; 2379#define I40E_AQ_TEST_OPEN 0 2380#define I40E_AQ_TEST_CLOSE 1 2381#define I40E_AQ_TEST_INC 2 2382 u8 reserved2[3]; 2383 __le32 address_high; 2384 __le32 address_low; 2385}; 2386 2387I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2388 2389/* Debug Read Register command (0xFF03) 2390 * Debug Write Register command (0xFF04) 2391 */ 2392struct i40e_aqc_debug_reg_read_write { 2393 __le32 reserved; 2394 __le32 address; 2395 __le32 value_high; 2396 __le32 value_low; 2397}; 2398 2399I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2400 2401/* Scatter/gather Reg Read (indirect 0xFF05) 2402 * Scatter/gather Reg Write (indirect 0xFF06) 2403 */ 2404 2405/* i40e_aq_desc is used for the command */ 2406struct i40e_aqc_debug_reg_sg_element_data { 2407 __le32 address; 2408 __le32 value; 2409}; 2410 2411/* Debug Modify register (direct 0xFF07) */ 2412struct i40e_aqc_debug_modify_reg { 2413 __le32 address; 2414 __le32 value; 2415 __le32 clear_mask; 2416 __le32 set_mask; 2417}; 2418 2419I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2420 2421/* dump internal data (0xFF08, indirect) */ 2422 2423#define I40E_AQ_CLUSTER_ID_AUX 0 2424#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2425#define I40E_AQ_CLUSTER_ID_TXSCHED 2 2426#define I40E_AQ_CLUSTER_ID_HMC 3 2427#define I40E_AQ_CLUSTER_ID_MAC0 4 2428#define I40E_AQ_CLUSTER_ID_MAC1 5 2429#define I40E_AQ_CLUSTER_ID_MAC2 6 2430#define I40E_AQ_CLUSTER_ID_MAC3 7 2431#define I40E_AQ_CLUSTER_ID_DCB 8 2432#define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2433#define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2434#define I40E_AQ_CLUSTER_ID_ALTRAM 11 2435 2436struct i40e_aqc_debug_dump_internals { 2437 u8 cluster_id; 2438 u8 table_id; 2439 __le16 data_size; 2440 __le32 idx; 2441 __le32 address_high; 2442 __le32 address_low; 2443}; 2444 2445I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2446 2447struct i40e_aqc_debug_modify_internals { 2448 u8 cluster_id; 2449 u8 cluster_specific_params[7]; 2450 __le32 address_high; 2451 __le32 address_low; 2452}; 2453 2454I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2455 2456#endif /* _I40E_ADMINQ_CMD_H_ */ 2457