i40e_adminq_cmd.h revision 299554
1266423Sjfv/****************************************************************************** 2266423Sjfv 3279033Sjfv Copyright (c) 2013-2015, Intel Corporation 4266423Sjfv All rights reserved. 5266423Sjfv 6266423Sjfv Redistribution and use in source and binary forms, with or without 7266423Sjfv modification, are permitted provided that the following conditions are met: 8266423Sjfv 9266423Sjfv 1. Redistributions of source code must retain the above copyright notice, 10266423Sjfv this list of conditions and the following disclaimer. 11266423Sjfv 12266423Sjfv 2. Redistributions in binary form must reproduce the above copyright 13266423Sjfv notice, this list of conditions and the following disclaimer in the 14266423Sjfv documentation and/or other materials provided with the distribution. 15266423Sjfv 16266423Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17266423Sjfv contributors may be used to endorse or promote products derived from 18266423Sjfv this software without specific prior written permission. 19266423Sjfv 20266423Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21266423Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22266423Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23266423Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24266423Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25266423Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26266423Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27266423Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28266423Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29266423Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30266423Sjfv POSSIBILITY OF SUCH DAMAGE. 31266423Sjfv 32266423Sjfv******************************************************************************/ 33266423Sjfv/*$FreeBSD: head/sys/dev/ixl/i40e_adminq_cmd.h 299554 2016-05-12 18:21:52Z erj $*/ 34266423Sjfv 35266423Sjfv#ifndef _I40E_ADMINQ_CMD_H_ 36266423Sjfv#define _I40E_ADMINQ_CMD_H_ 37266423Sjfv 38266423Sjfv/* This header file defines the i40e Admin Queue commands and is shared between 39266423Sjfv * i40e Firmware and Software. 40266423Sjfv * 41266423Sjfv * This file needs to comply with the Linux Kernel coding style. 42266423Sjfv */ 43266423Sjfv 44270346Sjfv#define I40E_FW_API_VERSION_MAJOR 0x0001 45299549Serj#define I40E_FW_API_VERSION_MINOR 0x0005 46266423Sjfv 47266423Sjfvstruct i40e_aq_desc { 48266423Sjfv __le16 flags; 49266423Sjfv __le16 opcode; 50266423Sjfv __le16 datalen; 51266423Sjfv __le16 retval; 52266423Sjfv __le32 cookie_high; 53266423Sjfv __le32 cookie_low; 54266423Sjfv union { 55266423Sjfv struct { 56266423Sjfv __le32 param0; 57266423Sjfv __le32 param1; 58266423Sjfv __le32 param2; 59266423Sjfv __le32 param3; 60266423Sjfv } internal; 61266423Sjfv struct { 62266423Sjfv __le32 param0; 63266423Sjfv __le32 param1; 64266423Sjfv __le32 addr_high; 65266423Sjfv __le32 addr_low; 66266423Sjfv } external; 67266423Sjfv u8 raw[16]; 68266423Sjfv } params; 69266423Sjfv}; 70266423Sjfv 71266423Sjfv/* Flags sub-structure 72266423Sjfv * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 73266423Sjfv * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 74266423Sjfv */ 75266423Sjfv 76266423Sjfv/* command flags and offsets*/ 77270346Sjfv#define I40E_AQ_FLAG_DD_SHIFT 0 78270346Sjfv#define I40E_AQ_FLAG_CMP_SHIFT 1 79270346Sjfv#define I40E_AQ_FLAG_ERR_SHIFT 2 80270346Sjfv#define I40E_AQ_FLAG_VFE_SHIFT 3 81270346Sjfv#define I40E_AQ_FLAG_LB_SHIFT 9 82270346Sjfv#define I40E_AQ_FLAG_RD_SHIFT 10 83270346Sjfv#define I40E_AQ_FLAG_VFC_SHIFT 11 84270346Sjfv#define I40E_AQ_FLAG_BUF_SHIFT 12 85270346Sjfv#define I40E_AQ_FLAG_SI_SHIFT 13 86270346Sjfv#define I40E_AQ_FLAG_EI_SHIFT 14 87270346Sjfv#define I40E_AQ_FLAG_FE_SHIFT 15 88266423Sjfv 89270346Sjfv#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 90270346Sjfv#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 91270346Sjfv#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 92270346Sjfv#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 93270346Sjfv#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 94270346Sjfv#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 95270346Sjfv#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 96270346Sjfv#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 97270346Sjfv#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 98270346Sjfv#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 99270346Sjfv#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 100266423Sjfv 101266423Sjfv/* error codes */ 102266423Sjfvenum i40e_admin_queue_err { 103270346Sjfv I40E_AQ_RC_OK = 0, /* success */ 104270346Sjfv I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 105270346Sjfv I40E_AQ_RC_ENOENT = 2, /* No such element */ 106270346Sjfv I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 107270346Sjfv I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 108270346Sjfv I40E_AQ_RC_EIO = 5, /* I/O error */ 109270346Sjfv I40E_AQ_RC_ENXIO = 6, /* No such resource */ 110270346Sjfv I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 111270346Sjfv I40E_AQ_RC_EAGAIN = 8, /* Try again */ 112270346Sjfv I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 113270346Sjfv I40E_AQ_RC_EACCES = 10, /* Permission denied */ 114270346Sjfv I40E_AQ_RC_EFAULT = 11, /* Bad address */ 115270346Sjfv I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 116270346Sjfv I40E_AQ_RC_EEXIST = 13, /* object already exists */ 117270346Sjfv I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 118270346Sjfv I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 119270346Sjfv I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 120270346Sjfv I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 121270346Sjfv I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 122270346Sjfv I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 123270346Sjfv I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 124270346Sjfv I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 125270346Sjfv I40E_AQ_RC_EFBIG = 22, /* File too large */ 126266423Sjfv}; 127266423Sjfv 128266423Sjfv/* Admin Queue command opcodes */ 129266423Sjfvenum i40e_admin_queue_opc { 130266423Sjfv /* aq commands */ 131270346Sjfv i40e_aqc_opc_get_version = 0x0001, 132270346Sjfv i40e_aqc_opc_driver_version = 0x0002, 133270346Sjfv i40e_aqc_opc_queue_shutdown = 0x0003, 134270346Sjfv i40e_aqc_opc_set_pf_context = 0x0004, 135266423Sjfv 136266423Sjfv /* resource ownership */ 137270346Sjfv i40e_aqc_opc_request_resource = 0x0008, 138270346Sjfv i40e_aqc_opc_release_resource = 0x0009, 139266423Sjfv 140270346Sjfv i40e_aqc_opc_list_func_capabilities = 0x000A, 141270346Sjfv i40e_aqc_opc_list_dev_capabilities = 0x000B, 142266423Sjfv 143266423Sjfv /* LAA */ 144270346Sjfv i40e_aqc_opc_mac_address_read = 0x0107, 145270346Sjfv i40e_aqc_opc_mac_address_write = 0x0108, 146266423Sjfv 147266423Sjfv /* PXE */ 148270346Sjfv i40e_aqc_opc_clear_pxe_mode = 0x0110, 149266423Sjfv 150266423Sjfv /* internal switch commands */ 151270346Sjfv i40e_aqc_opc_get_switch_config = 0x0200, 152270346Sjfv i40e_aqc_opc_add_statistics = 0x0201, 153270346Sjfv i40e_aqc_opc_remove_statistics = 0x0202, 154270346Sjfv i40e_aqc_opc_set_port_parameters = 0x0203, 155270346Sjfv i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 156299549Serj i40e_aqc_opc_set_switch_config = 0x0205, 157266423Sjfv 158270346Sjfv i40e_aqc_opc_add_vsi = 0x0210, 159270346Sjfv i40e_aqc_opc_update_vsi_parameters = 0x0211, 160270346Sjfv i40e_aqc_opc_get_vsi_parameters = 0x0212, 161266423Sjfv 162270346Sjfv i40e_aqc_opc_add_pv = 0x0220, 163270346Sjfv i40e_aqc_opc_update_pv_parameters = 0x0221, 164270346Sjfv i40e_aqc_opc_get_pv_parameters = 0x0222, 165266423Sjfv 166270346Sjfv i40e_aqc_opc_add_veb = 0x0230, 167270346Sjfv i40e_aqc_opc_update_veb_parameters = 0x0231, 168270346Sjfv i40e_aqc_opc_get_veb_parameters = 0x0232, 169266423Sjfv 170270346Sjfv i40e_aqc_opc_delete_element = 0x0243, 171266423Sjfv 172270346Sjfv i40e_aqc_opc_add_macvlan = 0x0250, 173270346Sjfv i40e_aqc_opc_remove_macvlan = 0x0251, 174270346Sjfv i40e_aqc_opc_add_vlan = 0x0252, 175270346Sjfv i40e_aqc_opc_remove_vlan = 0x0253, 176270346Sjfv i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 177270346Sjfv i40e_aqc_opc_add_tag = 0x0255, 178270346Sjfv i40e_aqc_opc_remove_tag = 0x0256, 179270346Sjfv i40e_aqc_opc_add_multicast_etag = 0x0257, 180270346Sjfv i40e_aqc_opc_remove_multicast_etag = 0x0258, 181270346Sjfv i40e_aqc_opc_update_tag = 0x0259, 182270346Sjfv i40e_aqc_opc_add_control_packet_filter = 0x025A, 183270346Sjfv i40e_aqc_opc_remove_control_packet_filter = 0x025B, 184270346Sjfv i40e_aqc_opc_add_cloud_filters = 0x025C, 185270346Sjfv i40e_aqc_opc_remove_cloud_filters = 0x025D, 186266423Sjfv 187270346Sjfv i40e_aqc_opc_add_mirror_rule = 0x0260, 188270346Sjfv i40e_aqc_opc_delete_mirror_rule = 0x0261, 189266423Sjfv 190266423Sjfv /* DCB commands */ 191270346Sjfv i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 192270346Sjfv i40e_aqc_opc_dcb_updated = 0x0302, 193266423Sjfv 194266423Sjfv /* TX scheduler */ 195270346Sjfv i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 196270346Sjfv i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 197270346Sjfv i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 198270346Sjfv i40e_aqc_opc_query_vsi_bw_config = 0x0408, 199270346Sjfv i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 200270346Sjfv i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 201266423Sjfv 202270346Sjfv i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 203270346Sjfv i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 204270346Sjfv i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 205270346Sjfv i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 206270346Sjfv i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 207270346Sjfv i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 208270346Sjfv i40e_aqc_opc_query_port_ets_config = 0x0419, 209270346Sjfv i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 210270346Sjfv i40e_aqc_opc_suspend_port_tx = 0x041B, 211270346Sjfv i40e_aqc_opc_resume_port_tx = 0x041C, 212270346Sjfv i40e_aqc_opc_configure_partition_bw = 0x041D, 213266423Sjfv 214266423Sjfv /* hmc */ 215270346Sjfv i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 216270346Sjfv i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 217266423Sjfv 218266423Sjfv /* phy commands*/ 219270346Sjfv i40e_aqc_opc_get_phy_abilities = 0x0600, 220270346Sjfv i40e_aqc_opc_set_phy_config = 0x0601, 221270346Sjfv i40e_aqc_opc_set_mac_config = 0x0603, 222270346Sjfv i40e_aqc_opc_set_link_restart_an = 0x0605, 223270346Sjfv i40e_aqc_opc_get_link_status = 0x0607, 224270346Sjfv i40e_aqc_opc_set_phy_int_mask = 0x0613, 225270346Sjfv i40e_aqc_opc_get_local_advt_reg = 0x0614, 226270346Sjfv i40e_aqc_opc_set_local_advt_reg = 0x0615, 227270346Sjfv i40e_aqc_opc_get_partner_advt = 0x0616, 228270346Sjfv i40e_aqc_opc_set_lb_modes = 0x0618, 229270346Sjfv i40e_aqc_opc_get_phy_wol_caps = 0x0621, 230270346Sjfv i40e_aqc_opc_set_phy_debug = 0x0622, 231270346Sjfv i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 232299549Serj i40e_aqc_opc_run_phy_activity = 0x0626, 233266423Sjfv 234266423Sjfv /* NVM commands */ 235270346Sjfv i40e_aqc_opc_nvm_read = 0x0701, 236270346Sjfv i40e_aqc_opc_nvm_erase = 0x0702, 237270346Sjfv i40e_aqc_opc_nvm_update = 0x0703, 238270346Sjfv i40e_aqc_opc_nvm_config_read = 0x0704, 239270346Sjfv i40e_aqc_opc_nvm_config_write = 0x0705, 240284049Sjfv i40e_aqc_opc_oem_post_update = 0x0720, 241299549Serj i40e_aqc_opc_thermal_sensor = 0x0721, 242266423Sjfv 243266423Sjfv /* virtualization commands */ 244270346Sjfv i40e_aqc_opc_send_msg_to_pf = 0x0801, 245270346Sjfv i40e_aqc_opc_send_msg_to_vf = 0x0802, 246270346Sjfv i40e_aqc_opc_send_msg_to_peer = 0x0803, 247266423Sjfv 248266423Sjfv /* alternate structure */ 249270346Sjfv i40e_aqc_opc_alternate_write = 0x0900, 250270346Sjfv i40e_aqc_opc_alternate_write_indirect = 0x0901, 251270346Sjfv i40e_aqc_opc_alternate_read = 0x0902, 252270346Sjfv i40e_aqc_opc_alternate_read_indirect = 0x0903, 253270346Sjfv i40e_aqc_opc_alternate_write_done = 0x0904, 254270346Sjfv i40e_aqc_opc_alternate_set_mode = 0x0905, 255270346Sjfv i40e_aqc_opc_alternate_clear_port = 0x0906, 256266423Sjfv 257266423Sjfv /* LLDP commands */ 258270346Sjfv i40e_aqc_opc_lldp_get_mib = 0x0A00, 259270346Sjfv i40e_aqc_opc_lldp_update_mib = 0x0A01, 260270346Sjfv i40e_aqc_opc_lldp_add_tlv = 0x0A02, 261270346Sjfv i40e_aqc_opc_lldp_update_tlv = 0x0A03, 262270346Sjfv i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 263270346Sjfv i40e_aqc_opc_lldp_stop = 0x0A05, 264270346Sjfv i40e_aqc_opc_lldp_start = 0x0A06, 265277082Sjfv i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 266277082Sjfv i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 267277082Sjfv i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 268266423Sjfv 269266423Sjfv /* Tunnel commands */ 270270346Sjfv i40e_aqc_opc_add_udp_tunnel = 0x0B00, 271270346Sjfv i40e_aqc_opc_del_udp_tunnel = 0x0B01, 272266423Sjfv 273266423Sjfv /* Async Events */ 274270346Sjfv i40e_aqc_opc_event_lan_overflow = 0x1001, 275266423Sjfv 276266423Sjfv /* OEM commands */ 277270346Sjfv i40e_aqc_opc_oem_parameter_change = 0xFE00, 278270346Sjfv i40e_aqc_opc_oem_device_status_change = 0xFE01, 279277082Sjfv i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 280277082Sjfv i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 281266423Sjfv 282266423Sjfv /* debug commands */ 283270346Sjfv i40e_aqc_opc_debug_read_reg = 0xFF03, 284270346Sjfv i40e_aqc_opc_debug_write_reg = 0xFF04, 285270346Sjfv i40e_aqc_opc_debug_modify_reg = 0xFF07, 286270346Sjfv i40e_aqc_opc_debug_dump_internals = 0xFF08, 287266423Sjfv}; 288266423Sjfv 289266423Sjfv/* command structures and indirect data structures */ 290266423Sjfv 291266423Sjfv/* Structure naming conventions: 292266423Sjfv * - no suffix for direct command descriptor structures 293266423Sjfv * - _data for indirect sent data 294266423Sjfv * - _resp for indirect return data (data which is both will use _data) 295266423Sjfv * - _completion for direct return data 296266423Sjfv * - _element_ for repeated elements (may also be _data or _resp) 297266423Sjfv * 298266423Sjfv * Command structures are expected to overlay the params.raw member of the basic 299266423Sjfv * descriptor, and as such cannot exceed 16 bytes in length. 300266423Sjfv */ 301266423Sjfv 302266423Sjfv/* This macro is used to generate a compilation error if a structure 303266423Sjfv * is not exactly the correct length. It gives a divide by zero error if the 304266423Sjfv * structure is not of the correct size, otherwise it creates an enum that is 305266423Sjfv * never used. 306266423Sjfv */ 307266423Sjfv#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 308266423Sjfv { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 309266423Sjfv 310266423Sjfv/* This macro is used extensively to ensure that command structures are 16 311266423Sjfv * bytes in length as they have to map to the raw array of that size. 312266423Sjfv */ 313270346Sjfv#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 314266423Sjfv 315266423Sjfv/* internal (0x00XX) commands */ 316266423Sjfv 317266423Sjfv/* Get version (direct 0x0001) */ 318266423Sjfvstruct i40e_aqc_get_version { 319266423Sjfv __le32 rom_ver; 320266423Sjfv __le32 fw_build; 321266423Sjfv __le16 fw_major; 322266423Sjfv __le16 fw_minor; 323266423Sjfv __le16 api_major; 324266423Sjfv __le16 api_minor; 325266423Sjfv}; 326266423Sjfv 327266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 328266423Sjfv 329266423Sjfv/* Send driver version (indirect 0x0002) */ 330266423Sjfvstruct i40e_aqc_driver_version { 331270346Sjfv u8 driver_major_ver; 332270346Sjfv u8 driver_minor_ver; 333270346Sjfv u8 driver_build_ver; 334270346Sjfv u8 driver_subbuild_ver; 335270346Sjfv u8 reserved[4]; 336270346Sjfv __le32 address_high; 337270346Sjfv __le32 address_low; 338266423Sjfv}; 339266423Sjfv 340266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 341266423Sjfv 342266423Sjfv/* Queue Shutdown (direct 0x0003) */ 343266423Sjfvstruct i40e_aqc_queue_shutdown { 344270346Sjfv __le32 driver_unloading; 345270346Sjfv#define I40E_AQ_DRIVER_UNLOADING 0x1 346270346Sjfv u8 reserved[12]; 347266423Sjfv}; 348266423Sjfv 349266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 350266423Sjfv 351266423Sjfv/* Set PF context (0x0004, direct) */ 352266423Sjfvstruct i40e_aqc_set_pf_context { 353266423Sjfv u8 pf_id; 354266423Sjfv u8 reserved[15]; 355266423Sjfv}; 356266423Sjfv 357266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 358266423Sjfv 359266423Sjfv/* Request resource ownership (direct 0x0008) 360266423Sjfv * Release resource ownership (direct 0x0009) 361266423Sjfv */ 362270346Sjfv#define I40E_AQ_RESOURCE_NVM 1 363270346Sjfv#define I40E_AQ_RESOURCE_SDP 2 364270346Sjfv#define I40E_AQ_RESOURCE_ACCESS_READ 1 365270346Sjfv#define I40E_AQ_RESOURCE_ACCESS_WRITE 2 366270346Sjfv#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 367270346Sjfv#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 368266423Sjfv 369266423Sjfvstruct i40e_aqc_request_resource { 370270346Sjfv __le16 resource_id; 371270346Sjfv __le16 access_type; 372270346Sjfv __le32 timeout; 373270346Sjfv __le32 resource_number; 374270346Sjfv u8 reserved[4]; 375266423Sjfv}; 376266423Sjfv 377266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 378266423Sjfv 379266423Sjfv/* Get function capabilities (indirect 0x000A) 380266423Sjfv * Get device capabilities (indirect 0x000B) 381266423Sjfv */ 382266423Sjfvstruct i40e_aqc_list_capabilites { 383266423Sjfv u8 command_flags; 384270346Sjfv#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 385266423Sjfv u8 pf_index; 386266423Sjfv u8 reserved[2]; 387266423Sjfv __le32 count; 388266423Sjfv __le32 addr_high; 389266423Sjfv __le32 addr_low; 390266423Sjfv}; 391266423Sjfv 392266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 393266423Sjfv 394266423Sjfvstruct i40e_aqc_list_capabilities_element_resp { 395270346Sjfv __le16 id; 396270346Sjfv u8 major_rev; 397270346Sjfv u8 minor_rev; 398270346Sjfv __le32 number; 399270346Sjfv __le32 logical_id; 400270346Sjfv __le32 phys_id; 401270346Sjfv u8 reserved[16]; 402266423Sjfv}; 403266423Sjfv 404266423Sjfv/* list of caps */ 405266423Sjfv 406270346Sjfv#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 407270346Sjfv#define I40E_AQ_CAP_ID_MNG_MODE 0x0002 408270346Sjfv#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 409270346Sjfv#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 410270346Sjfv#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 411270346Sjfv#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 412299548Serj#define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 413270346Sjfv#define I40E_AQ_CAP_ID_SRIOV 0x0012 414270346Sjfv#define I40E_AQ_CAP_ID_VF 0x0013 415270346Sjfv#define I40E_AQ_CAP_ID_VMDQ 0x0014 416270346Sjfv#define I40E_AQ_CAP_ID_8021QBG 0x0015 417270346Sjfv#define I40E_AQ_CAP_ID_8021QBR 0x0016 418270346Sjfv#define I40E_AQ_CAP_ID_VSI 0x0017 419270346Sjfv#define I40E_AQ_CAP_ID_DCB 0x0018 420270346Sjfv#define I40E_AQ_CAP_ID_FCOE 0x0021 421277082Sjfv#define I40E_AQ_CAP_ID_ISCSI 0x0022 422270346Sjfv#define I40E_AQ_CAP_ID_RSS 0x0040 423270346Sjfv#define I40E_AQ_CAP_ID_RXQ 0x0041 424270346Sjfv#define I40E_AQ_CAP_ID_TXQ 0x0042 425270346Sjfv#define I40E_AQ_CAP_ID_MSIX 0x0043 426270346Sjfv#define I40E_AQ_CAP_ID_VF_MSIX 0x0044 427270346Sjfv#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 428270346Sjfv#define I40E_AQ_CAP_ID_1588 0x0046 429270346Sjfv#define I40E_AQ_CAP_ID_IWARP 0x0051 430270346Sjfv#define I40E_AQ_CAP_ID_LED 0x0061 431270346Sjfv#define I40E_AQ_CAP_ID_SDP 0x0062 432270346Sjfv#define I40E_AQ_CAP_ID_MDIO 0x0063 433299548Serj#define I40E_AQ_CAP_ID_WSR_PROT 0x0064 434270346Sjfv#define I40E_AQ_CAP_ID_FLEX10 0x00F1 435270346Sjfv#define I40E_AQ_CAP_ID_CEM 0x00F2 436266423Sjfv 437266423Sjfv/* Set CPPM Configuration (direct 0x0103) */ 438266423Sjfvstruct i40e_aqc_cppm_configuration { 439270346Sjfv __le16 command_flags; 440270346Sjfv#define I40E_AQ_CPPM_EN_LTRC 0x0800 441270346Sjfv#define I40E_AQ_CPPM_EN_DMCTH 0x1000 442270346Sjfv#define I40E_AQ_CPPM_EN_DMCTLX 0x2000 443270346Sjfv#define I40E_AQ_CPPM_EN_HPTC 0x4000 444270346Sjfv#define I40E_AQ_CPPM_EN_DMARC 0x8000 445270346Sjfv __le16 ttlx; 446270346Sjfv __le32 dmacr; 447270346Sjfv __le16 dmcth; 448270346Sjfv u8 hptc; 449270346Sjfv u8 reserved; 450270346Sjfv __le32 pfltrc; 451266423Sjfv}; 452266423Sjfv 453266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 454266423Sjfv 455266423Sjfv/* Set ARP Proxy command / response (indirect 0x0104) */ 456266423Sjfvstruct i40e_aqc_arp_proxy_data { 457270346Sjfv __le16 command_flags; 458270346Sjfv#define I40E_AQ_ARP_INIT_IPV4 0x0008 459270346Sjfv#define I40E_AQ_ARP_UNSUP_CTL 0x0010 460270346Sjfv#define I40E_AQ_ARP_ENA 0x0020 461270346Sjfv#define I40E_AQ_ARP_ADD_IPV4 0x0040 462270346Sjfv#define I40E_AQ_ARP_DEL_IPV4 0x0080 463270346Sjfv __le16 table_id; 464270346Sjfv __le32 pfpm_proxyfc; 465270346Sjfv __le32 ip_addr; 466270346Sjfv u8 mac_addr[6]; 467277082Sjfv u8 reserved[2]; 468266423Sjfv}; 469266423Sjfv 470277082SjfvI40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 471277082Sjfv 472266423Sjfv/* Set NS Proxy Table Entry Command (indirect 0x0105) */ 473266423Sjfvstruct i40e_aqc_ns_proxy_data { 474270346Sjfv __le16 table_idx_mac_addr_0; 475270346Sjfv __le16 table_idx_mac_addr_1; 476270346Sjfv __le16 table_idx_ipv6_0; 477270346Sjfv __le16 table_idx_ipv6_1; 478270346Sjfv __le16 control; 479270346Sjfv#define I40E_AQ_NS_PROXY_ADD_0 0x0100 480270346Sjfv#define I40E_AQ_NS_PROXY_DEL_0 0x0200 481270346Sjfv#define I40E_AQ_NS_PROXY_ADD_1 0x0400 482270346Sjfv#define I40E_AQ_NS_PROXY_DEL_1 0x0800 483270346Sjfv#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 484270346Sjfv#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 485270346Sjfv#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 486270346Sjfv#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 487270346Sjfv#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 488270346Sjfv#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 489270346Sjfv#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 490270346Sjfv u8 mac_addr_0[6]; 491270346Sjfv u8 mac_addr_1[6]; 492270346Sjfv u8 local_mac_addr[6]; 493270346Sjfv u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 494270346Sjfv u8 ipv6_addr_1[16]; 495266423Sjfv}; 496266423Sjfv 497277082SjfvI40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 498277082Sjfv 499266423Sjfv/* Manage LAA Command (0x0106) - obsolete */ 500266423Sjfvstruct i40e_aqc_mng_laa { 501266423Sjfv __le16 command_flags; 502270346Sjfv#define I40E_AQ_LAA_FLAG_WR 0x8000 503270346Sjfv u8 reserved[2]; 504270346Sjfv __le32 sal; 505270346Sjfv __le16 sah; 506270346Sjfv u8 reserved2[6]; 507266423Sjfv}; 508266423Sjfv 509277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 510277082Sjfv 511266423Sjfv/* Manage MAC Address Read Command (indirect 0x0107) */ 512266423Sjfvstruct i40e_aqc_mac_address_read { 513266423Sjfv __le16 command_flags; 514270346Sjfv#define I40E_AQC_LAN_ADDR_VALID 0x10 515270346Sjfv#define I40E_AQC_SAN_ADDR_VALID 0x20 516270346Sjfv#define I40E_AQC_PORT_ADDR_VALID 0x40 517270346Sjfv#define I40E_AQC_WOL_ADDR_VALID 0x80 518284049Sjfv#define I40E_AQC_MC_MAG_EN_VALID 0x100 519284049Sjfv#define I40E_AQC_ADDR_VALID_MASK 0x1F0 520270346Sjfv u8 reserved[6]; 521270346Sjfv __le32 addr_high; 522270346Sjfv __le32 addr_low; 523266423Sjfv}; 524266423Sjfv 525266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 526266423Sjfv 527266423Sjfvstruct i40e_aqc_mac_address_read_data { 528266423Sjfv u8 pf_lan_mac[6]; 529266423Sjfv u8 pf_san_mac[6]; 530266423Sjfv u8 port_mac[6]; 531266423Sjfv u8 pf_wol_mac[6]; 532266423Sjfv}; 533266423Sjfv 534266423SjfvI40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 535266423Sjfv 536266423Sjfv/* Manage MAC Address Write Command (0x0108) */ 537266423Sjfvstruct i40e_aqc_mac_address_write { 538270346Sjfv __le16 command_flags; 539270346Sjfv#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 540270346Sjfv#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 541270346Sjfv#define I40E_AQC_WRITE_TYPE_PORT 0x8000 542284049Sjfv#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 543284049Sjfv#define I40E_AQC_WRITE_TYPE_MASK 0xC000 544284049Sjfv 545270346Sjfv __le16 mac_sah; 546270346Sjfv __le32 mac_sal; 547270346Sjfv u8 reserved[8]; 548266423Sjfv}; 549266423Sjfv 550266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 551266423Sjfv 552266423Sjfv/* PXE commands (0x011x) */ 553266423Sjfv 554266423Sjfv/* Clear PXE Command and response (direct 0x0110) */ 555266423Sjfvstruct i40e_aqc_clear_pxe { 556266423Sjfv u8 rx_cnt; 557266423Sjfv u8 reserved[15]; 558266423Sjfv}; 559266423Sjfv 560266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 561266423Sjfv 562266423Sjfv/* Switch configuration commands (0x02xx) */ 563266423Sjfv 564266423Sjfv/* Used by many indirect commands that only pass an seid and a buffer in the 565266423Sjfv * command 566266423Sjfv */ 567266423Sjfvstruct i40e_aqc_switch_seid { 568270346Sjfv __le16 seid; 569270346Sjfv u8 reserved[6]; 570270346Sjfv __le32 addr_high; 571270346Sjfv __le32 addr_low; 572266423Sjfv}; 573266423Sjfv 574266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 575266423Sjfv 576266423Sjfv/* Get Switch Configuration command (indirect 0x0200) 577266423Sjfv * uses i40e_aqc_switch_seid for the descriptor 578266423Sjfv */ 579266423Sjfvstruct i40e_aqc_get_switch_config_header_resp { 580270346Sjfv __le16 num_reported; 581270346Sjfv __le16 num_total; 582270346Sjfv u8 reserved[12]; 583266423Sjfv}; 584266423Sjfv 585277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 586277082Sjfv 587266423Sjfvstruct i40e_aqc_switch_config_element_resp { 588270346Sjfv u8 element_type; 589270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_MAC 1 590270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_PF 2 591270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_VF 3 592270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_EMP 4 593270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_BMC 5 594270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_PV 16 595270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_VEB 17 596270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_PA 18 597270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_VSI 19 598270346Sjfv u8 revision; 599270346Sjfv#define I40E_AQ_SW_ELEM_REV_1 1 600270346Sjfv __le16 seid; 601270346Sjfv __le16 uplink_seid; 602270346Sjfv __le16 downlink_seid; 603270346Sjfv u8 reserved[3]; 604270346Sjfv u8 connection_type; 605270346Sjfv#define I40E_AQ_CONN_TYPE_REGULAR 0x1 606270346Sjfv#define I40E_AQ_CONN_TYPE_DEFAULT 0x2 607270346Sjfv#define I40E_AQ_CONN_TYPE_CASCADED 0x3 608270346Sjfv __le16 scheduler_id; 609270346Sjfv __le16 element_info; 610266423Sjfv}; 611266423Sjfv 612277082SjfvI40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 613277082Sjfv 614266423Sjfv/* Get Switch Configuration (indirect 0x0200) 615266423Sjfv * an array of elements are returned in the response buffer 616266423Sjfv * the first in the array is the header, remainder are elements 617266423Sjfv */ 618266423Sjfvstruct i40e_aqc_get_switch_config_resp { 619270346Sjfv struct i40e_aqc_get_switch_config_header_resp header; 620270346Sjfv struct i40e_aqc_switch_config_element_resp element[1]; 621266423Sjfv}; 622266423Sjfv 623277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 624277082Sjfv 625266423Sjfv/* Add Statistics (direct 0x0201) 626266423Sjfv * Remove Statistics (direct 0x0202) 627266423Sjfv */ 628266423Sjfvstruct i40e_aqc_add_remove_statistics { 629270346Sjfv __le16 seid; 630270346Sjfv __le16 vlan; 631270346Sjfv __le16 stat_index; 632270346Sjfv u8 reserved[10]; 633266423Sjfv}; 634266423Sjfv 635266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 636266423Sjfv 637266423Sjfv/* Set Port Parameters command (direct 0x0203) */ 638266423Sjfvstruct i40e_aqc_set_port_parameters { 639270346Sjfv __le16 command_flags; 640270346Sjfv#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 641270346Sjfv#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 642270346Sjfv#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 643270346Sjfv __le16 bad_frame_vsi; 644270346Sjfv __le16 default_seid; /* reserved for command */ 645270346Sjfv u8 reserved[10]; 646266423Sjfv}; 647266423Sjfv 648266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 649266423Sjfv 650266423Sjfv/* Get Switch Resource Allocation (indirect 0x0204) */ 651266423Sjfvstruct i40e_aqc_get_switch_resource_alloc { 652270346Sjfv u8 num_entries; /* reserved for command */ 653270346Sjfv u8 reserved[7]; 654270346Sjfv __le32 addr_high; 655270346Sjfv __le32 addr_low; 656266423Sjfv}; 657266423Sjfv 658266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 659266423Sjfv 660266423Sjfv/* expect an array of these structs in the response buffer */ 661266423Sjfvstruct i40e_aqc_switch_resource_alloc_element_resp { 662270346Sjfv u8 resource_type; 663270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VEB 0x0 664270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VSI 0x1 665270346Sjfv#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 666270346Sjfv#define I40E_AQ_RESOURCE_TYPE_STAG 0x3 667270346Sjfv#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 668270346Sjfv#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 669270346Sjfv#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 670270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 671270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 672270346Sjfv#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 673270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 674270346Sjfv#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 675270346Sjfv#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 676270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 677270346Sjfv#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 678270346Sjfv#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 679270346Sjfv#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 680270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 681270346Sjfv#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 682270346Sjfv u8 reserved1; 683270346Sjfv __le16 guaranteed; 684270346Sjfv __le16 total; 685270346Sjfv __le16 used; 686270346Sjfv __le16 total_unalloced; 687270346Sjfv u8 reserved2[6]; 688266423Sjfv}; 689266423Sjfv 690277082SjfvI40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 691277082Sjfv 692299549Serj/* Set Switch Configuration (direct 0x0205) */ 693299549Serjstruct i40e_aqc_set_switch_config { 694299549Serj __le16 flags; 695299549Serj#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 696299549Serj#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 697299549Serj __le16 valid_flags; 698299549Serj u8 reserved[12]; 699299549Serj}; 700299549Serj 701299549SerjI40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 702299549Serj 703266423Sjfv/* Add VSI (indirect 0x0210) 704266423Sjfv * this indirect command uses struct i40e_aqc_vsi_properties_data 705266423Sjfv * as the indirect buffer (128 bytes) 706266423Sjfv * 707266423Sjfv * Update VSI (indirect 0x211) 708266423Sjfv * uses the same data structure as Add VSI 709266423Sjfv * 710266423Sjfv * Get VSI (indirect 0x0212) 711266423Sjfv * uses the same completion and data structure as Add VSI 712266423Sjfv */ 713266423Sjfvstruct i40e_aqc_add_get_update_vsi { 714270346Sjfv __le16 uplink_seid; 715270346Sjfv u8 connection_type; 716270346Sjfv#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 717270346Sjfv#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 718270346Sjfv#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 719270346Sjfv u8 reserved1; 720270346Sjfv u8 vf_id; 721270346Sjfv u8 reserved2; 722270346Sjfv __le16 vsi_flags; 723270346Sjfv#define I40E_AQ_VSI_TYPE_SHIFT 0x0 724270346Sjfv#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 725270346Sjfv#define I40E_AQ_VSI_TYPE_VF 0x0 726270346Sjfv#define I40E_AQ_VSI_TYPE_VMDQ2 0x1 727270346Sjfv#define I40E_AQ_VSI_TYPE_PF 0x2 728270346Sjfv#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 729270346Sjfv#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 730270346Sjfv __le32 addr_high; 731270346Sjfv __le32 addr_low; 732266423Sjfv}; 733266423Sjfv 734266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 735266423Sjfv 736266423Sjfvstruct i40e_aqc_add_get_update_vsi_completion { 737266423Sjfv __le16 seid; 738266423Sjfv __le16 vsi_number; 739266423Sjfv __le16 vsi_used; 740266423Sjfv __le16 vsi_free; 741266423Sjfv __le32 addr_high; 742266423Sjfv __le32 addr_low; 743266423Sjfv}; 744266423Sjfv 745266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 746266423Sjfv 747266423Sjfvstruct i40e_aqc_vsi_properties_data { 748266423Sjfv /* first 96 byte are written by SW */ 749270346Sjfv __le16 valid_sections; 750270346Sjfv#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 751270346Sjfv#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 752270346Sjfv#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 753270346Sjfv#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 754270346Sjfv#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 755270346Sjfv#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 756270346Sjfv#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 757270346Sjfv#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 758270346Sjfv#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 759270346Sjfv#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 760266423Sjfv /* switch section */ 761270346Sjfv __le16 switch_id; /* 12bit id combined with flags below */ 762270346Sjfv#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 763270346Sjfv#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 764270346Sjfv#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 765270346Sjfv#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 766270346Sjfv#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 767270346Sjfv u8 sw_reserved[2]; 768266423Sjfv /* security section */ 769270346Sjfv u8 sec_flags; 770270346Sjfv#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 771270346Sjfv#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 772270346Sjfv#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 773270346Sjfv u8 sec_reserved; 774266423Sjfv /* VLAN section */ 775270346Sjfv __le16 pvid; /* VLANS include priority bits */ 776270346Sjfv __le16 fcoe_pvid; 777270346Sjfv u8 port_vlan_flags; 778270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 779270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 780270346Sjfv I40E_AQ_VSI_PVLAN_MODE_SHIFT) 781270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 782270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 783270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 784270346Sjfv#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 785270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 786270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 787270346Sjfv I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 788270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 789270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 790270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 791270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 792270346Sjfv u8 pvlan_reserved[3]; 793266423Sjfv /* ingress egress up sections */ 794270346Sjfv __le32 ingress_table; /* bitmap, 3 bits per up */ 795270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 796270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 797270346Sjfv I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 798270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 799270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 800270346Sjfv I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 801270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 802270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 803270346Sjfv I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 804270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 805270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 806270346Sjfv I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 807270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 808270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 809270346Sjfv I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 810270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 811270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 812270346Sjfv I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 813270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 814270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 815270346Sjfv I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 816270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 817270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 818270346Sjfv I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 819270346Sjfv __le32 egress_table; /* same defines as for ingress table */ 820266423Sjfv /* cascaded PV section */ 821270346Sjfv __le16 cas_pv_tag; 822270346Sjfv u8 cas_pv_flags; 823270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 824270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 825270346Sjfv I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 826270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 827270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 828270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 829270346Sjfv#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 830270346Sjfv#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 831270346Sjfv#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 832270346Sjfv u8 cas_pv_reserved; 833266423Sjfv /* queue mapping section */ 834270346Sjfv __le16 mapping_flags; 835270346Sjfv#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 836270346Sjfv#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 837270346Sjfv __le16 queue_mapping[16]; 838270346Sjfv#define I40E_AQ_VSI_QUEUE_SHIFT 0x0 839270346Sjfv#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 840270346Sjfv __le16 tc_mapping[8]; 841270346Sjfv#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 842270346Sjfv#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 843270346Sjfv I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 844270346Sjfv#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 845270346Sjfv#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 846270346Sjfv I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 847266423Sjfv /* queueing option section */ 848270346Sjfv u8 queueing_opt_flags; 849270346Sjfv#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 850270346Sjfv#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 851270346Sjfv u8 queueing_opt_reserved[3]; 852266423Sjfv /* scheduler section */ 853270346Sjfv u8 up_enable_bits; 854270346Sjfv u8 sched_reserved; 855266423Sjfv /* outer up section */ 856270346Sjfv __le32 outer_up_table; /* same structure and defines as ingress table */ 857270346Sjfv u8 cmd_reserved[8]; 858266423Sjfv /* last 32 bytes are written by FW */ 859270346Sjfv __le16 qs_handle[8]; 860266423Sjfv#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 861270346Sjfv __le16 stat_counter_idx; 862270346Sjfv __le16 sched_id; 863270346Sjfv u8 resp_reserved[12]; 864266423Sjfv}; 865266423Sjfv 866266423SjfvI40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 867266423Sjfv 868266423Sjfv/* Add Port Virtualizer (direct 0x0220) 869266423Sjfv * also used for update PV (direct 0x0221) but only flags are used 870266423Sjfv * (IS_CTRL_PORT only works on add PV) 871266423Sjfv */ 872266423Sjfvstruct i40e_aqc_add_update_pv { 873270346Sjfv __le16 command_flags; 874270346Sjfv#define I40E_AQC_PV_FLAG_PV_TYPE 0x1 875270346Sjfv#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 876270346Sjfv#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 877270346Sjfv#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 878270346Sjfv __le16 uplink_seid; 879270346Sjfv __le16 connected_seid; 880270346Sjfv u8 reserved[10]; 881266423Sjfv}; 882266423Sjfv 883266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 884266423Sjfv 885266423Sjfvstruct i40e_aqc_add_update_pv_completion { 886266423Sjfv /* reserved for update; for add also encodes error if rc == ENOSPC */ 887270346Sjfv __le16 pv_seid; 888270346Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 889270346Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 890270346Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 891270346Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 892270346Sjfv u8 reserved[14]; 893266423Sjfv}; 894266423Sjfv 895266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 896266423Sjfv 897266423Sjfv/* Get PV Params (direct 0x0222) 898266423Sjfv * uses i40e_aqc_switch_seid for the descriptor 899266423Sjfv */ 900266423Sjfv 901266423Sjfvstruct i40e_aqc_get_pv_params_completion { 902270346Sjfv __le16 seid; 903270346Sjfv __le16 default_stag; 904270346Sjfv __le16 pv_flags; /* same flags as add_pv */ 905270346Sjfv#define I40E_AQC_GET_PV_PV_TYPE 0x1 906270346Sjfv#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 907270346Sjfv#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 908270346Sjfv u8 reserved[8]; 909270346Sjfv __le16 default_port_seid; 910266423Sjfv}; 911266423Sjfv 912266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 913266423Sjfv 914266423Sjfv/* Add VEB (direct 0x0230) */ 915266423Sjfvstruct i40e_aqc_add_veb { 916270346Sjfv __le16 uplink_seid; 917270346Sjfv __le16 downlink_seid; 918270346Sjfv __le16 veb_flags; 919270346Sjfv#define I40E_AQC_ADD_VEB_FLOATING 0x1 920270346Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 921270346Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 922266423Sjfv I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 923270346Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 924270346Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 925299549Serj#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 926299549Serj#define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 927270346Sjfv u8 enable_tcs; 928270346Sjfv u8 reserved[9]; 929266423Sjfv}; 930266423Sjfv 931266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 932266423Sjfv 933266423Sjfvstruct i40e_aqc_add_veb_completion { 934270346Sjfv u8 reserved[6]; 935270346Sjfv __le16 switch_seid; 936266423Sjfv /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 937270346Sjfv __le16 veb_seid; 938270346Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 939270346Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 940270346Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 941270346Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 942270346Sjfv __le16 statistic_index; 943270346Sjfv __le16 vebs_used; 944270346Sjfv __le16 vebs_free; 945266423Sjfv}; 946266423Sjfv 947266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 948266423Sjfv 949266423Sjfv/* Get VEB Parameters (direct 0x0232) 950266423Sjfv * uses i40e_aqc_switch_seid for the descriptor 951266423Sjfv */ 952266423Sjfvstruct i40e_aqc_get_veb_parameters_completion { 953270346Sjfv __le16 seid; 954270346Sjfv __le16 switch_id; 955270346Sjfv __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 956270346Sjfv __le16 statistic_index; 957270346Sjfv __le16 vebs_used; 958270346Sjfv __le16 vebs_free; 959270346Sjfv u8 reserved[4]; 960266423Sjfv}; 961266423Sjfv 962266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 963266423Sjfv 964266423Sjfv/* Delete Element (direct 0x0243) 965266423Sjfv * uses the generic i40e_aqc_switch_seid 966266423Sjfv */ 967266423Sjfv 968266423Sjfv/* Add MAC-VLAN (indirect 0x0250) */ 969266423Sjfv 970266423Sjfv/* used for the command for most vlan commands */ 971266423Sjfvstruct i40e_aqc_macvlan { 972270346Sjfv __le16 num_addresses; 973270346Sjfv __le16 seid[3]; 974270346Sjfv#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 975270346Sjfv#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 976266423Sjfv I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 977270346Sjfv#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 978270346Sjfv __le32 addr_high; 979270346Sjfv __le32 addr_low; 980266423Sjfv}; 981266423Sjfv 982266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 983266423Sjfv 984266423Sjfv/* indirect data for command and response */ 985266423Sjfvstruct i40e_aqc_add_macvlan_element_data { 986270346Sjfv u8 mac_addr[6]; 987270346Sjfv __le16 vlan_tag; 988270346Sjfv __le16 flags; 989270346Sjfv#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 990270346Sjfv#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 991270346Sjfv#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 992270346Sjfv#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 993299549Serj#define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 994270346Sjfv __le16 queue_number; 995270346Sjfv#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 996270346Sjfv#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 997266423Sjfv I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 998266423Sjfv /* response section */ 999270346Sjfv u8 match_method; 1000270346Sjfv#define I40E_AQC_MM_PERFECT_MATCH 0x01 1001270346Sjfv#define I40E_AQC_MM_HASH_MATCH 0x02 1002270346Sjfv#define I40E_AQC_MM_ERR_NO_RES 0xFF 1003270346Sjfv u8 reserved1[3]; 1004266423Sjfv}; 1005266423Sjfv 1006266423Sjfvstruct i40e_aqc_add_remove_macvlan_completion { 1007266423Sjfv __le16 perfect_mac_used; 1008266423Sjfv __le16 perfect_mac_free; 1009266423Sjfv __le16 unicast_hash_free; 1010266423Sjfv __le16 multicast_hash_free; 1011266423Sjfv __le32 addr_high; 1012266423Sjfv __le32 addr_low; 1013266423Sjfv}; 1014266423Sjfv 1015266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1016266423Sjfv 1017266423Sjfv/* Remove MAC-VLAN (indirect 0x0251) 1018266423Sjfv * uses i40e_aqc_macvlan for the descriptor 1019266423Sjfv * data points to an array of num_addresses of elements 1020266423Sjfv */ 1021266423Sjfv 1022266423Sjfvstruct i40e_aqc_remove_macvlan_element_data { 1023270346Sjfv u8 mac_addr[6]; 1024270346Sjfv __le16 vlan_tag; 1025270346Sjfv u8 flags; 1026270346Sjfv#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1027270346Sjfv#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1028270346Sjfv#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1029270346Sjfv#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1030270346Sjfv u8 reserved[3]; 1031266423Sjfv /* reply section */ 1032270346Sjfv u8 error_code; 1033270346Sjfv#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1034270346Sjfv#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1035270346Sjfv u8 reply_reserved[3]; 1036266423Sjfv}; 1037266423Sjfv 1038266423Sjfv/* Add VLAN (indirect 0x0252) 1039266423Sjfv * Remove VLAN (indirect 0x0253) 1040266423Sjfv * use the generic i40e_aqc_macvlan for the command 1041266423Sjfv */ 1042266423Sjfvstruct i40e_aqc_add_remove_vlan_element_data { 1043270346Sjfv __le16 vlan_tag; 1044270346Sjfv u8 vlan_flags; 1045266423Sjfv/* flags for add VLAN */ 1046270346Sjfv#define I40E_AQC_ADD_VLAN_LOCAL 0x1 1047270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1048270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1049270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1050270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1051270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1052270346Sjfv#define I40E_AQC_VLAN_PTYPE_SHIFT 3 1053270346Sjfv#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1054270346Sjfv#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1055270346Sjfv#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1056270346Sjfv#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1057270346Sjfv#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1058266423Sjfv/* flags for remove VLAN */ 1059270346Sjfv#define I40E_AQC_REMOVE_VLAN_ALL 0x1 1060270346Sjfv u8 reserved; 1061270346Sjfv u8 result; 1062266423Sjfv/* flags for add VLAN */ 1063270346Sjfv#define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1064270346Sjfv#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1065270346Sjfv#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1066266423Sjfv/* flags for remove VLAN */ 1067270346Sjfv#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1068270346Sjfv#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1069270346Sjfv u8 reserved1[3]; 1070266423Sjfv}; 1071266423Sjfv 1072266423Sjfvstruct i40e_aqc_add_remove_vlan_completion { 1073270346Sjfv u8 reserved[4]; 1074270346Sjfv __le16 vlans_used; 1075270346Sjfv __le16 vlans_free; 1076270346Sjfv __le32 addr_high; 1077270346Sjfv __le32 addr_low; 1078266423Sjfv}; 1079266423Sjfv 1080266423Sjfv/* Set VSI Promiscuous Modes (direct 0x0254) */ 1081266423Sjfvstruct i40e_aqc_set_vsi_promiscuous_modes { 1082270346Sjfv __le16 promiscuous_flags; 1083270346Sjfv __le16 valid_flags; 1084266423Sjfv/* flags used for both fields above */ 1085270346Sjfv#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1086270346Sjfv#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1087270346Sjfv#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1088270346Sjfv#define I40E_AQC_SET_VSI_DEFAULT 0x08 1089270346Sjfv#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1090299554Serj#define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 1091270346Sjfv __le16 seid; 1092270346Sjfv#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1093270346Sjfv __le16 vlan_tag; 1094284049Sjfv#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1095270346Sjfv#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1096270346Sjfv u8 reserved[8]; 1097266423Sjfv}; 1098266423Sjfv 1099266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1100266423Sjfv 1101266423Sjfv/* Add S/E-tag command (direct 0x0255) 1102266423Sjfv * Uses generic i40e_aqc_add_remove_tag_completion for completion 1103266423Sjfv */ 1104266423Sjfvstruct i40e_aqc_add_tag { 1105270346Sjfv __le16 flags; 1106270346Sjfv#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1107270346Sjfv __le16 seid; 1108270346Sjfv#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1109270346Sjfv#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1110266423Sjfv I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1111270346Sjfv __le16 tag; 1112270346Sjfv __le16 queue_number; 1113270346Sjfv u8 reserved[8]; 1114266423Sjfv}; 1115266423Sjfv 1116266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1117266423Sjfv 1118266423Sjfvstruct i40e_aqc_add_remove_tag_completion { 1119270346Sjfv u8 reserved[12]; 1120270346Sjfv __le16 tags_used; 1121270346Sjfv __le16 tags_free; 1122266423Sjfv}; 1123266423Sjfv 1124266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1125266423Sjfv 1126266423Sjfv/* Remove S/E-tag command (direct 0x0256) 1127266423Sjfv * Uses generic i40e_aqc_add_remove_tag_completion for completion 1128266423Sjfv */ 1129266423Sjfvstruct i40e_aqc_remove_tag { 1130270346Sjfv __le16 seid; 1131270346Sjfv#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1132270346Sjfv#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1133266423Sjfv I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1134270346Sjfv __le16 tag; 1135270346Sjfv u8 reserved[12]; 1136266423Sjfv}; 1137266423Sjfv 1138277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1139277082Sjfv 1140266423Sjfv/* Add multicast E-Tag (direct 0x0257) 1141266423Sjfv * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1142266423Sjfv * and no external data 1143266423Sjfv */ 1144266423Sjfvstruct i40e_aqc_add_remove_mcast_etag { 1145270346Sjfv __le16 pv_seid; 1146270346Sjfv __le16 etag; 1147270346Sjfv u8 num_unicast_etags; 1148270346Sjfv u8 reserved[3]; 1149270346Sjfv __le32 addr_high; /* address of array of 2-byte s-tags */ 1150270346Sjfv __le32 addr_low; 1151266423Sjfv}; 1152266423Sjfv 1153266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1154266423Sjfv 1155266423Sjfvstruct i40e_aqc_add_remove_mcast_etag_completion { 1156270346Sjfv u8 reserved[4]; 1157270346Sjfv __le16 mcast_etags_used; 1158270346Sjfv __le16 mcast_etags_free; 1159270346Sjfv __le32 addr_high; 1160270346Sjfv __le32 addr_low; 1161266423Sjfv 1162266423Sjfv}; 1163266423Sjfv 1164266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1165266423Sjfv 1166266423Sjfv/* Update S/E-Tag (direct 0x0259) */ 1167266423Sjfvstruct i40e_aqc_update_tag { 1168270346Sjfv __le16 seid; 1169270346Sjfv#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1170270346Sjfv#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1171266423Sjfv I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1172270346Sjfv __le16 old_tag; 1173270346Sjfv __le16 new_tag; 1174270346Sjfv u8 reserved[10]; 1175266423Sjfv}; 1176266423Sjfv 1177266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1178266423Sjfv 1179266423Sjfvstruct i40e_aqc_update_tag_completion { 1180270346Sjfv u8 reserved[12]; 1181270346Sjfv __le16 tags_used; 1182270346Sjfv __le16 tags_free; 1183266423Sjfv}; 1184266423Sjfv 1185266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1186266423Sjfv 1187266423Sjfv/* Add Control Packet filter (direct 0x025A) 1188266423Sjfv * Remove Control Packet filter (direct 0x025B) 1189266423Sjfv * uses the i40e_aqc_add_oveb_cloud, 1190266423Sjfv * and the generic direct completion structure 1191266423Sjfv */ 1192266423Sjfvstruct i40e_aqc_add_remove_control_packet_filter { 1193270346Sjfv u8 mac[6]; 1194270346Sjfv __le16 etype; 1195270346Sjfv __le16 flags; 1196270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1197270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1198270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1199270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1200270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1201270346Sjfv __le16 seid; 1202270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1203270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1204266423Sjfv I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1205270346Sjfv __le16 queue; 1206270346Sjfv u8 reserved[2]; 1207266423Sjfv}; 1208266423Sjfv 1209266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1210266423Sjfv 1211266423Sjfvstruct i40e_aqc_add_remove_control_packet_filter_completion { 1212270346Sjfv __le16 mac_etype_used; 1213270346Sjfv __le16 etype_used; 1214270346Sjfv __le16 mac_etype_free; 1215270346Sjfv __le16 etype_free; 1216270346Sjfv u8 reserved[8]; 1217266423Sjfv}; 1218266423Sjfv 1219266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1220266423Sjfv 1221266423Sjfv/* Add Cloud filters (indirect 0x025C) 1222266423Sjfv * Remove Cloud filters (indirect 0x025D) 1223266423Sjfv * uses the i40e_aqc_add_remove_cloud_filters, 1224266423Sjfv * and the generic indirect completion structure 1225266423Sjfv */ 1226266423Sjfvstruct i40e_aqc_add_remove_cloud_filters { 1227270346Sjfv u8 num_filters; 1228270346Sjfv u8 reserved; 1229270346Sjfv __le16 seid; 1230270346Sjfv#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1231270346Sjfv#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1232266423Sjfv I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1233270346Sjfv u8 reserved2[4]; 1234270346Sjfv __le32 addr_high; 1235270346Sjfv __le32 addr_low; 1236266423Sjfv}; 1237266423Sjfv 1238266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1239266423Sjfv 1240266423Sjfvstruct i40e_aqc_add_remove_cloud_filters_element_data { 1241270346Sjfv u8 outer_mac[6]; 1242270346Sjfv u8 inner_mac[6]; 1243270346Sjfv __le16 inner_vlan; 1244266423Sjfv union { 1245266423Sjfv struct { 1246266423Sjfv u8 reserved[12]; 1247266423Sjfv u8 data[4]; 1248266423Sjfv } v4; 1249266423Sjfv struct { 1250266423Sjfv u8 data[16]; 1251266423Sjfv } v6; 1252266423Sjfv } ipaddr; 1253270346Sjfv __le16 flags; 1254270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1255277082Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1256266423Sjfv I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1257266423Sjfv/* 0x0000 reserved */ 1258270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1259266423Sjfv/* 0x0002 reserved */ 1260270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1261270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1262266423Sjfv/* 0x0005 reserved */ 1263270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1264266423Sjfv/* 0x0007 reserved */ 1265266423Sjfv/* 0x0008 reserved */ 1266270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1267270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1268270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1269270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1270266423Sjfv 1271270346Sjfv#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1272270346Sjfv#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1273270346Sjfv#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1274270346Sjfv#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1275270346Sjfv#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1276266423Sjfv 1277270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1278270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1279299549Serj#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1280270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1281299549Serj#define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1282270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1283299549Serj#define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1284299549Serj#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1285266423Sjfv 1286299549Serj#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1287299549Serj#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1288299549Serj#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1289299549Serj 1290270346Sjfv __le32 tenant_id; 1291270346Sjfv u8 reserved[4]; 1292270346Sjfv __le16 queue_number; 1293270346Sjfv#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1294277082Sjfv#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1295270346Sjfv I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1296270346Sjfv u8 reserved2[14]; 1297266423Sjfv /* response section */ 1298270346Sjfv u8 allocation_result; 1299270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1300270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1301270346Sjfv u8 response_reserved[7]; 1302266423Sjfv}; 1303266423Sjfv 1304266423Sjfvstruct i40e_aqc_remove_cloud_filters_completion { 1305266423Sjfv __le16 perfect_ovlan_used; 1306266423Sjfv __le16 perfect_ovlan_free; 1307266423Sjfv __le16 vlan_used; 1308266423Sjfv __le16 vlan_free; 1309266423Sjfv __le32 addr_high; 1310266423Sjfv __le32 addr_low; 1311266423Sjfv}; 1312266423Sjfv 1313266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1314266423Sjfv 1315266423Sjfv/* Add Mirror Rule (indirect or direct 0x0260) 1316266423Sjfv * Delete Mirror Rule (indirect or direct 0x0261) 1317266423Sjfv * note: some rule types (4,5) do not use an external buffer. 1318266423Sjfv * take care to set the flags correctly. 1319266423Sjfv */ 1320266423Sjfvstruct i40e_aqc_add_delete_mirror_rule { 1321266423Sjfv __le16 seid; 1322266423Sjfv __le16 rule_type; 1323270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1324270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1325266423Sjfv I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1326270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1327270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1328270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1329270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1330270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1331266423Sjfv __le16 num_entries; 1332266423Sjfv __le16 destination; /* VSI for add, rule id for delete */ 1333266423Sjfv __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1334266423Sjfv __le32 addr_low; 1335266423Sjfv}; 1336266423Sjfv 1337266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1338266423Sjfv 1339266423Sjfvstruct i40e_aqc_add_delete_mirror_rule_completion { 1340270346Sjfv u8 reserved[2]; 1341270346Sjfv __le16 rule_id; /* only used on add */ 1342270346Sjfv __le16 mirror_rules_used; 1343270346Sjfv __le16 mirror_rules_free; 1344270346Sjfv __le32 addr_high; 1345270346Sjfv __le32 addr_low; 1346266423Sjfv}; 1347266423Sjfv 1348266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1349266423Sjfv 1350266423Sjfv/* DCB 0x03xx*/ 1351266423Sjfv 1352266423Sjfv/* PFC Ignore (direct 0x0301) 1353266423Sjfv * the command and response use the same descriptor structure 1354266423Sjfv */ 1355266423Sjfvstruct i40e_aqc_pfc_ignore { 1356270346Sjfv u8 tc_bitmap; 1357270346Sjfv u8 command_flags; /* unused on response */ 1358270346Sjfv#define I40E_AQC_PFC_IGNORE_SET 0x80 1359270346Sjfv#define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1360270346Sjfv u8 reserved[14]; 1361266423Sjfv}; 1362266423Sjfv 1363266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1364266423Sjfv 1365266423Sjfv/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1366266423Sjfv * with no parameters 1367266423Sjfv */ 1368266423Sjfv 1369266423Sjfv/* TX scheduler 0x04xx */ 1370266423Sjfv 1371266423Sjfv/* Almost all the indirect commands use 1372266423Sjfv * this generic struct to pass the SEID in param0 1373266423Sjfv */ 1374266423Sjfvstruct i40e_aqc_tx_sched_ind { 1375270346Sjfv __le16 vsi_seid; 1376270346Sjfv u8 reserved[6]; 1377270346Sjfv __le32 addr_high; 1378270346Sjfv __le32 addr_low; 1379266423Sjfv}; 1380266423Sjfv 1381266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1382266423Sjfv 1383266423Sjfv/* Several commands respond with a set of queue set handles */ 1384266423Sjfvstruct i40e_aqc_qs_handles_resp { 1385266423Sjfv __le16 qs_handles[8]; 1386266423Sjfv}; 1387266423Sjfv 1388266423Sjfv/* Configure VSI BW limits (direct 0x0400) */ 1389266423Sjfvstruct i40e_aqc_configure_vsi_bw_limit { 1390270346Sjfv __le16 vsi_seid; 1391270346Sjfv u8 reserved[2]; 1392270346Sjfv __le16 credit; 1393270346Sjfv u8 reserved1[2]; 1394270346Sjfv u8 max_credit; /* 0-3, limit = 2^max */ 1395270346Sjfv u8 reserved2[7]; 1396266423Sjfv}; 1397266423Sjfv 1398266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1399266423Sjfv 1400266423Sjfv/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1401266423Sjfv * responds with i40e_aqc_qs_handles_resp 1402266423Sjfv */ 1403266423Sjfvstruct i40e_aqc_configure_vsi_ets_sla_bw_data { 1404270346Sjfv u8 tc_valid_bits; 1405270346Sjfv u8 reserved[15]; 1406270346Sjfv __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1407266423Sjfv 1408266423Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1409270346Sjfv __le16 tc_bw_max[2]; 1410270346Sjfv u8 reserved1[28]; 1411266423Sjfv}; 1412266423Sjfv 1413277082SjfvI40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1414277082Sjfv 1415266423Sjfv/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1416266423Sjfv * responds with i40e_aqc_qs_handles_resp 1417266423Sjfv */ 1418266423Sjfvstruct i40e_aqc_configure_vsi_tc_bw_data { 1419270346Sjfv u8 tc_valid_bits; 1420270346Sjfv u8 reserved[3]; 1421270346Sjfv u8 tc_bw_credits[8]; 1422270346Sjfv u8 reserved1[4]; 1423270346Sjfv __le16 qs_handles[8]; 1424266423Sjfv}; 1425266423Sjfv 1426277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1427277082Sjfv 1428266423Sjfv/* Query vsi bw configuration (indirect 0x0408) */ 1429266423Sjfvstruct i40e_aqc_query_vsi_bw_config_resp { 1430270346Sjfv u8 tc_valid_bits; 1431270346Sjfv u8 tc_suspended_bits; 1432270346Sjfv u8 reserved[14]; 1433270346Sjfv __le16 qs_handles[8]; 1434270346Sjfv u8 reserved1[4]; 1435270346Sjfv __le16 port_bw_limit; 1436270346Sjfv u8 reserved2[2]; 1437270346Sjfv u8 max_bw; /* 0-3, limit = 2^max */ 1438270346Sjfv u8 reserved3[23]; 1439266423Sjfv}; 1440266423Sjfv 1441277082SjfvI40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1442277082Sjfv 1443266423Sjfv/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1444266423Sjfvstruct i40e_aqc_query_vsi_ets_sla_config_resp { 1445270346Sjfv u8 tc_valid_bits; 1446270346Sjfv u8 reserved[3]; 1447270346Sjfv u8 share_credits[8]; 1448270346Sjfv __le16 credits[8]; 1449266423Sjfv 1450266423Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1451270346Sjfv __le16 tc_bw_max[2]; 1452266423Sjfv}; 1453266423Sjfv 1454277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1455277082Sjfv 1456266423Sjfv/* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1457266423Sjfvstruct i40e_aqc_configure_switching_comp_bw_limit { 1458270346Sjfv __le16 seid; 1459270346Sjfv u8 reserved[2]; 1460270346Sjfv __le16 credit; 1461270346Sjfv u8 reserved1[2]; 1462270346Sjfv u8 max_bw; /* 0-3, limit = 2^max */ 1463270346Sjfv u8 reserved2[7]; 1464266423Sjfv}; 1465266423Sjfv 1466266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1467266423Sjfv 1468266423Sjfv/* Enable Physical Port ETS (indirect 0x0413) 1469266423Sjfv * Modify Physical Port ETS (indirect 0x0414) 1470266423Sjfv * Disable Physical Port ETS (indirect 0x0415) 1471266423Sjfv */ 1472266423Sjfvstruct i40e_aqc_configure_switching_comp_ets_data { 1473270346Sjfv u8 reserved[4]; 1474270346Sjfv u8 tc_valid_bits; 1475270346Sjfv u8 seepage; 1476270346Sjfv#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1477270346Sjfv u8 tc_strict_priority_flags; 1478270346Sjfv u8 reserved1[17]; 1479270346Sjfv u8 tc_bw_share_credits[8]; 1480270346Sjfv u8 reserved2[96]; 1481266423Sjfv}; 1482266423Sjfv 1483277082SjfvI40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1484277082Sjfv 1485266423Sjfv/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1486266423Sjfvstruct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1487270346Sjfv u8 tc_valid_bits; 1488270346Sjfv u8 reserved[15]; 1489270346Sjfv __le16 tc_bw_credit[8]; 1490266423Sjfv 1491266423Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1492270346Sjfv __le16 tc_bw_max[2]; 1493270346Sjfv u8 reserved1[28]; 1494266423Sjfv}; 1495266423Sjfv 1496277082SjfvI40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1497277082Sjfv 1498266423Sjfv/* Configure Switching Component Bandwidth Allocation per Tc 1499266423Sjfv * (indirect 0x0417) 1500266423Sjfv */ 1501266423Sjfvstruct i40e_aqc_configure_switching_comp_bw_config_data { 1502270346Sjfv u8 tc_valid_bits; 1503270346Sjfv u8 reserved[2]; 1504270346Sjfv u8 absolute_credits; /* bool */ 1505270346Sjfv u8 tc_bw_share_credits[8]; 1506270346Sjfv u8 reserved1[20]; 1507266423Sjfv}; 1508266423Sjfv 1509277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1510277082Sjfv 1511266423Sjfv/* Query Switching Component Configuration (indirect 0x0418) */ 1512266423Sjfvstruct i40e_aqc_query_switching_comp_ets_config_resp { 1513270346Sjfv u8 tc_valid_bits; 1514270346Sjfv u8 reserved[35]; 1515270346Sjfv __le16 port_bw_limit; 1516270346Sjfv u8 reserved1[2]; 1517270346Sjfv u8 tc_bw_max; /* 0-3, limit = 2^max */ 1518270346Sjfv u8 reserved2[23]; 1519266423Sjfv}; 1520266423Sjfv 1521277082SjfvI40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1522277082Sjfv 1523266423Sjfv/* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1524266423Sjfvstruct i40e_aqc_query_port_ets_config_resp { 1525270346Sjfv u8 reserved[4]; 1526270346Sjfv u8 tc_valid_bits; 1527270346Sjfv u8 reserved1; 1528270346Sjfv u8 tc_strict_priority_bits; 1529270346Sjfv u8 reserved2; 1530270346Sjfv u8 tc_bw_share_credits[8]; 1531270346Sjfv __le16 tc_bw_limits[8]; 1532266423Sjfv 1533266423Sjfv /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1534270346Sjfv __le16 tc_bw_max[2]; 1535270346Sjfv u8 reserved3[32]; 1536266423Sjfv}; 1537266423Sjfv 1538277082SjfvI40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1539277082Sjfv 1540266423Sjfv/* Query Switching Component Bandwidth Allocation per Traffic Type 1541266423Sjfv * (indirect 0x041A) 1542266423Sjfv */ 1543266423Sjfvstruct i40e_aqc_query_switching_comp_bw_config_resp { 1544270346Sjfv u8 tc_valid_bits; 1545270346Sjfv u8 reserved[2]; 1546270346Sjfv u8 absolute_credits_enable; /* bool */ 1547270346Sjfv u8 tc_bw_share_credits[8]; 1548270346Sjfv __le16 tc_bw_limits[8]; 1549266423Sjfv 1550266423Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1551270346Sjfv __le16 tc_bw_max[2]; 1552266423Sjfv}; 1553266423Sjfv 1554277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1555277082Sjfv 1556266423Sjfv/* Suspend/resume port TX traffic 1557266423Sjfv * (direct 0x041B and 0x041C) uses the generic SEID struct 1558266423Sjfv */ 1559266423Sjfv 1560266423Sjfv/* Configure partition BW 1561266423Sjfv * (indirect 0x041D) 1562266423Sjfv */ 1563266423Sjfvstruct i40e_aqc_configure_partition_bw_data { 1564270346Sjfv __le16 pf_valid_bits; 1565270346Sjfv u8 min_bw[16]; /* guaranteed bandwidth */ 1566270346Sjfv u8 max_bw[16]; /* bandwidth limit */ 1567266423Sjfv}; 1568266423Sjfv 1569277082SjfvI40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1570277082Sjfv 1571266423Sjfv/* Get and set the active HMC resource profile and status. 1572266423Sjfv * (direct 0x0500) and (direct 0x0501) 1573266423Sjfv */ 1574266423Sjfvstruct i40e_aq_get_set_hmc_resource_profile { 1575270346Sjfv u8 pm_profile; 1576270346Sjfv u8 pe_vf_enabled; 1577270346Sjfv u8 reserved[14]; 1578266423Sjfv}; 1579266423Sjfv 1580266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1581266423Sjfv 1582266423Sjfvenum i40e_aq_hmc_profile { 1583266423Sjfv /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1584270346Sjfv I40E_HMC_PROFILE_DEFAULT = 1, 1585270346Sjfv I40E_HMC_PROFILE_FAVOR_VF = 2, 1586270346Sjfv I40E_HMC_PROFILE_EQUAL = 3, 1587266423Sjfv}; 1588266423Sjfv 1589270346Sjfv#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF 1590270346Sjfv#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F 1591266423Sjfv 1592266423Sjfv/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1593266423Sjfv 1594266423Sjfv/* set in param0 for get phy abilities to report qualified modules */ 1595270346Sjfv#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1596270346Sjfv#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1597266423Sjfv 1598266423Sjfvenum i40e_aq_phy_type { 1599266423Sjfv I40E_PHY_TYPE_SGMII = 0x0, 1600266423Sjfv I40E_PHY_TYPE_1000BASE_KX = 0x1, 1601266423Sjfv I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1602266423Sjfv I40E_PHY_TYPE_10GBASE_KR = 0x3, 1603266423Sjfv I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1604266423Sjfv I40E_PHY_TYPE_XAUI = 0x5, 1605266423Sjfv I40E_PHY_TYPE_XFI = 0x6, 1606266423Sjfv I40E_PHY_TYPE_SFI = 0x7, 1607266423Sjfv I40E_PHY_TYPE_XLAUI = 0x8, 1608266423Sjfv I40E_PHY_TYPE_XLPPI = 0x9, 1609266423Sjfv I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1610266423Sjfv I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1611266423Sjfv I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1612266423Sjfv I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1613266423Sjfv I40E_PHY_TYPE_100BASE_TX = 0x11, 1614266423Sjfv I40E_PHY_TYPE_1000BASE_T = 0x12, 1615266423Sjfv I40E_PHY_TYPE_10GBASE_T = 0x13, 1616266423Sjfv I40E_PHY_TYPE_10GBASE_SR = 0x14, 1617266423Sjfv I40E_PHY_TYPE_10GBASE_LR = 0x15, 1618266423Sjfv I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1619266423Sjfv I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1620266423Sjfv I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1621266423Sjfv I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1622266423Sjfv I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1623266423Sjfv I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1624266423Sjfv I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1625266423Sjfv I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1626266423Sjfv I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1627266423Sjfv I40E_PHY_TYPE_MAX 1628266423Sjfv}; 1629266423Sjfv 1630266423Sjfv#define I40E_LINK_SPEED_100MB_SHIFT 0x1 1631266423Sjfv#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1632266423Sjfv#define I40E_LINK_SPEED_10GB_SHIFT 0x3 1633266423Sjfv#define I40E_LINK_SPEED_40GB_SHIFT 0x4 1634266423Sjfv#define I40E_LINK_SPEED_20GB_SHIFT 0x5 1635266423Sjfv 1636266423Sjfvenum i40e_aq_link_speed { 1637266423Sjfv I40E_LINK_SPEED_UNKNOWN = 0, 1638266423Sjfv I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1639266423Sjfv I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1640266423Sjfv I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1641266423Sjfv I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1642266423Sjfv I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) 1643266423Sjfv}; 1644266423Sjfv 1645266423Sjfvstruct i40e_aqc_module_desc { 1646266423Sjfv u8 oui[3]; 1647266423Sjfv u8 reserved1; 1648266423Sjfv u8 part_number[16]; 1649266423Sjfv u8 revision[4]; 1650266423Sjfv u8 reserved2[8]; 1651266423Sjfv}; 1652266423Sjfv 1653277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1654277082Sjfv 1655266423Sjfvstruct i40e_aq_get_phy_abilities_resp { 1656270346Sjfv __le32 phy_type; /* bitmap using the above enum for offsets */ 1657270346Sjfv u8 link_speed; /* bitmap using the above enum bit patterns */ 1658270346Sjfv u8 abilities; 1659270346Sjfv#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1660270346Sjfv#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1661270346Sjfv#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1662270346Sjfv#define I40E_AQ_PHY_LINK_ENABLED 0x08 1663270346Sjfv#define I40E_AQ_PHY_AN_ENABLED 0x10 1664270346Sjfv#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1665270346Sjfv __le16 eee_capability; 1666270346Sjfv#define I40E_AQ_EEE_100BASE_TX 0x0002 1667270346Sjfv#define I40E_AQ_EEE_1000BASE_T 0x0004 1668270346Sjfv#define I40E_AQ_EEE_10GBASE_T 0x0008 1669270346Sjfv#define I40E_AQ_EEE_1000BASE_KX 0x0010 1670270346Sjfv#define I40E_AQ_EEE_10GBASE_KX4 0x0020 1671270346Sjfv#define I40E_AQ_EEE_10GBASE_KR 0x0040 1672270346Sjfv __le32 eeer_val; 1673270346Sjfv u8 d3_lpan; 1674270346Sjfv#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1675270346Sjfv u8 reserved[3]; 1676270346Sjfv u8 phy_id[4]; 1677270346Sjfv u8 module_type[3]; 1678270346Sjfv u8 qualified_module_count; 1679270346Sjfv#define I40E_AQ_PHY_MAX_QMS 16 1680270346Sjfv struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1681266423Sjfv}; 1682266423Sjfv 1683277082SjfvI40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1684277082Sjfv 1685266423Sjfv/* Set PHY Config (direct 0x0601) */ 1686266423Sjfvstruct i40e_aq_set_phy_config { /* same bits as above in all */ 1687270346Sjfv __le32 phy_type; 1688270346Sjfv u8 link_speed; 1689270346Sjfv u8 abilities; 1690266423Sjfv/* bits 0-2 use the values from get_phy_abilities_resp */ 1691266423Sjfv#define I40E_AQ_PHY_ENABLE_LINK 0x08 1692266423Sjfv#define I40E_AQ_PHY_ENABLE_AN 0x10 1693266423Sjfv#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1694270346Sjfv __le16 eee_capability; 1695270346Sjfv __le32 eeer; 1696270346Sjfv u8 low_power_ctrl; 1697270346Sjfv u8 reserved[3]; 1698266423Sjfv}; 1699266423Sjfv 1700266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1701266423Sjfv 1702266423Sjfv/* Set MAC Config command data structure (direct 0x0603) */ 1703266423Sjfvstruct i40e_aq_set_mac_config { 1704270346Sjfv __le16 max_frame_size; 1705270346Sjfv u8 params; 1706270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1707270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1708270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1709270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1710270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1711270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1712270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1713270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1714270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1715270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1716270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1717270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1718270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1719270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1720270346Sjfv u8 tx_timer_priority; /* bitmap */ 1721270346Sjfv __le16 tx_timer_value; 1722270346Sjfv __le16 fc_refresh_threshold; 1723270346Sjfv u8 reserved[8]; 1724266423Sjfv}; 1725266423Sjfv 1726266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1727266423Sjfv 1728266423Sjfv/* Restart Auto-Negotiation (direct 0x605) */ 1729266423Sjfvstruct i40e_aqc_set_link_restart_an { 1730270346Sjfv u8 command; 1731270346Sjfv#define I40E_AQ_PHY_RESTART_AN 0x02 1732270346Sjfv#define I40E_AQ_PHY_LINK_ENABLE 0x04 1733270346Sjfv u8 reserved[15]; 1734266423Sjfv}; 1735266423Sjfv 1736266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1737266423Sjfv 1738266423Sjfv/* Get Link Status cmd & response data structure (direct 0x0607) */ 1739266423Sjfvstruct i40e_aqc_get_link_status { 1740270346Sjfv __le16 command_flags; /* only field set on command */ 1741270346Sjfv#define I40E_AQ_LSE_MASK 0x3 1742270346Sjfv#define I40E_AQ_LSE_NOP 0x0 1743270346Sjfv#define I40E_AQ_LSE_DISABLE 0x2 1744270346Sjfv#define I40E_AQ_LSE_ENABLE 0x3 1745266423Sjfv/* only response uses this flag */ 1746270346Sjfv#define I40E_AQ_LSE_IS_ENABLED 0x1 1747270346Sjfv u8 phy_type; /* i40e_aq_phy_type */ 1748270346Sjfv u8 link_speed; /* i40e_aq_link_speed */ 1749270346Sjfv u8 link_info; 1750284049Sjfv#define I40E_AQ_LINK_UP 0x01 /* obsolete */ 1751284049Sjfv#define I40E_AQ_LINK_UP_FUNCTION 0x01 1752270346Sjfv#define I40E_AQ_LINK_FAULT 0x02 1753270346Sjfv#define I40E_AQ_LINK_FAULT_TX 0x04 1754270346Sjfv#define I40E_AQ_LINK_FAULT_RX 0x08 1755270346Sjfv#define I40E_AQ_LINK_FAULT_REMOTE 0x10 1756284049Sjfv#define I40E_AQ_LINK_UP_PORT 0x20 1757270346Sjfv#define I40E_AQ_MEDIA_AVAILABLE 0x40 1758270346Sjfv#define I40E_AQ_SIGNAL_DETECT 0x80 1759270346Sjfv u8 an_info; 1760270346Sjfv#define I40E_AQ_AN_COMPLETED 0x01 1761270346Sjfv#define I40E_AQ_LP_AN_ABILITY 0x02 1762270346Sjfv#define I40E_AQ_PD_FAULT 0x04 1763270346Sjfv#define I40E_AQ_FEC_EN 0x08 1764270346Sjfv#define I40E_AQ_PHY_LOW_POWER 0x10 1765270346Sjfv#define I40E_AQ_LINK_PAUSE_TX 0x20 1766270346Sjfv#define I40E_AQ_LINK_PAUSE_RX 0x40 1767270346Sjfv#define I40E_AQ_QUALIFIED_MODULE 0x80 1768270346Sjfv u8 ext_info; 1769270346Sjfv#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1770270346Sjfv#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1771270346Sjfv#define I40E_AQ_LINK_TX_SHIFT 0x02 1772270346Sjfv#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1773270346Sjfv#define I40E_AQ_LINK_TX_ACTIVE 0x00 1774270346Sjfv#define I40E_AQ_LINK_TX_DRAINED 0x01 1775270346Sjfv#define I40E_AQ_LINK_TX_FLUSHED 0x03 1776270346Sjfv#define I40E_AQ_LINK_FORCED_40G 0x10 1777270346Sjfv u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1778270346Sjfv __le16 max_frame_size; 1779270346Sjfv u8 config; 1780270346Sjfv#define I40E_AQ_CONFIG_CRC_ENA 0x04 1781270346Sjfv#define I40E_AQ_CONFIG_PACING_MASK 0x78 1782299549Serj u8 external_power_ability; 1783299549Serj#define I40E_AQ_LINK_POWER_CLASS_1 0x00 1784299549Serj#define I40E_AQ_LINK_POWER_CLASS_2 0x01 1785299549Serj#define I40E_AQ_LINK_POWER_CLASS_3 0x02 1786299549Serj#define I40E_AQ_LINK_POWER_CLASS_4 0x03 1787299549Serj u8 reserved[4]; 1788266423Sjfv}; 1789266423Sjfv 1790266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1791266423Sjfv 1792266423Sjfv/* Set event mask command (direct 0x613) */ 1793266423Sjfvstruct i40e_aqc_set_phy_int_mask { 1794270346Sjfv u8 reserved[8]; 1795270346Sjfv __le16 event_mask; 1796270346Sjfv#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1797270346Sjfv#define I40E_AQ_EVENT_MEDIA_NA 0x0004 1798270346Sjfv#define I40E_AQ_EVENT_LINK_FAULT 0x0008 1799270346Sjfv#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1800270346Sjfv#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1801270346Sjfv#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1802270346Sjfv#define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1803270346Sjfv#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1804270346Sjfv#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1805270346Sjfv u8 reserved1[6]; 1806266423Sjfv}; 1807266423Sjfv 1808266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1809266423Sjfv 1810266423Sjfv/* Get Local AN advt register (direct 0x0614) 1811266423Sjfv * Set Local AN advt register (direct 0x0615) 1812266423Sjfv * Get Link Partner AN advt register (direct 0x0616) 1813266423Sjfv */ 1814266423Sjfvstruct i40e_aqc_an_advt_reg { 1815270346Sjfv __le32 local_an_reg0; 1816270346Sjfv __le16 local_an_reg1; 1817270346Sjfv u8 reserved[10]; 1818266423Sjfv}; 1819266423Sjfv 1820266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1821266423Sjfv 1822266423Sjfv/* Set Loopback mode (0x0618) */ 1823266423Sjfvstruct i40e_aqc_set_lb_mode { 1824270346Sjfv __le16 lb_mode; 1825270346Sjfv#define I40E_AQ_LB_PHY_LOCAL 0x01 1826270346Sjfv#define I40E_AQ_LB_PHY_REMOTE 0x02 1827270346Sjfv#define I40E_AQ_LB_MAC_LOCAL 0x04 1828270346Sjfv u8 reserved[14]; 1829266423Sjfv}; 1830266423Sjfv 1831266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1832266423Sjfv 1833266423Sjfv/* Set PHY Debug command (0x0622) */ 1834266423Sjfvstruct i40e_aqc_set_phy_debug { 1835270346Sjfv u8 command_flags; 1836266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1837266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1838270346Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1839270346Sjfv I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1840266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1841266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1842266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1843266423Sjfv#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1844270346Sjfv u8 reserved[15]; 1845266423Sjfv}; 1846266423Sjfv 1847266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1848266423Sjfv 1849266423Sjfvenum i40e_aq_phy_reg_type { 1850270346Sjfv I40E_AQC_PHY_REG_INTERNAL = 0x1, 1851270346Sjfv I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1852270346Sjfv I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1853266423Sjfv}; 1854266423Sjfv 1855299549Serj/* Run PHY Activity (0x0626) */ 1856299549Serjstruct i40e_aqc_run_phy_activity { 1857299549Serj __le16 activity_id; 1858299549Serj u8 flags; 1859299549Serj u8 reserved1; 1860299549Serj __le32 control; 1861299549Serj __le32 data; 1862299549Serj u8 reserved2[4]; 1863299549Serj}; 1864299549Serj 1865299549SerjI40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 1866299549Serj 1867266423Sjfv/* NVM Read command (indirect 0x0701) 1868266423Sjfv * NVM Erase commands (direct 0x0702) 1869266423Sjfv * NVM Update commands (indirect 0x0703) 1870266423Sjfv */ 1871266423Sjfvstruct i40e_aqc_nvm_update { 1872270346Sjfv u8 command_flags; 1873270346Sjfv#define I40E_AQ_NVM_LAST_CMD 0x01 1874270346Sjfv#define I40E_AQ_NVM_FLASH_ONLY 0x80 1875270346Sjfv u8 module_pointer; 1876270346Sjfv __le16 length; 1877270346Sjfv __le32 offset; 1878270346Sjfv __le32 addr_high; 1879270346Sjfv __le32 addr_low; 1880266423Sjfv}; 1881266423Sjfv 1882266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 1883266423Sjfv 1884266423Sjfv/* NVM Config Read (indirect 0x0704) */ 1885266423Sjfvstruct i40e_aqc_nvm_config_read { 1886270346Sjfv __le16 cmd_flags; 1887277082Sjfv#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 1888277082Sjfv#define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 1889277082Sjfv#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 1890270346Sjfv __le16 element_count; 1891277082Sjfv __le16 element_id; /* Feature/field ID */ 1892277082Sjfv __le16 element_id_msw; /* MSWord of field ID */ 1893270346Sjfv __le32 address_high; 1894270346Sjfv __le32 address_low; 1895266423Sjfv}; 1896266423Sjfv 1897266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 1898266423Sjfv 1899266423Sjfv/* NVM Config Write (indirect 0x0705) */ 1900266423Sjfvstruct i40e_aqc_nvm_config_write { 1901270346Sjfv __le16 cmd_flags; 1902270346Sjfv __le16 element_count; 1903270346Sjfv u8 reserved[4]; 1904270346Sjfv __le32 address_high; 1905270346Sjfv __le32 address_low; 1906266423Sjfv}; 1907266423Sjfv 1908266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 1909266423Sjfv 1910277082Sjfv/* Used for 0x0704 as well as for 0x0705 commands */ 1911277082Sjfv#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 1912277082Sjfv#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 1913277082Sjfv#define I40E_AQ_ANVM_FEATURE 0 1914277082Sjfv#define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 1915266423Sjfvstruct i40e_aqc_nvm_config_data_feature { 1916266423Sjfv __le16 feature_id; 1917277082Sjfv#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 1918277082Sjfv#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 1919277082Sjfv#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 1920266423Sjfv __le16 feature_options; 1921266423Sjfv __le16 feature_selection; 1922266423Sjfv}; 1923266423Sjfv 1924277082SjfvI40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 1925277082Sjfv 1926266423Sjfvstruct i40e_aqc_nvm_config_data_immediate_field { 1927277082Sjfv __le32 field_id; 1928277082Sjfv __le32 field_value; 1929266423Sjfv __le16 field_options; 1930277082Sjfv __le16 reserved; 1931266423Sjfv}; 1932266423Sjfv 1933277082SjfvI40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 1934277082Sjfv 1935284049Sjfv/* OEM Post Update (indirect 0x0720) 1936284049Sjfv * no command data struct used 1937284049Sjfv */ 1938284049Sjfv struct i40e_aqc_nvm_oem_post_update { 1939284049Sjfv#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 1940284049Sjfv u8 sel_data; 1941284049Sjfv u8 reserved[7]; 1942284049Sjfv}; 1943284049Sjfv 1944284049SjfvI40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 1945284049Sjfv 1946284049Sjfvstruct i40e_aqc_nvm_oem_post_update_buffer { 1947284049Sjfv u8 str_len; 1948284049Sjfv u8 dev_addr; 1949284049Sjfv __le16 eeprom_addr; 1950284049Sjfv u8 data[36]; 1951284049Sjfv}; 1952284049Sjfv 1953284049SjfvI40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 1954284049Sjfv 1955299549Serj/* Thermal Sensor (indirect 0x0721) 1956299549Serj * read or set thermal sensor configs and values 1957299549Serj * takes a sensor and command specific data buffer, not detailed here 1958299549Serj */ 1959299549Serjstruct i40e_aqc_thermal_sensor { 1960299549Serj u8 sensor_action; 1961299549Serj#define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 1962299549Serj#define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 1963299549Serj#define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 1964299549Serj u8 reserved[7]; 1965299549Serj __le32 addr_high; 1966299549Serj __le32 addr_low; 1967299549Serj}; 1968299549Serj 1969299549SerjI40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 1970299549Serj 1971266423Sjfv/* Send to PF command (indirect 0x0801) id is only used by PF 1972266423Sjfv * Send to VF command (indirect 0x0802) id is only used by PF 1973266423Sjfv * Send to Peer PF command (indirect 0x0803) 1974266423Sjfv */ 1975266423Sjfvstruct i40e_aqc_pf_vf_message { 1976270346Sjfv __le32 id; 1977270346Sjfv u8 reserved[4]; 1978270346Sjfv __le32 addr_high; 1979270346Sjfv __le32 addr_low; 1980266423Sjfv}; 1981266423Sjfv 1982266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 1983266423Sjfv 1984266423Sjfv/* Alternate structure */ 1985266423Sjfv 1986266423Sjfv/* Direct write (direct 0x0900) 1987266423Sjfv * Direct read (direct 0x0902) 1988266423Sjfv */ 1989266423Sjfvstruct i40e_aqc_alternate_write { 1990266423Sjfv __le32 address0; 1991266423Sjfv __le32 data0; 1992266423Sjfv __le32 address1; 1993266423Sjfv __le32 data1; 1994266423Sjfv}; 1995266423Sjfv 1996266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 1997266423Sjfv 1998266423Sjfv/* Indirect write (indirect 0x0901) 1999266423Sjfv * Indirect read (indirect 0x0903) 2000266423Sjfv */ 2001266423Sjfv 2002266423Sjfvstruct i40e_aqc_alternate_ind_write { 2003266423Sjfv __le32 address; 2004266423Sjfv __le32 length; 2005266423Sjfv __le32 addr_high; 2006266423Sjfv __le32 addr_low; 2007266423Sjfv}; 2008266423Sjfv 2009266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 2010266423Sjfv 2011266423Sjfv/* Done alternate write (direct 0x0904) 2012266423Sjfv * uses i40e_aq_desc 2013266423Sjfv */ 2014266423Sjfvstruct i40e_aqc_alternate_write_done { 2015270346Sjfv __le16 cmd_flags; 2016266423Sjfv#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 2017266423Sjfv#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 2018266423Sjfv#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 2019266423Sjfv#define I40E_AQ_ALTERNATE_RESET_NEEDED 2 2020270346Sjfv u8 reserved[14]; 2021266423Sjfv}; 2022266423Sjfv 2023266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2024266423Sjfv 2025266423Sjfv/* Set OEM mode (direct 0x0905) */ 2026266423Sjfvstruct i40e_aqc_alternate_set_mode { 2027270346Sjfv __le32 mode; 2028266423Sjfv#define I40E_AQ_ALTERNATE_MODE_NONE 0 2029266423Sjfv#define I40E_AQ_ALTERNATE_MODE_OEM 1 2030270346Sjfv u8 reserved[12]; 2031266423Sjfv}; 2032266423Sjfv 2033266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2034266423Sjfv 2035266423Sjfv/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2036266423Sjfv 2037266423Sjfv/* async events 0x10xx */ 2038266423Sjfv 2039266423Sjfv/* Lan Queue Overflow Event (direct, 0x1001) */ 2040266423Sjfvstruct i40e_aqc_lan_overflow { 2041270346Sjfv __le32 prtdcb_rupto; 2042270346Sjfv __le32 otx_ctl; 2043270346Sjfv u8 reserved[8]; 2044266423Sjfv}; 2045266423Sjfv 2046266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2047266423Sjfv 2048266423Sjfv/* Get LLDP MIB (indirect 0x0A00) */ 2049266423Sjfvstruct i40e_aqc_lldp_get_mib { 2050270346Sjfv u8 type; 2051270346Sjfv u8 reserved1; 2052270346Sjfv#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2053270346Sjfv#define I40E_AQ_LLDP_MIB_LOCAL 0x0 2054270346Sjfv#define I40E_AQ_LLDP_MIB_REMOTE 0x1 2055270346Sjfv#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2056270346Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2057270346Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2058270346Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2059270346Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2060270346Sjfv#define I40E_AQ_LLDP_TX_SHIFT 0x4 2061270346Sjfv#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2062266423Sjfv/* TX pause flags use I40E_AQ_LINK_TX_* above */ 2063270346Sjfv __le16 local_len; 2064270346Sjfv __le16 remote_len; 2065270346Sjfv u8 reserved2[2]; 2066270346Sjfv __le32 addr_high; 2067270346Sjfv __le32 addr_low; 2068266423Sjfv}; 2069266423Sjfv 2070266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2071266423Sjfv 2072266423Sjfv/* Configure LLDP MIB Change Event (direct 0x0A01) 2073266423Sjfv * also used for the event (with type in the command field) 2074266423Sjfv */ 2075266423Sjfvstruct i40e_aqc_lldp_update_mib { 2076270346Sjfv u8 command; 2077270346Sjfv#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2078270346Sjfv#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2079270346Sjfv u8 reserved[7]; 2080270346Sjfv __le32 addr_high; 2081270346Sjfv __le32 addr_low; 2082266423Sjfv}; 2083266423Sjfv 2084266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2085266423Sjfv 2086266423Sjfv/* Add LLDP TLV (indirect 0x0A02) 2087266423Sjfv * Delete LLDP TLV (indirect 0x0A04) 2088266423Sjfv */ 2089266423Sjfvstruct i40e_aqc_lldp_add_tlv { 2090270346Sjfv u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2091270346Sjfv u8 reserved1[1]; 2092270346Sjfv __le16 len; 2093270346Sjfv u8 reserved2[4]; 2094270346Sjfv __le32 addr_high; 2095270346Sjfv __le32 addr_low; 2096266423Sjfv}; 2097266423Sjfv 2098266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2099266423Sjfv 2100266423Sjfv/* Update LLDP TLV (indirect 0x0A03) */ 2101266423Sjfvstruct i40e_aqc_lldp_update_tlv { 2102270346Sjfv u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2103270346Sjfv u8 reserved; 2104270346Sjfv __le16 old_len; 2105270346Sjfv __le16 new_offset; 2106270346Sjfv __le16 new_len; 2107270346Sjfv __le32 addr_high; 2108270346Sjfv __le32 addr_low; 2109266423Sjfv}; 2110266423Sjfv 2111266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2112266423Sjfv 2113266423Sjfv/* Stop LLDP (direct 0x0A05) */ 2114266423Sjfvstruct i40e_aqc_lldp_stop { 2115270346Sjfv u8 command; 2116270346Sjfv#define I40E_AQ_LLDP_AGENT_STOP 0x0 2117270346Sjfv#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2118270346Sjfv u8 reserved[15]; 2119266423Sjfv}; 2120266423Sjfv 2121266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2122266423Sjfv 2123266423Sjfv/* Start LLDP (direct 0x0A06) */ 2124266423Sjfv 2125266423Sjfvstruct i40e_aqc_lldp_start { 2126270346Sjfv u8 command; 2127270346Sjfv#define I40E_AQ_LLDP_AGENT_START 0x1 2128270346Sjfv u8 reserved[15]; 2129266423Sjfv}; 2130266423Sjfv 2131266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2132266423Sjfv 2133277082Sjfv/* Get CEE DCBX Oper Config (0x0A07) 2134277082Sjfv * uses the generic descriptor struct 2135277082Sjfv * returns below as indirect response 2136266423Sjfv */ 2137266423Sjfv 2138277082Sjfv#define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2139277082Sjfv#define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2140277082Sjfv#define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2141277082Sjfv#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2142277082Sjfv#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2143277082Sjfv#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2144284049Sjfv 2145277082Sjfv#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2146277082Sjfv#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2147277082Sjfv#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2148277082Sjfv#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2149277082Sjfv#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2150277082Sjfv#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2151284049Sjfv#define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2152284049Sjfv#define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2153284049Sjfv#define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2154284049Sjfv#define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2155284049Sjfv#define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2156284049Sjfv#define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2157284049Sjfv 2158284049Sjfv/* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2159284049Sjfv * word boundary layout issues, which the Linux compilers silently deal 2160284049Sjfv * with by adding padding, making the actual struct larger than designed. 2161284049Sjfv * However, the FW compiler for the NIC is less lenient and complains 2162284049Sjfv * about the struct. Hence, the struct defined here has an extra byte in 2163284049Sjfv * fields reserved3 and reserved4 to directly acknowledge that padding, 2164284049Sjfv * and the new length is used in the length check macro. 2165284049Sjfv */ 2166277082Sjfvstruct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2167277082Sjfv u8 reserved1; 2168277082Sjfv u8 oper_num_tc; 2169277082Sjfv u8 oper_prio_tc[4]; 2170277082Sjfv u8 reserved2; 2171277082Sjfv u8 oper_tc_bw[8]; 2172277082Sjfv u8 oper_pfc_en; 2173284049Sjfv u8 reserved3[2]; 2174277082Sjfv __le16 oper_app_prio; 2175284049Sjfv u8 reserved4[2]; 2176277082Sjfv __le16 tlv_status; 2177277082Sjfv}; 2178277082Sjfv 2179277082SjfvI40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2180277082Sjfv 2181277082Sjfvstruct i40e_aqc_get_cee_dcb_cfg_resp { 2182277082Sjfv u8 oper_num_tc; 2183277082Sjfv u8 oper_prio_tc[4]; 2184277082Sjfv u8 oper_tc_bw[8]; 2185277082Sjfv u8 oper_pfc_en; 2186277082Sjfv __le16 oper_app_prio; 2187277082Sjfv __le32 tlv_status; 2188277082Sjfv u8 reserved[12]; 2189277082Sjfv}; 2190277082Sjfv 2191277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2192277082Sjfv 2193277082Sjfv/* Set Local LLDP MIB (indirect 0x0A08) 2194277082Sjfv * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2195277082Sjfv */ 2196277082Sjfvstruct i40e_aqc_lldp_set_local_mib { 2197277082Sjfv#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2198299545Serj#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \ 2199299545Serj SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2200299545Serj#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2201299545Serj#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2202299545Serj#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \ 2203299545Serj SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2204299545Serj#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2205277082Sjfv u8 type; 2206277082Sjfv u8 reserved0; 2207277082Sjfv __le16 length; 2208277082Sjfv u8 reserved1[4]; 2209277082Sjfv __le32 address_high; 2210277082Sjfv __le32 address_low; 2211277082Sjfv}; 2212277082Sjfv 2213277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2214277082Sjfv 2215299547Serjstruct i40e_aqc_lldp_set_local_mib_resp { 2216299547Serj#define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01 2217299547Serj u8 status; 2218299547Serj u8 reserved[15]; 2219299547Serj}; 2220299547Serj 2221299547SerjI40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp); 2222299547Serj 2223277082Sjfv/* Stop/Start LLDP Agent (direct 0x0A09) 2224277082Sjfv * Used for stopping/starting specific LLDP agent. e.g. DCBx 2225277082Sjfv */ 2226277082Sjfvstruct i40e_aqc_lldp_stop_start_specific_agent { 2227277082Sjfv#define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2228277082Sjfv#define I40E_AQC_START_SPECIFIC_AGENT_MASK (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2229277082Sjfv u8 command; 2230277082Sjfv u8 reserved[15]; 2231277082Sjfv}; 2232277082Sjfv 2233277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2234277082Sjfv 2235266423Sjfv/* Add Udp Tunnel command and completion (direct 0x0B00) */ 2236266423Sjfvstruct i40e_aqc_add_udp_tunnel { 2237270346Sjfv __le16 udp_port; 2238270346Sjfv u8 reserved0[3]; 2239270346Sjfv u8 protocol_type; 2240266423Sjfv#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2241266423Sjfv#define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2242266423Sjfv#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2243299549Serj#define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2244270346Sjfv u8 reserved1[10]; 2245266423Sjfv}; 2246266423Sjfv 2247266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2248266423Sjfv 2249266423Sjfvstruct i40e_aqc_add_udp_tunnel_completion { 2250266423Sjfv __le16 udp_port; 2251266423Sjfv u8 filter_entry_index; 2252266423Sjfv u8 multiple_pfs; 2253270346Sjfv#define I40E_AQC_SINGLE_PF 0x0 2254270346Sjfv#define I40E_AQC_MULTIPLE_PFS 0x1 2255266423Sjfv u8 total_filters; 2256266423Sjfv u8 reserved[11]; 2257266423Sjfv}; 2258266423Sjfv 2259266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2260266423Sjfv 2261266423Sjfv/* remove UDP Tunnel command (0x0B01) */ 2262266423Sjfvstruct i40e_aqc_remove_udp_tunnel { 2263270346Sjfv u8 reserved[2]; 2264270346Sjfv u8 index; /* 0 to 15 */ 2265270346Sjfv u8 reserved2[13]; 2266266423Sjfv}; 2267266423Sjfv 2268266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2269266423Sjfv 2270266423Sjfvstruct i40e_aqc_del_udp_tunnel_completion { 2271270346Sjfv __le16 udp_port; 2272270346Sjfv u8 index; /* 0 to 15 */ 2273270346Sjfv u8 multiple_pfs; 2274270346Sjfv u8 total_filters_used; 2275270346Sjfv u8 reserved1[11]; 2276266423Sjfv}; 2277266423Sjfv 2278266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2279266423Sjfv 2280266423Sjfv/* tunnel key structure 0x0B10 */ 2281266423Sjfv 2282266423Sjfvstruct i40e_aqc_tunnel_key_structure { 2283266423Sjfv u8 key1_off; 2284266423Sjfv u8 key2_off; 2285266423Sjfv u8 key1_len; /* 0 to 15 */ 2286266423Sjfv u8 key2_len; /* 0 to 15 */ 2287266423Sjfv u8 flags; 2288270346Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2289266423Sjfv/* response flags */ 2290270346Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2291270346Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2292270346Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2293266423Sjfv u8 network_key_index; 2294266423Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2295266423Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2296266423Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2297266423Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2298266423Sjfv u8 reserved[10]; 2299266423Sjfv}; 2300266423Sjfv 2301266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2302266423Sjfv 2303266423Sjfv/* OEM mode commands (direct 0xFE0x) */ 2304266423Sjfvstruct i40e_aqc_oem_param_change { 2305270346Sjfv __le32 param_type; 2306270346Sjfv#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2307270346Sjfv#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2308270346Sjfv#define I40E_AQ_OEM_PARAM_MAC 2 2309270346Sjfv __le32 param_value1; 2310277082Sjfv __le16 param_value2; 2311277082Sjfv u8 reserved[6]; 2312266423Sjfv}; 2313266423Sjfv 2314266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2315266423Sjfv 2316266423Sjfvstruct i40e_aqc_oem_state_change { 2317270346Sjfv __le32 state; 2318270346Sjfv#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2319270346Sjfv#define I40E_AQ_OEM_STATE_LINK_UP 0x1 2320270346Sjfv u8 reserved[12]; 2321266423Sjfv}; 2322266423Sjfv 2323266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2324266423Sjfv 2325277082Sjfv/* Initialize OCSD (0xFE02, direct) */ 2326277082Sjfvstruct i40e_aqc_opc_oem_ocsd_initialize { 2327277082Sjfv u8 type_status; 2328277082Sjfv u8 reserved1[3]; 2329277082Sjfv __le32 ocsd_memory_block_addr_high; 2330277082Sjfv __le32 ocsd_memory_block_addr_low; 2331277082Sjfv __le32 requested_update_interval; 2332277082Sjfv}; 2333277082Sjfv 2334277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2335277082Sjfv 2336277082Sjfv/* Initialize OCBB (0xFE03, direct) */ 2337277082Sjfvstruct i40e_aqc_opc_oem_ocbb_initialize { 2338277082Sjfv u8 type_status; 2339277082Sjfv u8 reserved1[3]; 2340277082Sjfv __le32 ocbb_memory_block_addr_high; 2341277082Sjfv __le32 ocbb_memory_block_addr_low; 2342277082Sjfv u8 reserved2[4]; 2343277082Sjfv}; 2344277082Sjfv 2345277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2346277082Sjfv 2347266423Sjfv/* debug commands */ 2348266423Sjfv 2349266423Sjfv/* get device id (0xFF00) uses the generic structure */ 2350266423Sjfv 2351266423Sjfv/* set test more (0xFF01, internal) */ 2352266423Sjfv 2353266423Sjfvstruct i40e_acq_set_test_mode { 2354270346Sjfv u8 mode; 2355270346Sjfv#define I40E_AQ_TEST_PARTIAL 0 2356270346Sjfv#define I40E_AQ_TEST_FULL 1 2357270346Sjfv#define I40E_AQ_TEST_NVM 2 2358270346Sjfv u8 reserved[3]; 2359270346Sjfv u8 command; 2360270346Sjfv#define I40E_AQ_TEST_OPEN 0 2361270346Sjfv#define I40E_AQ_TEST_CLOSE 1 2362270346Sjfv#define I40E_AQ_TEST_INC 2 2363270346Sjfv u8 reserved2[3]; 2364270346Sjfv __le32 address_high; 2365270346Sjfv __le32 address_low; 2366266423Sjfv}; 2367266423Sjfv 2368266423SjfvI40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2369266423Sjfv 2370266423Sjfv/* Debug Read Register command (0xFF03) 2371266423Sjfv * Debug Write Register command (0xFF04) 2372266423Sjfv */ 2373266423Sjfvstruct i40e_aqc_debug_reg_read_write { 2374266423Sjfv __le32 reserved; 2375266423Sjfv __le32 address; 2376266423Sjfv __le32 value_high; 2377266423Sjfv __le32 value_low; 2378266423Sjfv}; 2379266423Sjfv 2380266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2381266423Sjfv 2382266423Sjfv/* Scatter/gather Reg Read (indirect 0xFF05) 2383266423Sjfv * Scatter/gather Reg Write (indirect 0xFF06) 2384266423Sjfv */ 2385266423Sjfv 2386266423Sjfv/* i40e_aq_desc is used for the command */ 2387266423Sjfvstruct i40e_aqc_debug_reg_sg_element_data { 2388266423Sjfv __le32 address; 2389266423Sjfv __le32 value; 2390266423Sjfv}; 2391266423Sjfv 2392266423Sjfv/* Debug Modify register (direct 0xFF07) */ 2393266423Sjfvstruct i40e_aqc_debug_modify_reg { 2394266423Sjfv __le32 address; 2395266423Sjfv __le32 value; 2396266423Sjfv __le32 clear_mask; 2397266423Sjfv __le32 set_mask; 2398266423Sjfv}; 2399266423Sjfv 2400266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2401266423Sjfv 2402266423Sjfv/* dump internal data (0xFF08, indirect) */ 2403266423Sjfv 2404266423Sjfv#define I40E_AQ_CLUSTER_ID_AUX 0 2405266423Sjfv#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2406266423Sjfv#define I40E_AQ_CLUSTER_ID_TXSCHED 2 2407266423Sjfv#define I40E_AQ_CLUSTER_ID_HMC 3 2408266423Sjfv#define I40E_AQ_CLUSTER_ID_MAC0 4 2409266423Sjfv#define I40E_AQ_CLUSTER_ID_MAC1 5 2410266423Sjfv#define I40E_AQ_CLUSTER_ID_MAC2 6 2411266423Sjfv#define I40E_AQ_CLUSTER_ID_MAC3 7 2412266423Sjfv#define I40E_AQ_CLUSTER_ID_DCB 8 2413266423Sjfv#define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2414266423Sjfv#define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2415266423Sjfv#define I40E_AQ_CLUSTER_ID_ALTRAM 11 2416266423Sjfv 2417266423Sjfvstruct i40e_aqc_debug_dump_internals { 2418270346Sjfv u8 cluster_id; 2419270346Sjfv u8 table_id; 2420270346Sjfv __le16 data_size; 2421270346Sjfv __le32 idx; 2422270346Sjfv __le32 address_high; 2423270346Sjfv __le32 address_low; 2424266423Sjfv}; 2425266423Sjfv 2426266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2427266423Sjfv 2428266423Sjfvstruct i40e_aqc_debug_modify_internals { 2429270346Sjfv u8 cluster_id; 2430270346Sjfv u8 cluster_specific_params[7]; 2431270346Sjfv __le32 address_high; 2432270346Sjfv __le32 address_low; 2433266423Sjfv}; 2434266423Sjfv 2435266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2436266423Sjfv 2437299547Serj#endif /* _I40E_ADMINQ_CMD_H_ */ 2438