i40e_adminq_cmd.h revision 299549
167754Smsmith/****************************************************************************** 267754Smsmith 367754Smsmith Copyright (c) 2013-2015, Intel Corporation 467754Smsmith All rights reserved. 567754Smsmith 667754Smsmith Redistribution and use in source and binary forms, with or without 7217365Sjkim modification, are permitted provided that the following conditions are met: 8229989Sjkim 970243Smsmith 1. Redistributions of source code must retain the above copyright notice, 1067754Smsmith this list of conditions and the following disclaimer. 11217365Sjkim 12217365Sjkim 2. Redistributions in binary form must reproduce the above copyright 13217365Sjkim notice, this list of conditions and the following disclaimer in the 14217365Sjkim documentation and/or other materials provided with the distribution. 15217365Sjkim 16217365Sjkim 3. Neither the name of the Intel Corporation nor the names of its 17217365Sjkim contributors may be used to endorse or promote products derived from 18217365Sjkim this software without specific prior written permission. 19217365Sjkim 20217365Sjkim THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21217365Sjkim AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22217365Sjkim IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23217365Sjkim ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24217365Sjkim LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2567754Smsmith CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26217365Sjkim SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27217365Sjkim INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28217365Sjkim CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2967754Smsmith ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30217365Sjkim POSSIBILITY OF SUCH DAMAGE. 31217365Sjkim 32217365Sjkim******************************************************************************/ 33217365Sjkim/*$FreeBSD: head/sys/dev/ixl/i40e_adminq_cmd.h 299549 2016-05-12 18:20:36Z erj $*/ 34217365Sjkim 35217365Sjkim#ifndef _I40E_ADMINQ_CMD_H_ 36217365Sjkim#define _I40E_ADMINQ_CMD_H_ 37217365Sjkim 38217365Sjkim/* This header file defines the i40e Admin Queue commands and is shared between 39217365Sjkim * i40e Firmware and Software. 40217365Sjkim * 41217365Sjkim * This file needs to comply with the Linux Kernel coding style. 42217365Sjkim */ 4367754Smsmith 4467754Smsmith#define I40E_FW_API_VERSION_MAJOR 0x0001 4567754Smsmith#define I40E_FW_API_VERSION_MINOR 0x0005 4667754Smsmith 4767754Smsmithstruct i40e_aq_desc { 4867754Smsmith __le16 flags; 4967754Smsmith __le16 opcode; 50117521Snjl __le16 datalen; 5167754Smsmith __le16 retval; 5267754Smsmith __le32 cookie_high; 5367754Smsmith __le32 cookie_low; 5467754Smsmith union { 55102550Siwasaki struct { 5691116Smsmith __le32 param0; 5791116Smsmith __le32 param1; 5887031Smsmith __le32 param2; 5967754Smsmith __le32 param3; 6067754Smsmith } internal; 6187031Smsmith struct { 6267754Smsmith __le32 param0; 6367754Smsmith __le32 param1; 6467754Smsmith __le32 addr_high; 65129684Snjl __le32 addr_low; 66129684Snjl } external; 67129684Snjl u8 raw[16]; 68138287Smarks } params; 69129684Snjl}; 70129684Snjl 71129684Snjl/* Flags sub-structure 72129684Snjl * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 73129684Snjl * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 74129684Snjl */ 75117521Snjl 76117521Snjl/* command flags and offsets*/ 77151937Sjkim#define I40E_AQ_FLAG_DD_SHIFT 0 78117521Snjl#define I40E_AQ_FLAG_CMP_SHIFT 1 79151937Sjkim#define I40E_AQ_FLAG_ERR_SHIFT 2 80151937Sjkim#define I40E_AQ_FLAG_VFE_SHIFT 3 81167802Sjkim#define I40E_AQ_FLAG_LB_SHIFT 9 82117521Snjl#define I40E_AQ_FLAG_RD_SHIFT 10 83117521Snjl#define I40E_AQ_FLAG_VFC_SHIFT 11 84167802Sjkim#define I40E_AQ_FLAG_BUF_SHIFT 12 85117521Snjl#define I40E_AQ_FLAG_SI_SHIFT 13 86117521Snjl#define I40E_AQ_FLAG_EI_SHIFT 14 87117521Snjl#define I40E_AQ_FLAG_FE_SHIFT 15 88117521Snjl 89231844Sjkim#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 90231844Sjkim#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 91231844Sjkim#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 92231844Sjkim#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 93231844Sjkim#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 94231844Sjkim#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 95231844Sjkim#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 96231844Sjkim#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 97231844Sjkim#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 98231844Sjkim#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 99231844Sjkim#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 100231844Sjkim 101231844Sjkim/* error codes */ 102231844Sjkimenum i40e_admin_queue_err { 103231844Sjkim I40E_AQ_RC_OK = 0, /* success */ 104231844Sjkim I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 105117521Snjl I40E_AQ_RC_ENOENT = 2, /* No such element */ 106231844Sjkim I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 10767754Smsmith I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 10867754Smsmith I40E_AQ_RC_EIO = 5, /* I/O error */ 10967754Smsmith I40E_AQ_RC_ENXIO = 6, /* No such resource */ 11067754Smsmith I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 11167754Smsmith I40E_AQ_RC_EAGAIN = 8, /* Try again */ 11267754Smsmith I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 11385756Smsmith I40E_AQ_RC_EACCES = 10, /* Permission denied */ 11467754Smsmith I40E_AQ_RC_EFAULT = 11, /* Bad address */ 115231844Sjkim I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 11685756Smsmith I40E_AQ_RC_EEXIST = 13, /* object already exists */ 11767754Smsmith I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 11867754Smsmith I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 119114237Snjl I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 12067754Smsmith I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 121167802Sjkim I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 12267754Smsmith I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 123167802Sjkim I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 12467754Smsmith I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 125199337Sjkim I40E_AQ_RC_EFBIG = 22, /* File too large */ 12667754Smsmith}; 127199337Sjkim 12867754Smsmith/* Admin Queue command opcodes */ 129167802Sjkimenum i40e_admin_queue_opc { 13067754Smsmith /* aq commands */ 131167802Sjkim i40e_aqc_opc_get_version = 0x0001, 132167802Sjkim i40e_aqc_opc_driver_version = 0x0002, 133167802Sjkim i40e_aqc_opc_queue_shutdown = 0x0003, 134167802Sjkim i40e_aqc_opc_set_pf_context = 0x0004, 135167802Sjkim 136167802Sjkim /* resource ownership */ 137193267Sjkim i40e_aqc_opc_request_resource = 0x0008, 138167802Sjkim i40e_aqc_opc_release_resource = 0x0009, 139193267Sjkim 140193267Sjkim i40e_aqc_opc_list_func_capabilities = 0x000A, 141209746Sjkim i40e_aqc_opc_list_dev_capabilities = 0x000B, 142193267Sjkim 143228110Sjkim /* LAA */ 144209746Sjkim i40e_aqc_opc_mac_address_read = 0x0107, 145229989Sjkim i40e_aqc_opc_mac_address_write = 0x0108, 146209746Sjkim 147229989Sjkim /* PXE */ 148229989Sjkim i40e_aqc_opc_clear_pxe_mode = 0x0110, 149229989Sjkim 15091116Smsmith /* internal switch commands */ 15191116Smsmith i40e_aqc_opc_get_switch_config = 0x0200, 15267754Smsmith i40e_aqc_opc_add_statistics = 0x0201, 15367754Smsmith i40e_aqc_opc_remove_statistics = 0x0202, 15467754Smsmith i40e_aqc_opc_set_port_parameters = 0x0203, 15567754Smsmith i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 156151937Sjkim i40e_aqc_opc_set_switch_config = 0x0205, 157151937Sjkim 158114237Snjl i40e_aqc_opc_add_vsi = 0x0210, 159114237Snjl i40e_aqc_opc_update_vsi_parameters = 0x0211, 16067754Smsmith i40e_aqc_opc_get_vsi_parameters = 0x0212, 161114237Snjl 162114237Snjl i40e_aqc_opc_add_pv = 0x0220, 16367754Smsmith i40e_aqc_opc_update_pv_parameters = 0x0221, 16467754Smsmith i40e_aqc_opc_get_pv_parameters = 0x0222, 165114237Snjl 16667754Smsmith i40e_aqc_opc_add_veb = 0x0230, 167114237Snjl i40e_aqc_opc_update_veb_parameters = 0x0231, 168114237Snjl i40e_aqc_opc_get_veb_parameters = 0x0232, 16967754Smsmith 170167802Sjkim i40e_aqc_opc_delete_element = 0x0243, 171167802Sjkim 172167802Sjkim i40e_aqc_opc_add_macvlan = 0x0250, 173167802Sjkim i40e_aqc_opc_remove_macvlan = 0x0251, 174167802Sjkim i40e_aqc_opc_add_vlan = 0x0252, 175167802Sjkim i40e_aqc_opc_remove_vlan = 0x0253, 176167802Sjkim i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 177167802Sjkim i40e_aqc_opc_add_tag = 0x0255, 178167802Sjkim i40e_aqc_opc_remove_tag = 0x0256, 179167802Sjkim i40e_aqc_opc_add_multicast_etag = 0x0257, 180167802Sjkim i40e_aqc_opc_remove_multicast_etag = 0x0258, 18167754Smsmith i40e_aqc_opc_update_tag = 0x0259, 18267754Smsmith i40e_aqc_opc_add_control_packet_filter = 0x025A, 183131440Smarks i40e_aqc_opc_remove_control_packet_filter = 0x025B, 184131440Smarks i40e_aqc_opc_add_cloud_filters = 0x025C, 185131440Smarks i40e_aqc_opc_remove_cloud_filters = 0x025D, 186131440Smarks 187131440Smarks i40e_aqc_opc_add_mirror_rule = 0x0260, 188114237Snjl i40e_aqc_opc_delete_mirror_rule = 0x0261, 18967754Smsmith 19087031Smsmith /* DCB commands */ 19187031Smsmith i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 19299679Siwasaki i40e_aqc_opc_dcb_updated = 0x0302, 19387031Smsmith 19477424Smsmith /* TX scheduler */ 19567754Smsmith i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 19699679Siwasaki i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 19777424Smsmith i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 198100966Siwasaki i40e_aqc_opc_query_vsi_bw_config = 0x0408, 199100966Siwasaki i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 200167802Sjkim i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 201100966Siwasaki 20291116Smsmith i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 20377424Smsmith i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 20499679Siwasaki i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 20599679Siwasaki i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 20691116Smsmith i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 207228110Sjkim i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 20891116Smsmith i40e_aqc_opc_query_port_ets_config = 0x0419, 209107325Siwasaki i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 210228110Sjkim i40e_aqc_opc_suspend_port_tx = 0x041B, 211197104Sjkim i40e_aqc_opc_resume_port_tx = 0x041C, 212107325Siwasaki i40e_aqc_opc_configure_partition_bw = 0x041D, 213197104Sjkim 214107325Siwasaki /* hmc */ 215197104Sjkim i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 216197104Sjkim i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 217197104Sjkim 218197104Sjkim /* phy commands*/ 21991116Smsmith i40e_aqc_opc_get_phy_abilities = 0x0600, 22091116Smsmith i40e_aqc_opc_set_phy_config = 0x0601, 22191116Smsmith i40e_aqc_opc_set_mac_config = 0x0603, 22291116Smsmith i40e_aqc_opc_set_link_restart_an = 0x0605, 22391116Smsmith i40e_aqc_opc_get_link_status = 0x0607, 22491116Smsmith i40e_aqc_opc_set_phy_int_mask = 0x0613, 225222544Sjkim i40e_aqc_opc_get_local_advt_reg = 0x0614, 226222544Sjkim i40e_aqc_opc_set_local_advt_reg = 0x0615, 22791116Smsmith i40e_aqc_opc_get_partner_advt = 0x0616, 22899679Siwasaki i40e_aqc_opc_set_lb_modes = 0x0618, 22999679Siwasaki i40e_aqc_opc_get_phy_wol_caps = 0x0621, 23091116Smsmith i40e_aqc_opc_set_phy_debug = 0x0622, 23191116Smsmith i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 23267754Smsmith i40e_aqc_opc_run_phy_activity = 0x0626, 23367754Smsmith 234 /* NVM commands */ 235 i40e_aqc_opc_nvm_read = 0x0701, 236 i40e_aqc_opc_nvm_erase = 0x0702, 237 i40e_aqc_opc_nvm_update = 0x0703, 238 i40e_aqc_opc_nvm_config_read = 0x0704, 239 i40e_aqc_opc_nvm_config_write = 0x0705, 240 i40e_aqc_opc_oem_post_update = 0x0720, 241 i40e_aqc_opc_thermal_sensor = 0x0721, 242 243 /* virtualization commands */ 244 i40e_aqc_opc_send_msg_to_pf = 0x0801, 245 i40e_aqc_opc_send_msg_to_vf = 0x0802, 246 i40e_aqc_opc_send_msg_to_peer = 0x0803, 247 248 /* alternate structure */ 249 i40e_aqc_opc_alternate_write = 0x0900, 250 i40e_aqc_opc_alternate_write_indirect = 0x0901, 251 i40e_aqc_opc_alternate_read = 0x0902, 252 i40e_aqc_opc_alternate_read_indirect = 0x0903, 253 i40e_aqc_opc_alternate_write_done = 0x0904, 254 i40e_aqc_opc_alternate_set_mode = 0x0905, 255 i40e_aqc_opc_alternate_clear_port = 0x0906, 256 257 /* LLDP commands */ 258 i40e_aqc_opc_lldp_get_mib = 0x0A00, 259 i40e_aqc_opc_lldp_update_mib = 0x0A01, 260 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 261 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 262 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 263 i40e_aqc_opc_lldp_stop = 0x0A05, 264 i40e_aqc_opc_lldp_start = 0x0A06, 265 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 266 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 267 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 268 269 /* Tunnel commands */ 270 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 271 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 272 273 /* Async Events */ 274 i40e_aqc_opc_event_lan_overflow = 0x1001, 275 276 /* OEM commands */ 277 i40e_aqc_opc_oem_parameter_change = 0xFE00, 278 i40e_aqc_opc_oem_device_status_change = 0xFE01, 279 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 280 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 281 282 /* debug commands */ 283 i40e_aqc_opc_debug_read_reg = 0xFF03, 284 i40e_aqc_opc_debug_write_reg = 0xFF04, 285 i40e_aqc_opc_debug_modify_reg = 0xFF07, 286 i40e_aqc_opc_debug_dump_internals = 0xFF08, 287}; 288 289/* command structures and indirect data structures */ 290 291/* Structure naming conventions: 292 * - no suffix for direct command descriptor structures 293 * - _data for indirect sent data 294 * - _resp for indirect return data (data which is both will use _data) 295 * - _completion for direct return data 296 * - _element_ for repeated elements (may also be _data or _resp) 297 * 298 * Command structures are expected to overlay the params.raw member of the basic 299 * descriptor, and as such cannot exceed 16 bytes in length. 300 */ 301 302/* This macro is used to generate a compilation error if a structure 303 * is not exactly the correct length. It gives a divide by zero error if the 304 * structure is not of the correct size, otherwise it creates an enum that is 305 * never used. 306 */ 307#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 308 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 309 310/* This macro is used extensively to ensure that command structures are 16 311 * bytes in length as they have to map to the raw array of that size. 312 */ 313#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 314 315/* internal (0x00XX) commands */ 316 317/* Get version (direct 0x0001) */ 318struct i40e_aqc_get_version { 319 __le32 rom_ver; 320 __le32 fw_build; 321 __le16 fw_major; 322 __le16 fw_minor; 323 __le16 api_major; 324 __le16 api_minor; 325}; 326 327I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 328 329/* Send driver version (indirect 0x0002) */ 330struct i40e_aqc_driver_version { 331 u8 driver_major_ver; 332 u8 driver_minor_ver; 333 u8 driver_build_ver; 334 u8 driver_subbuild_ver; 335 u8 reserved[4]; 336 __le32 address_high; 337 __le32 address_low; 338}; 339 340I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 341 342/* Queue Shutdown (direct 0x0003) */ 343struct i40e_aqc_queue_shutdown { 344 __le32 driver_unloading; 345#define I40E_AQ_DRIVER_UNLOADING 0x1 346 u8 reserved[12]; 347}; 348 349I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 350 351/* Set PF context (0x0004, direct) */ 352struct i40e_aqc_set_pf_context { 353 u8 pf_id; 354 u8 reserved[15]; 355}; 356 357I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 358 359/* Request resource ownership (direct 0x0008) 360 * Release resource ownership (direct 0x0009) 361 */ 362#define I40E_AQ_RESOURCE_NVM 1 363#define I40E_AQ_RESOURCE_SDP 2 364#define I40E_AQ_RESOURCE_ACCESS_READ 1 365#define I40E_AQ_RESOURCE_ACCESS_WRITE 2 366#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 367#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 368 369struct i40e_aqc_request_resource { 370 __le16 resource_id; 371 __le16 access_type; 372 __le32 timeout; 373 __le32 resource_number; 374 u8 reserved[4]; 375}; 376 377I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 378 379/* Get function capabilities (indirect 0x000A) 380 * Get device capabilities (indirect 0x000B) 381 */ 382struct i40e_aqc_list_capabilites { 383 u8 command_flags; 384#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 385 u8 pf_index; 386 u8 reserved[2]; 387 __le32 count; 388 __le32 addr_high; 389 __le32 addr_low; 390}; 391 392I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 393 394struct i40e_aqc_list_capabilities_element_resp { 395 __le16 id; 396 u8 major_rev; 397 u8 minor_rev; 398 __le32 number; 399 __le32 logical_id; 400 __le32 phys_id; 401 u8 reserved[16]; 402}; 403 404/* list of caps */ 405 406#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 407#define I40E_AQ_CAP_ID_MNG_MODE 0x0002 408#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 409#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 410#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 411#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 412#define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 413#define I40E_AQ_CAP_ID_SRIOV 0x0012 414#define I40E_AQ_CAP_ID_VF 0x0013 415#define I40E_AQ_CAP_ID_VMDQ 0x0014 416#define I40E_AQ_CAP_ID_8021QBG 0x0015 417#define I40E_AQ_CAP_ID_8021QBR 0x0016 418#define I40E_AQ_CAP_ID_VSI 0x0017 419#define I40E_AQ_CAP_ID_DCB 0x0018 420#define I40E_AQ_CAP_ID_FCOE 0x0021 421#define I40E_AQ_CAP_ID_ISCSI 0x0022 422#define I40E_AQ_CAP_ID_RSS 0x0040 423#define I40E_AQ_CAP_ID_RXQ 0x0041 424#define I40E_AQ_CAP_ID_TXQ 0x0042 425#define I40E_AQ_CAP_ID_MSIX 0x0043 426#define I40E_AQ_CAP_ID_VF_MSIX 0x0044 427#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 428#define I40E_AQ_CAP_ID_1588 0x0046 429#define I40E_AQ_CAP_ID_IWARP 0x0051 430#define I40E_AQ_CAP_ID_LED 0x0061 431#define I40E_AQ_CAP_ID_SDP 0x0062 432#define I40E_AQ_CAP_ID_MDIO 0x0063 433#define I40E_AQ_CAP_ID_WSR_PROT 0x0064 434#define I40E_AQ_CAP_ID_FLEX10 0x00F1 435#define I40E_AQ_CAP_ID_CEM 0x00F2 436 437/* Set CPPM Configuration (direct 0x0103) */ 438struct i40e_aqc_cppm_configuration { 439 __le16 command_flags; 440#define I40E_AQ_CPPM_EN_LTRC 0x0800 441#define I40E_AQ_CPPM_EN_DMCTH 0x1000 442#define I40E_AQ_CPPM_EN_DMCTLX 0x2000 443#define I40E_AQ_CPPM_EN_HPTC 0x4000 444#define I40E_AQ_CPPM_EN_DMARC 0x8000 445 __le16 ttlx; 446 __le32 dmacr; 447 __le16 dmcth; 448 u8 hptc; 449 u8 reserved; 450 __le32 pfltrc; 451}; 452 453I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 454 455/* Set ARP Proxy command / response (indirect 0x0104) */ 456struct i40e_aqc_arp_proxy_data { 457 __le16 command_flags; 458#define I40E_AQ_ARP_INIT_IPV4 0x0008 459#define I40E_AQ_ARP_UNSUP_CTL 0x0010 460#define I40E_AQ_ARP_ENA 0x0020 461#define I40E_AQ_ARP_ADD_IPV4 0x0040 462#define I40E_AQ_ARP_DEL_IPV4 0x0080 463 __le16 table_id; 464 __le32 pfpm_proxyfc; 465 __le32 ip_addr; 466 u8 mac_addr[6]; 467 u8 reserved[2]; 468}; 469 470I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 471 472/* Set NS Proxy Table Entry Command (indirect 0x0105) */ 473struct i40e_aqc_ns_proxy_data { 474 __le16 table_idx_mac_addr_0; 475 __le16 table_idx_mac_addr_1; 476 __le16 table_idx_ipv6_0; 477 __le16 table_idx_ipv6_1; 478 __le16 control; 479#define I40E_AQ_NS_PROXY_ADD_0 0x0100 480#define I40E_AQ_NS_PROXY_DEL_0 0x0200 481#define I40E_AQ_NS_PROXY_ADD_1 0x0400 482#define I40E_AQ_NS_PROXY_DEL_1 0x0800 483#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 484#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 485#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 486#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 487#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 488#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 489#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 490 u8 mac_addr_0[6]; 491 u8 mac_addr_1[6]; 492 u8 local_mac_addr[6]; 493 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 494 u8 ipv6_addr_1[16]; 495}; 496 497I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 498 499/* Manage LAA Command (0x0106) - obsolete */ 500struct i40e_aqc_mng_laa { 501 __le16 command_flags; 502#define I40E_AQ_LAA_FLAG_WR 0x8000 503 u8 reserved[2]; 504 __le32 sal; 505 __le16 sah; 506 u8 reserved2[6]; 507}; 508 509I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 510 511/* Manage MAC Address Read Command (indirect 0x0107) */ 512struct i40e_aqc_mac_address_read { 513 __le16 command_flags; 514#define I40E_AQC_LAN_ADDR_VALID 0x10 515#define I40E_AQC_SAN_ADDR_VALID 0x20 516#define I40E_AQC_PORT_ADDR_VALID 0x40 517#define I40E_AQC_WOL_ADDR_VALID 0x80 518#define I40E_AQC_MC_MAG_EN_VALID 0x100 519#define I40E_AQC_ADDR_VALID_MASK 0x1F0 520 u8 reserved[6]; 521 __le32 addr_high; 522 __le32 addr_low; 523}; 524 525I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 526 527struct i40e_aqc_mac_address_read_data { 528 u8 pf_lan_mac[6]; 529 u8 pf_san_mac[6]; 530 u8 port_mac[6]; 531 u8 pf_wol_mac[6]; 532}; 533 534I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 535 536/* Manage MAC Address Write Command (0x0108) */ 537struct i40e_aqc_mac_address_write { 538 __le16 command_flags; 539#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 540#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 541#define I40E_AQC_WRITE_TYPE_PORT 0x8000 542#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 543#define I40E_AQC_WRITE_TYPE_MASK 0xC000 544 545 __le16 mac_sah; 546 __le32 mac_sal; 547 u8 reserved[8]; 548}; 549 550I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 551 552/* PXE commands (0x011x) */ 553 554/* Clear PXE Command and response (direct 0x0110) */ 555struct i40e_aqc_clear_pxe { 556 u8 rx_cnt; 557 u8 reserved[15]; 558}; 559 560I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 561 562/* Switch configuration commands (0x02xx) */ 563 564/* Used by many indirect commands that only pass an seid and a buffer in the 565 * command 566 */ 567struct i40e_aqc_switch_seid { 568 __le16 seid; 569 u8 reserved[6]; 570 __le32 addr_high; 571 __le32 addr_low; 572}; 573 574I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 575 576/* Get Switch Configuration command (indirect 0x0200) 577 * uses i40e_aqc_switch_seid for the descriptor 578 */ 579struct i40e_aqc_get_switch_config_header_resp { 580 __le16 num_reported; 581 __le16 num_total; 582 u8 reserved[12]; 583}; 584 585I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 586 587struct i40e_aqc_switch_config_element_resp { 588 u8 element_type; 589#define I40E_AQ_SW_ELEM_TYPE_MAC 1 590#define I40E_AQ_SW_ELEM_TYPE_PF 2 591#define I40E_AQ_SW_ELEM_TYPE_VF 3 592#define I40E_AQ_SW_ELEM_TYPE_EMP 4 593#define I40E_AQ_SW_ELEM_TYPE_BMC 5 594#define I40E_AQ_SW_ELEM_TYPE_PV 16 595#define I40E_AQ_SW_ELEM_TYPE_VEB 17 596#define I40E_AQ_SW_ELEM_TYPE_PA 18 597#define I40E_AQ_SW_ELEM_TYPE_VSI 19 598 u8 revision; 599#define I40E_AQ_SW_ELEM_REV_1 1 600 __le16 seid; 601 __le16 uplink_seid; 602 __le16 downlink_seid; 603 u8 reserved[3]; 604 u8 connection_type; 605#define I40E_AQ_CONN_TYPE_REGULAR 0x1 606#define I40E_AQ_CONN_TYPE_DEFAULT 0x2 607#define I40E_AQ_CONN_TYPE_CASCADED 0x3 608 __le16 scheduler_id; 609 __le16 element_info; 610}; 611 612I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 613 614/* Get Switch Configuration (indirect 0x0200) 615 * an array of elements are returned in the response buffer 616 * the first in the array is the header, remainder are elements 617 */ 618struct i40e_aqc_get_switch_config_resp { 619 struct i40e_aqc_get_switch_config_header_resp header; 620 struct i40e_aqc_switch_config_element_resp element[1]; 621}; 622 623I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 624 625/* Add Statistics (direct 0x0201) 626 * Remove Statistics (direct 0x0202) 627 */ 628struct i40e_aqc_add_remove_statistics { 629 __le16 seid; 630 __le16 vlan; 631 __le16 stat_index; 632 u8 reserved[10]; 633}; 634 635I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 636 637/* Set Port Parameters command (direct 0x0203) */ 638struct i40e_aqc_set_port_parameters { 639 __le16 command_flags; 640#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 641#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 642#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 643 __le16 bad_frame_vsi; 644 __le16 default_seid; /* reserved for command */ 645 u8 reserved[10]; 646}; 647 648I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 649 650/* Get Switch Resource Allocation (indirect 0x0204) */ 651struct i40e_aqc_get_switch_resource_alloc { 652 u8 num_entries; /* reserved for command */ 653 u8 reserved[7]; 654 __le32 addr_high; 655 __le32 addr_low; 656}; 657 658I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 659 660/* expect an array of these structs in the response buffer */ 661struct i40e_aqc_switch_resource_alloc_element_resp { 662 u8 resource_type; 663#define I40E_AQ_RESOURCE_TYPE_VEB 0x0 664#define I40E_AQ_RESOURCE_TYPE_VSI 0x1 665#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 666#define I40E_AQ_RESOURCE_TYPE_STAG 0x3 667#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 668#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 669#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 670#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 671#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 672#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 673#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 674#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 675#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 676#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 677#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 678#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 679#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 680#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 681#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 682 u8 reserved1; 683 __le16 guaranteed; 684 __le16 total; 685 __le16 used; 686 __le16 total_unalloced; 687 u8 reserved2[6]; 688}; 689 690I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 691 692/* Set Switch Configuration (direct 0x0205) */ 693struct i40e_aqc_set_switch_config { 694 __le16 flags; 695#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 696#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 697 __le16 valid_flags; 698 u8 reserved[12]; 699}; 700 701I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 702 703/* Add VSI (indirect 0x0210) 704 * this indirect command uses struct i40e_aqc_vsi_properties_data 705 * as the indirect buffer (128 bytes) 706 * 707 * Update VSI (indirect 0x211) 708 * uses the same data structure as Add VSI 709 * 710 * Get VSI (indirect 0x0212) 711 * uses the same completion and data structure as Add VSI 712 */ 713struct i40e_aqc_add_get_update_vsi { 714 __le16 uplink_seid; 715 u8 connection_type; 716#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 717#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 718#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 719 u8 reserved1; 720 u8 vf_id; 721 u8 reserved2; 722 __le16 vsi_flags; 723#define I40E_AQ_VSI_TYPE_SHIFT 0x0 724#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 725#define I40E_AQ_VSI_TYPE_VF 0x0 726#define I40E_AQ_VSI_TYPE_VMDQ2 0x1 727#define I40E_AQ_VSI_TYPE_PF 0x2 728#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 729#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 730 __le32 addr_high; 731 __le32 addr_low; 732}; 733 734I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 735 736struct i40e_aqc_add_get_update_vsi_completion { 737 __le16 seid; 738 __le16 vsi_number; 739 __le16 vsi_used; 740 __le16 vsi_free; 741 __le32 addr_high; 742 __le32 addr_low; 743}; 744 745I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 746 747struct i40e_aqc_vsi_properties_data { 748 /* first 96 byte are written by SW */ 749 __le16 valid_sections; 750#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 751#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 752#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 753#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 754#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 755#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 756#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 757#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 758#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 759#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 760 /* switch section */ 761 __le16 switch_id; /* 12bit id combined with flags below */ 762#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 763#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 764#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 765#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 766#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 767 u8 sw_reserved[2]; 768 /* security section */ 769 u8 sec_flags; 770#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 771#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 772#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 773 u8 sec_reserved; 774 /* VLAN section */ 775 __le16 pvid; /* VLANS include priority bits */ 776 __le16 fcoe_pvid; 777 u8 port_vlan_flags; 778#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 779#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 780 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 781#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 782#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 783#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 784#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 785#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 786#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 787 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 788#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 789#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 790#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 791#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 792 u8 pvlan_reserved[3]; 793 /* ingress egress up sections */ 794 __le32 ingress_table; /* bitmap, 3 bits per up */ 795#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 796#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 797 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 798#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 799#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 800 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 801#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 802#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 803 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 804#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 805#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 806 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 807#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 808#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 809 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 810#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 811#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 812 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 813#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 814#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 815 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 816#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 817#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 818 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 819 __le32 egress_table; /* same defines as for ingress table */ 820 /* cascaded PV section */ 821 __le16 cas_pv_tag; 822 u8 cas_pv_flags; 823#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 824#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 825 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 826#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 827#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 828#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 829#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 830#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 831#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 832 u8 cas_pv_reserved; 833 /* queue mapping section */ 834 __le16 mapping_flags; 835#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 836#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 837 __le16 queue_mapping[16]; 838#define I40E_AQ_VSI_QUEUE_SHIFT 0x0 839#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 840 __le16 tc_mapping[8]; 841#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 842#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 843 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 844#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 845#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 846 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 847 /* queueing option section */ 848 u8 queueing_opt_flags; 849#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 850#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 851 u8 queueing_opt_reserved[3]; 852 /* scheduler section */ 853 u8 up_enable_bits; 854 u8 sched_reserved; 855 /* outer up section */ 856 __le32 outer_up_table; /* same structure and defines as ingress table */ 857 u8 cmd_reserved[8]; 858 /* last 32 bytes are written by FW */ 859 __le16 qs_handle[8]; 860#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 861 __le16 stat_counter_idx; 862 __le16 sched_id; 863 u8 resp_reserved[12]; 864}; 865 866I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 867 868/* Add Port Virtualizer (direct 0x0220) 869 * also used for update PV (direct 0x0221) but only flags are used 870 * (IS_CTRL_PORT only works on add PV) 871 */ 872struct i40e_aqc_add_update_pv { 873 __le16 command_flags; 874#define I40E_AQC_PV_FLAG_PV_TYPE 0x1 875#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 876#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 877#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 878 __le16 uplink_seid; 879 __le16 connected_seid; 880 u8 reserved[10]; 881}; 882 883I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 884 885struct i40e_aqc_add_update_pv_completion { 886 /* reserved for update; for add also encodes error if rc == ENOSPC */ 887 __le16 pv_seid; 888#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 889#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 890#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 891#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 892 u8 reserved[14]; 893}; 894 895I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 896 897/* Get PV Params (direct 0x0222) 898 * uses i40e_aqc_switch_seid for the descriptor 899 */ 900 901struct i40e_aqc_get_pv_params_completion { 902 __le16 seid; 903 __le16 default_stag; 904 __le16 pv_flags; /* same flags as add_pv */ 905#define I40E_AQC_GET_PV_PV_TYPE 0x1 906#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 907#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 908 u8 reserved[8]; 909 __le16 default_port_seid; 910}; 911 912I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 913 914/* Add VEB (direct 0x0230) */ 915struct i40e_aqc_add_veb { 916 __le16 uplink_seid; 917 __le16 downlink_seid; 918 __le16 veb_flags; 919#define I40E_AQC_ADD_VEB_FLOATING 0x1 920#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 921#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 922 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 923#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 924#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 925#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 926#define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 927 u8 enable_tcs; 928 u8 reserved[9]; 929}; 930 931I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 932 933struct i40e_aqc_add_veb_completion { 934 u8 reserved[6]; 935 __le16 switch_seid; 936 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 937 __le16 veb_seid; 938#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 939#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 940#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 941#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 942 __le16 statistic_index; 943 __le16 vebs_used; 944 __le16 vebs_free; 945}; 946 947I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 948 949/* Get VEB Parameters (direct 0x0232) 950 * uses i40e_aqc_switch_seid for the descriptor 951 */ 952struct i40e_aqc_get_veb_parameters_completion { 953 __le16 seid; 954 __le16 switch_id; 955 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 956 __le16 statistic_index; 957 __le16 vebs_used; 958 __le16 vebs_free; 959 u8 reserved[4]; 960}; 961 962I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 963 964/* Delete Element (direct 0x0243) 965 * uses the generic i40e_aqc_switch_seid 966 */ 967 968/* Add MAC-VLAN (indirect 0x0250) */ 969 970/* used for the command for most vlan commands */ 971struct i40e_aqc_macvlan { 972 __le16 num_addresses; 973 __le16 seid[3]; 974#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 975#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 976 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 977#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 978 __le32 addr_high; 979 __le32 addr_low; 980}; 981 982I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 983 984/* indirect data for command and response */ 985struct i40e_aqc_add_macvlan_element_data { 986 u8 mac_addr[6]; 987 __le16 vlan_tag; 988 __le16 flags; 989#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 990#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 991#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 992#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 993#define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 994 __le16 queue_number; 995#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 996#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 997 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 998 /* response section */ 999 u8 match_method; 1000#define I40E_AQC_MM_PERFECT_MATCH 0x01 1001#define I40E_AQC_MM_HASH_MATCH 0x02 1002#define I40E_AQC_MM_ERR_NO_RES 0xFF 1003 u8 reserved1[3]; 1004}; 1005 1006struct i40e_aqc_add_remove_macvlan_completion { 1007 __le16 perfect_mac_used; 1008 __le16 perfect_mac_free; 1009 __le16 unicast_hash_free; 1010 __le16 multicast_hash_free; 1011 __le32 addr_high; 1012 __le32 addr_low; 1013}; 1014 1015I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1016 1017/* Remove MAC-VLAN (indirect 0x0251) 1018 * uses i40e_aqc_macvlan for the descriptor 1019 * data points to an array of num_addresses of elements 1020 */ 1021 1022struct i40e_aqc_remove_macvlan_element_data { 1023 u8 mac_addr[6]; 1024 __le16 vlan_tag; 1025 u8 flags; 1026#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1027#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1028#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1029#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1030 u8 reserved[3]; 1031 /* reply section */ 1032 u8 error_code; 1033#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1034#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1035 u8 reply_reserved[3]; 1036}; 1037 1038/* Add VLAN (indirect 0x0252) 1039 * Remove VLAN (indirect 0x0253) 1040 * use the generic i40e_aqc_macvlan for the command 1041 */ 1042struct i40e_aqc_add_remove_vlan_element_data { 1043 __le16 vlan_tag; 1044 u8 vlan_flags; 1045/* flags for add VLAN */ 1046#define I40E_AQC_ADD_VLAN_LOCAL 0x1 1047#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1048#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1049#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1050#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1051#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1052#define I40E_AQC_VLAN_PTYPE_SHIFT 3 1053#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1054#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1055#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1056#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1057#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1058/* flags for remove VLAN */ 1059#define I40E_AQC_REMOVE_VLAN_ALL 0x1 1060 u8 reserved; 1061 u8 result; 1062/* flags for add VLAN */ 1063#define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1064#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1065#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1066/* flags for remove VLAN */ 1067#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1068#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1069 u8 reserved1[3]; 1070}; 1071 1072struct i40e_aqc_add_remove_vlan_completion { 1073 u8 reserved[4]; 1074 __le16 vlans_used; 1075 __le16 vlans_free; 1076 __le32 addr_high; 1077 __le32 addr_low; 1078}; 1079 1080/* Set VSI Promiscuous Modes (direct 0x0254) */ 1081struct i40e_aqc_set_vsi_promiscuous_modes { 1082 __le16 promiscuous_flags; 1083 __le16 valid_flags; 1084/* flags used for both fields above */ 1085#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1086#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1087#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1088#define I40E_AQC_SET_VSI_DEFAULT 0x08 1089#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1090 __le16 seid; 1091#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1092 __le16 vlan_tag; 1093#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1094#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1095 u8 reserved[8]; 1096}; 1097 1098I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1099 1100/* Add S/E-tag command (direct 0x0255) 1101 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1102 */ 1103struct i40e_aqc_add_tag { 1104 __le16 flags; 1105#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1106 __le16 seid; 1107#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1108#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1109 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1110 __le16 tag; 1111 __le16 queue_number; 1112 u8 reserved[8]; 1113}; 1114 1115I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1116 1117struct i40e_aqc_add_remove_tag_completion { 1118 u8 reserved[12]; 1119 __le16 tags_used; 1120 __le16 tags_free; 1121}; 1122 1123I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1124 1125/* Remove S/E-tag command (direct 0x0256) 1126 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1127 */ 1128struct i40e_aqc_remove_tag { 1129 __le16 seid; 1130#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1131#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1132 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1133 __le16 tag; 1134 u8 reserved[12]; 1135}; 1136 1137I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1138 1139/* Add multicast E-Tag (direct 0x0257) 1140 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1141 * and no external data 1142 */ 1143struct i40e_aqc_add_remove_mcast_etag { 1144 __le16 pv_seid; 1145 __le16 etag; 1146 u8 num_unicast_etags; 1147 u8 reserved[3]; 1148 __le32 addr_high; /* address of array of 2-byte s-tags */ 1149 __le32 addr_low; 1150}; 1151 1152I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1153 1154struct i40e_aqc_add_remove_mcast_etag_completion { 1155 u8 reserved[4]; 1156 __le16 mcast_etags_used; 1157 __le16 mcast_etags_free; 1158 __le32 addr_high; 1159 __le32 addr_low; 1160 1161}; 1162 1163I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1164 1165/* Update S/E-Tag (direct 0x0259) */ 1166struct i40e_aqc_update_tag { 1167 __le16 seid; 1168#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1169#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1170 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1171 __le16 old_tag; 1172 __le16 new_tag; 1173 u8 reserved[10]; 1174}; 1175 1176I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1177 1178struct i40e_aqc_update_tag_completion { 1179 u8 reserved[12]; 1180 __le16 tags_used; 1181 __le16 tags_free; 1182}; 1183 1184I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1185 1186/* Add Control Packet filter (direct 0x025A) 1187 * Remove Control Packet filter (direct 0x025B) 1188 * uses the i40e_aqc_add_oveb_cloud, 1189 * and the generic direct completion structure 1190 */ 1191struct i40e_aqc_add_remove_control_packet_filter { 1192 u8 mac[6]; 1193 __le16 etype; 1194 __le16 flags; 1195#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1196#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1197#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1198#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1199#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1200 __le16 seid; 1201#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1202#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1203 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1204 __le16 queue; 1205 u8 reserved[2]; 1206}; 1207 1208I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1209 1210struct i40e_aqc_add_remove_control_packet_filter_completion { 1211 __le16 mac_etype_used; 1212 __le16 etype_used; 1213 __le16 mac_etype_free; 1214 __le16 etype_free; 1215 u8 reserved[8]; 1216}; 1217 1218I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1219 1220/* Add Cloud filters (indirect 0x025C) 1221 * Remove Cloud filters (indirect 0x025D) 1222 * uses the i40e_aqc_add_remove_cloud_filters, 1223 * and the generic indirect completion structure 1224 */ 1225struct i40e_aqc_add_remove_cloud_filters { 1226 u8 num_filters; 1227 u8 reserved; 1228 __le16 seid; 1229#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1230#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1231 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1232 u8 reserved2[4]; 1233 __le32 addr_high; 1234 __le32 addr_low; 1235}; 1236 1237I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1238 1239struct i40e_aqc_add_remove_cloud_filters_element_data { 1240 u8 outer_mac[6]; 1241 u8 inner_mac[6]; 1242 __le16 inner_vlan; 1243 union { 1244 struct { 1245 u8 reserved[12]; 1246 u8 data[4]; 1247 } v4; 1248 struct { 1249 u8 data[16]; 1250 } v6; 1251 } ipaddr; 1252 __le16 flags; 1253#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1254#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1255 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1256/* 0x0000 reserved */ 1257#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1258/* 0x0002 reserved */ 1259#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1260#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1261/* 0x0005 reserved */ 1262#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1263/* 0x0007 reserved */ 1264/* 0x0008 reserved */ 1265#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1266#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1267#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1268#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1269 1270#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1271#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1272#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1273#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1274#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1275 1276#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1277#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1278#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1279#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1280#define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1281#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1282#define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1283#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1284 1285#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1286#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1287#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1288 1289 __le32 tenant_id; 1290 u8 reserved[4]; 1291 __le16 queue_number; 1292#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1293#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1294 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1295 u8 reserved2[14]; 1296 /* response section */ 1297 u8 allocation_result; 1298#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1299#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1300 u8 response_reserved[7]; 1301}; 1302 1303struct i40e_aqc_remove_cloud_filters_completion { 1304 __le16 perfect_ovlan_used; 1305 __le16 perfect_ovlan_free; 1306 __le16 vlan_used; 1307 __le16 vlan_free; 1308 __le32 addr_high; 1309 __le32 addr_low; 1310}; 1311 1312I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1313 1314/* Add Mirror Rule (indirect or direct 0x0260) 1315 * Delete Mirror Rule (indirect or direct 0x0261) 1316 * note: some rule types (4,5) do not use an external buffer. 1317 * take care to set the flags correctly. 1318 */ 1319struct i40e_aqc_add_delete_mirror_rule { 1320 __le16 seid; 1321 __le16 rule_type; 1322#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1323#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1324 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1325#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1326#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1327#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1328#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1329#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1330 __le16 num_entries; 1331 __le16 destination; /* VSI for add, rule id for delete */ 1332 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1333 __le32 addr_low; 1334}; 1335 1336I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1337 1338struct i40e_aqc_add_delete_mirror_rule_completion { 1339 u8 reserved[2]; 1340 __le16 rule_id; /* only used on add */ 1341 __le16 mirror_rules_used; 1342 __le16 mirror_rules_free; 1343 __le32 addr_high; 1344 __le32 addr_low; 1345}; 1346 1347I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1348 1349/* DCB 0x03xx*/ 1350 1351/* PFC Ignore (direct 0x0301) 1352 * the command and response use the same descriptor structure 1353 */ 1354struct i40e_aqc_pfc_ignore { 1355 u8 tc_bitmap; 1356 u8 command_flags; /* unused on response */ 1357#define I40E_AQC_PFC_IGNORE_SET 0x80 1358#define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1359 u8 reserved[14]; 1360}; 1361 1362I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1363 1364/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1365 * with no parameters 1366 */ 1367 1368/* TX scheduler 0x04xx */ 1369 1370/* Almost all the indirect commands use 1371 * this generic struct to pass the SEID in param0 1372 */ 1373struct i40e_aqc_tx_sched_ind { 1374 __le16 vsi_seid; 1375 u8 reserved[6]; 1376 __le32 addr_high; 1377 __le32 addr_low; 1378}; 1379 1380I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1381 1382/* Several commands respond with a set of queue set handles */ 1383struct i40e_aqc_qs_handles_resp { 1384 __le16 qs_handles[8]; 1385}; 1386 1387/* Configure VSI BW limits (direct 0x0400) */ 1388struct i40e_aqc_configure_vsi_bw_limit { 1389 __le16 vsi_seid; 1390 u8 reserved[2]; 1391 __le16 credit; 1392 u8 reserved1[2]; 1393 u8 max_credit; /* 0-3, limit = 2^max */ 1394 u8 reserved2[7]; 1395}; 1396 1397I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1398 1399/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1400 * responds with i40e_aqc_qs_handles_resp 1401 */ 1402struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1403 u8 tc_valid_bits; 1404 u8 reserved[15]; 1405 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1406 1407 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1408 __le16 tc_bw_max[2]; 1409 u8 reserved1[28]; 1410}; 1411 1412I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1413 1414/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1415 * responds with i40e_aqc_qs_handles_resp 1416 */ 1417struct i40e_aqc_configure_vsi_tc_bw_data { 1418 u8 tc_valid_bits; 1419 u8 reserved[3]; 1420 u8 tc_bw_credits[8]; 1421 u8 reserved1[4]; 1422 __le16 qs_handles[8]; 1423}; 1424 1425I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1426 1427/* Query vsi bw configuration (indirect 0x0408) */ 1428struct i40e_aqc_query_vsi_bw_config_resp { 1429 u8 tc_valid_bits; 1430 u8 tc_suspended_bits; 1431 u8 reserved[14]; 1432 __le16 qs_handles[8]; 1433 u8 reserved1[4]; 1434 __le16 port_bw_limit; 1435 u8 reserved2[2]; 1436 u8 max_bw; /* 0-3, limit = 2^max */ 1437 u8 reserved3[23]; 1438}; 1439 1440I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1441 1442/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1443struct i40e_aqc_query_vsi_ets_sla_config_resp { 1444 u8 tc_valid_bits; 1445 u8 reserved[3]; 1446 u8 share_credits[8]; 1447 __le16 credits[8]; 1448 1449 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1450 __le16 tc_bw_max[2]; 1451}; 1452 1453I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1454 1455/* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1456struct i40e_aqc_configure_switching_comp_bw_limit { 1457 __le16 seid; 1458 u8 reserved[2]; 1459 __le16 credit; 1460 u8 reserved1[2]; 1461 u8 max_bw; /* 0-3, limit = 2^max */ 1462 u8 reserved2[7]; 1463}; 1464 1465I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1466 1467/* Enable Physical Port ETS (indirect 0x0413) 1468 * Modify Physical Port ETS (indirect 0x0414) 1469 * Disable Physical Port ETS (indirect 0x0415) 1470 */ 1471struct i40e_aqc_configure_switching_comp_ets_data { 1472 u8 reserved[4]; 1473 u8 tc_valid_bits; 1474 u8 seepage; 1475#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1476 u8 tc_strict_priority_flags; 1477 u8 reserved1[17]; 1478 u8 tc_bw_share_credits[8]; 1479 u8 reserved2[96]; 1480}; 1481 1482I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1483 1484/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1485struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1486 u8 tc_valid_bits; 1487 u8 reserved[15]; 1488 __le16 tc_bw_credit[8]; 1489 1490 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1491 __le16 tc_bw_max[2]; 1492 u8 reserved1[28]; 1493}; 1494 1495I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1496 1497/* Configure Switching Component Bandwidth Allocation per Tc 1498 * (indirect 0x0417) 1499 */ 1500struct i40e_aqc_configure_switching_comp_bw_config_data { 1501 u8 tc_valid_bits; 1502 u8 reserved[2]; 1503 u8 absolute_credits; /* bool */ 1504 u8 tc_bw_share_credits[8]; 1505 u8 reserved1[20]; 1506}; 1507 1508I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1509 1510/* Query Switching Component Configuration (indirect 0x0418) */ 1511struct i40e_aqc_query_switching_comp_ets_config_resp { 1512 u8 tc_valid_bits; 1513 u8 reserved[35]; 1514 __le16 port_bw_limit; 1515 u8 reserved1[2]; 1516 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1517 u8 reserved2[23]; 1518}; 1519 1520I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1521 1522/* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1523struct i40e_aqc_query_port_ets_config_resp { 1524 u8 reserved[4]; 1525 u8 tc_valid_bits; 1526 u8 reserved1; 1527 u8 tc_strict_priority_bits; 1528 u8 reserved2; 1529 u8 tc_bw_share_credits[8]; 1530 __le16 tc_bw_limits[8]; 1531 1532 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1533 __le16 tc_bw_max[2]; 1534 u8 reserved3[32]; 1535}; 1536 1537I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1538 1539/* Query Switching Component Bandwidth Allocation per Traffic Type 1540 * (indirect 0x041A) 1541 */ 1542struct i40e_aqc_query_switching_comp_bw_config_resp { 1543 u8 tc_valid_bits; 1544 u8 reserved[2]; 1545 u8 absolute_credits_enable; /* bool */ 1546 u8 tc_bw_share_credits[8]; 1547 __le16 tc_bw_limits[8]; 1548 1549 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1550 __le16 tc_bw_max[2]; 1551}; 1552 1553I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1554 1555/* Suspend/resume port TX traffic 1556 * (direct 0x041B and 0x041C) uses the generic SEID struct 1557 */ 1558 1559/* Configure partition BW 1560 * (indirect 0x041D) 1561 */ 1562struct i40e_aqc_configure_partition_bw_data { 1563 __le16 pf_valid_bits; 1564 u8 min_bw[16]; /* guaranteed bandwidth */ 1565 u8 max_bw[16]; /* bandwidth limit */ 1566}; 1567 1568I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1569 1570/* Get and set the active HMC resource profile and status. 1571 * (direct 0x0500) and (direct 0x0501) 1572 */ 1573struct i40e_aq_get_set_hmc_resource_profile { 1574 u8 pm_profile; 1575 u8 pe_vf_enabled; 1576 u8 reserved[14]; 1577}; 1578 1579I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1580 1581enum i40e_aq_hmc_profile { 1582 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1583 I40E_HMC_PROFILE_DEFAULT = 1, 1584 I40E_HMC_PROFILE_FAVOR_VF = 2, 1585 I40E_HMC_PROFILE_EQUAL = 3, 1586}; 1587 1588#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF 1589#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F 1590 1591/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1592 1593/* set in param0 for get phy abilities to report qualified modules */ 1594#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1595#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1596 1597enum i40e_aq_phy_type { 1598 I40E_PHY_TYPE_SGMII = 0x0, 1599 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1600 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1601 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1602 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1603 I40E_PHY_TYPE_XAUI = 0x5, 1604 I40E_PHY_TYPE_XFI = 0x6, 1605 I40E_PHY_TYPE_SFI = 0x7, 1606 I40E_PHY_TYPE_XLAUI = 0x8, 1607 I40E_PHY_TYPE_XLPPI = 0x9, 1608 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1609 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1610 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1611 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1612 I40E_PHY_TYPE_100BASE_TX = 0x11, 1613 I40E_PHY_TYPE_1000BASE_T = 0x12, 1614 I40E_PHY_TYPE_10GBASE_T = 0x13, 1615 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1616 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1617 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1618 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1619 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1620 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1621 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1622 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1623 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1624 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1625 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1626 I40E_PHY_TYPE_MAX 1627}; 1628 1629#define I40E_LINK_SPEED_100MB_SHIFT 0x1 1630#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1631#define I40E_LINK_SPEED_10GB_SHIFT 0x3 1632#define I40E_LINK_SPEED_40GB_SHIFT 0x4 1633#define I40E_LINK_SPEED_20GB_SHIFT 0x5 1634 1635enum i40e_aq_link_speed { 1636 I40E_LINK_SPEED_UNKNOWN = 0, 1637 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1638 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1639 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1640 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1641 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) 1642}; 1643 1644struct i40e_aqc_module_desc { 1645 u8 oui[3]; 1646 u8 reserved1; 1647 u8 part_number[16]; 1648 u8 revision[4]; 1649 u8 reserved2[8]; 1650}; 1651 1652I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1653 1654struct i40e_aq_get_phy_abilities_resp { 1655 __le32 phy_type; /* bitmap using the above enum for offsets */ 1656 u8 link_speed; /* bitmap using the above enum bit patterns */ 1657 u8 abilities; 1658#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1659#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1660#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1661#define I40E_AQ_PHY_LINK_ENABLED 0x08 1662#define I40E_AQ_PHY_AN_ENABLED 0x10 1663#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1664 __le16 eee_capability; 1665#define I40E_AQ_EEE_100BASE_TX 0x0002 1666#define I40E_AQ_EEE_1000BASE_T 0x0004 1667#define I40E_AQ_EEE_10GBASE_T 0x0008 1668#define I40E_AQ_EEE_1000BASE_KX 0x0010 1669#define I40E_AQ_EEE_10GBASE_KX4 0x0020 1670#define I40E_AQ_EEE_10GBASE_KR 0x0040 1671 __le32 eeer_val; 1672 u8 d3_lpan; 1673#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1674 u8 reserved[3]; 1675 u8 phy_id[4]; 1676 u8 module_type[3]; 1677 u8 qualified_module_count; 1678#define I40E_AQ_PHY_MAX_QMS 16 1679 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1680}; 1681 1682I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1683 1684/* Set PHY Config (direct 0x0601) */ 1685struct i40e_aq_set_phy_config { /* same bits as above in all */ 1686 __le32 phy_type; 1687 u8 link_speed; 1688 u8 abilities; 1689/* bits 0-2 use the values from get_phy_abilities_resp */ 1690#define I40E_AQ_PHY_ENABLE_LINK 0x08 1691#define I40E_AQ_PHY_ENABLE_AN 0x10 1692#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1693 __le16 eee_capability; 1694 __le32 eeer; 1695 u8 low_power_ctrl; 1696 u8 reserved[3]; 1697}; 1698 1699I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1700 1701/* Set MAC Config command data structure (direct 0x0603) */ 1702struct i40e_aq_set_mac_config { 1703 __le16 max_frame_size; 1704 u8 params; 1705#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1706#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1707#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1708#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1709#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1710#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1711#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1712#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1713#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1714#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1715#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1716#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1717#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1718#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1719 u8 tx_timer_priority; /* bitmap */ 1720 __le16 tx_timer_value; 1721 __le16 fc_refresh_threshold; 1722 u8 reserved[8]; 1723}; 1724 1725I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1726 1727/* Restart Auto-Negotiation (direct 0x605) */ 1728struct i40e_aqc_set_link_restart_an { 1729 u8 command; 1730#define I40E_AQ_PHY_RESTART_AN 0x02 1731#define I40E_AQ_PHY_LINK_ENABLE 0x04 1732 u8 reserved[15]; 1733}; 1734 1735I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1736 1737/* Get Link Status cmd & response data structure (direct 0x0607) */ 1738struct i40e_aqc_get_link_status { 1739 __le16 command_flags; /* only field set on command */ 1740#define I40E_AQ_LSE_MASK 0x3 1741#define I40E_AQ_LSE_NOP 0x0 1742#define I40E_AQ_LSE_DISABLE 0x2 1743#define I40E_AQ_LSE_ENABLE 0x3 1744/* only response uses this flag */ 1745#define I40E_AQ_LSE_IS_ENABLED 0x1 1746 u8 phy_type; /* i40e_aq_phy_type */ 1747 u8 link_speed; /* i40e_aq_link_speed */ 1748 u8 link_info; 1749#define I40E_AQ_LINK_UP 0x01 /* obsolete */ 1750#define I40E_AQ_LINK_UP_FUNCTION 0x01 1751#define I40E_AQ_LINK_FAULT 0x02 1752#define I40E_AQ_LINK_FAULT_TX 0x04 1753#define I40E_AQ_LINK_FAULT_RX 0x08 1754#define I40E_AQ_LINK_FAULT_REMOTE 0x10 1755#define I40E_AQ_LINK_UP_PORT 0x20 1756#define I40E_AQ_MEDIA_AVAILABLE 0x40 1757#define I40E_AQ_SIGNAL_DETECT 0x80 1758 u8 an_info; 1759#define I40E_AQ_AN_COMPLETED 0x01 1760#define I40E_AQ_LP_AN_ABILITY 0x02 1761#define I40E_AQ_PD_FAULT 0x04 1762#define I40E_AQ_FEC_EN 0x08 1763#define I40E_AQ_PHY_LOW_POWER 0x10 1764#define I40E_AQ_LINK_PAUSE_TX 0x20 1765#define I40E_AQ_LINK_PAUSE_RX 0x40 1766#define I40E_AQ_QUALIFIED_MODULE 0x80 1767 u8 ext_info; 1768#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1769#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1770#define I40E_AQ_LINK_TX_SHIFT 0x02 1771#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1772#define I40E_AQ_LINK_TX_ACTIVE 0x00 1773#define I40E_AQ_LINK_TX_DRAINED 0x01 1774#define I40E_AQ_LINK_TX_FLUSHED 0x03 1775#define I40E_AQ_LINK_FORCED_40G 0x10 1776 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1777 __le16 max_frame_size; 1778 u8 config; 1779#define I40E_AQ_CONFIG_CRC_ENA 0x04 1780#define I40E_AQ_CONFIG_PACING_MASK 0x78 1781 u8 external_power_ability; 1782#define I40E_AQ_LINK_POWER_CLASS_1 0x00 1783#define I40E_AQ_LINK_POWER_CLASS_2 0x01 1784#define I40E_AQ_LINK_POWER_CLASS_3 0x02 1785#define I40E_AQ_LINK_POWER_CLASS_4 0x03 1786 u8 reserved[4]; 1787}; 1788 1789I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1790 1791/* Set event mask command (direct 0x613) */ 1792struct i40e_aqc_set_phy_int_mask { 1793 u8 reserved[8]; 1794 __le16 event_mask; 1795#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1796#define I40E_AQ_EVENT_MEDIA_NA 0x0004 1797#define I40E_AQ_EVENT_LINK_FAULT 0x0008 1798#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1799#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1800#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1801#define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1802#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1803#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1804 u8 reserved1[6]; 1805}; 1806 1807I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1808 1809/* Get Local AN advt register (direct 0x0614) 1810 * Set Local AN advt register (direct 0x0615) 1811 * Get Link Partner AN advt register (direct 0x0616) 1812 */ 1813struct i40e_aqc_an_advt_reg { 1814 __le32 local_an_reg0; 1815 __le16 local_an_reg1; 1816 u8 reserved[10]; 1817}; 1818 1819I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1820 1821/* Set Loopback mode (0x0618) */ 1822struct i40e_aqc_set_lb_mode { 1823 __le16 lb_mode; 1824#define I40E_AQ_LB_PHY_LOCAL 0x01 1825#define I40E_AQ_LB_PHY_REMOTE 0x02 1826#define I40E_AQ_LB_MAC_LOCAL 0x04 1827 u8 reserved[14]; 1828}; 1829 1830I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1831 1832/* Set PHY Debug command (0x0622) */ 1833struct i40e_aqc_set_phy_debug { 1834 u8 command_flags; 1835#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1836#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1837#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1838 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1839#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1840#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1841#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1842#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1843 u8 reserved[15]; 1844}; 1845 1846I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1847 1848enum i40e_aq_phy_reg_type { 1849 I40E_AQC_PHY_REG_INTERNAL = 0x1, 1850 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1851 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1852}; 1853 1854/* Run PHY Activity (0x0626) */ 1855struct i40e_aqc_run_phy_activity { 1856 __le16 activity_id; 1857 u8 flags; 1858 u8 reserved1; 1859 __le32 control; 1860 __le32 data; 1861 u8 reserved2[4]; 1862}; 1863 1864I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 1865 1866/* NVM Read command (indirect 0x0701) 1867 * NVM Erase commands (direct 0x0702) 1868 * NVM Update commands (indirect 0x0703) 1869 */ 1870struct i40e_aqc_nvm_update { 1871 u8 command_flags; 1872#define I40E_AQ_NVM_LAST_CMD 0x01 1873#define I40E_AQ_NVM_FLASH_ONLY 0x80 1874 u8 module_pointer; 1875 __le16 length; 1876 __le32 offset; 1877 __le32 addr_high; 1878 __le32 addr_low; 1879}; 1880 1881I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 1882 1883/* NVM Config Read (indirect 0x0704) */ 1884struct i40e_aqc_nvm_config_read { 1885 __le16 cmd_flags; 1886#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 1887#define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 1888#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 1889 __le16 element_count; 1890 __le16 element_id; /* Feature/field ID */ 1891 __le16 element_id_msw; /* MSWord of field ID */ 1892 __le32 address_high; 1893 __le32 address_low; 1894}; 1895 1896I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 1897 1898/* NVM Config Write (indirect 0x0705) */ 1899struct i40e_aqc_nvm_config_write { 1900 __le16 cmd_flags; 1901 __le16 element_count; 1902 u8 reserved[4]; 1903 __le32 address_high; 1904 __le32 address_low; 1905}; 1906 1907I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 1908 1909/* Used for 0x0704 as well as for 0x0705 commands */ 1910#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 1911#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 1912#define I40E_AQ_ANVM_FEATURE 0 1913#define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 1914struct i40e_aqc_nvm_config_data_feature { 1915 __le16 feature_id; 1916#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 1917#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 1918#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 1919 __le16 feature_options; 1920 __le16 feature_selection; 1921}; 1922 1923I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 1924 1925struct i40e_aqc_nvm_config_data_immediate_field { 1926 __le32 field_id; 1927 __le32 field_value; 1928 __le16 field_options; 1929 __le16 reserved; 1930}; 1931 1932I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 1933 1934/* OEM Post Update (indirect 0x0720) 1935 * no command data struct used 1936 */ 1937 struct i40e_aqc_nvm_oem_post_update { 1938#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 1939 u8 sel_data; 1940 u8 reserved[7]; 1941}; 1942 1943I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 1944 1945struct i40e_aqc_nvm_oem_post_update_buffer { 1946 u8 str_len; 1947 u8 dev_addr; 1948 __le16 eeprom_addr; 1949 u8 data[36]; 1950}; 1951 1952I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 1953 1954/* Thermal Sensor (indirect 0x0721) 1955 * read or set thermal sensor configs and values 1956 * takes a sensor and command specific data buffer, not detailed here 1957 */ 1958struct i40e_aqc_thermal_sensor { 1959 u8 sensor_action; 1960#define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 1961#define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 1962#define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 1963 u8 reserved[7]; 1964 __le32 addr_high; 1965 __le32 addr_low; 1966}; 1967 1968I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 1969 1970/* Send to PF command (indirect 0x0801) id is only used by PF 1971 * Send to VF command (indirect 0x0802) id is only used by PF 1972 * Send to Peer PF command (indirect 0x0803) 1973 */ 1974struct i40e_aqc_pf_vf_message { 1975 __le32 id; 1976 u8 reserved[4]; 1977 __le32 addr_high; 1978 __le32 addr_low; 1979}; 1980 1981I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 1982 1983/* Alternate structure */ 1984 1985/* Direct write (direct 0x0900) 1986 * Direct read (direct 0x0902) 1987 */ 1988struct i40e_aqc_alternate_write { 1989 __le32 address0; 1990 __le32 data0; 1991 __le32 address1; 1992 __le32 data1; 1993}; 1994 1995I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 1996 1997/* Indirect write (indirect 0x0901) 1998 * Indirect read (indirect 0x0903) 1999 */ 2000 2001struct i40e_aqc_alternate_ind_write { 2002 __le32 address; 2003 __le32 length; 2004 __le32 addr_high; 2005 __le32 addr_low; 2006}; 2007 2008I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 2009 2010/* Done alternate write (direct 0x0904) 2011 * uses i40e_aq_desc 2012 */ 2013struct i40e_aqc_alternate_write_done { 2014 __le16 cmd_flags; 2015#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 2016#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 2017#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 2018#define I40E_AQ_ALTERNATE_RESET_NEEDED 2 2019 u8 reserved[14]; 2020}; 2021 2022I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2023 2024/* Set OEM mode (direct 0x0905) */ 2025struct i40e_aqc_alternate_set_mode { 2026 __le32 mode; 2027#define I40E_AQ_ALTERNATE_MODE_NONE 0 2028#define I40E_AQ_ALTERNATE_MODE_OEM 1 2029 u8 reserved[12]; 2030}; 2031 2032I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2033 2034/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2035 2036/* async events 0x10xx */ 2037 2038/* Lan Queue Overflow Event (direct, 0x1001) */ 2039struct i40e_aqc_lan_overflow { 2040 __le32 prtdcb_rupto; 2041 __le32 otx_ctl; 2042 u8 reserved[8]; 2043}; 2044 2045I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2046 2047/* Get LLDP MIB (indirect 0x0A00) */ 2048struct i40e_aqc_lldp_get_mib { 2049 u8 type; 2050 u8 reserved1; 2051#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2052#define I40E_AQ_LLDP_MIB_LOCAL 0x0 2053#define I40E_AQ_LLDP_MIB_REMOTE 0x1 2054#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2055#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2056#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2057#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2058#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2059#define I40E_AQ_LLDP_TX_SHIFT 0x4 2060#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2061/* TX pause flags use I40E_AQ_LINK_TX_* above */ 2062 __le16 local_len; 2063 __le16 remote_len; 2064 u8 reserved2[2]; 2065 __le32 addr_high; 2066 __le32 addr_low; 2067}; 2068 2069I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2070 2071/* Configure LLDP MIB Change Event (direct 0x0A01) 2072 * also used for the event (with type in the command field) 2073 */ 2074struct i40e_aqc_lldp_update_mib { 2075 u8 command; 2076#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2077#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2078 u8 reserved[7]; 2079 __le32 addr_high; 2080 __le32 addr_low; 2081}; 2082 2083I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2084 2085/* Add LLDP TLV (indirect 0x0A02) 2086 * Delete LLDP TLV (indirect 0x0A04) 2087 */ 2088struct i40e_aqc_lldp_add_tlv { 2089 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2090 u8 reserved1[1]; 2091 __le16 len; 2092 u8 reserved2[4]; 2093 __le32 addr_high; 2094 __le32 addr_low; 2095}; 2096 2097I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2098 2099/* Update LLDP TLV (indirect 0x0A03) */ 2100struct i40e_aqc_lldp_update_tlv { 2101 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2102 u8 reserved; 2103 __le16 old_len; 2104 __le16 new_offset; 2105 __le16 new_len; 2106 __le32 addr_high; 2107 __le32 addr_low; 2108}; 2109 2110I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2111 2112/* Stop LLDP (direct 0x0A05) */ 2113struct i40e_aqc_lldp_stop { 2114 u8 command; 2115#define I40E_AQ_LLDP_AGENT_STOP 0x0 2116#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2117 u8 reserved[15]; 2118}; 2119 2120I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2121 2122/* Start LLDP (direct 0x0A06) */ 2123 2124struct i40e_aqc_lldp_start { 2125 u8 command; 2126#define I40E_AQ_LLDP_AGENT_START 0x1 2127 u8 reserved[15]; 2128}; 2129 2130I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2131 2132/* Get CEE DCBX Oper Config (0x0A07) 2133 * uses the generic descriptor struct 2134 * returns below as indirect response 2135 */ 2136 2137#define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2138#define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2139#define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2140#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2141#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2142#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2143 2144#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2145#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2146#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2147#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2148#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2149#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2150#define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2151#define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2152#define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2153#define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2154#define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2155#define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2156 2157/* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2158 * word boundary layout issues, which the Linux compilers silently deal 2159 * with by adding padding, making the actual struct larger than designed. 2160 * However, the FW compiler for the NIC is less lenient and complains 2161 * about the struct. Hence, the struct defined here has an extra byte in 2162 * fields reserved3 and reserved4 to directly acknowledge that padding, 2163 * and the new length is used in the length check macro. 2164 */ 2165struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2166 u8 reserved1; 2167 u8 oper_num_tc; 2168 u8 oper_prio_tc[4]; 2169 u8 reserved2; 2170 u8 oper_tc_bw[8]; 2171 u8 oper_pfc_en; 2172 u8 reserved3[2]; 2173 __le16 oper_app_prio; 2174 u8 reserved4[2]; 2175 __le16 tlv_status; 2176}; 2177 2178I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2179 2180struct i40e_aqc_get_cee_dcb_cfg_resp { 2181 u8 oper_num_tc; 2182 u8 oper_prio_tc[4]; 2183 u8 oper_tc_bw[8]; 2184 u8 oper_pfc_en; 2185 __le16 oper_app_prio; 2186 __le32 tlv_status; 2187 u8 reserved[12]; 2188}; 2189 2190I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2191 2192/* Set Local LLDP MIB (indirect 0x0A08) 2193 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2194 */ 2195struct i40e_aqc_lldp_set_local_mib { 2196#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2197#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \ 2198 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2199#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2200#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2201#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \ 2202 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2203#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2204 u8 type; 2205 u8 reserved0; 2206 __le16 length; 2207 u8 reserved1[4]; 2208 __le32 address_high; 2209 __le32 address_low; 2210}; 2211 2212I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2213 2214struct i40e_aqc_lldp_set_local_mib_resp { 2215#define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01 2216 u8 status; 2217 u8 reserved[15]; 2218}; 2219 2220I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp); 2221 2222/* Stop/Start LLDP Agent (direct 0x0A09) 2223 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2224 */ 2225struct i40e_aqc_lldp_stop_start_specific_agent { 2226#define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2227#define I40E_AQC_START_SPECIFIC_AGENT_MASK (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2228 u8 command; 2229 u8 reserved[15]; 2230}; 2231 2232I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2233 2234/* Add Udp Tunnel command and completion (direct 0x0B00) */ 2235struct i40e_aqc_add_udp_tunnel { 2236 __le16 udp_port; 2237 u8 reserved0[3]; 2238 u8 protocol_type; 2239#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2240#define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2241#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2242#define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2243 u8 reserved1[10]; 2244}; 2245 2246I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2247 2248struct i40e_aqc_add_udp_tunnel_completion { 2249 __le16 udp_port; 2250 u8 filter_entry_index; 2251 u8 multiple_pfs; 2252#define I40E_AQC_SINGLE_PF 0x0 2253#define I40E_AQC_MULTIPLE_PFS 0x1 2254 u8 total_filters; 2255 u8 reserved[11]; 2256}; 2257 2258I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2259 2260/* remove UDP Tunnel command (0x0B01) */ 2261struct i40e_aqc_remove_udp_tunnel { 2262 u8 reserved[2]; 2263 u8 index; /* 0 to 15 */ 2264 u8 reserved2[13]; 2265}; 2266 2267I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2268 2269struct i40e_aqc_del_udp_tunnel_completion { 2270 __le16 udp_port; 2271 u8 index; /* 0 to 15 */ 2272 u8 multiple_pfs; 2273 u8 total_filters_used; 2274 u8 reserved1[11]; 2275}; 2276 2277I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2278 2279/* tunnel key structure 0x0B10 */ 2280 2281struct i40e_aqc_tunnel_key_structure { 2282 u8 key1_off; 2283 u8 key2_off; 2284 u8 key1_len; /* 0 to 15 */ 2285 u8 key2_len; /* 0 to 15 */ 2286 u8 flags; 2287#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2288/* response flags */ 2289#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2290#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2291#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2292 u8 network_key_index; 2293#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2294#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2295#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2296#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2297 u8 reserved[10]; 2298}; 2299 2300I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2301 2302/* OEM mode commands (direct 0xFE0x) */ 2303struct i40e_aqc_oem_param_change { 2304 __le32 param_type; 2305#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2306#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2307#define I40E_AQ_OEM_PARAM_MAC 2 2308 __le32 param_value1; 2309 __le16 param_value2; 2310 u8 reserved[6]; 2311}; 2312 2313I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2314 2315struct i40e_aqc_oem_state_change { 2316 __le32 state; 2317#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2318#define I40E_AQ_OEM_STATE_LINK_UP 0x1 2319 u8 reserved[12]; 2320}; 2321 2322I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2323 2324/* Initialize OCSD (0xFE02, direct) */ 2325struct i40e_aqc_opc_oem_ocsd_initialize { 2326 u8 type_status; 2327 u8 reserved1[3]; 2328 __le32 ocsd_memory_block_addr_high; 2329 __le32 ocsd_memory_block_addr_low; 2330 __le32 requested_update_interval; 2331}; 2332 2333I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2334 2335/* Initialize OCBB (0xFE03, direct) */ 2336struct i40e_aqc_opc_oem_ocbb_initialize { 2337 u8 type_status; 2338 u8 reserved1[3]; 2339 __le32 ocbb_memory_block_addr_high; 2340 __le32 ocbb_memory_block_addr_low; 2341 u8 reserved2[4]; 2342}; 2343 2344I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2345 2346/* debug commands */ 2347 2348/* get device id (0xFF00) uses the generic structure */ 2349 2350/* set test more (0xFF01, internal) */ 2351 2352struct i40e_acq_set_test_mode { 2353 u8 mode; 2354#define I40E_AQ_TEST_PARTIAL 0 2355#define I40E_AQ_TEST_FULL 1 2356#define I40E_AQ_TEST_NVM 2 2357 u8 reserved[3]; 2358 u8 command; 2359#define I40E_AQ_TEST_OPEN 0 2360#define I40E_AQ_TEST_CLOSE 1 2361#define I40E_AQ_TEST_INC 2 2362 u8 reserved2[3]; 2363 __le32 address_high; 2364 __le32 address_low; 2365}; 2366 2367I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2368 2369/* Debug Read Register command (0xFF03) 2370 * Debug Write Register command (0xFF04) 2371 */ 2372struct i40e_aqc_debug_reg_read_write { 2373 __le32 reserved; 2374 __le32 address; 2375 __le32 value_high; 2376 __le32 value_low; 2377}; 2378 2379I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2380 2381/* Scatter/gather Reg Read (indirect 0xFF05) 2382 * Scatter/gather Reg Write (indirect 0xFF06) 2383 */ 2384 2385/* i40e_aq_desc is used for the command */ 2386struct i40e_aqc_debug_reg_sg_element_data { 2387 __le32 address; 2388 __le32 value; 2389}; 2390 2391/* Debug Modify register (direct 0xFF07) */ 2392struct i40e_aqc_debug_modify_reg { 2393 __le32 address; 2394 __le32 value; 2395 __le32 clear_mask; 2396 __le32 set_mask; 2397}; 2398 2399I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2400 2401/* dump internal data (0xFF08, indirect) */ 2402 2403#define I40E_AQ_CLUSTER_ID_AUX 0 2404#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2405#define I40E_AQ_CLUSTER_ID_TXSCHED 2 2406#define I40E_AQ_CLUSTER_ID_HMC 3 2407#define I40E_AQ_CLUSTER_ID_MAC0 4 2408#define I40E_AQ_CLUSTER_ID_MAC1 5 2409#define I40E_AQ_CLUSTER_ID_MAC2 6 2410#define I40E_AQ_CLUSTER_ID_MAC3 7 2411#define I40E_AQ_CLUSTER_ID_DCB 8 2412#define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2413#define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2414#define I40E_AQ_CLUSTER_ID_ALTRAM 11 2415 2416struct i40e_aqc_debug_dump_internals { 2417 u8 cluster_id; 2418 u8 table_id; 2419 __le16 data_size; 2420 __le32 idx; 2421 __le32 address_high; 2422 __le32 address_low; 2423}; 2424 2425I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2426 2427struct i40e_aqc_debug_modify_internals { 2428 u8 cluster_id; 2429 u8 cluster_specific_params[7]; 2430 __le32 address_high; 2431 __le32 address_low; 2432}; 2433 2434I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2435 2436#endif /* _I40E_ADMINQ_CMD_H_ */ 2437