i40e_adminq_cmd.h revision 299545
1/****************************************************************************** 2 3 Copyright (c) 2013-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/ixl/i40e_adminq_cmd.h 299545 2016-05-12 18:18:55Z erj $*/ 34 35#ifndef _I40E_ADMINQ_CMD_H_ 36#define _I40E_ADMINQ_CMD_H_ 37 38/* This header file defines the i40e Admin Queue commands and is shared between 39 * i40e Firmware and Software. 40 * 41 * This file needs to comply with the Linux Kernel coding style. 42 */ 43 44#define I40E_FW_API_VERSION_MAJOR 0x0001 45#define I40E_FW_API_VERSION_MINOR 0x0004 46 47struct i40e_aq_desc { 48 __le16 flags; 49 __le16 opcode; 50 __le16 datalen; 51 __le16 retval; 52 __le32 cookie_high; 53 __le32 cookie_low; 54 union { 55 struct { 56 __le32 param0; 57 __le32 param1; 58 __le32 param2; 59 __le32 param3; 60 } internal; 61 struct { 62 __le32 param0; 63 __le32 param1; 64 __le32 addr_high; 65 __le32 addr_low; 66 } external; 67 u8 raw[16]; 68 } params; 69}; 70 71/* Flags sub-structure 72 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 73 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 74 */ 75 76/* command flags and offsets*/ 77#define I40E_AQ_FLAG_DD_SHIFT 0 78#define I40E_AQ_FLAG_CMP_SHIFT 1 79#define I40E_AQ_FLAG_ERR_SHIFT 2 80#define I40E_AQ_FLAG_VFE_SHIFT 3 81#define I40E_AQ_FLAG_LB_SHIFT 9 82#define I40E_AQ_FLAG_RD_SHIFT 10 83#define I40E_AQ_FLAG_VFC_SHIFT 11 84#define I40E_AQ_FLAG_BUF_SHIFT 12 85#define I40E_AQ_FLAG_SI_SHIFT 13 86#define I40E_AQ_FLAG_EI_SHIFT 14 87#define I40E_AQ_FLAG_FE_SHIFT 15 88 89#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 90#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 91#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 92#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 93#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 94#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 95#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 96#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 97#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 98#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 99#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 100 101/* error codes */ 102enum i40e_admin_queue_err { 103 I40E_AQ_RC_OK = 0, /* success */ 104 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 105 I40E_AQ_RC_ENOENT = 2, /* No such element */ 106 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 107 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 108 I40E_AQ_RC_EIO = 5, /* I/O error */ 109 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 110 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 111 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 112 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 113 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 114 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 115 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 116 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 117 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 118 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 119 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 120 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 121 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 122 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 123 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 124 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 125 I40E_AQ_RC_EFBIG = 22, /* File too large */ 126}; 127 128/* Admin Queue command opcodes */ 129enum i40e_admin_queue_opc { 130 /* aq commands */ 131 i40e_aqc_opc_get_version = 0x0001, 132 i40e_aqc_opc_driver_version = 0x0002, 133 i40e_aqc_opc_queue_shutdown = 0x0003, 134 i40e_aqc_opc_set_pf_context = 0x0004, 135 136 /* resource ownership */ 137 i40e_aqc_opc_request_resource = 0x0008, 138 i40e_aqc_opc_release_resource = 0x0009, 139 140 i40e_aqc_opc_list_func_capabilities = 0x000A, 141 i40e_aqc_opc_list_dev_capabilities = 0x000B, 142 143 /* LAA */ 144 i40e_aqc_opc_mac_address_read = 0x0107, 145 i40e_aqc_opc_mac_address_write = 0x0108, 146 147 /* PXE */ 148 i40e_aqc_opc_clear_pxe_mode = 0x0110, 149 150 /* internal switch commands */ 151 i40e_aqc_opc_get_switch_config = 0x0200, 152 i40e_aqc_opc_add_statistics = 0x0201, 153 i40e_aqc_opc_remove_statistics = 0x0202, 154 i40e_aqc_opc_set_port_parameters = 0x0203, 155 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 156 157 i40e_aqc_opc_add_vsi = 0x0210, 158 i40e_aqc_opc_update_vsi_parameters = 0x0211, 159 i40e_aqc_opc_get_vsi_parameters = 0x0212, 160 161 i40e_aqc_opc_add_pv = 0x0220, 162 i40e_aqc_opc_update_pv_parameters = 0x0221, 163 i40e_aqc_opc_get_pv_parameters = 0x0222, 164 165 i40e_aqc_opc_add_veb = 0x0230, 166 i40e_aqc_opc_update_veb_parameters = 0x0231, 167 i40e_aqc_opc_get_veb_parameters = 0x0232, 168 169 i40e_aqc_opc_delete_element = 0x0243, 170 171 i40e_aqc_opc_add_macvlan = 0x0250, 172 i40e_aqc_opc_remove_macvlan = 0x0251, 173 i40e_aqc_opc_add_vlan = 0x0252, 174 i40e_aqc_opc_remove_vlan = 0x0253, 175 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 176 i40e_aqc_opc_add_tag = 0x0255, 177 i40e_aqc_opc_remove_tag = 0x0256, 178 i40e_aqc_opc_add_multicast_etag = 0x0257, 179 i40e_aqc_opc_remove_multicast_etag = 0x0258, 180 i40e_aqc_opc_update_tag = 0x0259, 181 i40e_aqc_opc_add_control_packet_filter = 0x025A, 182 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 183 i40e_aqc_opc_add_cloud_filters = 0x025C, 184 i40e_aqc_opc_remove_cloud_filters = 0x025D, 185 186 i40e_aqc_opc_add_mirror_rule = 0x0260, 187 i40e_aqc_opc_delete_mirror_rule = 0x0261, 188 189 /* DCB commands */ 190 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 191 i40e_aqc_opc_dcb_updated = 0x0302, 192 193 /* TX scheduler */ 194 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 195 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 196 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 197 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 198 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 199 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 200 201 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 202 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 203 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 204 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 205 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 206 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 207 i40e_aqc_opc_query_port_ets_config = 0x0419, 208 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 209 i40e_aqc_opc_suspend_port_tx = 0x041B, 210 i40e_aqc_opc_resume_port_tx = 0x041C, 211 i40e_aqc_opc_configure_partition_bw = 0x041D, 212 213 /* hmc */ 214 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 215 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 216 217 /* phy commands*/ 218 i40e_aqc_opc_get_phy_abilities = 0x0600, 219 i40e_aqc_opc_set_phy_config = 0x0601, 220 i40e_aqc_opc_set_mac_config = 0x0603, 221 i40e_aqc_opc_set_link_restart_an = 0x0605, 222 i40e_aqc_opc_get_link_status = 0x0607, 223 i40e_aqc_opc_set_phy_int_mask = 0x0613, 224 i40e_aqc_opc_get_local_advt_reg = 0x0614, 225 i40e_aqc_opc_set_local_advt_reg = 0x0615, 226 i40e_aqc_opc_get_partner_advt = 0x0616, 227 i40e_aqc_opc_set_lb_modes = 0x0618, 228 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 229 i40e_aqc_opc_set_phy_debug = 0x0622, 230 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 231 232 /* NVM commands */ 233 i40e_aqc_opc_nvm_read = 0x0701, 234 i40e_aqc_opc_nvm_erase = 0x0702, 235 i40e_aqc_opc_nvm_update = 0x0703, 236 i40e_aqc_opc_nvm_config_read = 0x0704, 237 i40e_aqc_opc_nvm_config_write = 0x0705, 238 i40e_aqc_opc_oem_post_update = 0x0720, 239 240 /* virtualization commands */ 241 i40e_aqc_opc_send_msg_to_pf = 0x0801, 242 i40e_aqc_opc_send_msg_to_vf = 0x0802, 243 i40e_aqc_opc_send_msg_to_peer = 0x0803, 244 245 /* alternate structure */ 246 i40e_aqc_opc_alternate_write = 0x0900, 247 i40e_aqc_opc_alternate_write_indirect = 0x0901, 248 i40e_aqc_opc_alternate_read = 0x0902, 249 i40e_aqc_opc_alternate_read_indirect = 0x0903, 250 i40e_aqc_opc_alternate_write_done = 0x0904, 251 i40e_aqc_opc_alternate_set_mode = 0x0905, 252 i40e_aqc_opc_alternate_clear_port = 0x0906, 253 254 /* LLDP commands */ 255 i40e_aqc_opc_lldp_get_mib = 0x0A00, 256 i40e_aqc_opc_lldp_update_mib = 0x0A01, 257 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 258 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 259 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 260 i40e_aqc_opc_lldp_stop = 0x0A05, 261 i40e_aqc_opc_lldp_start = 0x0A06, 262 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 263 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 264 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 265 266 /* Tunnel commands */ 267 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 268 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 269 270 /* Async Events */ 271 i40e_aqc_opc_event_lan_overflow = 0x1001, 272 273 /* OEM commands */ 274 i40e_aqc_opc_oem_parameter_change = 0xFE00, 275 i40e_aqc_opc_oem_device_status_change = 0xFE01, 276 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 277 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 278 279 /* debug commands */ 280 i40e_aqc_opc_debug_read_reg = 0xFF03, 281 i40e_aqc_opc_debug_write_reg = 0xFF04, 282 i40e_aqc_opc_debug_modify_reg = 0xFF07, 283 i40e_aqc_opc_debug_dump_internals = 0xFF08, 284}; 285 286/* command structures and indirect data structures */ 287 288/* Structure naming conventions: 289 * - no suffix for direct command descriptor structures 290 * - _data for indirect sent data 291 * - _resp for indirect return data (data which is both will use _data) 292 * - _completion for direct return data 293 * - _element_ for repeated elements (may also be _data or _resp) 294 * 295 * Command structures are expected to overlay the params.raw member of the basic 296 * descriptor, and as such cannot exceed 16 bytes in length. 297 */ 298 299/* This macro is used to generate a compilation error if a structure 300 * is not exactly the correct length. It gives a divide by zero error if the 301 * structure is not of the correct size, otherwise it creates an enum that is 302 * never used. 303 */ 304#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 305 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 306 307/* This macro is used extensively to ensure that command structures are 16 308 * bytes in length as they have to map to the raw array of that size. 309 */ 310#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 311 312/* internal (0x00XX) commands */ 313 314/* Get version (direct 0x0001) */ 315struct i40e_aqc_get_version { 316 __le32 rom_ver; 317 __le32 fw_build; 318 __le16 fw_major; 319 __le16 fw_minor; 320 __le16 api_major; 321 __le16 api_minor; 322}; 323 324I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 325 326/* Send driver version (indirect 0x0002) */ 327struct i40e_aqc_driver_version { 328 u8 driver_major_ver; 329 u8 driver_minor_ver; 330 u8 driver_build_ver; 331 u8 driver_subbuild_ver; 332 u8 reserved[4]; 333 __le32 address_high; 334 __le32 address_low; 335}; 336 337I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 338 339/* Queue Shutdown (direct 0x0003) */ 340struct i40e_aqc_queue_shutdown { 341 __le32 driver_unloading; 342#define I40E_AQ_DRIVER_UNLOADING 0x1 343 u8 reserved[12]; 344}; 345 346I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 347 348/* Set PF context (0x0004, direct) */ 349struct i40e_aqc_set_pf_context { 350 u8 pf_id; 351 u8 reserved[15]; 352}; 353 354I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 355 356/* Request resource ownership (direct 0x0008) 357 * Release resource ownership (direct 0x0009) 358 */ 359#define I40E_AQ_RESOURCE_NVM 1 360#define I40E_AQ_RESOURCE_SDP 2 361#define I40E_AQ_RESOURCE_ACCESS_READ 1 362#define I40E_AQ_RESOURCE_ACCESS_WRITE 2 363#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 364#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 365 366struct i40e_aqc_request_resource { 367 __le16 resource_id; 368 __le16 access_type; 369 __le32 timeout; 370 __le32 resource_number; 371 u8 reserved[4]; 372}; 373 374I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 375 376/* Get function capabilities (indirect 0x000A) 377 * Get device capabilities (indirect 0x000B) 378 */ 379struct i40e_aqc_list_capabilites { 380 u8 command_flags; 381#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 382 u8 pf_index; 383 u8 reserved[2]; 384 __le32 count; 385 __le32 addr_high; 386 __le32 addr_low; 387}; 388 389I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 390 391struct i40e_aqc_list_capabilities_element_resp { 392 __le16 id; 393 u8 major_rev; 394 u8 minor_rev; 395 __le32 number; 396 __le32 logical_id; 397 __le32 phys_id; 398 u8 reserved[16]; 399}; 400 401/* list of caps */ 402 403#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 404#define I40E_AQ_CAP_ID_MNG_MODE 0x0002 405#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 406#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 407#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 408#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 409#define I40E_AQ_CAP_ID_SRIOV 0x0012 410#define I40E_AQ_CAP_ID_VF 0x0013 411#define I40E_AQ_CAP_ID_VMDQ 0x0014 412#define I40E_AQ_CAP_ID_8021QBG 0x0015 413#define I40E_AQ_CAP_ID_8021QBR 0x0016 414#define I40E_AQ_CAP_ID_VSI 0x0017 415#define I40E_AQ_CAP_ID_DCB 0x0018 416#define I40E_AQ_CAP_ID_FCOE 0x0021 417#define I40E_AQ_CAP_ID_ISCSI 0x0022 418#define I40E_AQ_CAP_ID_RSS 0x0040 419#define I40E_AQ_CAP_ID_RXQ 0x0041 420#define I40E_AQ_CAP_ID_TXQ 0x0042 421#define I40E_AQ_CAP_ID_MSIX 0x0043 422#define I40E_AQ_CAP_ID_VF_MSIX 0x0044 423#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 424#define I40E_AQ_CAP_ID_1588 0x0046 425#define I40E_AQ_CAP_ID_IWARP 0x0051 426#define I40E_AQ_CAP_ID_LED 0x0061 427#define I40E_AQ_CAP_ID_SDP 0x0062 428#define I40E_AQ_CAP_ID_MDIO 0x0063 429#define I40E_AQ_CAP_ID_FLEX10 0x00F1 430#define I40E_AQ_CAP_ID_CEM 0x00F2 431 432/* Set CPPM Configuration (direct 0x0103) */ 433struct i40e_aqc_cppm_configuration { 434 __le16 command_flags; 435#define I40E_AQ_CPPM_EN_LTRC 0x0800 436#define I40E_AQ_CPPM_EN_DMCTH 0x1000 437#define I40E_AQ_CPPM_EN_DMCTLX 0x2000 438#define I40E_AQ_CPPM_EN_HPTC 0x4000 439#define I40E_AQ_CPPM_EN_DMARC 0x8000 440 __le16 ttlx; 441 __le32 dmacr; 442 __le16 dmcth; 443 u8 hptc; 444 u8 reserved; 445 __le32 pfltrc; 446}; 447 448I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 449 450/* Set ARP Proxy command / response (indirect 0x0104) */ 451struct i40e_aqc_arp_proxy_data { 452 __le16 command_flags; 453#define I40E_AQ_ARP_INIT_IPV4 0x0008 454#define I40E_AQ_ARP_UNSUP_CTL 0x0010 455#define I40E_AQ_ARP_ENA 0x0020 456#define I40E_AQ_ARP_ADD_IPV4 0x0040 457#define I40E_AQ_ARP_DEL_IPV4 0x0080 458 __le16 table_id; 459 __le32 pfpm_proxyfc; 460 __le32 ip_addr; 461 u8 mac_addr[6]; 462 u8 reserved[2]; 463}; 464 465I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 466 467/* Set NS Proxy Table Entry Command (indirect 0x0105) */ 468struct i40e_aqc_ns_proxy_data { 469 __le16 table_idx_mac_addr_0; 470 __le16 table_idx_mac_addr_1; 471 __le16 table_idx_ipv6_0; 472 __le16 table_idx_ipv6_1; 473 __le16 control; 474#define I40E_AQ_NS_PROXY_ADD_0 0x0100 475#define I40E_AQ_NS_PROXY_DEL_0 0x0200 476#define I40E_AQ_NS_PROXY_ADD_1 0x0400 477#define I40E_AQ_NS_PROXY_DEL_1 0x0800 478#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 479#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 480#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 481#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 482#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 483#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 484#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 485 u8 mac_addr_0[6]; 486 u8 mac_addr_1[6]; 487 u8 local_mac_addr[6]; 488 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 489 u8 ipv6_addr_1[16]; 490}; 491 492I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 493 494/* Manage LAA Command (0x0106) - obsolete */ 495struct i40e_aqc_mng_laa { 496 __le16 command_flags; 497#define I40E_AQ_LAA_FLAG_WR 0x8000 498 u8 reserved[2]; 499 __le32 sal; 500 __le16 sah; 501 u8 reserved2[6]; 502}; 503 504I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 505 506/* Manage MAC Address Read Command (indirect 0x0107) */ 507struct i40e_aqc_mac_address_read { 508 __le16 command_flags; 509#define I40E_AQC_LAN_ADDR_VALID 0x10 510#define I40E_AQC_SAN_ADDR_VALID 0x20 511#define I40E_AQC_PORT_ADDR_VALID 0x40 512#define I40E_AQC_WOL_ADDR_VALID 0x80 513#define I40E_AQC_MC_MAG_EN_VALID 0x100 514#define I40E_AQC_ADDR_VALID_MASK 0x1F0 515 u8 reserved[6]; 516 __le32 addr_high; 517 __le32 addr_low; 518}; 519 520I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 521 522struct i40e_aqc_mac_address_read_data { 523 u8 pf_lan_mac[6]; 524 u8 pf_san_mac[6]; 525 u8 port_mac[6]; 526 u8 pf_wol_mac[6]; 527}; 528 529I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 530 531/* Manage MAC Address Write Command (0x0108) */ 532struct i40e_aqc_mac_address_write { 533 __le16 command_flags; 534#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 535#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 536#define I40E_AQC_WRITE_TYPE_PORT 0x8000 537#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 538#define I40E_AQC_WRITE_TYPE_MASK 0xC000 539 540 __le16 mac_sah; 541 __le32 mac_sal; 542 u8 reserved[8]; 543}; 544 545I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 546 547/* PXE commands (0x011x) */ 548 549/* Clear PXE Command and response (direct 0x0110) */ 550struct i40e_aqc_clear_pxe { 551 u8 rx_cnt; 552 u8 reserved[15]; 553}; 554 555I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 556 557/* Switch configuration commands (0x02xx) */ 558 559/* Used by many indirect commands that only pass an seid and a buffer in the 560 * command 561 */ 562struct i40e_aqc_switch_seid { 563 __le16 seid; 564 u8 reserved[6]; 565 __le32 addr_high; 566 __le32 addr_low; 567}; 568 569I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 570 571/* Get Switch Configuration command (indirect 0x0200) 572 * uses i40e_aqc_switch_seid for the descriptor 573 */ 574struct i40e_aqc_get_switch_config_header_resp { 575 __le16 num_reported; 576 __le16 num_total; 577 u8 reserved[12]; 578}; 579 580I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 581 582struct i40e_aqc_switch_config_element_resp { 583 u8 element_type; 584#define I40E_AQ_SW_ELEM_TYPE_MAC 1 585#define I40E_AQ_SW_ELEM_TYPE_PF 2 586#define I40E_AQ_SW_ELEM_TYPE_VF 3 587#define I40E_AQ_SW_ELEM_TYPE_EMP 4 588#define I40E_AQ_SW_ELEM_TYPE_BMC 5 589#define I40E_AQ_SW_ELEM_TYPE_PV 16 590#define I40E_AQ_SW_ELEM_TYPE_VEB 17 591#define I40E_AQ_SW_ELEM_TYPE_PA 18 592#define I40E_AQ_SW_ELEM_TYPE_VSI 19 593 u8 revision; 594#define I40E_AQ_SW_ELEM_REV_1 1 595 __le16 seid; 596 __le16 uplink_seid; 597 __le16 downlink_seid; 598 u8 reserved[3]; 599 u8 connection_type; 600#define I40E_AQ_CONN_TYPE_REGULAR 0x1 601#define I40E_AQ_CONN_TYPE_DEFAULT 0x2 602#define I40E_AQ_CONN_TYPE_CASCADED 0x3 603 __le16 scheduler_id; 604 __le16 element_info; 605}; 606 607I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 608 609/* Get Switch Configuration (indirect 0x0200) 610 * an array of elements are returned in the response buffer 611 * the first in the array is the header, remainder are elements 612 */ 613struct i40e_aqc_get_switch_config_resp { 614 struct i40e_aqc_get_switch_config_header_resp header; 615 struct i40e_aqc_switch_config_element_resp element[1]; 616}; 617 618I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 619 620/* Add Statistics (direct 0x0201) 621 * Remove Statistics (direct 0x0202) 622 */ 623struct i40e_aqc_add_remove_statistics { 624 __le16 seid; 625 __le16 vlan; 626 __le16 stat_index; 627 u8 reserved[10]; 628}; 629 630I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 631 632/* Set Port Parameters command (direct 0x0203) */ 633struct i40e_aqc_set_port_parameters { 634 __le16 command_flags; 635#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 636#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 637#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 638 __le16 bad_frame_vsi; 639 __le16 default_seid; /* reserved for command */ 640 u8 reserved[10]; 641}; 642 643I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 644 645/* Get Switch Resource Allocation (indirect 0x0204) */ 646struct i40e_aqc_get_switch_resource_alloc { 647 u8 num_entries; /* reserved for command */ 648 u8 reserved[7]; 649 __le32 addr_high; 650 __le32 addr_low; 651}; 652 653I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 654 655/* expect an array of these structs in the response buffer */ 656struct i40e_aqc_switch_resource_alloc_element_resp { 657 u8 resource_type; 658#define I40E_AQ_RESOURCE_TYPE_VEB 0x0 659#define I40E_AQ_RESOURCE_TYPE_VSI 0x1 660#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 661#define I40E_AQ_RESOURCE_TYPE_STAG 0x3 662#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 663#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 664#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 665#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 666#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 667#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 668#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 669#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 670#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 671#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 672#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 673#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 674#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 675#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 676#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 677 u8 reserved1; 678 __le16 guaranteed; 679 __le16 total; 680 __le16 used; 681 __le16 total_unalloced; 682 u8 reserved2[6]; 683}; 684 685I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 686 687/* Add VSI (indirect 0x0210) 688 * this indirect command uses struct i40e_aqc_vsi_properties_data 689 * as the indirect buffer (128 bytes) 690 * 691 * Update VSI (indirect 0x211) 692 * uses the same data structure as Add VSI 693 * 694 * Get VSI (indirect 0x0212) 695 * uses the same completion and data structure as Add VSI 696 */ 697struct i40e_aqc_add_get_update_vsi { 698 __le16 uplink_seid; 699 u8 connection_type; 700#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 701#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 702#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 703 u8 reserved1; 704 u8 vf_id; 705 u8 reserved2; 706 __le16 vsi_flags; 707#define I40E_AQ_VSI_TYPE_SHIFT 0x0 708#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 709#define I40E_AQ_VSI_TYPE_VF 0x0 710#define I40E_AQ_VSI_TYPE_VMDQ2 0x1 711#define I40E_AQ_VSI_TYPE_PF 0x2 712#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 713#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 714 __le32 addr_high; 715 __le32 addr_low; 716}; 717 718I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 719 720struct i40e_aqc_add_get_update_vsi_completion { 721 __le16 seid; 722 __le16 vsi_number; 723 __le16 vsi_used; 724 __le16 vsi_free; 725 __le32 addr_high; 726 __le32 addr_low; 727}; 728 729I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 730 731struct i40e_aqc_vsi_properties_data { 732 /* first 96 byte are written by SW */ 733 __le16 valid_sections; 734#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 735#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 736#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 737#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 738#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 739#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 740#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 741#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 742#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 743#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 744 /* switch section */ 745 __le16 switch_id; /* 12bit id combined with flags below */ 746#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 747#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 748#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 749#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 750#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 751 u8 sw_reserved[2]; 752 /* security section */ 753 u8 sec_flags; 754#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 755#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 756#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 757 u8 sec_reserved; 758 /* VLAN section */ 759 __le16 pvid; /* VLANS include priority bits */ 760 __le16 fcoe_pvid; 761 u8 port_vlan_flags; 762#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 763#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 764 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 765#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 766#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 767#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 768#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 769#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 770#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 771 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 772#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 773#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 774#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 775#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 776 u8 pvlan_reserved[3]; 777 /* ingress egress up sections */ 778 __le32 ingress_table; /* bitmap, 3 bits per up */ 779#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 780#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 781 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 782#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 783#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 784 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 785#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 786#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 787 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 788#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 789#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 790 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 791#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 792#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 793 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 794#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 795#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 796 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 797#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 798#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 799 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 800#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 801#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 802 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 803 __le32 egress_table; /* same defines as for ingress table */ 804 /* cascaded PV section */ 805 __le16 cas_pv_tag; 806 u8 cas_pv_flags; 807#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 808#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 809 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 810#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 811#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 812#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 813#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 814#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 815#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 816 u8 cas_pv_reserved; 817 /* queue mapping section */ 818 __le16 mapping_flags; 819#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 820#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 821 __le16 queue_mapping[16]; 822#define I40E_AQ_VSI_QUEUE_SHIFT 0x0 823#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 824 __le16 tc_mapping[8]; 825#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 826#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 827 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 828#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 829#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 830 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 831 /* queueing option section */ 832 u8 queueing_opt_flags; 833#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 834#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 835 u8 queueing_opt_reserved[3]; 836 /* scheduler section */ 837 u8 up_enable_bits; 838 u8 sched_reserved; 839 /* outer up section */ 840 __le32 outer_up_table; /* same structure and defines as ingress table */ 841 u8 cmd_reserved[8]; 842 /* last 32 bytes are written by FW */ 843 __le16 qs_handle[8]; 844#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 845 __le16 stat_counter_idx; 846 __le16 sched_id; 847 u8 resp_reserved[12]; 848}; 849 850I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 851 852/* Add Port Virtualizer (direct 0x0220) 853 * also used for update PV (direct 0x0221) but only flags are used 854 * (IS_CTRL_PORT only works on add PV) 855 */ 856struct i40e_aqc_add_update_pv { 857 __le16 command_flags; 858#define I40E_AQC_PV_FLAG_PV_TYPE 0x1 859#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 860#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 861#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 862 __le16 uplink_seid; 863 __le16 connected_seid; 864 u8 reserved[10]; 865}; 866 867I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 868 869struct i40e_aqc_add_update_pv_completion { 870 /* reserved for update; for add also encodes error if rc == ENOSPC */ 871 __le16 pv_seid; 872#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 873#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 874#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 875#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 876 u8 reserved[14]; 877}; 878 879I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 880 881/* Get PV Params (direct 0x0222) 882 * uses i40e_aqc_switch_seid for the descriptor 883 */ 884 885struct i40e_aqc_get_pv_params_completion { 886 __le16 seid; 887 __le16 default_stag; 888 __le16 pv_flags; /* same flags as add_pv */ 889#define I40E_AQC_GET_PV_PV_TYPE 0x1 890#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 891#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 892 u8 reserved[8]; 893 __le16 default_port_seid; 894}; 895 896I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 897 898/* Add VEB (direct 0x0230) */ 899struct i40e_aqc_add_veb { 900 __le16 uplink_seid; 901 __le16 downlink_seid; 902 __le16 veb_flags; 903#define I40E_AQC_ADD_VEB_FLOATING 0x1 904#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 905#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 906 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 907#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 908#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 909#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 910 u8 enable_tcs; 911 u8 reserved[9]; 912}; 913 914I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 915 916struct i40e_aqc_add_veb_completion { 917 u8 reserved[6]; 918 __le16 switch_seid; 919 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 920 __le16 veb_seid; 921#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 922#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 923#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 924#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 925 __le16 statistic_index; 926 __le16 vebs_used; 927 __le16 vebs_free; 928}; 929 930I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 931 932/* Get VEB Parameters (direct 0x0232) 933 * uses i40e_aqc_switch_seid for the descriptor 934 */ 935struct i40e_aqc_get_veb_parameters_completion { 936 __le16 seid; 937 __le16 switch_id; 938 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 939 __le16 statistic_index; 940 __le16 vebs_used; 941 __le16 vebs_free; 942 u8 reserved[4]; 943}; 944 945I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 946 947/* Delete Element (direct 0x0243) 948 * uses the generic i40e_aqc_switch_seid 949 */ 950 951/* Add MAC-VLAN (indirect 0x0250) */ 952 953/* used for the command for most vlan commands */ 954struct i40e_aqc_macvlan { 955 __le16 num_addresses; 956 __le16 seid[3]; 957#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 958#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 959 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 960#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 961 __le32 addr_high; 962 __le32 addr_low; 963}; 964 965I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 966 967/* indirect data for command and response */ 968struct i40e_aqc_add_macvlan_element_data { 969 u8 mac_addr[6]; 970 __le16 vlan_tag; 971 __le16 flags; 972#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 973#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 974#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 975#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 976 __le16 queue_number; 977#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 978#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 979 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 980 /* response section */ 981 u8 match_method; 982#define I40E_AQC_MM_PERFECT_MATCH 0x01 983#define I40E_AQC_MM_HASH_MATCH 0x02 984#define I40E_AQC_MM_ERR_NO_RES 0xFF 985 u8 reserved1[3]; 986}; 987 988struct i40e_aqc_add_remove_macvlan_completion { 989 __le16 perfect_mac_used; 990 __le16 perfect_mac_free; 991 __le16 unicast_hash_free; 992 __le16 multicast_hash_free; 993 __le32 addr_high; 994 __le32 addr_low; 995}; 996 997I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 998 999/* Remove MAC-VLAN (indirect 0x0251) 1000 * uses i40e_aqc_macvlan for the descriptor 1001 * data points to an array of num_addresses of elements 1002 */ 1003 1004struct i40e_aqc_remove_macvlan_element_data { 1005 u8 mac_addr[6]; 1006 __le16 vlan_tag; 1007 u8 flags; 1008#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1009#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1010#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1011#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1012 u8 reserved[3]; 1013 /* reply section */ 1014 u8 error_code; 1015#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1016#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1017 u8 reply_reserved[3]; 1018}; 1019 1020/* Add VLAN (indirect 0x0252) 1021 * Remove VLAN (indirect 0x0253) 1022 * use the generic i40e_aqc_macvlan for the command 1023 */ 1024struct i40e_aqc_add_remove_vlan_element_data { 1025 __le16 vlan_tag; 1026 u8 vlan_flags; 1027/* flags for add VLAN */ 1028#define I40E_AQC_ADD_VLAN_LOCAL 0x1 1029#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1030#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1031#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1032#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1033#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1034#define I40E_AQC_VLAN_PTYPE_SHIFT 3 1035#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1036#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1037#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1038#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1039#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1040/* flags for remove VLAN */ 1041#define I40E_AQC_REMOVE_VLAN_ALL 0x1 1042 u8 reserved; 1043 u8 result; 1044/* flags for add VLAN */ 1045#define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1046#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1047#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1048/* flags for remove VLAN */ 1049#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1050#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1051 u8 reserved1[3]; 1052}; 1053 1054struct i40e_aqc_add_remove_vlan_completion { 1055 u8 reserved[4]; 1056 __le16 vlans_used; 1057 __le16 vlans_free; 1058 __le32 addr_high; 1059 __le32 addr_low; 1060}; 1061 1062/* Set VSI Promiscuous Modes (direct 0x0254) */ 1063struct i40e_aqc_set_vsi_promiscuous_modes { 1064 __le16 promiscuous_flags; 1065 __le16 valid_flags; 1066/* flags used for both fields above */ 1067#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1068#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1069#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1070#define I40E_AQC_SET_VSI_DEFAULT 0x08 1071#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1072 __le16 seid; 1073#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1074 __le16 vlan_tag; 1075#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1076#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1077 u8 reserved[8]; 1078}; 1079 1080I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1081 1082/* Add S/E-tag command (direct 0x0255) 1083 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1084 */ 1085struct i40e_aqc_add_tag { 1086 __le16 flags; 1087#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1088 __le16 seid; 1089#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1090#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1091 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1092 __le16 tag; 1093 __le16 queue_number; 1094 u8 reserved[8]; 1095}; 1096 1097I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1098 1099struct i40e_aqc_add_remove_tag_completion { 1100 u8 reserved[12]; 1101 __le16 tags_used; 1102 __le16 tags_free; 1103}; 1104 1105I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1106 1107/* Remove S/E-tag command (direct 0x0256) 1108 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1109 */ 1110struct i40e_aqc_remove_tag { 1111 __le16 seid; 1112#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1113#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1114 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1115 __le16 tag; 1116 u8 reserved[12]; 1117}; 1118 1119I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1120 1121/* Add multicast E-Tag (direct 0x0257) 1122 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1123 * and no external data 1124 */ 1125struct i40e_aqc_add_remove_mcast_etag { 1126 __le16 pv_seid; 1127 __le16 etag; 1128 u8 num_unicast_etags; 1129 u8 reserved[3]; 1130 __le32 addr_high; /* address of array of 2-byte s-tags */ 1131 __le32 addr_low; 1132}; 1133 1134I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1135 1136struct i40e_aqc_add_remove_mcast_etag_completion { 1137 u8 reserved[4]; 1138 __le16 mcast_etags_used; 1139 __le16 mcast_etags_free; 1140 __le32 addr_high; 1141 __le32 addr_low; 1142 1143}; 1144 1145I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1146 1147/* Update S/E-Tag (direct 0x0259) */ 1148struct i40e_aqc_update_tag { 1149 __le16 seid; 1150#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1151#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1152 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1153 __le16 old_tag; 1154 __le16 new_tag; 1155 u8 reserved[10]; 1156}; 1157 1158I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1159 1160struct i40e_aqc_update_tag_completion { 1161 u8 reserved[12]; 1162 __le16 tags_used; 1163 __le16 tags_free; 1164}; 1165 1166I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1167 1168/* Add Control Packet filter (direct 0x025A) 1169 * Remove Control Packet filter (direct 0x025B) 1170 * uses the i40e_aqc_add_oveb_cloud, 1171 * and the generic direct completion structure 1172 */ 1173struct i40e_aqc_add_remove_control_packet_filter { 1174 u8 mac[6]; 1175 __le16 etype; 1176 __le16 flags; 1177#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1178#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1179#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1180#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1181#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1182 __le16 seid; 1183#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1184#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1185 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1186 __le16 queue; 1187 u8 reserved[2]; 1188}; 1189 1190I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1191 1192struct i40e_aqc_add_remove_control_packet_filter_completion { 1193 __le16 mac_etype_used; 1194 __le16 etype_used; 1195 __le16 mac_etype_free; 1196 __le16 etype_free; 1197 u8 reserved[8]; 1198}; 1199 1200I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1201 1202/* Add Cloud filters (indirect 0x025C) 1203 * Remove Cloud filters (indirect 0x025D) 1204 * uses the i40e_aqc_add_remove_cloud_filters, 1205 * and the generic indirect completion structure 1206 */ 1207struct i40e_aqc_add_remove_cloud_filters { 1208 u8 num_filters; 1209 u8 reserved; 1210 __le16 seid; 1211#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1212#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1213 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1214 u8 reserved2[4]; 1215 __le32 addr_high; 1216 __le32 addr_low; 1217}; 1218 1219I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1220 1221struct i40e_aqc_add_remove_cloud_filters_element_data { 1222 u8 outer_mac[6]; 1223 u8 inner_mac[6]; 1224 __le16 inner_vlan; 1225 union { 1226 struct { 1227 u8 reserved[12]; 1228 u8 data[4]; 1229 } v4; 1230 struct { 1231 u8 data[16]; 1232 } v6; 1233 } ipaddr; 1234 __le16 flags; 1235#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1236#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1237 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1238/* 0x0000 reserved */ 1239#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1240/* 0x0002 reserved */ 1241#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1242#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1243/* 0x0005 reserved */ 1244#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1245/* 0x0007 reserved */ 1246/* 0x0008 reserved */ 1247#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1248#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1249#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1250#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1251 1252#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1253#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1254#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1255#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1256#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1257 1258#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1259#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1260#define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0 1261#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1262#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2 1263#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1264 1265 __le32 tenant_id; 1266 u8 reserved[4]; 1267 __le16 queue_number; 1268#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1269#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1270 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1271 u8 reserved2[14]; 1272 /* response section */ 1273 u8 allocation_result; 1274#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1275#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1276 u8 response_reserved[7]; 1277}; 1278 1279struct i40e_aqc_remove_cloud_filters_completion { 1280 __le16 perfect_ovlan_used; 1281 __le16 perfect_ovlan_free; 1282 __le16 vlan_used; 1283 __le16 vlan_free; 1284 __le32 addr_high; 1285 __le32 addr_low; 1286}; 1287 1288I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1289 1290/* Add Mirror Rule (indirect or direct 0x0260) 1291 * Delete Mirror Rule (indirect or direct 0x0261) 1292 * note: some rule types (4,5) do not use an external buffer. 1293 * take care to set the flags correctly. 1294 */ 1295struct i40e_aqc_add_delete_mirror_rule { 1296 __le16 seid; 1297 __le16 rule_type; 1298#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1299#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1300 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1301#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1302#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1303#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1304#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1305#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1306 __le16 num_entries; 1307 __le16 destination; /* VSI for add, rule id for delete */ 1308 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1309 __le32 addr_low; 1310}; 1311 1312I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1313 1314struct i40e_aqc_add_delete_mirror_rule_completion { 1315 u8 reserved[2]; 1316 __le16 rule_id; /* only used on add */ 1317 __le16 mirror_rules_used; 1318 __le16 mirror_rules_free; 1319 __le32 addr_high; 1320 __le32 addr_low; 1321}; 1322 1323I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1324 1325/* DCB 0x03xx*/ 1326 1327/* PFC Ignore (direct 0x0301) 1328 * the command and response use the same descriptor structure 1329 */ 1330struct i40e_aqc_pfc_ignore { 1331 u8 tc_bitmap; 1332 u8 command_flags; /* unused on response */ 1333#define I40E_AQC_PFC_IGNORE_SET 0x80 1334#define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1335 u8 reserved[14]; 1336}; 1337 1338I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1339 1340/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1341 * with no parameters 1342 */ 1343 1344/* TX scheduler 0x04xx */ 1345 1346/* Almost all the indirect commands use 1347 * this generic struct to pass the SEID in param0 1348 */ 1349struct i40e_aqc_tx_sched_ind { 1350 __le16 vsi_seid; 1351 u8 reserved[6]; 1352 __le32 addr_high; 1353 __le32 addr_low; 1354}; 1355 1356I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1357 1358/* Several commands respond with a set of queue set handles */ 1359struct i40e_aqc_qs_handles_resp { 1360 __le16 qs_handles[8]; 1361}; 1362 1363/* Configure VSI BW limits (direct 0x0400) */ 1364struct i40e_aqc_configure_vsi_bw_limit { 1365 __le16 vsi_seid; 1366 u8 reserved[2]; 1367 __le16 credit; 1368 u8 reserved1[2]; 1369 u8 max_credit; /* 0-3, limit = 2^max */ 1370 u8 reserved2[7]; 1371}; 1372 1373I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1374 1375/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1376 * responds with i40e_aqc_qs_handles_resp 1377 */ 1378struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1379 u8 tc_valid_bits; 1380 u8 reserved[15]; 1381 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1382 1383 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1384 __le16 tc_bw_max[2]; 1385 u8 reserved1[28]; 1386}; 1387 1388I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1389 1390/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1391 * responds with i40e_aqc_qs_handles_resp 1392 */ 1393struct i40e_aqc_configure_vsi_tc_bw_data { 1394 u8 tc_valid_bits; 1395 u8 reserved[3]; 1396 u8 tc_bw_credits[8]; 1397 u8 reserved1[4]; 1398 __le16 qs_handles[8]; 1399}; 1400 1401I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1402 1403/* Query vsi bw configuration (indirect 0x0408) */ 1404struct i40e_aqc_query_vsi_bw_config_resp { 1405 u8 tc_valid_bits; 1406 u8 tc_suspended_bits; 1407 u8 reserved[14]; 1408 __le16 qs_handles[8]; 1409 u8 reserved1[4]; 1410 __le16 port_bw_limit; 1411 u8 reserved2[2]; 1412 u8 max_bw; /* 0-3, limit = 2^max */ 1413 u8 reserved3[23]; 1414}; 1415 1416I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1417 1418/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1419struct i40e_aqc_query_vsi_ets_sla_config_resp { 1420 u8 tc_valid_bits; 1421 u8 reserved[3]; 1422 u8 share_credits[8]; 1423 __le16 credits[8]; 1424 1425 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1426 __le16 tc_bw_max[2]; 1427}; 1428 1429I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1430 1431/* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1432struct i40e_aqc_configure_switching_comp_bw_limit { 1433 __le16 seid; 1434 u8 reserved[2]; 1435 __le16 credit; 1436 u8 reserved1[2]; 1437 u8 max_bw; /* 0-3, limit = 2^max */ 1438 u8 reserved2[7]; 1439}; 1440 1441I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1442 1443/* Enable Physical Port ETS (indirect 0x0413) 1444 * Modify Physical Port ETS (indirect 0x0414) 1445 * Disable Physical Port ETS (indirect 0x0415) 1446 */ 1447struct i40e_aqc_configure_switching_comp_ets_data { 1448 u8 reserved[4]; 1449 u8 tc_valid_bits; 1450 u8 seepage; 1451#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1452 u8 tc_strict_priority_flags; 1453 u8 reserved1[17]; 1454 u8 tc_bw_share_credits[8]; 1455 u8 reserved2[96]; 1456}; 1457 1458I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1459 1460/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1461struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1462 u8 tc_valid_bits; 1463 u8 reserved[15]; 1464 __le16 tc_bw_credit[8]; 1465 1466 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1467 __le16 tc_bw_max[2]; 1468 u8 reserved1[28]; 1469}; 1470 1471I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1472 1473/* Configure Switching Component Bandwidth Allocation per Tc 1474 * (indirect 0x0417) 1475 */ 1476struct i40e_aqc_configure_switching_comp_bw_config_data { 1477 u8 tc_valid_bits; 1478 u8 reserved[2]; 1479 u8 absolute_credits; /* bool */ 1480 u8 tc_bw_share_credits[8]; 1481 u8 reserved1[20]; 1482}; 1483 1484I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1485 1486/* Query Switching Component Configuration (indirect 0x0418) */ 1487struct i40e_aqc_query_switching_comp_ets_config_resp { 1488 u8 tc_valid_bits; 1489 u8 reserved[35]; 1490 __le16 port_bw_limit; 1491 u8 reserved1[2]; 1492 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1493 u8 reserved2[23]; 1494}; 1495 1496I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1497 1498/* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1499struct i40e_aqc_query_port_ets_config_resp { 1500 u8 reserved[4]; 1501 u8 tc_valid_bits; 1502 u8 reserved1; 1503 u8 tc_strict_priority_bits; 1504 u8 reserved2; 1505 u8 tc_bw_share_credits[8]; 1506 __le16 tc_bw_limits[8]; 1507 1508 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1509 __le16 tc_bw_max[2]; 1510 u8 reserved3[32]; 1511}; 1512 1513I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1514 1515/* Query Switching Component Bandwidth Allocation per Traffic Type 1516 * (indirect 0x041A) 1517 */ 1518struct i40e_aqc_query_switching_comp_bw_config_resp { 1519 u8 tc_valid_bits; 1520 u8 reserved[2]; 1521 u8 absolute_credits_enable; /* bool */ 1522 u8 tc_bw_share_credits[8]; 1523 __le16 tc_bw_limits[8]; 1524 1525 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1526 __le16 tc_bw_max[2]; 1527}; 1528 1529I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1530 1531/* Suspend/resume port TX traffic 1532 * (direct 0x041B and 0x041C) uses the generic SEID struct 1533 */ 1534 1535/* Configure partition BW 1536 * (indirect 0x041D) 1537 */ 1538struct i40e_aqc_configure_partition_bw_data { 1539 __le16 pf_valid_bits; 1540 u8 min_bw[16]; /* guaranteed bandwidth */ 1541 u8 max_bw[16]; /* bandwidth limit */ 1542}; 1543 1544I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1545 1546/* Get and set the active HMC resource profile and status. 1547 * (direct 0x0500) and (direct 0x0501) 1548 */ 1549struct i40e_aq_get_set_hmc_resource_profile { 1550 u8 pm_profile; 1551 u8 pe_vf_enabled; 1552 u8 reserved[14]; 1553}; 1554 1555I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1556 1557enum i40e_aq_hmc_profile { 1558 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1559 I40E_HMC_PROFILE_DEFAULT = 1, 1560 I40E_HMC_PROFILE_FAVOR_VF = 2, 1561 I40E_HMC_PROFILE_EQUAL = 3, 1562}; 1563 1564#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF 1565#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F 1566 1567/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1568 1569/* set in param0 for get phy abilities to report qualified modules */ 1570#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1571#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1572 1573enum i40e_aq_phy_type { 1574 I40E_PHY_TYPE_SGMII = 0x0, 1575 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1576 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1577 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1578 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1579 I40E_PHY_TYPE_XAUI = 0x5, 1580 I40E_PHY_TYPE_XFI = 0x6, 1581 I40E_PHY_TYPE_SFI = 0x7, 1582 I40E_PHY_TYPE_XLAUI = 0x8, 1583 I40E_PHY_TYPE_XLPPI = 0x9, 1584 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1585 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1586 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1587 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1588 I40E_PHY_TYPE_100BASE_TX = 0x11, 1589 I40E_PHY_TYPE_1000BASE_T = 0x12, 1590 I40E_PHY_TYPE_10GBASE_T = 0x13, 1591 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1592 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1593 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1594 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1595 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1596 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1597 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1598 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1599 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1600 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1601 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1602 I40E_PHY_TYPE_MAX 1603}; 1604 1605#define I40E_LINK_SPEED_100MB_SHIFT 0x1 1606#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1607#define I40E_LINK_SPEED_10GB_SHIFT 0x3 1608#define I40E_LINK_SPEED_40GB_SHIFT 0x4 1609#define I40E_LINK_SPEED_20GB_SHIFT 0x5 1610 1611enum i40e_aq_link_speed { 1612 I40E_LINK_SPEED_UNKNOWN = 0, 1613 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1614 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1615 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1616 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1617 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) 1618}; 1619 1620struct i40e_aqc_module_desc { 1621 u8 oui[3]; 1622 u8 reserved1; 1623 u8 part_number[16]; 1624 u8 revision[4]; 1625 u8 reserved2[8]; 1626}; 1627 1628I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1629 1630struct i40e_aq_get_phy_abilities_resp { 1631 __le32 phy_type; /* bitmap using the above enum for offsets */ 1632 u8 link_speed; /* bitmap using the above enum bit patterns */ 1633 u8 abilities; 1634#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1635#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1636#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1637#define I40E_AQ_PHY_LINK_ENABLED 0x08 1638#define I40E_AQ_PHY_AN_ENABLED 0x10 1639#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1640 __le16 eee_capability; 1641#define I40E_AQ_EEE_100BASE_TX 0x0002 1642#define I40E_AQ_EEE_1000BASE_T 0x0004 1643#define I40E_AQ_EEE_10GBASE_T 0x0008 1644#define I40E_AQ_EEE_1000BASE_KX 0x0010 1645#define I40E_AQ_EEE_10GBASE_KX4 0x0020 1646#define I40E_AQ_EEE_10GBASE_KR 0x0040 1647 __le32 eeer_val; 1648 u8 d3_lpan; 1649#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1650 u8 reserved[3]; 1651 u8 phy_id[4]; 1652 u8 module_type[3]; 1653 u8 qualified_module_count; 1654#define I40E_AQ_PHY_MAX_QMS 16 1655 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1656}; 1657 1658I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1659 1660/* Set PHY Config (direct 0x0601) */ 1661struct i40e_aq_set_phy_config { /* same bits as above in all */ 1662 __le32 phy_type; 1663 u8 link_speed; 1664 u8 abilities; 1665/* bits 0-2 use the values from get_phy_abilities_resp */ 1666#define I40E_AQ_PHY_ENABLE_LINK 0x08 1667#define I40E_AQ_PHY_ENABLE_AN 0x10 1668#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1669 __le16 eee_capability; 1670 __le32 eeer; 1671 u8 low_power_ctrl; 1672 u8 reserved[3]; 1673}; 1674 1675I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1676 1677/* Set MAC Config command data structure (direct 0x0603) */ 1678struct i40e_aq_set_mac_config { 1679 __le16 max_frame_size; 1680 u8 params; 1681#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1682#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1683#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1684#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1685#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1686#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1687#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1688#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1689#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1690#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1691#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1692#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1693#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1694#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1695 u8 tx_timer_priority; /* bitmap */ 1696 __le16 tx_timer_value; 1697 __le16 fc_refresh_threshold; 1698 u8 reserved[8]; 1699}; 1700 1701I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1702 1703/* Restart Auto-Negotiation (direct 0x605) */ 1704struct i40e_aqc_set_link_restart_an { 1705 u8 command; 1706#define I40E_AQ_PHY_RESTART_AN 0x02 1707#define I40E_AQ_PHY_LINK_ENABLE 0x04 1708 u8 reserved[15]; 1709}; 1710 1711I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1712 1713/* Get Link Status cmd & response data structure (direct 0x0607) */ 1714struct i40e_aqc_get_link_status { 1715 __le16 command_flags; /* only field set on command */ 1716#define I40E_AQ_LSE_MASK 0x3 1717#define I40E_AQ_LSE_NOP 0x0 1718#define I40E_AQ_LSE_DISABLE 0x2 1719#define I40E_AQ_LSE_ENABLE 0x3 1720/* only response uses this flag */ 1721#define I40E_AQ_LSE_IS_ENABLED 0x1 1722 u8 phy_type; /* i40e_aq_phy_type */ 1723 u8 link_speed; /* i40e_aq_link_speed */ 1724 u8 link_info; 1725#define I40E_AQ_LINK_UP 0x01 /* obsolete */ 1726#define I40E_AQ_LINK_UP_FUNCTION 0x01 1727#define I40E_AQ_LINK_FAULT 0x02 1728#define I40E_AQ_LINK_FAULT_TX 0x04 1729#define I40E_AQ_LINK_FAULT_RX 0x08 1730#define I40E_AQ_LINK_FAULT_REMOTE 0x10 1731#define I40E_AQ_LINK_UP_PORT 0x20 1732#define I40E_AQ_MEDIA_AVAILABLE 0x40 1733#define I40E_AQ_SIGNAL_DETECT 0x80 1734 u8 an_info; 1735#define I40E_AQ_AN_COMPLETED 0x01 1736#define I40E_AQ_LP_AN_ABILITY 0x02 1737#define I40E_AQ_PD_FAULT 0x04 1738#define I40E_AQ_FEC_EN 0x08 1739#define I40E_AQ_PHY_LOW_POWER 0x10 1740#define I40E_AQ_LINK_PAUSE_TX 0x20 1741#define I40E_AQ_LINK_PAUSE_RX 0x40 1742#define I40E_AQ_QUALIFIED_MODULE 0x80 1743 u8 ext_info; 1744#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1745#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1746#define I40E_AQ_LINK_TX_SHIFT 0x02 1747#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1748#define I40E_AQ_LINK_TX_ACTIVE 0x00 1749#define I40E_AQ_LINK_TX_DRAINED 0x01 1750#define I40E_AQ_LINK_TX_FLUSHED 0x03 1751#define I40E_AQ_LINK_FORCED_40G 0x10 1752 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1753 __le16 max_frame_size; 1754 u8 config; 1755#define I40E_AQ_CONFIG_CRC_ENA 0x04 1756#define I40E_AQ_CONFIG_PACING_MASK 0x78 1757 u8 reserved[5]; 1758}; 1759 1760I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1761 1762/* Set event mask command (direct 0x613) */ 1763struct i40e_aqc_set_phy_int_mask { 1764 u8 reserved[8]; 1765 __le16 event_mask; 1766#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1767#define I40E_AQ_EVENT_MEDIA_NA 0x0004 1768#define I40E_AQ_EVENT_LINK_FAULT 0x0008 1769#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1770#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1771#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1772#define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1773#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1774#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1775 u8 reserved1[6]; 1776}; 1777 1778I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1779 1780/* Get Local AN advt register (direct 0x0614) 1781 * Set Local AN advt register (direct 0x0615) 1782 * Get Link Partner AN advt register (direct 0x0616) 1783 */ 1784struct i40e_aqc_an_advt_reg { 1785 __le32 local_an_reg0; 1786 __le16 local_an_reg1; 1787 u8 reserved[10]; 1788}; 1789 1790I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1791 1792/* Set Loopback mode (0x0618) */ 1793struct i40e_aqc_set_lb_mode { 1794 __le16 lb_mode; 1795#define I40E_AQ_LB_PHY_LOCAL 0x01 1796#define I40E_AQ_LB_PHY_REMOTE 0x02 1797#define I40E_AQ_LB_MAC_LOCAL 0x04 1798 u8 reserved[14]; 1799}; 1800 1801I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1802 1803/* Set PHY Debug command (0x0622) */ 1804struct i40e_aqc_set_phy_debug { 1805 u8 command_flags; 1806#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1807#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1808#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1809 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1810#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1811#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1812#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1813#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1814 u8 reserved[15]; 1815}; 1816 1817I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1818 1819enum i40e_aq_phy_reg_type { 1820 I40E_AQC_PHY_REG_INTERNAL = 0x1, 1821 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1822 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1823}; 1824 1825/* NVM Read command (indirect 0x0701) 1826 * NVM Erase commands (direct 0x0702) 1827 * NVM Update commands (indirect 0x0703) 1828 */ 1829struct i40e_aqc_nvm_update { 1830 u8 command_flags; 1831#define I40E_AQ_NVM_LAST_CMD 0x01 1832#define I40E_AQ_NVM_FLASH_ONLY 0x80 1833 u8 module_pointer; 1834 __le16 length; 1835 __le32 offset; 1836 __le32 addr_high; 1837 __le32 addr_low; 1838}; 1839 1840I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 1841 1842/* NVM Config Read (indirect 0x0704) */ 1843struct i40e_aqc_nvm_config_read { 1844 __le16 cmd_flags; 1845#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 1846#define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 1847#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 1848 __le16 element_count; 1849 __le16 element_id; /* Feature/field ID */ 1850 __le16 element_id_msw; /* MSWord of field ID */ 1851 __le32 address_high; 1852 __le32 address_low; 1853}; 1854 1855I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 1856 1857/* NVM Config Write (indirect 0x0705) */ 1858struct i40e_aqc_nvm_config_write { 1859 __le16 cmd_flags; 1860 __le16 element_count; 1861 u8 reserved[4]; 1862 __le32 address_high; 1863 __le32 address_low; 1864}; 1865 1866I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 1867 1868/* Used for 0x0704 as well as for 0x0705 commands */ 1869#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 1870#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 1871#define I40E_AQ_ANVM_FEATURE 0 1872#define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 1873struct i40e_aqc_nvm_config_data_feature { 1874 __le16 feature_id; 1875#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 1876#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 1877#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 1878 __le16 feature_options; 1879 __le16 feature_selection; 1880}; 1881 1882I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 1883 1884struct i40e_aqc_nvm_config_data_immediate_field { 1885 __le32 field_id; 1886 __le32 field_value; 1887 __le16 field_options; 1888 __le16 reserved; 1889}; 1890 1891I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 1892 1893/* OEM Post Update (indirect 0x0720) 1894 * no command data struct used 1895 */ 1896 struct i40e_aqc_nvm_oem_post_update { 1897#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 1898 u8 sel_data; 1899 u8 reserved[7]; 1900}; 1901 1902I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 1903 1904struct i40e_aqc_nvm_oem_post_update_buffer { 1905 u8 str_len; 1906 u8 dev_addr; 1907 __le16 eeprom_addr; 1908 u8 data[36]; 1909}; 1910 1911I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 1912 1913/* Send to PF command (indirect 0x0801) id is only used by PF 1914 * Send to VF command (indirect 0x0802) id is only used by PF 1915 * Send to Peer PF command (indirect 0x0803) 1916 */ 1917struct i40e_aqc_pf_vf_message { 1918 __le32 id; 1919 u8 reserved[4]; 1920 __le32 addr_high; 1921 __le32 addr_low; 1922}; 1923 1924I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 1925 1926/* Alternate structure */ 1927 1928/* Direct write (direct 0x0900) 1929 * Direct read (direct 0x0902) 1930 */ 1931struct i40e_aqc_alternate_write { 1932 __le32 address0; 1933 __le32 data0; 1934 __le32 address1; 1935 __le32 data1; 1936}; 1937 1938I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 1939 1940/* Indirect write (indirect 0x0901) 1941 * Indirect read (indirect 0x0903) 1942 */ 1943 1944struct i40e_aqc_alternate_ind_write { 1945 __le32 address; 1946 __le32 length; 1947 __le32 addr_high; 1948 __le32 addr_low; 1949}; 1950 1951I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 1952 1953/* Done alternate write (direct 0x0904) 1954 * uses i40e_aq_desc 1955 */ 1956struct i40e_aqc_alternate_write_done { 1957 __le16 cmd_flags; 1958#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 1959#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 1960#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 1961#define I40E_AQ_ALTERNATE_RESET_NEEDED 2 1962 u8 reserved[14]; 1963}; 1964 1965I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 1966 1967/* Set OEM mode (direct 0x0905) */ 1968struct i40e_aqc_alternate_set_mode { 1969 __le32 mode; 1970#define I40E_AQ_ALTERNATE_MODE_NONE 0 1971#define I40E_AQ_ALTERNATE_MODE_OEM 1 1972 u8 reserved[12]; 1973}; 1974 1975I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 1976 1977/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 1978 1979/* async events 0x10xx */ 1980 1981/* Lan Queue Overflow Event (direct, 0x1001) */ 1982struct i40e_aqc_lan_overflow { 1983 __le32 prtdcb_rupto; 1984 __le32 otx_ctl; 1985 u8 reserved[8]; 1986}; 1987 1988I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 1989 1990/* Get LLDP MIB (indirect 0x0A00) */ 1991struct i40e_aqc_lldp_get_mib { 1992 u8 type; 1993 u8 reserved1; 1994#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 1995#define I40E_AQ_LLDP_MIB_LOCAL 0x0 1996#define I40E_AQ_LLDP_MIB_REMOTE 0x1 1997#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 1998#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 1999#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2000#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2001#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2002#define I40E_AQ_LLDP_TX_SHIFT 0x4 2003#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2004/* TX pause flags use I40E_AQ_LINK_TX_* above */ 2005 __le16 local_len; 2006 __le16 remote_len; 2007 u8 reserved2[2]; 2008 __le32 addr_high; 2009 __le32 addr_low; 2010}; 2011 2012I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2013 2014/* Configure LLDP MIB Change Event (direct 0x0A01) 2015 * also used for the event (with type in the command field) 2016 */ 2017struct i40e_aqc_lldp_update_mib { 2018 u8 command; 2019#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2020#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2021 u8 reserved[7]; 2022 __le32 addr_high; 2023 __le32 addr_low; 2024}; 2025 2026I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2027 2028/* Add LLDP TLV (indirect 0x0A02) 2029 * Delete LLDP TLV (indirect 0x0A04) 2030 */ 2031struct i40e_aqc_lldp_add_tlv { 2032 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2033 u8 reserved1[1]; 2034 __le16 len; 2035 u8 reserved2[4]; 2036 __le32 addr_high; 2037 __le32 addr_low; 2038}; 2039 2040I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2041 2042/* Update LLDP TLV (indirect 0x0A03) */ 2043struct i40e_aqc_lldp_update_tlv { 2044 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2045 u8 reserved; 2046 __le16 old_len; 2047 __le16 new_offset; 2048 __le16 new_len; 2049 __le32 addr_high; 2050 __le32 addr_low; 2051}; 2052 2053I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2054 2055/* Stop LLDP (direct 0x0A05) */ 2056struct i40e_aqc_lldp_stop { 2057 u8 command; 2058#define I40E_AQ_LLDP_AGENT_STOP 0x0 2059#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2060 u8 reserved[15]; 2061}; 2062 2063I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2064 2065/* Start LLDP (direct 0x0A06) */ 2066 2067struct i40e_aqc_lldp_start { 2068 u8 command; 2069#define I40E_AQ_LLDP_AGENT_START 0x1 2070 u8 reserved[15]; 2071}; 2072 2073I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2074 2075/* Get CEE DCBX Oper Config (0x0A07) 2076 * uses the generic descriptor struct 2077 * returns below as indirect response 2078 */ 2079 2080#define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2081#define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2082#define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2083#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2084#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2085#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2086 2087#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2088#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2089#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2090#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2091#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2092#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2093#define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2094#define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2095#define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2096#define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2097#define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2098#define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2099 2100/* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2101 * word boundary layout issues, which the Linux compilers silently deal 2102 * with by adding padding, making the actual struct larger than designed. 2103 * However, the FW compiler for the NIC is less lenient and complains 2104 * about the struct. Hence, the struct defined here has an extra byte in 2105 * fields reserved3 and reserved4 to directly acknowledge that padding, 2106 * and the new length is used in the length check macro. 2107 */ 2108struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2109 u8 reserved1; 2110 u8 oper_num_tc; 2111 u8 oper_prio_tc[4]; 2112 u8 reserved2; 2113 u8 oper_tc_bw[8]; 2114 u8 oper_pfc_en; 2115 u8 reserved3[2]; 2116 __le16 oper_app_prio; 2117 u8 reserved4[2]; 2118 __le16 tlv_status; 2119}; 2120 2121I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2122 2123struct i40e_aqc_get_cee_dcb_cfg_resp { 2124 u8 oper_num_tc; 2125 u8 oper_prio_tc[4]; 2126 u8 oper_tc_bw[8]; 2127 u8 oper_pfc_en; 2128 __le16 oper_app_prio; 2129 __le32 tlv_status; 2130 u8 reserved[12]; 2131}; 2132 2133I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2134 2135/* Set Local LLDP MIB (indirect 0x0A08) 2136 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2137 */ 2138struct i40e_aqc_lldp_set_local_mib { 2139#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2140#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \ 2141 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2142#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2143#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2144#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \ 2145 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2146#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2147 u8 type; 2148 u8 reserved0; 2149 __le16 length; 2150 u8 reserved1[4]; 2151 __le32 address_high; 2152 __le32 address_low; 2153}; 2154 2155I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2156 2157/* Stop/Start LLDP Agent (direct 0x0A09) 2158 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2159 */ 2160struct i40e_aqc_lldp_stop_start_specific_agent { 2161#define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2162#define I40E_AQC_START_SPECIFIC_AGENT_MASK (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2163 u8 command; 2164 u8 reserved[15]; 2165}; 2166 2167I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2168 2169/* Add Udp Tunnel command and completion (direct 0x0B00) */ 2170struct i40e_aqc_add_udp_tunnel { 2171 __le16 udp_port; 2172 u8 reserved0[3]; 2173 u8 protocol_type; 2174#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2175#define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2176#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2177 u8 reserved1[10]; 2178}; 2179 2180I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2181 2182struct i40e_aqc_add_udp_tunnel_completion { 2183 __le16 udp_port; 2184 u8 filter_entry_index; 2185 u8 multiple_pfs; 2186#define I40E_AQC_SINGLE_PF 0x0 2187#define I40E_AQC_MULTIPLE_PFS 0x1 2188 u8 total_filters; 2189 u8 reserved[11]; 2190}; 2191 2192I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2193 2194/* remove UDP Tunnel command (0x0B01) */ 2195struct i40e_aqc_remove_udp_tunnel { 2196 u8 reserved[2]; 2197 u8 index; /* 0 to 15 */ 2198 u8 reserved2[13]; 2199}; 2200 2201I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2202 2203struct i40e_aqc_del_udp_tunnel_completion { 2204 __le16 udp_port; 2205 u8 index; /* 0 to 15 */ 2206 u8 multiple_pfs; 2207 u8 total_filters_used; 2208 u8 reserved1[11]; 2209}; 2210 2211I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2212 2213/* tunnel key structure 0x0B10 */ 2214 2215struct i40e_aqc_tunnel_key_structure { 2216 u8 key1_off; 2217 u8 key2_off; 2218 u8 key1_len; /* 0 to 15 */ 2219 u8 key2_len; /* 0 to 15 */ 2220 u8 flags; 2221#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2222/* response flags */ 2223#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2224#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2225#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2226 u8 network_key_index; 2227#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2228#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2229#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2230#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2231 u8 reserved[10]; 2232}; 2233 2234I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2235 2236/* OEM mode commands (direct 0xFE0x) */ 2237struct i40e_aqc_oem_param_change { 2238 __le32 param_type; 2239#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2240#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2241#define I40E_AQ_OEM_PARAM_MAC 2 2242 __le32 param_value1; 2243 __le16 param_value2; 2244 u8 reserved[6]; 2245}; 2246 2247I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2248 2249struct i40e_aqc_oem_state_change { 2250 __le32 state; 2251#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2252#define I40E_AQ_OEM_STATE_LINK_UP 0x1 2253 u8 reserved[12]; 2254}; 2255 2256I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2257 2258/* Initialize OCSD (0xFE02, direct) */ 2259struct i40e_aqc_opc_oem_ocsd_initialize { 2260 u8 type_status; 2261 u8 reserved1[3]; 2262 __le32 ocsd_memory_block_addr_high; 2263 __le32 ocsd_memory_block_addr_low; 2264 __le32 requested_update_interval; 2265}; 2266 2267I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2268 2269/* Initialize OCBB (0xFE03, direct) */ 2270struct i40e_aqc_opc_oem_ocbb_initialize { 2271 u8 type_status; 2272 u8 reserved1[3]; 2273 __le32 ocbb_memory_block_addr_high; 2274 __le32 ocbb_memory_block_addr_low; 2275 u8 reserved2[4]; 2276}; 2277 2278I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2279 2280/* debug commands */ 2281 2282/* get device id (0xFF00) uses the generic structure */ 2283 2284/* set test more (0xFF01, internal) */ 2285 2286struct i40e_acq_set_test_mode { 2287 u8 mode; 2288#define I40E_AQ_TEST_PARTIAL 0 2289#define I40E_AQ_TEST_FULL 1 2290#define I40E_AQ_TEST_NVM 2 2291 u8 reserved[3]; 2292 u8 command; 2293#define I40E_AQ_TEST_OPEN 0 2294#define I40E_AQ_TEST_CLOSE 1 2295#define I40E_AQ_TEST_INC 2 2296 u8 reserved2[3]; 2297 __le32 address_high; 2298 __le32 address_low; 2299}; 2300 2301I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2302 2303/* Debug Read Register command (0xFF03) 2304 * Debug Write Register command (0xFF04) 2305 */ 2306struct i40e_aqc_debug_reg_read_write { 2307 __le32 reserved; 2308 __le32 address; 2309 __le32 value_high; 2310 __le32 value_low; 2311}; 2312 2313I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2314 2315/* Scatter/gather Reg Read (indirect 0xFF05) 2316 * Scatter/gather Reg Write (indirect 0xFF06) 2317 */ 2318 2319/* i40e_aq_desc is used for the command */ 2320struct i40e_aqc_debug_reg_sg_element_data { 2321 __le32 address; 2322 __le32 value; 2323}; 2324 2325/* Debug Modify register (direct 0xFF07) */ 2326struct i40e_aqc_debug_modify_reg { 2327 __le32 address; 2328 __le32 value; 2329 __le32 clear_mask; 2330 __le32 set_mask; 2331}; 2332 2333I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2334 2335/* dump internal data (0xFF08, indirect) */ 2336 2337#define I40E_AQ_CLUSTER_ID_AUX 0 2338#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2339#define I40E_AQ_CLUSTER_ID_TXSCHED 2 2340#define I40E_AQ_CLUSTER_ID_HMC 3 2341#define I40E_AQ_CLUSTER_ID_MAC0 4 2342#define I40E_AQ_CLUSTER_ID_MAC1 5 2343#define I40E_AQ_CLUSTER_ID_MAC2 6 2344#define I40E_AQ_CLUSTER_ID_MAC3 7 2345#define I40E_AQ_CLUSTER_ID_DCB 8 2346#define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2347#define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2348#define I40E_AQ_CLUSTER_ID_ALTRAM 11 2349 2350struct i40e_aqc_debug_dump_internals { 2351 u8 cluster_id; 2352 u8 table_id; 2353 __le16 data_size; 2354 __le32 idx; 2355 __le32 address_high; 2356 __le32 address_low; 2357}; 2358 2359I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2360 2361struct i40e_aqc_debug_modify_internals { 2362 u8 cluster_id; 2363 u8 cluster_specific_params[7]; 2364 __le32 address_high; 2365 __le32 address_low; 2366}; 2367 2368I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2369 2370#endif 2371