i40e_adminq_cmd.h revision 277082
12061Sjkh/****************************************************************************** 250479Speter 32061Sjkh Copyright (c) 2013-2014, Intel Corporation 438666Sjb All rights reserved. 532427Sjb 6103985Sphk Redistribution and use in source and binary forms, with or without 7103985Sphk modification, are permitted provided that the following conditions are met: 838666Sjb 938666Sjb 1. Redistributions of source code must retain the above copyright notice, 1038666Sjb this list of conditions and the following disclaimer. 1138666Sjb 1264049Salex 2. Redistributions in binary form must reproduce the above copyright 1364049Salex notice, this list of conditions and the following disclaimer in the 1466071Smarkm documentation and/or other materials provided with the distribution. 1573504Sobrien 1638666Sjb 3. Neither the name of the Intel Corporation nor the names of its 1744918Sjkh contributors may be used to endorse or promote products derived from 1838666Sjb this software without specific prior written permission. 1938666Sjb 2038666Sjb THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2138666Sjb AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2238666Sjb IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2338666Sjb ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 2438666Sjb LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2538978Sjb CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2638978Sjb SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2732427Sjb INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2838666Sjb CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2938666Sjb ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3038666Sjb POSSIBILITY OF SUCH DAMAGE. 3138666Sjb 3238666Sjb******************************************************************************/ 3338666Sjb/*$FreeBSD: head/sys/dev/ixl/i40e_adminq_cmd.h 277082 2015-01-12 18:32:45Z jfv $*/ 3417308Speter 3591606Skeramida#ifndef _I40E_ADMINQ_CMD_H_ 3619175Sbde#define _I40E_ADMINQ_CMD_H_ 3796205Sjwd 3896205Sjwd/* This header file defines the i40e Admin Queue commands and is shared between 3938042Sbde * i40e Firmware and Software. 4096205Sjwd * 4196205Sjwd * This file needs to comply with the Linux Kernel coding style. 4238042Sbde */ 4396205Sjwd 4496205Sjwd#define I40E_FW_API_VERSION_MAJOR 0x0001 4517308Speter#define I40E_FW_API_VERSION_MINOR 0x0002 4696205Sjwd 4796205Sjwdstruct i40e_aq_desc { 4817308Speter __le16 flags; 4996205Sjwd __le16 opcode; 5096205Sjwd __le16 datalen; 5196205Sjwd __le16 retval; 5296205Sjwd __le32 cookie_high; 5396205Sjwd __le32 cookie_low; 5496205Sjwd union { 5596205Sjwd struct { 5696205Sjwd __le32 param0; 5796205Sjwd __le32 param1; 5896205Sjwd __le32 param2; 5996205Sjwd __le32 param3; 6096205Sjwd } internal; 6198775Sdillon struct { 6298723Sdillon __le32 param0; 6398723Sdillon __le32 param1; 6498723Sdillon __le32 addr_high; 6598723Sdillon __le32 addr_low; 6638666Sjb } external; 6717308Speter u8 raw[16]; 6838666Sjb } params; 6917308Speter}; 7027910Sasami 7143226Sjkh/* Flags sub-structure 7243226Sjkh * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 7343226Sjkh * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 7438666Sjb */ 7527910Sasami 7638666Sjb/* command flags and offsets*/ 7738666Sjb#define I40E_AQ_FLAG_DD_SHIFT 0 7838666Sjb#define I40E_AQ_FLAG_CMP_SHIFT 1 7927910Sasami#define I40E_AQ_FLAG_ERR_SHIFT 2 8038666Sjb#define I40E_AQ_FLAG_VFE_SHIFT 3 8138666Sjb#define I40E_AQ_FLAG_LB_SHIFT 9 8243226Sjkh#define I40E_AQ_FLAG_RD_SHIFT 10 8343226Sjkh#define I40E_AQ_FLAG_VFC_SHIFT 11 8427910Sasami#define I40E_AQ_FLAG_BUF_SHIFT 12 8538666Sjb#define I40E_AQ_FLAG_SI_SHIFT 13 8627910Sasami#define I40E_AQ_FLAG_EI_SHIFT 14 8717308Speter#define I40E_AQ_FLAG_FE_SHIFT 15 8838666Sjb 8938666Sjb#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 9017308Speter#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 9195509Sru#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 9295793Sru#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 9397252Sru#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 9496164Sru#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 9595146Sgshapiro#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 962061Sjkh#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 9797769Sru#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 9897252Sru#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 9997252Sru#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 10095730Sru 10195793Sru/* error codes */ 10295730Sruenum i40e_admin_queue_err { 10395730Sru I40E_AQ_RC_OK = 0, /* success */ 10495730Sru I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 10555026Smarcel I40E_AQ_RC_ENOENT = 2, /* No such element */ 10655026Smarcel I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 10754324Smarcel I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 10817308Speter I40E_AQ_RC_EIO = 5, /* I/O error */ 10938666Sjb I40E_AQ_RC_ENXIO = 6, /* No such resource */ 11017308Speter I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 11197252Sru I40E_AQ_RC_EAGAIN = 8, /* Try again */ 11238666Sjb I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 11354324Smarcel I40E_AQ_RC_EACCES = 10, /* Permission denied */ 1142302Spaul I40E_AQ_RC_EFAULT = 11, /* Bad address */ 11539206Sjkh I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 11639206Sjkh I40E_AQ_RC_EEXIST = 13, /* object already exists */ 11739206Sjkh I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 11873349Sru I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 11917308Speter I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 12054324Smarcel I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 12154324Smarcel I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 12254324Smarcel I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 12354324Smarcel I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 12454324Smarcel I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 12554324Smarcel I40E_AQ_RC_EFBIG = 22, /* File too large */ 12654324Smarcel}; 127103436Speter 12854324Smarcel/* Admin Queue command opcodes */ 12954324Smarcelenum i40e_admin_queue_opc { 13054324Smarcel /* aq commands */ 13154324Smarcel i40e_aqc_opc_get_version = 0x0001, 13254324Smarcel i40e_aqc_opc_driver_version = 0x0002, 13354324Smarcel i40e_aqc_opc_queue_shutdown = 0x0003, 13454324Smarcel i40e_aqc_opc_set_pf_context = 0x0004, 13554324Smarcel 13654324Smarcel /* resource ownership */ 13754324Smarcel i40e_aqc_opc_request_resource = 0x0008, 13854324Smarcel i40e_aqc_opc_release_resource = 0x0009, 13954324Smarcel 14054324Smarcel i40e_aqc_opc_list_func_capabilities = 0x000A, 14154324Smarcel i40e_aqc_opc_list_dev_capabilities = 0x000B, 14254324Smarcel 14354324Smarcel i40e_aqc_opc_set_cppm_configuration = 0x0103, 14454324Smarcel i40e_aqc_opc_set_arp_proxy_entry = 0x0104, 14554324Smarcel i40e_aqc_opc_set_ns_proxy_entry = 0x0105, 14654324Smarcel 147103436Speter /* LAA */ 14854324Smarcel i40e_aqc_opc_mng_laa = 0x0106, /* AQ obsolete */ 14954324Smarcel i40e_aqc_opc_mac_address_read = 0x0107, 15054324Smarcel i40e_aqc_opc_mac_address_write = 0x0108, 15195730Sru 15295730Sru /* PXE */ 15395730Sru i40e_aqc_opc_clear_pxe_mode = 0x0110, 15495730Sru 15595730Sru /* internal switch commands */ 15695730Sru i40e_aqc_opc_get_switch_config = 0x0200, 15795730Sru i40e_aqc_opc_add_statistics = 0x0201, 15838666Sjb i40e_aqc_opc_remove_statistics = 0x0202, 15938666Sjb i40e_aqc_opc_set_port_parameters = 0x0203, 16017308Speter i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 16138666Sjb 16238666Sjb i40e_aqc_opc_add_vsi = 0x0210, 16338666Sjb i40e_aqc_opc_update_vsi_parameters = 0x0211, 16417308Speter i40e_aqc_opc_get_vsi_parameters = 0x0212, 16555678Smarcel 16655678Smarcel i40e_aqc_opc_add_pv = 0x0220, 167100402Sru i40e_aqc_opc_update_pv_parameters = 0x0221, 168100402Sru i40e_aqc_opc_get_pv_parameters = 0x0222, 169100402Sru 17090395Sru i40e_aqc_opc_add_veb = 0x0230, 171100402Sru i40e_aqc_opc_update_veb_parameters = 0x0231, 172100402Sru i40e_aqc_opc_get_veb_parameters = 0x0232, 173100402Sru 174100402Sru i40e_aqc_opc_delete_element = 0x0243, 1752061Sjkh 17617308Speter i40e_aqc_opc_add_macvlan = 0x0250, 17738666Sjb i40e_aqc_opc_remove_macvlan = 0x0251, 178100401Sru i40e_aqc_opc_add_vlan = 0x0252, 179100401Sru i40e_aqc_opc_remove_vlan = 0x0253, 18017308Speter i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 18155678Smarcel i40e_aqc_opc_add_tag = 0x0255, 182100401Sru i40e_aqc_opc_remove_tag = 0x0256, 183100401Sru i40e_aqc_opc_add_multicast_etag = 0x0257, 184100401Sru i40e_aqc_opc_remove_multicast_etag = 0x0258, 185100401Sru i40e_aqc_opc_update_tag = 0x0259, 186100401Sru i40e_aqc_opc_add_control_packet_filter = 0x025A, 1873626Swollman i40e_aqc_opc_remove_control_packet_filter = 0x025B, 18817308Speter i40e_aqc_opc_add_cloud_filters = 0x025C, 18955678Smarcel i40e_aqc_opc_remove_cloud_filters = 0x025D, 19055678Smarcel 19155678Smarcel i40e_aqc_opc_add_mirror_rule = 0x0260, 19255678Smarcel i40e_aqc_opc_delete_mirror_rule = 0x0261, 19355678Smarcel 19455678Smarcel /* DCB commands */ 19555678Smarcel i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 19655678Smarcel i40e_aqc_opc_dcb_updated = 0x0302, 19755678Smarcel 19855678Smarcel /* TX scheduler */ 199102692Speter i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 200102692Speter i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 20155678Smarcel i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 20255678Smarcel i40e_aqc_opc_query_vsi_bw_config = 0x0408, 20338666Sjb i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 20438666Sjb i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 20517308Speter 20655678Smarcel i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 20738978Sjb i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 2083626Swollman i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 20917308Speter i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 21038666Sjb i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 21117308Speter i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 21243226Sjkh i40e_aqc_opc_query_port_ets_config = 0x0419, 21343226Sjkh i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 21443226Sjkh i40e_aqc_opc_suspend_port_tx = 0x041B, 21538666Sjb i40e_aqc_opc_resume_port_tx = 0x041C, 21638666Sjb i40e_aqc_opc_configure_partition_bw = 0x041D, 21744103Smsmith 218103985Sphk /* hmc */ 219103985Sphk i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 220103985Sphk i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 221103985Sphk 222103985Sphk /* phy commands*/ 223103985Sphk i40e_aqc_opc_get_phy_abilities = 0x0600, 224104370Sphk i40e_aqc_opc_set_phy_config = 0x0601, 225103985Sphk i40e_aqc_opc_set_mac_config = 0x0603, 226103985Sphk i40e_aqc_opc_set_link_restart_an = 0x0605, 227103985Sphk i40e_aqc_opc_get_link_status = 0x0607, 228103985Sphk i40e_aqc_opc_set_phy_int_mask = 0x0613, 229103985Sphk i40e_aqc_opc_get_local_advt_reg = 0x0614, 230104277Sphk i40e_aqc_opc_set_local_advt_reg = 0x0615, 231104277Sphk i40e_aqc_opc_get_partner_advt = 0x0616, 232103985Sphk i40e_aqc_opc_set_lb_modes = 0x0618, 233103985Sphk i40e_aqc_opc_get_phy_wol_caps = 0x0621, 234103985Sphk i40e_aqc_opc_set_phy_debug = 0x0622, 235103985Sphk i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 236103985Sphk 237104370Sphk /* NVM commands */ 238104370Sphk i40e_aqc_opc_nvm_read = 0x0701, 239104370Sphk i40e_aqc_opc_nvm_erase = 0x0702, 240103985Sphk i40e_aqc_opc_nvm_update = 0x0703, 241103985Sphk i40e_aqc_opc_nvm_config_read = 0x0704, 242103985Sphk i40e_aqc_opc_nvm_config_write = 0x0705, 243103985Sphk 244103985Sphk /* virtualization commands */ 245103985Sphk i40e_aqc_opc_send_msg_to_pf = 0x0801, 246103985Sphk i40e_aqc_opc_send_msg_to_vf = 0x0802, 247103985Sphk i40e_aqc_opc_send_msg_to_peer = 0x0803, 248103985Sphk 249103985Sphk /* alternate structure */ 250103985Sphk i40e_aqc_opc_alternate_write = 0x0900, 251103985Sphk i40e_aqc_opc_alternate_write_indirect = 0x0901, 252103985Sphk i40e_aqc_opc_alternate_read = 0x0902, 253103985Sphk i40e_aqc_opc_alternate_read_indirect = 0x0903, 254103985Sphk i40e_aqc_opc_alternate_write_done = 0x0904, 255103985Sphk i40e_aqc_opc_alternate_set_mode = 0x0905, 256103985Sphk i40e_aqc_opc_alternate_clear_port = 0x0906, 257 258 /* LLDP commands */ 259 i40e_aqc_opc_lldp_get_mib = 0x0A00, 260 i40e_aqc_opc_lldp_update_mib = 0x0A01, 261 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 262 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 263 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 264 i40e_aqc_opc_lldp_stop = 0x0A05, 265 i40e_aqc_opc_lldp_start = 0x0A06, 266 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 267 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 268 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 269 270 /* Tunnel commands */ 271 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 272 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 273 i40e_aqc_opc_tunnel_key_structure = 0x0B10, 274 275 /* Async Events */ 276 i40e_aqc_opc_event_lan_overflow = 0x1001, 277 278 /* OEM commands */ 279 i40e_aqc_opc_oem_parameter_change = 0xFE00, 280 i40e_aqc_opc_oem_device_status_change = 0xFE01, 281 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 282 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 283 284 /* debug commands */ 285 i40e_aqc_opc_debug_get_deviceid = 0xFF00, 286 i40e_aqc_opc_debug_set_mode = 0xFF01, 287 i40e_aqc_opc_debug_read_reg = 0xFF03, 288 i40e_aqc_opc_debug_write_reg = 0xFF04, 289 i40e_aqc_opc_debug_modify_reg = 0xFF07, 290 i40e_aqc_opc_debug_dump_internals = 0xFF08, 291}; 292 293/* command structures and indirect data structures */ 294 295/* Structure naming conventions: 296 * - no suffix for direct command descriptor structures 297 * - _data for indirect sent data 298 * - _resp for indirect return data (data which is both will use _data) 299 * - _completion for direct return data 300 * - _element_ for repeated elements (may also be _data or _resp) 301 * 302 * Command structures are expected to overlay the params.raw member of the basic 303 * descriptor, and as such cannot exceed 16 bytes in length. 304 */ 305 306/* This macro is used to generate a compilation error if a structure 307 * is not exactly the correct length. It gives a divide by zero error if the 308 * structure is not of the correct size, otherwise it creates an enum that is 309 * never used. 310 */ 311#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 312 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 313 314/* This macro is used extensively to ensure that command structures are 16 315 * bytes in length as they have to map to the raw array of that size. 316 */ 317#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 318 319/* internal (0x00XX) commands */ 320 321/* Get version (direct 0x0001) */ 322struct i40e_aqc_get_version { 323 __le32 rom_ver; 324 __le32 fw_build; 325 __le16 fw_major; 326 __le16 fw_minor; 327 __le16 api_major; 328 __le16 api_minor; 329}; 330 331I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 332 333/* Send driver version (indirect 0x0002) */ 334struct i40e_aqc_driver_version { 335 u8 driver_major_ver; 336 u8 driver_minor_ver; 337 u8 driver_build_ver; 338 u8 driver_subbuild_ver; 339 u8 reserved[4]; 340 __le32 address_high; 341 __le32 address_low; 342}; 343 344I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 345 346/* Queue Shutdown (direct 0x0003) */ 347struct i40e_aqc_queue_shutdown { 348 __le32 driver_unloading; 349#define I40E_AQ_DRIVER_UNLOADING 0x1 350 u8 reserved[12]; 351}; 352 353I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 354 355/* Set PF context (0x0004, direct) */ 356struct i40e_aqc_set_pf_context { 357 u8 pf_id; 358 u8 reserved[15]; 359}; 360 361I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 362 363/* Request resource ownership (direct 0x0008) 364 * Release resource ownership (direct 0x0009) 365 */ 366#define I40E_AQ_RESOURCE_NVM 1 367#define I40E_AQ_RESOURCE_SDP 2 368#define I40E_AQ_RESOURCE_ACCESS_READ 1 369#define I40E_AQ_RESOURCE_ACCESS_WRITE 2 370#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 371#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 372 373struct i40e_aqc_request_resource { 374 __le16 resource_id; 375 __le16 access_type; 376 __le32 timeout; 377 __le32 resource_number; 378 u8 reserved[4]; 379}; 380 381I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 382 383/* Get function capabilities (indirect 0x000A) 384 * Get device capabilities (indirect 0x000B) 385 */ 386struct i40e_aqc_list_capabilites { 387 u8 command_flags; 388#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 389 u8 pf_index; 390 u8 reserved[2]; 391 __le32 count; 392 __le32 addr_high; 393 __le32 addr_low; 394}; 395 396I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 397 398struct i40e_aqc_list_capabilities_element_resp { 399 __le16 id; 400 u8 major_rev; 401 u8 minor_rev; 402 __le32 number; 403 __le32 logical_id; 404 __le32 phys_id; 405 u8 reserved[16]; 406}; 407 408/* list of caps */ 409 410#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 411#define I40E_AQ_CAP_ID_MNG_MODE 0x0002 412#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 413#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 414#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 415#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 416#define I40E_AQ_CAP_ID_SRIOV 0x0012 417#define I40E_AQ_CAP_ID_VF 0x0013 418#define I40E_AQ_CAP_ID_VMDQ 0x0014 419#define I40E_AQ_CAP_ID_8021QBG 0x0015 420#define I40E_AQ_CAP_ID_8021QBR 0x0016 421#define I40E_AQ_CAP_ID_VSI 0x0017 422#define I40E_AQ_CAP_ID_DCB 0x0018 423#define I40E_AQ_CAP_ID_FCOE 0x0021 424#define I40E_AQ_CAP_ID_ISCSI 0x0022 425#define I40E_AQ_CAP_ID_RSS 0x0040 426#define I40E_AQ_CAP_ID_RXQ 0x0041 427#define I40E_AQ_CAP_ID_TXQ 0x0042 428#define I40E_AQ_CAP_ID_MSIX 0x0043 429#define I40E_AQ_CAP_ID_VF_MSIX 0x0044 430#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 431#define I40E_AQ_CAP_ID_1588 0x0046 432#define I40E_AQ_CAP_ID_IWARP 0x0051 433#define I40E_AQ_CAP_ID_LED 0x0061 434#define I40E_AQ_CAP_ID_SDP 0x0062 435#define I40E_AQ_CAP_ID_MDIO 0x0063 436#define I40E_AQ_CAP_ID_FLEX10 0x00F1 437#define I40E_AQ_CAP_ID_CEM 0x00F2 438 439/* Set CPPM Configuration (direct 0x0103) */ 440struct i40e_aqc_cppm_configuration { 441 __le16 command_flags; 442#define I40E_AQ_CPPM_EN_LTRC 0x0800 443#define I40E_AQ_CPPM_EN_DMCTH 0x1000 444#define I40E_AQ_CPPM_EN_DMCTLX 0x2000 445#define I40E_AQ_CPPM_EN_HPTC 0x4000 446#define I40E_AQ_CPPM_EN_DMARC 0x8000 447 __le16 ttlx; 448 __le32 dmacr; 449 __le16 dmcth; 450 u8 hptc; 451 u8 reserved; 452 __le32 pfltrc; 453}; 454 455I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 456 457/* Set ARP Proxy command / response (indirect 0x0104) */ 458struct i40e_aqc_arp_proxy_data { 459 __le16 command_flags; 460#define I40E_AQ_ARP_INIT_IPV4 0x0008 461#define I40E_AQ_ARP_UNSUP_CTL 0x0010 462#define I40E_AQ_ARP_ENA 0x0020 463#define I40E_AQ_ARP_ADD_IPV4 0x0040 464#define I40E_AQ_ARP_DEL_IPV4 0x0080 465 __le16 table_id; 466 __le32 pfpm_proxyfc; 467 __le32 ip_addr; 468 u8 mac_addr[6]; 469 u8 reserved[2]; 470}; 471 472I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 473 474/* Set NS Proxy Table Entry Command (indirect 0x0105) */ 475struct i40e_aqc_ns_proxy_data { 476 __le16 table_idx_mac_addr_0; 477 __le16 table_idx_mac_addr_1; 478 __le16 table_idx_ipv6_0; 479 __le16 table_idx_ipv6_1; 480 __le16 control; 481#define I40E_AQ_NS_PROXY_ADD_0 0x0100 482#define I40E_AQ_NS_PROXY_DEL_0 0x0200 483#define I40E_AQ_NS_PROXY_ADD_1 0x0400 484#define I40E_AQ_NS_PROXY_DEL_1 0x0800 485#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 486#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 487#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 488#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 489#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 490#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 491#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 492 u8 mac_addr_0[6]; 493 u8 mac_addr_1[6]; 494 u8 local_mac_addr[6]; 495 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 496 u8 ipv6_addr_1[16]; 497}; 498 499I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 500 501/* Manage LAA Command (0x0106) - obsolete */ 502struct i40e_aqc_mng_laa { 503 __le16 command_flags; 504#define I40E_AQ_LAA_FLAG_WR 0x8000 505 u8 reserved[2]; 506 __le32 sal; 507 __le16 sah; 508 u8 reserved2[6]; 509}; 510 511I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 512 513/* Manage MAC Address Read Command (indirect 0x0107) */ 514struct i40e_aqc_mac_address_read { 515 __le16 command_flags; 516#define I40E_AQC_LAN_ADDR_VALID 0x10 517#define I40E_AQC_SAN_ADDR_VALID 0x20 518#define I40E_AQC_PORT_ADDR_VALID 0x40 519#define I40E_AQC_WOL_ADDR_VALID 0x80 520#define I40E_AQC_ADDR_VALID_MASK 0xf0 521 u8 reserved[6]; 522 __le32 addr_high; 523 __le32 addr_low; 524}; 525 526I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 527 528struct i40e_aqc_mac_address_read_data { 529 u8 pf_lan_mac[6]; 530 u8 pf_san_mac[6]; 531 u8 port_mac[6]; 532 u8 pf_wol_mac[6]; 533}; 534 535I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 536 537/* Manage MAC Address Write Command (0x0108) */ 538struct i40e_aqc_mac_address_write { 539 __le16 command_flags; 540#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 541#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 542#define I40E_AQC_WRITE_TYPE_PORT 0x8000 543#define I40E_AQC_WRITE_TYPE_MASK 0xc000 544 __le16 mac_sah; 545 __le32 mac_sal; 546 u8 reserved[8]; 547}; 548 549I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 550 551/* PXE commands (0x011x) */ 552 553/* Clear PXE Command and response (direct 0x0110) */ 554struct i40e_aqc_clear_pxe { 555 u8 rx_cnt; 556 u8 reserved[15]; 557}; 558 559I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 560 561/* Switch configuration commands (0x02xx) */ 562 563/* Used by many indirect commands that only pass an seid and a buffer in the 564 * command 565 */ 566struct i40e_aqc_switch_seid { 567 __le16 seid; 568 u8 reserved[6]; 569 __le32 addr_high; 570 __le32 addr_low; 571}; 572 573I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 574 575/* Get Switch Configuration command (indirect 0x0200) 576 * uses i40e_aqc_switch_seid for the descriptor 577 */ 578struct i40e_aqc_get_switch_config_header_resp { 579 __le16 num_reported; 580 __le16 num_total; 581 u8 reserved[12]; 582}; 583 584I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 585 586struct i40e_aqc_switch_config_element_resp { 587 u8 element_type; 588#define I40E_AQ_SW_ELEM_TYPE_MAC 1 589#define I40E_AQ_SW_ELEM_TYPE_PF 2 590#define I40E_AQ_SW_ELEM_TYPE_VF 3 591#define I40E_AQ_SW_ELEM_TYPE_EMP 4 592#define I40E_AQ_SW_ELEM_TYPE_BMC 5 593#define I40E_AQ_SW_ELEM_TYPE_PV 16 594#define I40E_AQ_SW_ELEM_TYPE_VEB 17 595#define I40E_AQ_SW_ELEM_TYPE_PA 18 596#define I40E_AQ_SW_ELEM_TYPE_VSI 19 597 u8 revision; 598#define I40E_AQ_SW_ELEM_REV_1 1 599 __le16 seid; 600 __le16 uplink_seid; 601 __le16 downlink_seid; 602 u8 reserved[3]; 603 u8 connection_type; 604#define I40E_AQ_CONN_TYPE_REGULAR 0x1 605#define I40E_AQ_CONN_TYPE_DEFAULT 0x2 606#define I40E_AQ_CONN_TYPE_CASCADED 0x3 607 __le16 scheduler_id; 608 __le16 element_info; 609}; 610 611I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 612 613/* Get Switch Configuration (indirect 0x0200) 614 * an array of elements are returned in the response buffer 615 * the first in the array is the header, remainder are elements 616 */ 617struct i40e_aqc_get_switch_config_resp { 618 struct i40e_aqc_get_switch_config_header_resp header; 619 struct i40e_aqc_switch_config_element_resp element[1]; 620}; 621 622I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 623 624/* Add Statistics (direct 0x0201) 625 * Remove Statistics (direct 0x0202) 626 */ 627struct i40e_aqc_add_remove_statistics { 628 __le16 seid; 629 __le16 vlan; 630 __le16 stat_index; 631 u8 reserved[10]; 632}; 633 634I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 635 636/* Set Port Parameters command (direct 0x0203) */ 637struct i40e_aqc_set_port_parameters { 638 __le16 command_flags; 639#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 640#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 641#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 642 __le16 bad_frame_vsi; 643 __le16 default_seid; /* reserved for command */ 644 u8 reserved[10]; 645}; 646 647I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 648 649/* Get Switch Resource Allocation (indirect 0x0204) */ 650struct i40e_aqc_get_switch_resource_alloc { 651 u8 num_entries; /* reserved for command */ 652 u8 reserved[7]; 653 __le32 addr_high; 654 __le32 addr_low; 655}; 656 657I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 658 659/* expect an array of these structs in the response buffer */ 660struct i40e_aqc_switch_resource_alloc_element_resp { 661 u8 resource_type; 662#define I40E_AQ_RESOURCE_TYPE_VEB 0x0 663#define I40E_AQ_RESOURCE_TYPE_VSI 0x1 664#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 665#define I40E_AQ_RESOURCE_TYPE_STAG 0x3 666#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 667#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 668#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 669#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 670#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 671#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 672#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 673#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 674#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 675#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 676#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 677#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 678#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 679#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 680#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 681 u8 reserved1; 682 __le16 guaranteed; 683 __le16 total; 684 __le16 used; 685 __le16 total_unalloced; 686 u8 reserved2[6]; 687}; 688 689I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 690 691/* Add VSI (indirect 0x0210) 692 * this indirect command uses struct i40e_aqc_vsi_properties_data 693 * as the indirect buffer (128 bytes) 694 * 695 * Update VSI (indirect 0x211) 696 * uses the same data structure as Add VSI 697 * 698 * Get VSI (indirect 0x0212) 699 * uses the same completion and data structure as Add VSI 700 */ 701struct i40e_aqc_add_get_update_vsi { 702 __le16 uplink_seid; 703 u8 connection_type; 704#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 705#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 706#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 707 u8 reserved1; 708 u8 vf_id; 709 u8 reserved2; 710 __le16 vsi_flags; 711#define I40E_AQ_VSI_TYPE_SHIFT 0x0 712#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 713#define I40E_AQ_VSI_TYPE_VF 0x0 714#define I40E_AQ_VSI_TYPE_VMDQ2 0x1 715#define I40E_AQ_VSI_TYPE_PF 0x2 716#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 717#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 718 __le32 addr_high; 719 __le32 addr_low; 720}; 721 722I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 723 724struct i40e_aqc_add_get_update_vsi_completion { 725 __le16 seid; 726 __le16 vsi_number; 727 __le16 vsi_used; 728 __le16 vsi_free; 729 __le32 addr_high; 730 __le32 addr_low; 731}; 732 733I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 734 735struct i40e_aqc_vsi_properties_data { 736 /* first 96 byte are written by SW */ 737 __le16 valid_sections; 738#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 739#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 740#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 741#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 742#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 743#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 744#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 745#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 746#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 747#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 748 /* switch section */ 749 __le16 switch_id; /* 12bit id combined with flags below */ 750#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 751#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 752#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 753#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 754#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 755 u8 sw_reserved[2]; 756 /* security section */ 757 u8 sec_flags; 758#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 759#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 760#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 761 u8 sec_reserved; 762 /* VLAN section */ 763 __le16 pvid; /* VLANS include priority bits */ 764 __le16 fcoe_pvid; 765 u8 port_vlan_flags; 766#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 767#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 768 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 769#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 770#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 771#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 772#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 773#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 774#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 775 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 776#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 777#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 778#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 779#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 780 u8 pvlan_reserved[3]; 781 /* ingress egress up sections */ 782 __le32 ingress_table; /* bitmap, 3 bits per up */ 783#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 784#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 785 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 786#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 787#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 788 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 789#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 790#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 791 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 792#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 793#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 794 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 795#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 796#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 797 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 798#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 799#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 800 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 801#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 802#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 803 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 804#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 805#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 806 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 807 __le32 egress_table; /* same defines as for ingress table */ 808 /* cascaded PV section */ 809 __le16 cas_pv_tag; 810 u8 cas_pv_flags; 811#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 812#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 813 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 814#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 815#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 816#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 817#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 818#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 819#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 820 u8 cas_pv_reserved; 821 /* queue mapping section */ 822 __le16 mapping_flags; 823#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 824#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 825 __le16 queue_mapping[16]; 826#define I40E_AQ_VSI_QUEUE_SHIFT 0x0 827#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 828 __le16 tc_mapping[8]; 829#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 830#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 831 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 832#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 833#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 834 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 835 /* queueing option section */ 836 u8 queueing_opt_flags; 837#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 838#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 839 u8 queueing_opt_reserved[3]; 840 /* scheduler section */ 841 u8 up_enable_bits; 842 u8 sched_reserved; 843 /* outer up section */ 844 __le32 outer_up_table; /* same structure and defines as ingress table */ 845 u8 cmd_reserved[8]; 846 /* last 32 bytes are written by FW */ 847 __le16 qs_handle[8]; 848#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 849 __le16 stat_counter_idx; 850 __le16 sched_id; 851 u8 resp_reserved[12]; 852}; 853 854I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 855 856/* Add Port Virtualizer (direct 0x0220) 857 * also used for update PV (direct 0x0221) but only flags are used 858 * (IS_CTRL_PORT only works on add PV) 859 */ 860struct i40e_aqc_add_update_pv { 861 __le16 command_flags; 862#define I40E_AQC_PV_FLAG_PV_TYPE 0x1 863#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 864#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 865#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 866 __le16 uplink_seid; 867 __le16 connected_seid; 868 u8 reserved[10]; 869}; 870 871I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 872 873struct i40e_aqc_add_update_pv_completion { 874 /* reserved for update; for add also encodes error if rc == ENOSPC */ 875 __le16 pv_seid; 876#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 877#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 878#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 879#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 880 u8 reserved[14]; 881}; 882 883I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 884 885/* Get PV Params (direct 0x0222) 886 * uses i40e_aqc_switch_seid for the descriptor 887 */ 888 889struct i40e_aqc_get_pv_params_completion { 890 __le16 seid; 891 __le16 default_stag; 892 __le16 pv_flags; /* same flags as add_pv */ 893#define I40E_AQC_GET_PV_PV_TYPE 0x1 894#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 895#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 896 u8 reserved[8]; 897 __le16 default_port_seid; 898}; 899 900I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 901 902/* Add VEB (direct 0x0230) */ 903struct i40e_aqc_add_veb { 904 __le16 uplink_seid; 905 __le16 downlink_seid; 906 __le16 veb_flags; 907#define I40E_AQC_ADD_VEB_FLOATING 0x1 908#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 909#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 910 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 911#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 912#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 913#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 914 u8 enable_tcs; 915 u8 reserved[9]; 916}; 917 918I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 919 920struct i40e_aqc_add_veb_completion { 921 u8 reserved[6]; 922 __le16 switch_seid; 923 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 924 __le16 veb_seid; 925#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 926#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 927#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 928#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 929 __le16 statistic_index; 930 __le16 vebs_used; 931 __le16 vebs_free; 932}; 933 934I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 935 936/* Get VEB Parameters (direct 0x0232) 937 * uses i40e_aqc_switch_seid for the descriptor 938 */ 939struct i40e_aqc_get_veb_parameters_completion { 940 __le16 seid; 941 __le16 switch_id; 942 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 943 __le16 statistic_index; 944 __le16 vebs_used; 945 __le16 vebs_free; 946 u8 reserved[4]; 947}; 948 949I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 950 951/* Delete Element (direct 0x0243) 952 * uses the generic i40e_aqc_switch_seid 953 */ 954 955/* Add MAC-VLAN (indirect 0x0250) */ 956 957/* used for the command for most vlan commands */ 958struct i40e_aqc_macvlan { 959 __le16 num_addresses; 960 __le16 seid[3]; 961#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 962#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 963 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 964#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 965 __le32 addr_high; 966 __le32 addr_low; 967}; 968 969I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 970 971/* indirect data for command and response */ 972struct i40e_aqc_add_macvlan_element_data { 973 u8 mac_addr[6]; 974 __le16 vlan_tag; 975 __le16 flags; 976#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 977#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 978#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 979#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 980 __le16 queue_number; 981#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 982#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 983 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 984 /* response section */ 985 u8 match_method; 986#define I40E_AQC_MM_PERFECT_MATCH 0x01 987#define I40E_AQC_MM_HASH_MATCH 0x02 988#define I40E_AQC_MM_ERR_NO_RES 0xFF 989 u8 reserved1[3]; 990}; 991 992struct i40e_aqc_add_remove_macvlan_completion { 993 __le16 perfect_mac_used; 994 __le16 perfect_mac_free; 995 __le16 unicast_hash_free; 996 __le16 multicast_hash_free; 997 __le32 addr_high; 998 __le32 addr_low; 999}; 1000 1001I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1002 1003/* Remove MAC-VLAN (indirect 0x0251) 1004 * uses i40e_aqc_macvlan for the descriptor 1005 * data points to an array of num_addresses of elements 1006 */ 1007 1008struct i40e_aqc_remove_macvlan_element_data { 1009 u8 mac_addr[6]; 1010 __le16 vlan_tag; 1011 u8 flags; 1012#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1013#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1014#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1015#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1016 u8 reserved[3]; 1017 /* reply section */ 1018 u8 error_code; 1019#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1020#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1021 u8 reply_reserved[3]; 1022}; 1023 1024/* Add VLAN (indirect 0x0252) 1025 * Remove VLAN (indirect 0x0253) 1026 * use the generic i40e_aqc_macvlan for the command 1027 */ 1028struct i40e_aqc_add_remove_vlan_element_data { 1029 __le16 vlan_tag; 1030 u8 vlan_flags; 1031/* flags for add VLAN */ 1032#define I40E_AQC_ADD_VLAN_LOCAL 0x1 1033#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1034#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1035#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1036#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1037#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1038#define I40E_AQC_VLAN_PTYPE_SHIFT 3 1039#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1040#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1041#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1042#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1043#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1044/* flags for remove VLAN */ 1045#define I40E_AQC_REMOVE_VLAN_ALL 0x1 1046 u8 reserved; 1047 u8 result; 1048/* flags for add VLAN */ 1049#define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1050#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1051#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1052/* flags for remove VLAN */ 1053#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1054#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1055 u8 reserved1[3]; 1056}; 1057 1058struct i40e_aqc_add_remove_vlan_completion { 1059 u8 reserved[4]; 1060 __le16 vlans_used; 1061 __le16 vlans_free; 1062 __le32 addr_high; 1063 __le32 addr_low; 1064}; 1065 1066/* Set VSI Promiscuous Modes (direct 0x0254) */ 1067struct i40e_aqc_set_vsi_promiscuous_modes { 1068 __le16 promiscuous_flags; 1069 __le16 valid_flags; 1070/* flags used for both fields above */ 1071#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1072#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1073#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1074#define I40E_AQC_SET_VSI_DEFAULT 0x08 1075#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1076 __le16 seid; 1077#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1078 __le16 vlan_tag; 1079#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1080 u8 reserved[8]; 1081}; 1082 1083I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1084 1085/* Add S/E-tag command (direct 0x0255) 1086 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1087 */ 1088struct i40e_aqc_add_tag { 1089 __le16 flags; 1090#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1091 __le16 seid; 1092#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1093#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1094 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1095 __le16 tag; 1096 __le16 queue_number; 1097 u8 reserved[8]; 1098}; 1099 1100I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1101 1102struct i40e_aqc_add_remove_tag_completion { 1103 u8 reserved[12]; 1104 __le16 tags_used; 1105 __le16 tags_free; 1106}; 1107 1108I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1109 1110/* Remove S/E-tag command (direct 0x0256) 1111 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1112 */ 1113struct i40e_aqc_remove_tag { 1114 __le16 seid; 1115#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1116#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1117 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1118 __le16 tag; 1119 u8 reserved[12]; 1120}; 1121 1122I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1123 1124/* Add multicast E-Tag (direct 0x0257) 1125 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1126 * and no external data 1127 */ 1128struct i40e_aqc_add_remove_mcast_etag { 1129 __le16 pv_seid; 1130 __le16 etag; 1131 u8 num_unicast_etags; 1132 u8 reserved[3]; 1133 __le32 addr_high; /* address of array of 2-byte s-tags */ 1134 __le32 addr_low; 1135}; 1136 1137I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1138 1139struct i40e_aqc_add_remove_mcast_etag_completion { 1140 u8 reserved[4]; 1141 __le16 mcast_etags_used; 1142 __le16 mcast_etags_free; 1143 __le32 addr_high; 1144 __le32 addr_low; 1145 1146}; 1147 1148I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1149 1150/* Update S/E-Tag (direct 0x0259) */ 1151struct i40e_aqc_update_tag { 1152 __le16 seid; 1153#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1154#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1155 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1156 __le16 old_tag; 1157 __le16 new_tag; 1158 u8 reserved[10]; 1159}; 1160 1161I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1162 1163struct i40e_aqc_update_tag_completion { 1164 u8 reserved[12]; 1165 __le16 tags_used; 1166 __le16 tags_free; 1167}; 1168 1169I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1170 1171/* Add Control Packet filter (direct 0x025A) 1172 * Remove Control Packet filter (direct 0x025B) 1173 * uses the i40e_aqc_add_oveb_cloud, 1174 * and the generic direct completion structure 1175 */ 1176struct i40e_aqc_add_remove_control_packet_filter { 1177 u8 mac[6]; 1178 __le16 etype; 1179 __le16 flags; 1180#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1181#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1182#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1183#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1184#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1185 __le16 seid; 1186#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1187#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1188 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1189 __le16 queue; 1190 u8 reserved[2]; 1191}; 1192 1193I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1194 1195struct i40e_aqc_add_remove_control_packet_filter_completion { 1196 __le16 mac_etype_used; 1197 __le16 etype_used; 1198 __le16 mac_etype_free; 1199 __le16 etype_free; 1200 u8 reserved[8]; 1201}; 1202 1203I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1204 1205/* Add Cloud filters (indirect 0x025C) 1206 * Remove Cloud filters (indirect 0x025D) 1207 * uses the i40e_aqc_add_remove_cloud_filters, 1208 * and the generic indirect completion structure 1209 */ 1210struct i40e_aqc_add_remove_cloud_filters { 1211 u8 num_filters; 1212 u8 reserved; 1213 __le16 seid; 1214#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1215#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1216 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1217 u8 reserved2[4]; 1218 __le32 addr_high; 1219 __le32 addr_low; 1220}; 1221 1222I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1223 1224struct i40e_aqc_add_remove_cloud_filters_element_data { 1225 u8 outer_mac[6]; 1226 u8 inner_mac[6]; 1227 __le16 inner_vlan; 1228 union { 1229 struct { 1230 u8 reserved[12]; 1231 u8 data[4]; 1232 } v4; 1233 struct { 1234 u8 data[16]; 1235 } v6; 1236 } ipaddr; 1237 __le16 flags; 1238#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1239#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1240 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1241/* 0x0000 reserved */ 1242#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1243/* 0x0002 reserved */ 1244#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1245#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1246/* 0x0005 reserved */ 1247#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1248/* 0x0007 reserved */ 1249/* 0x0008 reserved */ 1250#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1251#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1252#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1253#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1254 1255#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1256#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1257#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1258#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1259#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1260 1261#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1262#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1263#define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0 1264#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1265#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2 1266#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1267 1268 __le32 tenant_id; 1269 u8 reserved[4]; 1270 __le16 queue_number; 1271#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1272#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1273 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1274 u8 reserved2[14]; 1275 /* response section */ 1276 u8 allocation_result; 1277#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1278#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1279 u8 response_reserved[7]; 1280}; 1281 1282struct i40e_aqc_remove_cloud_filters_completion { 1283 __le16 perfect_ovlan_used; 1284 __le16 perfect_ovlan_free; 1285 __le16 vlan_used; 1286 __le16 vlan_free; 1287 __le32 addr_high; 1288 __le32 addr_low; 1289}; 1290 1291I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1292 1293/* Add Mirror Rule (indirect or direct 0x0260) 1294 * Delete Mirror Rule (indirect or direct 0x0261) 1295 * note: some rule types (4,5) do not use an external buffer. 1296 * take care to set the flags correctly. 1297 */ 1298struct i40e_aqc_add_delete_mirror_rule { 1299 __le16 seid; 1300 __le16 rule_type; 1301#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1302#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1303 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1304#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1305#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1306#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1307#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1308#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1309 __le16 num_entries; 1310 __le16 destination; /* VSI for add, rule id for delete */ 1311 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1312 __le32 addr_low; 1313}; 1314 1315I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1316 1317struct i40e_aqc_add_delete_mirror_rule_completion { 1318 u8 reserved[2]; 1319 __le16 rule_id; /* only used on add */ 1320 __le16 mirror_rules_used; 1321 __le16 mirror_rules_free; 1322 __le32 addr_high; 1323 __le32 addr_low; 1324}; 1325 1326I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1327 1328/* DCB 0x03xx*/ 1329 1330/* PFC Ignore (direct 0x0301) 1331 * the command and response use the same descriptor structure 1332 */ 1333struct i40e_aqc_pfc_ignore { 1334 u8 tc_bitmap; 1335 u8 command_flags; /* unused on response */ 1336#define I40E_AQC_PFC_IGNORE_SET 0x80 1337#define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1338 u8 reserved[14]; 1339}; 1340 1341I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1342 1343/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1344 * with no parameters 1345 */ 1346 1347/* TX scheduler 0x04xx */ 1348 1349/* Almost all the indirect commands use 1350 * this generic struct to pass the SEID in param0 1351 */ 1352struct i40e_aqc_tx_sched_ind { 1353 __le16 vsi_seid; 1354 u8 reserved[6]; 1355 __le32 addr_high; 1356 __le32 addr_low; 1357}; 1358 1359I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1360 1361/* Several commands respond with a set of queue set handles */ 1362struct i40e_aqc_qs_handles_resp { 1363 __le16 qs_handles[8]; 1364}; 1365 1366/* Configure VSI BW limits (direct 0x0400) */ 1367struct i40e_aqc_configure_vsi_bw_limit { 1368 __le16 vsi_seid; 1369 u8 reserved[2]; 1370 __le16 credit; 1371 u8 reserved1[2]; 1372 u8 max_credit; /* 0-3, limit = 2^max */ 1373 u8 reserved2[7]; 1374}; 1375 1376I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1377 1378/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1379 * responds with i40e_aqc_qs_handles_resp 1380 */ 1381struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1382 u8 tc_valid_bits; 1383 u8 reserved[15]; 1384 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1385 1386 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1387 __le16 tc_bw_max[2]; 1388 u8 reserved1[28]; 1389}; 1390 1391I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1392 1393/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1394 * responds with i40e_aqc_qs_handles_resp 1395 */ 1396struct i40e_aqc_configure_vsi_tc_bw_data { 1397 u8 tc_valid_bits; 1398 u8 reserved[3]; 1399 u8 tc_bw_credits[8]; 1400 u8 reserved1[4]; 1401 __le16 qs_handles[8]; 1402}; 1403 1404I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1405 1406/* Query vsi bw configuration (indirect 0x0408) */ 1407struct i40e_aqc_query_vsi_bw_config_resp { 1408 u8 tc_valid_bits; 1409 u8 tc_suspended_bits; 1410 u8 reserved[14]; 1411 __le16 qs_handles[8]; 1412 u8 reserved1[4]; 1413 __le16 port_bw_limit; 1414 u8 reserved2[2]; 1415 u8 max_bw; /* 0-3, limit = 2^max */ 1416 u8 reserved3[23]; 1417}; 1418 1419I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1420 1421/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1422struct i40e_aqc_query_vsi_ets_sla_config_resp { 1423 u8 tc_valid_bits; 1424 u8 reserved[3]; 1425 u8 share_credits[8]; 1426 __le16 credits[8]; 1427 1428 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1429 __le16 tc_bw_max[2]; 1430}; 1431 1432I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1433 1434/* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1435struct i40e_aqc_configure_switching_comp_bw_limit { 1436 __le16 seid; 1437 u8 reserved[2]; 1438 __le16 credit; 1439 u8 reserved1[2]; 1440 u8 max_bw; /* 0-3, limit = 2^max */ 1441 u8 reserved2[7]; 1442}; 1443 1444I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1445 1446/* Enable Physical Port ETS (indirect 0x0413) 1447 * Modify Physical Port ETS (indirect 0x0414) 1448 * Disable Physical Port ETS (indirect 0x0415) 1449 */ 1450struct i40e_aqc_configure_switching_comp_ets_data { 1451 u8 reserved[4]; 1452 u8 tc_valid_bits; 1453 u8 seepage; 1454#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1455 u8 tc_strict_priority_flags; 1456 u8 reserved1[17]; 1457 u8 tc_bw_share_credits[8]; 1458 u8 reserved2[96]; 1459}; 1460 1461I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1462 1463/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1464struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1465 u8 tc_valid_bits; 1466 u8 reserved[15]; 1467 __le16 tc_bw_credit[8]; 1468 1469 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1470 __le16 tc_bw_max[2]; 1471 u8 reserved1[28]; 1472}; 1473 1474I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1475 1476/* Configure Switching Component Bandwidth Allocation per Tc 1477 * (indirect 0x0417) 1478 */ 1479struct i40e_aqc_configure_switching_comp_bw_config_data { 1480 u8 tc_valid_bits; 1481 u8 reserved[2]; 1482 u8 absolute_credits; /* bool */ 1483 u8 tc_bw_share_credits[8]; 1484 u8 reserved1[20]; 1485}; 1486 1487I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1488 1489/* Query Switching Component Configuration (indirect 0x0418) */ 1490struct i40e_aqc_query_switching_comp_ets_config_resp { 1491 u8 tc_valid_bits; 1492 u8 reserved[35]; 1493 __le16 port_bw_limit; 1494 u8 reserved1[2]; 1495 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1496 u8 reserved2[23]; 1497}; 1498 1499I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1500 1501/* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1502struct i40e_aqc_query_port_ets_config_resp { 1503 u8 reserved[4]; 1504 u8 tc_valid_bits; 1505 u8 reserved1; 1506 u8 tc_strict_priority_bits; 1507 u8 reserved2; 1508 u8 tc_bw_share_credits[8]; 1509 __le16 tc_bw_limits[8]; 1510 1511 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1512 __le16 tc_bw_max[2]; 1513 u8 reserved3[32]; 1514}; 1515 1516I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1517 1518/* Query Switching Component Bandwidth Allocation per Traffic Type 1519 * (indirect 0x041A) 1520 */ 1521struct i40e_aqc_query_switching_comp_bw_config_resp { 1522 u8 tc_valid_bits; 1523 u8 reserved[2]; 1524 u8 absolute_credits_enable; /* bool */ 1525 u8 tc_bw_share_credits[8]; 1526 __le16 tc_bw_limits[8]; 1527 1528 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1529 __le16 tc_bw_max[2]; 1530}; 1531 1532I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1533 1534/* Suspend/resume port TX traffic 1535 * (direct 0x041B and 0x041C) uses the generic SEID struct 1536 */ 1537 1538/* Configure partition BW 1539 * (indirect 0x041D) 1540 */ 1541struct i40e_aqc_configure_partition_bw_data { 1542 __le16 pf_valid_bits; 1543 u8 min_bw[16]; /* guaranteed bandwidth */ 1544 u8 max_bw[16]; /* bandwidth limit */ 1545}; 1546 1547I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1548 1549/* Get and set the active HMC resource profile and status. 1550 * (direct 0x0500) and (direct 0x0501) 1551 */ 1552struct i40e_aq_get_set_hmc_resource_profile { 1553 u8 pm_profile; 1554 u8 pe_vf_enabled; 1555 u8 reserved[14]; 1556}; 1557 1558I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1559 1560enum i40e_aq_hmc_profile { 1561 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1562 I40E_HMC_PROFILE_DEFAULT = 1, 1563 I40E_HMC_PROFILE_FAVOR_VF = 2, 1564 I40E_HMC_PROFILE_EQUAL = 3, 1565}; 1566 1567#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF 1568#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F 1569 1570/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1571 1572/* set in param0 for get phy abilities to report qualified modules */ 1573#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1574#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1575 1576enum i40e_aq_phy_type { 1577 I40E_PHY_TYPE_SGMII = 0x0, 1578 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1579 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1580 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1581 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1582 I40E_PHY_TYPE_XAUI = 0x5, 1583 I40E_PHY_TYPE_XFI = 0x6, 1584 I40E_PHY_TYPE_SFI = 0x7, 1585 I40E_PHY_TYPE_XLAUI = 0x8, 1586 I40E_PHY_TYPE_XLPPI = 0x9, 1587 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1588 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1589 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1590 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1591 I40E_PHY_TYPE_100BASE_TX = 0x11, 1592 I40E_PHY_TYPE_1000BASE_T = 0x12, 1593 I40E_PHY_TYPE_10GBASE_T = 0x13, 1594 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1595 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1596 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1597 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1598 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1599 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1600 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1601 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1602 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1603 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1604 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1605 I40E_PHY_TYPE_MAX 1606}; 1607 1608#define I40E_LINK_SPEED_100MB_SHIFT 0x1 1609#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1610#define I40E_LINK_SPEED_10GB_SHIFT 0x3 1611#define I40E_LINK_SPEED_40GB_SHIFT 0x4 1612#define I40E_LINK_SPEED_20GB_SHIFT 0x5 1613 1614enum i40e_aq_link_speed { 1615 I40E_LINK_SPEED_UNKNOWN = 0, 1616 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1617 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1618 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1619 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1620 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) 1621}; 1622 1623struct i40e_aqc_module_desc { 1624 u8 oui[3]; 1625 u8 reserved1; 1626 u8 part_number[16]; 1627 u8 revision[4]; 1628 u8 reserved2[8]; 1629}; 1630 1631I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1632 1633struct i40e_aq_get_phy_abilities_resp { 1634 __le32 phy_type; /* bitmap using the above enum for offsets */ 1635 u8 link_speed; /* bitmap using the above enum bit patterns */ 1636 u8 abilities; 1637#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1638#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1639#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1640#define I40E_AQ_PHY_LINK_ENABLED 0x08 1641#define I40E_AQ_PHY_AN_ENABLED 0x10 1642#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1643 __le16 eee_capability; 1644#define I40E_AQ_EEE_100BASE_TX 0x0002 1645#define I40E_AQ_EEE_1000BASE_T 0x0004 1646#define I40E_AQ_EEE_10GBASE_T 0x0008 1647#define I40E_AQ_EEE_1000BASE_KX 0x0010 1648#define I40E_AQ_EEE_10GBASE_KX4 0x0020 1649#define I40E_AQ_EEE_10GBASE_KR 0x0040 1650 __le32 eeer_val; 1651 u8 d3_lpan; 1652#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1653 u8 reserved[3]; 1654 u8 phy_id[4]; 1655 u8 module_type[3]; 1656 u8 qualified_module_count; 1657#define I40E_AQ_PHY_MAX_QMS 16 1658 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1659}; 1660 1661I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1662 1663/* Set PHY Config (direct 0x0601) */ 1664struct i40e_aq_set_phy_config { /* same bits as above in all */ 1665 __le32 phy_type; 1666 u8 link_speed; 1667 u8 abilities; 1668/* bits 0-2 use the values from get_phy_abilities_resp */ 1669#define I40E_AQ_PHY_ENABLE_LINK 0x08 1670#define I40E_AQ_PHY_ENABLE_AN 0x10 1671#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1672 __le16 eee_capability; 1673 __le32 eeer; 1674 u8 low_power_ctrl; 1675 u8 reserved[3]; 1676}; 1677 1678I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1679 1680/* Set MAC Config command data structure (direct 0x0603) */ 1681struct i40e_aq_set_mac_config { 1682 __le16 max_frame_size; 1683 u8 params; 1684#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1685#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1686#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1687#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1688#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1689#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1690#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1691#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1692#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1693#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1694#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1695#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1696#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1697#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1698 u8 tx_timer_priority; /* bitmap */ 1699 __le16 tx_timer_value; 1700 __le16 fc_refresh_threshold; 1701 u8 reserved[8]; 1702}; 1703 1704I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1705 1706/* Restart Auto-Negotiation (direct 0x605) */ 1707struct i40e_aqc_set_link_restart_an { 1708 u8 command; 1709#define I40E_AQ_PHY_RESTART_AN 0x02 1710#define I40E_AQ_PHY_LINK_ENABLE 0x04 1711 u8 reserved[15]; 1712}; 1713 1714I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1715 1716/* Get Link Status cmd & response data structure (direct 0x0607) */ 1717struct i40e_aqc_get_link_status { 1718 __le16 command_flags; /* only field set on command */ 1719#define I40E_AQ_LSE_MASK 0x3 1720#define I40E_AQ_LSE_NOP 0x0 1721#define I40E_AQ_LSE_DISABLE 0x2 1722#define I40E_AQ_LSE_ENABLE 0x3 1723/* only response uses this flag */ 1724#define I40E_AQ_LSE_IS_ENABLED 0x1 1725 u8 phy_type; /* i40e_aq_phy_type */ 1726 u8 link_speed; /* i40e_aq_link_speed */ 1727 u8 link_info; 1728#define I40E_AQ_LINK_UP 0x01 1729#define I40E_AQ_LINK_FAULT 0x02 1730#define I40E_AQ_LINK_FAULT_TX 0x04 1731#define I40E_AQ_LINK_FAULT_RX 0x08 1732#define I40E_AQ_LINK_FAULT_REMOTE 0x10 1733#define I40E_AQ_MEDIA_AVAILABLE 0x40 1734#define I40E_AQ_SIGNAL_DETECT 0x80 1735 u8 an_info; 1736#define I40E_AQ_AN_COMPLETED 0x01 1737#define I40E_AQ_LP_AN_ABILITY 0x02 1738#define I40E_AQ_PD_FAULT 0x04 1739#define I40E_AQ_FEC_EN 0x08 1740#define I40E_AQ_PHY_LOW_POWER 0x10 1741#define I40E_AQ_LINK_PAUSE_TX 0x20 1742#define I40E_AQ_LINK_PAUSE_RX 0x40 1743#define I40E_AQ_QUALIFIED_MODULE 0x80 1744 u8 ext_info; 1745#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1746#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1747#define I40E_AQ_LINK_TX_SHIFT 0x02 1748#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1749#define I40E_AQ_LINK_TX_ACTIVE 0x00 1750#define I40E_AQ_LINK_TX_DRAINED 0x01 1751#define I40E_AQ_LINK_TX_FLUSHED 0x03 1752#define I40E_AQ_LINK_FORCED_40G 0x10 1753 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1754 __le16 max_frame_size; 1755 u8 config; 1756#define I40E_AQ_CONFIG_CRC_ENA 0x04 1757#define I40E_AQ_CONFIG_PACING_MASK 0x78 1758 u8 reserved[5]; 1759}; 1760 1761I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1762 1763/* Set event mask command (direct 0x613) */ 1764struct i40e_aqc_set_phy_int_mask { 1765 u8 reserved[8]; 1766 __le16 event_mask; 1767#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1768#define I40E_AQ_EVENT_MEDIA_NA 0x0004 1769#define I40E_AQ_EVENT_LINK_FAULT 0x0008 1770#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1771#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1772#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1773#define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1774#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1775#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1776 u8 reserved1[6]; 1777}; 1778 1779I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1780 1781/* Get Local AN advt register (direct 0x0614) 1782 * Set Local AN advt register (direct 0x0615) 1783 * Get Link Partner AN advt register (direct 0x0616) 1784 */ 1785struct i40e_aqc_an_advt_reg { 1786 __le32 local_an_reg0; 1787 __le16 local_an_reg1; 1788 u8 reserved[10]; 1789}; 1790 1791I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1792 1793/* Set Loopback mode (0x0618) */ 1794struct i40e_aqc_set_lb_mode { 1795 __le16 lb_mode; 1796#define I40E_AQ_LB_PHY_LOCAL 0x01 1797#define I40E_AQ_LB_PHY_REMOTE 0x02 1798#define I40E_AQ_LB_MAC_LOCAL 0x04 1799 u8 reserved[14]; 1800}; 1801 1802I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1803 1804/* Set PHY Debug command (0x0622) */ 1805struct i40e_aqc_set_phy_debug { 1806 u8 command_flags; 1807#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1808#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1809#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1810 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1811#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1812#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1813#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1814#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1815 u8 reserved[15]; 1816}; 1817 1818I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1819 1820enum i40e_aq_phy_reg_type { 1821 I40E_AQC_PHY_REG_INTERNAL = 0x1, 1822 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1823 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1824}; 1825 1826/* NVM Read command (indirect 0x0701) 1827 * NVM Erase commands (direct 0x0702) 1828 * NVM Update commands (indirect 0x0703) 1829 */ 1830struct i40e_aqc_nvm_update { 1831 u8 command_flags; 1832#define I40E_AQ_NVM_LAST_CMD 0x01 1833#define I40E_AQ_NVM_FLASH_ONLY 0x80 1834 u8 module_pointer; 1835 __le16 length; 1836 __le32 offset; 1837 __le32 addr_high; 1838 __le32 addr_low; 1839}; 1840 1841I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 1842 1843/* NVM Config Read (indirect 0x0704) */ 1844struct i40e_aqc_nvm_config_read { 1845 __le16 cmd_flags; 1846#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 1847#define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 1848#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 1849 __le16 element_count; 1850 __le16 element_id; /* Feature/field ID */ 1851 __le16 element_id_msw; /* MSWord of field ID */ 1852 __le32 address_high; 1853 __le32 address_low; 1854}; 1855 1856I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 1857 1858/* NVM Config Write (indirect 0x0705) */ 1859struct i40e_aqc_nvm_config_write { 1860 __le16 cmd_flags; 1861 __le16 element_count; 1862 u8 reserved[4]; 1863 __le32 address_high; 1864 __le32 address_low; 1865}; 1866 1867I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 1868 1869/* Used for 0x0704 as well as for 0x0705 commands */ 1870#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 1871#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 1872#define I40E_AQ_ANVM_FEATURE 0 1873#define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 1874struct i40e_aqc_nvm_config_data_feature { 1875 __le16 feature_id; 1876#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 1877#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 1878#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 1879 __le16 feature_options; 1880 __le16 feature_selection; 1881}; 1882 1883I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 1884 1885struct i40e_aqc_nvm_config_data_immediate_field { 1886 __le32 field_id; 1887 __le32 field_value; 1888 __le16 field_options; 1889 __le16 reserved; 1890}; 1891 1892I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 1893 1894/* Send to PF command (indirect 0x0801) id is only used by PF 1895 * Send to VF command (indirect 0x0802) id is only used by PF 1896 * Send to Peer PF command (indirect 0x0803) 1897 */ 1898struct i40e_aqc_pf_vf_message { 1899 __le32 id; 1900 u8 reserved[4]; 1901 __le32 addr_high; 1902 __le32 addr_low; 1903}; 1904 1905I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 1906 1907/* Alternate structure */ 1908 1909/* Direct write (direct 0x0900) 1910 * Direct read (direct 0x0902) 1911 */ 1912struct i40e_aqc_alternate_write { 1913 __le32 address0; 1914 __le32 data0; 1915 __le32 address1; 1916 __le32 data1; 1917}; 1918 1919I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 1920 1921/* Indirect write (indirect 0x0901) 1922 * Indirect read (indirect 0x0903) 1923 */ 1924 1925struct i40e_aqc_alternate_ind_write { 1926 __le32 address; 1927 __le32 length; 1928 __le32 addr_high; 1929 __le32 addr_low; 1930}; 1931 1932I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 1933 1934/* Done alternate write (direct 0x0904) 1935 * uses i40e_aq_desc 1936 */ 1937struct i40e_aqc_alternate_write_done { 1938 __le16 cmd_flags; 1939#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 1940#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 1941#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 1942#define I40E_AQ_ALTERNATE_RESET_NEEDED 2 1943 u8 reserved[14]; 1944}; 1945 1946I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 1947 1948/* Set OEM mode (direct 0x0905) */ 1949struct i40e_aqc_alternate_set_mode { 1950 __le32 mode; 1951#define I40E_AQ_ALTERNATE_MODE_NONE 0 1952#define I40E_AQ_ALTERNATE_MODE_OEM 1 1953 u8 reserved[12]; 1954}; 1955 1956I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 1957 1958/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 1959 1960/* async events 0x10xx */ 1961 1962/* Lan Queue Overflow Event (direct, 0x1001) */ 1963struct i40e_aqc_lan_overflow { 1964 __le32 prtdcb_rupto; 1965 __le32 otx_ctl; 1966 u8 reserved[8]; 1967}; 1968 1969I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 1970 1971/* Get LLDP MIB (indirect 0x0A00) */ 1972struct i40e_aqc_lldp_get_mib { 1973 u8 type; 1974 u8 reserved1; 1975#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 1976#define I40E_AQ_LLDP_MIB_LOCAL 0x0 1977#define I40E_AQ_LLDP_MIB_REMOTE 0x1 1978#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 1979#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 1980#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 1981#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 1982#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 1983#define I40E_AQ_LLDP_TX_SHIFT 0x4 1984#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 1985/* TX pause flags use I40E_AQ_LINK_TX_* above */ 1986 __le16 local_len; 1987 __le16 remote_len; 1988 u8 reserved2[2]; 1989 __le32 addr_high; 1990 __le32 addr_low; 1991}; 1992 1993I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 1994 1995/* Configure LLDP MIB Change Event (direct 0x0A01) 1996 * also used for the event (with type in the command field) 1997 */ 1998struct i40e_aqc_lldp_update_mib { 1999 u8 command; 2000#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2001#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2002 u8 reserved[7]; 2003 __le32 addr_high; 2004 __le32 addr_low; 2005}; 2006 2007I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2008 2009/* Add LLDP TLV (indirect 0x0A02) 2010 * Delete LLDP TLV (indirect 0x0A04) 2011 */ 2012struct i40e_aqc_lldp_add_tlv { 2013 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2014 u8 reserved1[1]; 2015 __le16 len; 2016 u8 reserved2[4]; 2017 __le32 addr_high; 2018 __le32 addr_low; 2019}; 2020 2021I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2022 2023/* Update LLDP TLV (indirect 0x0A03) */ 2024struct i40e_aqc_lldp_update_tlv { 2025 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2026 u8 reserved; 2027 __le16 old_len; 2028 __le16 new_offset; 2029 __le16 new_len; 2030 __le32 addr_high; 2031 __le32 addr_low; 2032}; 2033 2034I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2035 2036/* Stop LLDP (direct 0x0A05) */ 2037struct i40e_aqc_lldp_stop { 2038 u8 command; 2039#define I40E_AQ_LLDP_AGENT_STOP 0x0 2040#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2041 u8 reserved[15]; 2042}; 2043 2044I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2045 2046/* Start LLDP (direct 0x0A06) */ 2047 2048struct i40e_aqc_lldp_start { 2049 u8 command; 2050#define I40E_AQ_LLDP_AGENT_START 0x1 2051 u8 reserved[15]; 2052}; 2053 2054I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2055 2056/* Get CEE DCBX Oper Config (0x0A07) 2057 * uses the generic descriptor struct 2058 * returns below as indirect response 2059 */ 2060 2061#define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2062#define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2063#define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2064#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2065#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2066#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2067#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2068#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2069#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2070#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2071#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2072#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2073struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2074 u8 reserved1; 2075 u8 oper_num_tc; 2076 u8 oper_prio_tc[4]; 2077 u8 reserved2; 2078 u8 oper_tc_bw[8]; 2079 u8 oper_pfc_en; 2080 u8 reserved3; 2081 __le16 oper_app_prio; 2082 u8 reserved4; 2083 __le16 tlv_status; 2084}; 2085 2086I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2087 2088struct i40e_aqc_get_cee_dcb_cfg_resp { 2089 u8 oper_num_tc; 2090 u8 oper_prio_tc[4]; 2091 u8 oper_tc_bw[8]; 2092 u8 oper_pfc_en; 2093 __le16 oper_app_prio; 2094 __le32 tlv_status; 2095 u8 reserved[12]; 2096}; 2097 2098I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2099 2100/* Set Local LLDP MIB (indirect 0x0A08) 2101 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2102 */ 2103struct i40e_aqc_lldp_set_local_mib { 2104#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2105#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2106 u8 type; 2107 u8 reserved0; 2108 __le16 length; 2109 u8 reserved1[4]; 2110 __le32 address_high; 2111 __le32 address_low; 2112}; 2113 2114I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2115 2116/* Stop/Start LLDP Agent (direct 0x0A09) 2117 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2118 */ 2119struct i40e_aqc_lldp_stop_start_specific_agent { 2120#define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2121#define I40E_AQC_START_SPECIFIC_AGENT_MASK (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2122 u8 command; 2123 u8 reserved[15]; 2124}; 2125 2126I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2127 2128/* Add Udp Tunnel command and completion (direct 0x0B00) */ 2129struct i40e_aqc_add_udp_tunnel { 2130 __le16 udp_port; 2131 u8 reserved0[3]; 2132 u8 protocol_type; 2133#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2134#define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2135#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2136 u8 reserved1[10]; 2137}; 2138 2139I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2140 2141struct i40e_aqc_add_udp_tunnel_completion { 2142 __le16 udp_port; 2143 u8 filter_entry_index; 2144 u8 multiple_pfs; 2145#define I40E_AQC_SINGLE_PF 0x0 2146#define I40E_AQC_MULTIPLE_PFS 0x1 2147 u8 total_filters; 2148 u8 reserved[11]; 2149}; 2150 2151I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2152 2153/* remove UDP Tunnel command (0x0B01) */ 2154struct i40e_aqc_remove_udp_tunnel { 2155 u8 reserved[2]; 2156 u8 index; /* 0 to 15 */ 2157 u8 reserved2[13]; 2158}; 2159 2160I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2161 2162struct i40e_aqc_del_udp_tunnel_completion { 2163 __le16 udp_port; 2164 u8 index; /* 0 to 15 */ 2165 u8 multiple_pfs; 2166 u8 total_filters_used; 2167 u8 reserved1[11]; 2168}; 2169 2170I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2171 2172/* tunnel key structure 0x0B10 */ 2173 2174struct i40e_aqc_tunnel_key_structure { 2175 u8 key1_off; 2176 u8 key2_off; 2177 u8 key1_len; /* 0 to 15 */ 2178 u8 key2_len; /* 0 to 15 */ 2179 u8 flags; 2180#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2181/* response flags */ 2182#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2183#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2184#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2185 u8 network_key_index; 2186#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2187#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2188#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2189#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2190 u8 reserved[10]; 2191}; 2192 2193I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2194 2195/* OEM mode commands (direct 0xFE0x) */ 2196struct i40e_aqc_oem_param_change { 2197 __le32 param_type; 2198#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2199#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2200#define I40E_AQ_OEM_PARAM_MAC 2 2201 __le32 param_value1; 2202 __le16 param_value2; 2203 u8 reserved[6]; 2204}; 2205 2206I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2207 2208struct i40e_aqc_oem_state_change { 2209 __le32 state; 2210#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2211#define I40E_AQ_OEM_STATE_LINK_UP 0x1 2212 u8 reserved[12]; 2213}; 2214 2215I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2216 2217/* Initialize OCSD (0xFE02, direct) */ 2218struct i40e_aqc_opc_oem_ocsd_initialize { 2219 u8 type_status; 2220 u8 reserved1[3]; 2221 __le32 ocsd_memory_block_addr_high; 2222 __le32 ocsd_memory_block_addr_low; 2223 __le32 requested_update_interval; 2224}; 2225 2226I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2227 2228/* Initialize OCBB (0xFE03, direct) */ 2229struct i40e_aqc_opc_oem_ocbb_initialize { 2230 u8 type_status; 2231 u8 reserved1[3]; 2232 __le32 ocbb_memory_block_addr_high; 2233 __le32 ocbb_memory_block_addr_low; 2234 u8 reserved2[4]; 2235}; 2236 2237I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2238 2239/* debug commands */ 2240 2241/* get device id (0xFF00) uses the generic structure */ 2242 2243/* set test more (0xFF01, internal) */ 2244 2245struct i40e_acq_set_test_mode { 2246 u8 mode; 2247#define I40E_AQ_TEST_PARTIAL 0 2248#define I40E_AQ_TEST_FULL 1 2249#define I40E_AQ_TEST_NVM 2 2250 u8 reserved[3]; 2251 u8 command; 2252#define I40E_AQ_TEST_OPEN 0 2253#define I40E_AQ_TEST_CLOSE 1 2254#define I40E_AQ_TEST_INC 2 2255 u8 reserved2[3]; 2256 __le32 address_high; 2257 __le32 address_low; 2258}; 2259 2260I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2261 2262/* Debug Read Register command (0xFF03) 2263 * Debug Write Register command (0xFF04) 2264 */ 2265struct i40e_aqc_debug_reg_read_write { 2266 __le32 reserved; 2267 __le32 address; 2268 __le32 value_high; 2269 __le32 value_low; 2270}; 2271 2272I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2273 2274/* Scatter/gather Reg Read (indirect 0xFF05) 2275 * Scatter/gather Reg Write (indirect 0xFF06) 2276 */ 2277 2278/* i40e_aq_desc is used for the command */ 2279struct i40e_aqc_debug_reg_sg_element_data { 2280 __le32 address; 2281 __le32 value; 2282}; 2283 2284/* Debug Modify register (direct 0xFF07) */ 2285struct i40e_aqc_debug_modify_reg { 2286 __le32 address; 2287 __le32 value; 2288 __le32 clear_mask; 2289 __le32 set_mask; 2290}; 2291 2292I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2293 2294/* dump internal data (0xFF08, indirect) */ 2295 2296#define I40E_AQ_CLUSTER_ID_AUX 0 2297#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2298#define I40E_AQ_CLUSTER_ID_TXSCHED 2 2299#define I40E_AQ_CLUSTER_ID_HMC 3 2300#define I40E_AQ_CLUSTER_ID_MAC0 4 2301#define I40E_AQ_CLUSTER_ID_MAC1 5 2302#define I40E_AQ_CLUSTER_ID_MAC2 6 2303#define I40E_AQ_CLUSTER_ID_MAC3 7 2304#define I40E_AQ_CLUSTER_ID_DCB 8 2305#define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2306#define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2307#define I40E_AQ_CLUSTER_ID_ALTRAM 11 2308 2309struct i40e_aqc_debug_dump_internals { 2310 u8 cluster_id; 2311 u8 table_id; 2312 __le16 data_size; 2313 __le32 idx; 2314 __le32 address_high; 2315 __le32 address_low; 2316}; 2317 2318I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2319 2320struct i40e_aqc_debug_modify_internals { 2321 u8 cluster_id; 2322 u8 cluster_specific_params[7]; 2323 __le32 address_high; 2324 __le32 address_low; 2325}; 2326 2327I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2328 2329#endif 2330