i40e_adminq_cmd.h revision 270346
1266423Sjfv/****************************************************************************** 2266423Sjfv 3266423Sjfv Copyright (c) 2013-2014, Intel Corporation 4266423Sjfv All rights reserved. 5266423Sjfv 6266423Sjfv Redistribution and use in source and binary forms, with or without 7266423Sjfv modification, are permitted provided that the following conditions are met: 8266423Sjfv 9266423Sjfv 1. Redistributions of source code must retain the above copyright notice, 10266423Sjfv this list of conditions and the following disclaimer. 11266423Sjfv 12266423Sjfv 2. Redistributions in binary form must reproduce the above copyright 13266423Sjfv notice, this list of conditions and the following disclaimer in the 14266423Sjfv documentation and/or other materials provided with the distribution. 15266423Sjfv 16266423Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17266423Sjfv contributors may be used to endorse or promote products derived from 18266423Sjfv this software without specific prior written permission. 19266423Sjfv 20266423Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21266423Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22266423Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23266423Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24266423Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25266423Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26266423Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27266423Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28266423Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29266423Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30266423Sjfv POSSIBILITY OF SUCH DAMAGE. 31266423Sjfv 32266423Sjfv******************************************************************************/ 33266423Sjfv/*$FreeBSD: head/sys/dev/ixl/i40e_adminq_cmd.h 270346 2014-08-22 18:59:19Z jfv $*/ 34266423Sjfv 35266423Sjfv#ifndef _I40E_ADMINQ_CMD_H_ 36266423Sjfv#define _I40E_ADMINQ_CMD_H_ 37266423Sjfv 38266423Sjfv/* This header file defines the i40e Admin Queue commands and is shared between 39266423Sjfv * i40e Firmware and Software. 40266423Sjfv * 41266423Sjfv * This file needs to comply with the Linux Kernel coding style. 42266423Sjfv */ 43266423Sjfv 44270346Sjfv#define I40E_FW_API_VERSION_MAJOR 0x0001 45270346Sjfv#define I40E_FW_API_VERSION_MINOR 0x0002 46266423Sjfv 47266423Sjfvstruct i40e_aq_desc { 48266423Sjfv __le16 flags; 49266423Sjfv __le16 opcode; 50266423Sjfv __le16 datalen; 51266423Sjfv __le16 retval; 52266423Sjfv __le32 cookie_high; 53266423Sjfv __le32 cookie_low; 54266423Sjfv union { 55266423Sjfv struct { 56266423Sjfv __le32 param0; 57266423Sjfv __le32 param1; 58266423Sjfv __le32 param2; 59266423Sjfv __le32 param3; 60266423Sjfv } internal; 61266423Sjfv struct { 62266423Sjfv __le32 param0; 63266423Sjfv __le32 param1; 64266423Sjfv __le32 addr_high; 65266423Sjfv __le32 addr_low; 66266423Sjfv } external; 67266423Sjfv u8 raw[16]; 68266423Sjfv } params; 69266423Sjfv}; 70266423Sjfv 71266423Sjfv/* Flags sub-structure 72266423Sjfv * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 73266423Sjfv * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 74266423Sjfv */ 75266423Sjfv 76266423Sjfv/* command flags and offsets*/ 77270346Sjfv#define I40E_AQ_FLAG_DD_SHIFT 0 78270346Sjfv#define I40E_AQ_FLAG_CMP_SHIFT 1 79270346Sjfv#define I40E_AQ_FLAG_ERR_SHIFT 2 80270346Sjfv#define I40E_AQ_FLAG_VFE_SHIFT 3 81270346Sjfv#define I40E_AQ_FLAG_LB_SHIFT 9 82270346Sjfv#define I40E_AQ_FLAG_RD_SHIFT 10 83270346Sjfv#define I40E_AQ_FLAG_VFC_SHIFT 11 84270346Sjfv#define I40E_AQ_FLAG_BUF_SHIFT 12 85270346Sjfv#define I40E_AQ_FLAG_SI_SHIFT 13 86270346Sjfv#define I40E_AQ_FLAG_EI_SHIFT 14 87270346Sjfv#define I40E_AQ_FLAG_FE_SHIFT 15 88266423Sjfv 89270346Sjfv#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 90270346Sjfv#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 91270346Sjfv#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 92270346Sjfv#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 93270346Sjfv#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 94270346Sjfv#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 95270346Sjfv#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 96270346Sjfv#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 97270346Sjfv#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 98270346Sjfv#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 99270346Sjfv#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 100266423Sjfv 101266423Sjfv/* error codes */ 102266423Sjfvenum i40e_admin_queue_err { 103270346Sjfv I40E_AQ_RC_OK = 0, /* success */ 104270346Sjfv I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 105270346Sjfv I40E_AQ_RC_ENOENT = 2, /* No such element */ 106270346Sjfv I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 107270346Sjfv I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 108270346Sjfv I40E_AQ_RC_EIO = 5, /* I/O error */ 109270346Sjfv I40E_AQ_RC_ENXIO = 6, /* No such resource */ 110270346Sjfv I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 111270346Sjfv I40E_AQ_RC_EAGAIN = 8, /* Try again */ 112270346Sjfv I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 113270346Sjfv I40E_AQ_RC_EACCES = 10, /* Permission denied */ 114270346Sjfv I40E_AQ_RC_EFAULT = 11, /* Bad address */ 115270346Sjfv I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 116270346Sjfv I40E_AQ_RC_EEXIST = 13, /* object already exists */ 117270346Sjfv I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 118270346Sjfv I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 119270346Sjfv I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 120270346Sjfv I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 121270346Sjfv I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 122270346Sjfv I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 123270346Sjfv I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 124270346Sjfv I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 125270346Sjfv I40E_AQ_RC_EFBIG = 22, /* File too large */ 126266423Sjfv}; 127266423Sjfv 128266423Sjfv/* Admin Queue command opcodes */ 129266423Sjfvenum i40e_admin_queue_opc { 130266423Sjfv /* aq commands */ 131270346Sjfv i40e_aqc_opc_get_version = 0x0001, 132270346Sjfv i40e_aqc_opc_driver_version = 0x0002, 133270346Sjfv i40e_aqc_opc_queue_shutdown = 0x0003, 134270346Sjfv i40e_aqc_opc_set_pf_context = 0x0004, 135266423Sjfv 136266423Sjfv /* resource ownership */ 137270346Sjfv i40e_aqc_opc_request_resource = 0x0008, 138270346Sjfv i40e_aqc_opc_release_resource = 0x0009, 139266423Sjfv 140270346Sjfv i40e_aqc_opc_list_func_capabilities = 0x000A, 141270346Sjfv i40e_aqc_opc_list_dev_capabilities = 0x000B, 142266423Sjfv 143270346Sjfv i40e_aqc_opc_set_cppm_configuration = 0x0103, 144270346Sjfv i40e_aqc_opc_set_arp_proxy_entry = 0x0104, 145270346Sjfv i40e_aqc_opc_set_ns_proxy_entry = 0x0105, 146266423Sjfv 147266423Sjfv /* LAA */ 148270346Sjfv i40e_aqc_opc_mng_laa = 0x0106, /* AQ obsolete */ 149270346Sjfv i40e_aqc_opc_mac_address_read = 0x0107, 150270346Sjfv i40e_aqc_opc_mac_address_write = 0x0108, 151266423Sjfv 152266423Sjfv /* PXE */ 153270346Sjfv i40e_aqc_opc_clear_pxe_mode = 0x0110, 154266423Sjfv 155266423Sjfv /* internal switch commands */ 156270346Sjfv i40e_aqc_opc_get_switch_config = 0x0200, 157270346Sjfv i40e_aqc_opc_add_statistics = 0x0201, 158270346Sjfv i40e_aqc_opc_remove_statistics = 0x0202, 159270346Sjfv i40e_aqc_opc_set_port_parameters = 0x0203, 160270346Sjfv i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 161266423Sjfv 162270346Sjfv i40e_aqc_opc_add_vsi = 0x0210, 163270346Sjfv i40e_aqc_opc_update_vsi_parameters = 0x0211, 164270346Sjfv i40e_aqc_opc_get_vsi_parameters = 0x0212, 165266423Sjfv 166270346Sjfv i40e_aqc_opc_add_pv = 0x0220, 167270346Sjfv i40e_aqc_opc_update_pv_parameters = 0x0221, 168270346Sjfv i40e_aqc_opc_get_pv_parameters = 0x0222, 169266423Sjfv 170270346Sjfv i40e_aqc_opc_add_veb = 0x0230, 171270346Sjfv i40e_aqc_opc_update_veb_parameters = 0x0231, 172270346Sjfv i40e_aqc_opc_get_veb_parameters = 0x0232, 173266423Sjfv 174270346Sjfv i40e_aqc_opc_delete_element = 0x0243, 175266423Sjfv 176270346Sjfv i40e_aqc_opc_add_macvlan = 0x0250, 177270346Sjfv i40e_aqc_opc_remove_macvlan = 0x0251, 178270346Sjfv i40e_aqc_opc_add_vlan = 0x0252, 179270346Sjfv i40e_aqc_opc_remove_vlan = 0x0253, 180270346Sjfv i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 181270346Sjfv i40e_aqc_opc_add_tag = 0x0255, 182270346Sjfv i40e_aqc_opc_remove_tag = 0x0256, 183270346Sjfv i40e_aqc_opc_add_multicast_etag = 0x0257, 184270346Sjfv i40e_aqc_opc_remove_multicast_etag = 0x0258, 185270346Sjfv i40e_aqc_opc_update_tag = 0x0259, 186270346Sjfv i40e_aqc_opc_add_control_packet_filter = 0x025A, 187270346Sjfv i40e_aqc_opc_remove_control_packet_filter = 0x025B, 188270346Sjfv i40e_aqc_opc_add_cloud_filters = 0x025C, 189270346Sjfv i40e_aqc_opc_remove_cloud_filters = 0x025D, 190266423Sjfv 191270346Sjfv i40e_aqc_opc_add_mirror_rule = 0x0260, 192270346Sjfv i40e_aqc_opc_delete_mirror_rule = 0x0261, 193266423Sjfv 194266423Sjfv /* DCB commands */ 195270346Sjfv i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 196270346Sjfv i40e_aqc_opc_dcb_updated = 0x0302, 197266423Sjfv 198266423Sjfv /* TX scheduler */ 199270346Sjfv i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 200270346Sjfv i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 201270346Sjfv i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 202270346Sjfv i40e_aqc_opc_query_vsi_bw_config = 0x0408, 203270346Sjfv i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 204270346Sjfv i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 205266423Sjfv 206270346Sjfv i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 207270346Sjfv i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 208270346Sjfv i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 209270346Sjfv i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 210270346Sjfv i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 211270346Sjfv i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 212270346Sjfv i40e_aqc_opc_query_port_ets_config = 0x0419, 213270346Sjfv i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 214270346Sjfv i40e_aqc_opc_suspend_port_tx = 0x041B, 215270346Sjfv i40e_aqc_opc_resume_port_tx = 0x041C, 216270346Sjfv i40e_aqc_opc_configure_partition_bw = 0x041D, 217266423Sjfv 218266423Sjfv /* hmc */ 219270346Sjfv i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 220270346Sjfv i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 221266423Sjfv 222266423Sjfv /* phy commands*/ 223270346Sjfv i40e_aqc_opc_get_phy_abilities = 0x0600, 224270346Sjfv i40e_aqc_opc_set_phy_config = 0x0601, 225270346Sjfv i40e_aqc_opc_set_mac_config = 0x0603, 226270346Sjfv i40e_aqc_opc_set_link_restart_an = 0x0605, 227270346Sjfv i40e_aqc_opc_get_link_status = 0x0607, 228270346Sjfv i40e_aqc_opc_set_phy_int_mask = 0x0613, 229270346Sjfv i40e_aqc_opc_get_local_advt_reg = 0x0614, 230270346Sjfv i40e_aqc_opc_set_local_advt_reg = 0x0615, 231270346Sjfv i40e_aqc_opc_get_partner_advt = 0x0616, 232270346Sjfv i40e_aqc_opc_set_lb_modes = 0x0618, 233270346Sjfv i40e_aqc_opc_get_phy_wol_caps = 0x0621, 234270346Sjfv i40e_aqc_opc_set_phy_debug = 0x0622, 235270346Sjfv i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 236266423Sjfv 237266423Sjfv /* NVM commands */ 238270346Sjfv i40e_aqc_opc_nvm_read = 0x0701, 239270346Sjfv i40e_aqc_opc_nvm_erase = 0x0702, 240270346Sjfv i40e_aqc_opc_nvm_update = 0x0703, 241270346Sjfv i40e_aqc_opc_nvm_config_read = 0x0704, 242270346Sjfv i40e_aqc_opc_nvm_config_write = 0x0705, 243266423Sjfv 244266423Sjfv /* virtualization commands */ 245270346Sjfv i40e_aqc_opc_send_msg_to_pf = 0x0801, 246270346Sjfv i40e_aqc_opc_send_msg_to_vf = 0x0802, 247270346Sjfv i40e_aqc_opc_send_msg_to_peer = 0x0803, 248266423Sjfv 249266423Sjfv /* alternate structure */ 250270346Sjfv i40e_aqc_opc_alternate_write = 0x0900, 251270346Sjfv i40e_aqc_opc_alternate_write_indirect = 0x0901, 252270346Sjfv i40e_aqc_opc_alternate_read = 0x0902, 253270346Sjfv i40e_aqc_opc_alternate_read_indirect = 0x0903, 254270346Sjfv i40e_aqc_opc_alternate_write_done = 0x0904, 255270346Sjfv i40e_aqc_opc_alternate_set_mode = 0x0905, 256270346Sjfv i40e_aqc_opc_alternate_clear_port = 0x0906, 257266423Sjfv 258266423Sjfv /* LLDP commands */ 259270346Sjfv i40e_aqc_opc_lldp_get_mib = 0x0A00, 260270346Sjfv i40e_aqc_opc_lldp_update_mib = 0x0A01, 261270346Sjfv i40e_aqc_opc_lldp_add_tlv = 0x0A02, 262270346Sjfv i40e_aqc_opc_lldp_update_tlv = 0x0A03, 263270346Sjfv i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 264270346Sjfv i40e_aqc_opc_lldp_stop = 0x0A05, 265270346Sjfv i40e_aqc_opc_lldp_start = 0x0A06, 266266423Sjfv 267266423Sjfv /* Tunnel commands */ 268270346Sjfv i40e_aqc_opc_add_udp_tunnel = 0x0B00, 269270346Sjfv i40e_aqc_opc_del_udp_tunnel = 0x0B01, 270270346Sjfv i40e_aqc_opc_tunnel_key_structure = 0x0B10, 271266423Sjfv 272266423Sjfv /* Async Events */ 273270346Sjfv i40e_aqc_opc_event_lan_overflow = 0x1001, 274266423Sjfv 275266423Sjfv /* OEM commands */ 276270346Sjfv i40e_aqc_opc_oem_parameter_change = 0xFE00, 277270346Sjfv i40e_aqc_opc_oem_device_status_change = 0xFE01, 278266423Sjfv 279266423Sjfv /* debug commands */ 280270346Sjfv i40e_aqc_opc_debug_get_deviceid = 0xFF00, 281270346Sjfv i40e_aqc_opc_debug_set_mode = 0xFF01, 282270346Sjfv i40e_aqc_opc_debug_read_reg = 0xFF03, 283270346Sjfv i40e_aqc_opc_debug_write_reg = 0xFF04, 284270346Sjfv i40e_aqc_opc_debug_modify_reg = 0xFF07, 285270346Sjfv i40e_aqc_opc_debug_dump_internals = 0xFF08, 286270346Sjfv i40e_aqc_opc_debug_modify_internals = 0xFF09, 287266423Sjfv}; 288266423Sjfv 289266423Sjfv/* command structures and indirect data structures */ 290266423Sjfv 291266423Sjfv/* Structure naming conventions: 292266423Sjfv * - no suffix for direct command descriptor structures 293266423Sjfv * - _data for indirect sent data 294266423Sjfv * - _resp for indirect return data (data which is both will use _data) 295266423Sjfv * - _completion for direct return data 296266423Sjfv * - _element_ for repeated elements (may also be _data or _resp) 297266423Sjfv * 298266423Sjfv * Command structures are expected to overlay the params.raw member of the basic 299266423Sjfv * descriptor, and as such cannot exceed 16 bytes in length. 300266423Sjfv */ 301266423Sjfv 302266423Sjfv/* This macro is used to generate a compilation error if a structure 303266423Sjfv * is not exactly the correct length. It gives a divide by zero error if the 304266423Sjfv * structure is not of the correct size, otherwise it creates an enum that is 305266423Sjfv * never used. 306266423Sjfv */ 307266423Sjfv#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 308266423Sjfv { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 309266423Sjfv 310266423Sjfv/* This macro is used extensively to ensure that command structures are 16 311266423Sjfv * bytes in length as they have to map to the raw array of that size. 312266423Sjfv */ 313270346Sjfv#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 314266423Sjfv 315266423Sjfv/* internal (0x00XX) commands */ 316266423Sjfv 317266423Sjfv/* Get version (direct 0x0001) */ 318266423Sjfvstruct i40e_aqc_get_version { 319266423Sjfv __le32 rom_ver; 320266423Sjfv __le32 fw_build; 321266423Sjfv __le16 fw_major; 322266423Sjfv __le16 fw_minor; 323266423Sjfv __le16 api_major; 324266423Sjfv __le16 api_minor; 325266423Sjfv}; 326266423Sjfv 327266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 328266423Sjfv 329266423Sjfv/* Send driver version (indirect 0x0002) */ 330266423Sjfvstruct i40e_aqc_driver_version { 331270346Sjfv u8 driver_major_ver; 332270346Sjfv u8 driver_minor_ver; 333270346Sjfv u8 driver_build_ver; 334270346Sjfv u8 driver_subbuild_ver; 335270346Sjfv u8 reserved[4]; 336270346Sjfv __le32 address_high; 337270346Sjfv __le32 address_low; 338266423Sjfv}; 339266423Sjfv 340266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 341266423Sjfv 342266423Sjfv/* Queue Shutdown (direct 0x0003) */ 343266423Sjfvstruct i40e_aqc_queue_shutdown { 344270346Sjfv __le32 driver_unloading; 345270346Sjfv#define I40E_AQ_DRIVER_UNLOADING 0x1 346270346Sjfv u8 reserved[12]; 347266423Sjfv}; 348266423Sjfv 349266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 350266423Sjfv 351266423Sjfv/* Set PF context (0x0004, direct) */ 352266423Sjfvstruct i40e_aqc_set_pf_context { 353266423Sjfv u8 pf_id; 354266423Sjfv u8 reserved[15]; 355266423Sjfv}; 356266423Sjfv 357266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 358266423Sjfv 359266423Sjfv/* Request resource ownership (direct 0x0008) 360266423Sjfv * Release resource ownership (direct 0x0009) 361266423Sjfv */ 362270346Sjfv#define I40E_AQ_RESOURCE_NVM 1 363270346Sjfv#define I40E_AQ_RESOURCE_SDP 2 364270346Sjfv#define I40E_AQ_RESOURCE_ACCESS_READ 1 365270346Sjfv#define I40E_AQ_RESOURCE_ACCESS_WRITE 2 366270346Sjfv#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 367270346Sjfv#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 368266423Sjfv 369266423Sjfvstruct i40e_aqc_request_resource { 370270346Sjfv __le16 resource_id; 371270346Sjfv __le16 access_type; 372270346Sjfv __le32 timeout; 373270346Sjfv __le32 resource_number; 374270346Sjfv u8 reserved[4]; 375266423Sjfv}; 376266423Sjfv 377266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 378266423Sjfv 379266423Sjfv/* Get function capabilities (indirect 0x000A) 380266423Sjfv * Get device capabilities (indirect 0x000B) 381266423Sjfv */ 382266423Sjfvstruct i40e_aqc_list_capabilites { 383266423Sjfv u8 command_flags; 384270346Sjfv#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 385266423Sjfv u8 pf_index; 386266423Sjfv u8 reserved[2]; 387266423Sjfv __le32 count; 388266423Sjfv __le32 addr_high; 389266423Sjfv __le32 addr_low; 390266423Sjfv}; 391266423Sjfv 392266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 393266423Sjfv 394266423Sjfvstruct i40e_aqc_list_capabilities_element_resp { 395270346Sjfv __le16 id; 396270346Sjfv u8 major_rev; 397270346Sjfv u8 minor_rev; 398270346Sjfv __le32 number; 399270346Sjfv __le32 logical_id; 400270346Sjfv __le32 phys_id; 401270346Sjfv u8 reserved[16]; 402266423Sjfv}; 403266423Sjfv 404266423Sjfv/* list of caps */ 405266423Sjfv 406270346Sjfv#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 407270346Sjfv#define I40E_AQ_CAP_ID_MNG_MODE 0x0002 408270346Sjfv#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 409270346Sjfv#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 410270346Sjfv#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 411270346Sjfv#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 412270346Sjfv#define I40E_AQ_CAP_ID_SRIOV 0x0012 413270346Sjfv#define I40E_AQ_CAP_ID_VF 0x0013 414270346Sjfv#define I40E_AQ_CAP_ID_VMDQ 0x0014 415270346Sjfv#define I40E_AQ_CAP_ID_8021QBG 0x0015 416270346Sjfv#define I40E_AQ_CAP_ID_8021QBR 0x0016 417270346Sjfv#define I40E_AQ_CAP_ID_VSI 0x0017 418270346Sjfv#define I40E_AQ_CAP_ID_DCB 0x0018 419270346Sjfv#define I40E_AQ_CAP_ID_FCOE 0x0021 420270346Sjfv#define I40E_AQ_CAP_ID_RSS 0x0040 421270346Sjfv#define I40E_AQ_CAP_ID_RXQ 0x0041 422270346Sjfv#define I40E_AQ_CAP_ID_TXQ 0x0042 423270346Sjfv#define I40E_AQ_CAP_ID_MSIX 0x0043 424270346Sjfv#define I40E_AQ_CAP_ID_VF_MSIX 0x0044 425270346Sjfv#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 426270346Sjfv#define I40E_AQ_CAP_ID_1588 0x0046 427270346Sjfv#define I40E_AQ_CAP_ID_IWARP 0x0051 428270346Sjfv#define I40E_AQ_CAP_ID_LED 0x0061 429270346Sjfv#define I40E_AQ_CAP_ID_SDP 0x0062 430270346Sjfv#define I40E_AQ_CAP_ID_MDIO 0x0063 431270346Sjfv#define I40E_AQ_CAP_ID_FLEX10 0x00F1 432270346Sjfv#define I40E_AQ_CAP_ID_CEM 0x00F2 433266423Sjfv 434266423Sjfv/* Set CPPM Configuration (direct 0x0103) */ 435266423Sjfvstruct i40e_aqc_cppm_configuration { 436270346Sjfv __le16 command_flags; 437270346Sjfv#define I40E_AQ_CPPM_EN_LTRC 0x0800 438270346Sjfv#define I40E_AQ_CPPM_EN_DMCTH 0x1000 439270346Sjfv#define I40E_AQ_CPPM_EN_DMCTLX 0x2000 440270346Sjfv#define I40E_AQ_CPPM_EN_HPTC 0x4000 441270346Sjfv#define I40E_AQ_CPPM_EN_DMARC 0x8000 442270346Sjfv __le16 ttlx; 443270346Sjfv __le32 dmacr; 444270346Sjfv __le16 dmcth; 445270346Sjfv u8 hptc; 446270346Sjfv u8 reserved; 447270346Sjfv __le32 pfltrc; 448266423Sjfv}; 449266423Sjfv 450266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 451266423Sjfv 452266423Sjfv/* Set ARP Proxy command / response (indirect 0x0104) */ 453266423Sjfvstruct i40e_aqc_arp_proxy_data { 454270346Sjfv __le16 command_flags; 455270346Sjfv#define I40E_AQ_ARP_INIT_IPV4 0x0008 456270346Sjfv#define I40E_AQ_ARP_UNSUP_CTL 0x0010 457270346Sjfv#define I40E_AQ_ARP_ENA 0x0020 458270346Sjfv#define I40E_AQ_ARP_ADD_IPV4 0x0040 459270346Sjfv#define I40E_AQ_ARP_DEL_IPV4 0x0080 460270346Sjfv __le16 table_id; 461270346Sjfv __le32 pfpm_proxyfc; 462270346Sjfv __le32 ip_addr; 463270346Sjfv u8 mac_addr[6]; 464266423Sjfv}; 465266423Sjfv 466266423Sjfv/* Set NS Proxy Table Entry Command (indirect 0x0105) */ 467266423Sjfvstruct i40e_aqc_ns_proxy_data { 468270346Sjfv __le16 table_idx_mac_addr_0; 469270346Sjfv __le16 table_idx_mac_addr_1; 470270346Sjfv __le16 table_idx_ipv6_0; 471270346Sjfv __le16 table_idx_ipv6_1; 472270346Sjfv __le16 control; 473270346Sjfv#define I40E_AQ_NS_PROXY_ADD_0 0x0100 474270346Sjfv#define I40E_AQ_NS_PROXY_DEL_0 0x0200 475270346Sjfv#define I40E_AQ_NS_PROXY_ADD_1 0x0400 476270346Sjfv#define I40E_AQ_NS_PROXY_DEL_1 0x0800 477270346Sjfv#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 478270346Sjfv#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 479270346Sjfv#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 480270346Sjfv#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 481270346Sjfv#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 482270346Sjfv#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 483270346Sjfv#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 484270346Sjfv u8 mac_addr_0[6]; 485270346Sjfv u8 mac_addr_1[6]; 486270346Sjfv u8 local_mac_addr[6]; 487270346Sjfv u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 488270346Sjfv u8 ipv6_addr_1[16]; 489266423Sjfv}; 490266423Sjfv 491266423Sjfv/* Manage LAA Command (0x0106) - obsolete */ 492266423Sjfvstruct i40e_aqc_mng_laa { 493266423Sjfv __le16 command_flags; 494270346Sjfv#define I40E_AQ_LAA_FLAG_WR 0x8000 495270346Sjfv u8 reserved[2]; 496270346Sjfv __le32 sal; 497270346Sjfv __le16 sah; 498270346Sjfv u8 reserved2[6]; 499266423Sjfv}; 500266423Sjfv 501266423Sjfv/* Manage MAC Address Read Command (indirect 0x0107) */ 502266423Sjfvstruct i40e_aqc_mac_address_read { 503266423Sjfv __le16 command_flags; 504270346Sjfv#define I40E_AQC_LAN_ADDR_VALID 0x10 505270346Sjfv#define I40E_AQC_SAN_ADDR_VALID 0x20 506270346Sjfv#define I40E_AQC_PORT_ADDR_VALID 0x40 507270346Sjfv#define I40E_AQC_WOL_ADDR_VALID 0x80 508270346Sjfv#define I40E_AQC_ADDR_VALID_MASK 0xf0 509270346Sjfv u8 reserved[6]; 510270346Sjfv __le32 addr_high; 511270346Sjfv __le32 addr_low; 512266423Sjfv}; 513266423Sjfv 514266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 515266423Sjfv 516266423Sjfvstruct i40e_aqc_mac_address_read_data { 517266423Sjfv u8 pf_lan_mac[6]; 518266423Sjfv u8 pf_san_mac[6]; 519266423Sjfv u8 port_mac[6]; 520266423Sjfv u8 pf_wol_mac[6]; 521266423Sjfv}; 522266423Sjfv 523266423SjfvI40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 524266423Sjfv 525266423Sjfv/* Manage MAC Address Write Command (0x0108) */ 526266423Sjfvstruct i40e_aqc_mac_address_write { 527270346Sjfv __le16 command_flags; 528270346Sjfv#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 529270346Sjfv#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 530270346Sjfv#define I40E_AQC_WRITE_TYPE_PORT 0x8000 531270346Sjfv#define I40E_AQC_WRITE_TYPE_MASK 0xc000 532270346Sjfv __le16 mac_sah; 533270346Sjfv __le32 mac_sal; 534270346Sjfv u8 reserved[8]; 535266423Sjfv}; 536266423Sjfv 537266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 538266423Sjfv 539266423Sjfv/* PXE commands (0x011x) */ 540266423Sjfv 541266423Sjfv/* Clear PXE Command and response (direct 0x0110) */ 542266423Sjfvstruct i40e_aqc_clear_pxe { 543266423Sjfv u8 rx_cnt; 544266423Sjfv u8 reserved[15]; 545266423Sjfv}; 546266423Sjfv 547266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 548266423Sjfv 549266423Sjfv/* Switch configuration commands (0x02xx) */ 550266423Sjfv 551266423Sjfv/* Used by many indirect commands that only pass an seid and a buffer in the 552266423Sjfv * command 553266423Sjfv */ 554266423Sjfvstruct i40e_aqc_switch_seid { 555270346Sjfv __le16 seid; 556270346Sjfv u8 reserved[6]; 557270346Sjfv __le32 addr_high; 558270346Sjfv __le32 addr_low; 559266423Sjfv}; 560266423Sjfv 561266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 562266423Sjfv 563266423Sjfv/* Get Switch Configuration command (indirect 0x0200) 564266423Sjfv * uses i40e_aqc_switch_seid for the descriptor 565266423Sjfv */ 566266423Sjfvstruct i40e_aqc_get_switch_config_header_resp { 567270346Sjfv __le16 num_reported; 568270346Sjfv __le16 num_total; 569270346Sjfv u8 reserved[12]; 570266423Sjfv}; 571266423Sjfv 572266423Sjfvstruct i40e_aqc_switch_config_element_resp { 573270346Sjfv u8 element_type; 574270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_MAC 1 575270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_PF 2 576270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_VF 3 577270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_EMP 4 578270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_BMC 5 579270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_PV 16 580270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_VEB 17 581270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_PA 18 582270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_VSI 19 583270346Sjfv u8 revision; 584270346Sjfv#define I40E_AQ_SW_ELEM_REV_1 1 585270346Sjfv __le16 seid; 586270346Sjfv __le16 uplink_seid; 587270346Sjfv __le16 downlink_seid; 588270346Sjfv u8 reserved[3]; 589270346Sjfv u8 connection_type; 590270346Sjfv#define I40E_AQ_CONN_TYPE_REGULAR 0x1 591270346Sjfv#define I40E_AQ_CONN_TYPE_DEFAULT 0x2 592270346Sjfv#define I40E_AQ_CONN_TYPE_CASCADED 0x3 593270346Sjfv __le16 scheduler_id; 594270346Sjfv __le16 element_info; 595266423Sjfv}; 596266423Sjfv 597266423Sjfv/* Get Switch Configuration (indirect 0x0200) 598266423Sjfv * an array of elements are returned in the response buffer 599266423Sjfv * the first in the array is the header, remainder are elements 600266423Sjfv */ 601266423Sjfvstruct i40e_aqc_get_switch_config_resp { 602270346Sjfv struct i40e_aqc_get_switch_config_header_resp header; 603270346Sjfv struct i40e_aqc_switch_config_element_resp element[1]; 604266423Sjfv}; 605266423Sjfv 606266423Sjfv/* Add Statistics (direct 0x0201) 607266423Sjfv * Remove Statistics (direct 0x0202) 608266423Sjfv */ 609266423Sjfvstruct i40e_aqc_add_remove_statistics { 610270346Sjfv __le16 seid; 611270346Sjfv __le16 vlan; 612270346Sjfv __le16 stat_index; 613270346Sjfv u8 reserved[10]; 614266423Sjfv}; 615266423Sjfv 616266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 617266423Sjfv 618266423Sjfv/* Set Port Parameters command (direct 0x0203) */ 619266423Sjfvstruct i40e_aqc_set_port_parameters { 620270346Sjfv __le16 command_flags; 621270346Sjfv#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 622270346Sjfv#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 623270346Sjfv#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 624270346Sjfv __le16 bad_frame_vsi; 625270346Sjfv __le16 default_seid; /* reserved for command */ 626270346Sjfv u8 reserved[10]; 627266423Sjfv}; 628266423Sjfv 629266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 630266423Sjfv 631266423Sjfv/* Get Switch Resource Allocation (indirect 0x0204) */ 632266423Sjfvstruct i40e_aqc_get_switch_resource_alloc { 633270346Sjfv u8 num_entries; /* reserved for command */ 634270346Sjfv u8 reserved[7]; 635270346Sjfv __le32 addr_high; 636270346Sjfv __le32 addr_low; 637266423Sjfv}; 638266423Sjfv 639266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 640266423Sjfv 641266423Sjfv/* expect an array of these structs in the response buffer */ 642266423Sjfvstruct i40e_aqc_switch_resource_alloc_element_resp { 643270346Sjfv u8 resource_type; 644270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VEB 0x0 645270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VSI 0x1 646270346Sjfv#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 647270346Sjfv#define I40E_AQ_RESOURCE_TYPE_STAG 0x3 648270346Sjfv#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 649270346Sjfv#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 650270346Sjfv#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 651270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 652270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 653270346Sjfv#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 654270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 655270346Sjfv#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 656270346Sjfv#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 657270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 658270346Sjfv#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 659270346Sjfv#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 660270346Sjfv#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 661270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 662270346Sjfv#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 663270346Sjfv u8 reserved1; 664270346Sjfv __le16 guaranteed; 665270346Sjfv __le16 total; 666270346Sjfv __le16 used; 667270346Sjfv __le16 total_unalloced; 668270346Sjfv u8 reserved2[6]; 669266423Sjfv}; 670266423Sjfv 671266423Sjfv/* Add VSI (indirect 0x0210) 672266423Sjfv * this indirect command uses struct i40e_aqc_vsi_properties_data 673266423Sjfv * as the indirect buffer (128 bytes) 674266423Sjfv * 675266423Sjfv * Update VSI (indirect 0x211) 676266423Sjfv * uses the same data structure as Add VSI 677266423Sjfv * 678266423Sjfv * Get VSI (indirect 0x0212) 679266423Sjfv * uses the same completion and data structure as Add VSI 680266423Sjfv */ 681266423Sjfvstruct i40e_aqc_add_get_update_vsi { 682270346Sjfv __le16 uplink_seid; 683270346Sjfv u8 connection_type; 684270346Sjfv#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 685270346Sjfv#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 686270346Sjfv#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 687270346Sjfv u8 reserved1; 688270346Sjfv u8 vf_id; 689270346Sjfv u8 reserved2; 690270346Sjfv __le16 vsi_flags; 691270346Sjfv#define I40E_AQ_VSI_TYPE_SHIFT 0x0 692270346Sjfv#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 693270346Sjfv#define I40E_AQ_VSI_TYPE_VF 0x0 694270346Sjfv#define I40E_AQ_VSI_TYPE_VMDQ2 0x1 695270346Sjfv#define I40E_AQ_VSI_TYPE_PF 0x2 696270346Sjfv#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 697270346Sjfv#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 698270346Sjfv __le32 addr_high; 699270346Sjfv __le32 addr_low; 700266423Sjfv}; 701266423Sjfv 702266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 703266423Sjfv 704266423Sjfvstruct i40e_aqc_add_get_update_vsi_completion { 705266423Sjfv __le16 seid; 706266423Sjfv __le16 vsi_number; 707266423Sjfv __le16 vsi_used; 708266423Sjfv __le16 vsi_free; 709266423Sjfv __le32 addr_high; 710266423Sjfv __le32 addr_low; 711266423Sjfv}; 712266423Sjfv 713266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 714266423Sjfv 715266423Sjfvstruct i40e_aqc_vsi_properties_data { 716266423Sjfv /* first 96 byte are written by SW */ 717270346Sjfv __le16 valid_sections; 718270346Sjfv#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 719270346Sjfv#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 720270346Sjfv#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 721270346Sjfv#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 722270346Sjfv#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 723270346Sjfv#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 724270346Sjfv#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 725270346Sjfv#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 726270346Sjfv#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 727270346Sjfv#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 728266423Sjfv /* switch section */ 729270346Sjfv __le16 switch_id; /* 12bit id combined with flags below */ 730270346Sjfv#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 731270346Sjfv#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 732270346Sjfv#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 733270346Sjfv#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 734270346Sjfv#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 735270346Sjfv u8 sw_reserved[2]; 736266423Sjfv /* security section */ 737270346Sjfv u8 sec_flags; 738270346Sjfv#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 739270346Sjfv#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 740270346Sjfv#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 741270346Sjfv u8 sec_reserved; 742266423Sjfv /* VLAN section */ 743270346Sjfv __le16 pvid; /* VLANS include priority bits */ 744270346Sjfv __le16 fcoe_pvid; 745270346Sjfv u8 port_vlan_flags; 746270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 747270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 748270346Sjfv I40E_AQ_VSI_PVLAN_MODE_SHIFT) 749270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 750270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 751270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 752270346Sjfv#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 753270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 754270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 755270346Sjfv I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 756270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 757270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 758270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 759270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 760270346Sjfv u8 pvlan_reserved[3]; 761266423Sjfv /* ingress egress up sections */ 762270346Sjfv __le32 ingress_table; /* bitmap, 3 bits per up */ 763270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 764270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 765270346Sjfv I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 766270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 767270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 768270346Sjfv I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 769270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 770270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 771270346Sjfv I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 772270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 773270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 774270346Sjfv I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 775270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 776270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 777270346Sjfv I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 778270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 779270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 780270346Sjfv I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 781270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 782270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 783270346Sjfv I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 784270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 785270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 786270346Sjfv I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 787270346Sjfv __le32 egress_table; /* same defines as for ingress table */ 788266423Sjfv /* cascaded PV section */ 789270346Sjfv __le16 cas_pv_tag; 790270346Sjfv u8 cas_pv_flags; 791270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 792270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 793270346Sjfv I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 794270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 795270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 796270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 797270346Sjfv#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 798270346Sjfv#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 799270346Sjfv#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 800270346Sjfv u8 cas_pv_reserved; 801266423Sjfv /* queue mapping section */ 802270346Sjfv __le16 mapping_flags; 803270346Sjfv#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 804270346Sjfv#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 805270346Sjfv __le16 queue_mapping[16]; 806270346Sjfv#define I40E_AQ_VSI_QUEUE_SHIFT 0x0 807270346Sjfv#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 808270346Sjfv __le16 tc_mapping[8]; 809270346Sjfv#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 810270346Sjfv#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 811270346Sjfv I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 812270346Sjfv#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 813270346Sjfv#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 814270346Sjfv I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 815266423Sjfv /* queueing option section */ 816270346Sjfv u8 queueing_opt_flags; 817270346Sjfv#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 818270346Sjfv#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 819270346Sjfv u8 queueing_opt_reserved[3]; 820266423Sjfv /* scheduler section */ 821270346Sjfv u8 up_enable_bits; 822270346Sjfv u8 sched_reserved; 823266423Sjfv /* outer up section */ 824270346Sjfv __le32 outer_up_table; /* same structure and defines as ingress table */ 825270346Sjfv u8 cmd_reserved[8]; 826266423Sjfv /* last 32 bytes are written by FW */ 827270346Sjfv __le16 qs_handle[8]; 828266423Sjfv#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 829270346Sjfv __le16 stat_counter_idx; 830270346Sjfv __le16 sched_id; 831270346Sjfv u8 resp_reserved[12]; 832266423Sjfv}; 833266423Sjfv 834266423SjfvI40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 835266423Sjfv 836266423Sjfv/* Add Port Virtualizer (direct 0x0220) 837266423Sjfv * also used for update PV (direct 0x0221) but only flags are used 838266423Sjfv * (IS_CTRL_PORT only works on add PV) 839266423Sjfv */ 840266423Sjfvstruct i40e_aqc_add_update_pv { 841270346Sjfv __le16 command_flags; 842270346Sjfv#define I40E_AQC_PV_FLAG_PV_TYPE 0x1 843270346Sjfv#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 844270346Sjfv#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 845270346Sjfv#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 846270346Sjfv __le16 uplink_seid; 847270346Sjfv __le16 connected_seid; 848270346Sjfv u8 reserved[10]; 849266423Sjfv}; 850266423Sjfv 851266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 852266423Sjfv 853266423Sjfvstruct i40e_aqc_add_update_pv_completion { 854266423Sjfv /* reserved for update; for add also encodes error if rc == ENOSPC */ 855270346Sjfv __le16 pv_seid; 856270346Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 857270346Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 858270346Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 859270346Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 860270346Sjfv u8 reserved[14]; 861266423Sjfv}; 862266423Sjfv 863266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 864266423Sjfv 865266423Sjfv/* Get PV Params (direct 0x0222) 866266423Sjfv * uses i40e_aqc_switch_seid for the descriptor 867266423Sjfv */ 868266423Sjfv 869266423Sjfvstruct i40e_aqc_get_pv_params_completion { 870270346Sjfv __le16 seid; 871270346Sjfv __le16 default_stag; 872270346Sjfv __le16 pv_flags; /* same flags as add_pv */ 873270346Sjfv#define I40E_AQC_GET_PV_PV_TYPE 0x1 874270346Sjfv#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 875270346Sjfv#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 876270346Sjfv u8 reserved[8]; 877270346Sjfv __le16 default_port_seid; 878266423Sjfv}; 879266423Sjfv 880266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 881266423Sjfv 882266423Sjfv/* Add VEB (direct 0x0230) */ 883266423Sjfvstruct i40e_aqc_add_veb { 884270346Sjfv __le16 uplink_seid; 885270346Sjfv __le16 downlink_seid; 886270346Sjfv __le16 veb_flags; 887270346Sjfv#define I40E_AQC_ADD_VEB_FLOATING 0x1 888270346Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 889270346Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 890266423Sjfv I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 891270346Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 892270346Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 893270346Sjfv#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 894270346Sjfv u8 enable_tcs; 895270346Sjfv u8 reserved[9]; 896266423Sjfv}; 897266423Sjfv 898266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 899266423Sjfv 900266423Sjfvstruct i40e_aqc_add_veb_completion { 901270346Sjfv u8 reserved[6]; 902270346Sjfv __le16 switch_seid; 903266423Sjfv /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 904270346Sjfv __le16 veb_seid; 905270346Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 906270346Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 907270346Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 908270346Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 909270346Sjfv __le16 statistic_index; 910270346Sjfv __le16 vebs_used; 911270346Sjfv __le16 vebs_free; 912266423Sjfv}; 913266423Sjfv 914266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 915266423Sjfv 916266423Sjfv/* Get VEB Parameters (direct 0x0232) 917266423Sjfv * uses i40e_aqc_switch_seid for the descriptor 918266423Sjfv */ 919266423Sjfvstruct i40e_aqc_get_veb_parameters_completion { 920270346Sjfv __le16 seid; 921270346Sjfv __le16 switch_id; 922270346Sjfv __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 923270346Sjfv __le16 statistic_index; 924270346Sjfv __le16 vebs_used; 925270346Sjfv __le16 vebs_free; 926270346Sjfv u8 reserved[4]; 927266423Sjfv}; 928266423Sjfv 929266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 930266423Sjfv 931266423Sjfv/* Delete Element (direct 0x0243) 932266423Sjfv * uses the generic i40e_aqc_switch_seid 933266423Sjfv */ 934266423Sjfv 935266423Sjfv/* Add MAC-VLAN (indirect 0x0250) */ 936266423Sjfv 937266423Sjfv/* used for the command for most vlan commands */ 938266423Sjfvstruct i40e_aqc_macvlan { 939270346Sjfv __le16 num_addresses; 940270346Sjfv __le16 seid[3]; 941270346Sjfv#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 942270346Sjfv#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 943266423Sjfv I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 944270346Sjfv#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 945270346Sjfv __le32 addr_high; 946270346Sjfv __le32 addr_low; 947266423Sjfv}; 948266423Sjfv 949266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 950266423Sjfv 951266423Sjfv/* indirect data for command and response */ 952266423Sjfvstruct i40e_aqc_add_macvlan_element_data { 953270346Sjfv u8 mac_addr[6]; 954270346Sjfv __le16 vlan_tag; 955270346Sjfv __le16 flags; 956270346Sjfv#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 957270346Sjfv#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 958270346Sjfv#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 959270346Sjfv#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 960270346Sjfv __le16 queue_number; 961270346Sjfv#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 962270346Sjfv#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 963266423Sjfv I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 964266423Sjfv /* response section */ 965270346Sjfv u8 match_method; 966270346Sjfv#define I40E_AQC_MM_PERFECT_MATCH 0x01 967270346Sjfv#define I40E_AQC_MM_HASH_MATCH 0x02 968270346Sjfv#define I40E_AQC_MM_ERR_NO_RES 0xFF 969270346Sjfv u8 reserved1[3]; 970266423Sjfv}; 971266423Sjfv 972266423Sjfvstruct i40e_aqc_add_remove_macvlan_completion { 973266423Sjfv __le16 perfect_mac_used; 974266423Sjfv __le16 perfect_mac_free; 975266423Sjfv __le16 unicast_hash_free; 976266423Sjfv __le16 multicast_hash_free; 977266423Sjfv __le32 addr_high; 978266423Sjfv __le32 addr_low; 979266423Sjfv}; 980266423Sjfv 981266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 982266423Sjfv 983266423Sjfv/* Remove MAC-VLAN (indirect 0x0251) 984266423Sjfv * uses i40e_aqc_macvlan for the descriptor 985266423Sjfv * data points to an array of num_addresses of elements 986266423Sjfv */ 987266423Sjfv 988266423Sjfvstruct i40e_aqc_remove_macvlan_element_data { 989270346Sjfv u8 mac_addr[6]; 990270346Sjfv __le16 vlan_tag; 991270346Sjfv u8 flags; 992270346Sjfv#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 993270346Sjfv#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 994270346Sjfv#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 995270346Sjfv#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 996270346Sjfv u8 reserved[3]; 997266423Sjfv /* reply section */ 998270346Sjfv u8 error_code; 999270346Sjfv#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1000270346Sjfv#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1001270346Sjfv u8 reply_reserved[3]; 1002266423Sjfv}; 1003266423Sjfv 1004266423Sjfv/* Add VLAN (indirect 0x0252) 1005266423Sjfv * Remove VLAN (indirect 0x0253) 1006266423Sjfv * use the generic i40e_aqc_macvlan for the command 1007266423Sjfv */ 1008266423Sjfvstruct i40e_aqc_add_remove_vlan_element_data { 1009270346Sjfv __le16 vlan_tag; 1010270346Sjfv u8 vlan_flags; 1011266423Sjfv/* flags for add VLAN */ 1012270346Sjfv#define I40E_AQC_ADD_VLAN_LOCAL 0x1 1013270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1014270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1015270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1016270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1017270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1018270346Sjfv#define I40E_AQC_VLAN_PTYPE_SHIFT 3 1019270346Sjfv#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1020270346Sjfv#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1021270346Sjfv#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1022270346Sjfv#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1023270346Sjfv#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1024266423Sjfv/* flags for remove VLAN */ 1025270346Sjfv#define I40E_AQC_REMOVE_VLAN_ALL 0x1 1026270346Sjfv u8 reserved; 1027270346Sjfv u8 result; 1028266423Sjfv/* flags for add VLAN */ 1029270346Sjfv#define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1030270346Sjfv#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1031270346Sjfv#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1032266423Sjfv/* flags for remove VLAN */ 1033270346Sjfv#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1034270346Sjfv#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1035270346Sjfv u8 reserved1[3]; 1036266423Sjfv}; 1037266423Sjfv 1038266423Sjfvstruct i40e_aqc_add_remove_vlan_completion { 1039270346Sjfv u8 reserved[4]; 1040270346Sjfv __le16 vlans_used; 1041270346Sjfv __le16 vlans_free; 1042270346Sjfv __le32 addr_high; 1043270346Sjfv __le32 addr_low; 1044266423Sjfv}; 1045266423Sjfv 1046266423Sjfv/* Set VSI Promiscuous Modes (direct 0x0254) */ 1047266423Sjfvstruct i40e_aqc_set_vsi_promiscuous_modes { 1048270346Sjfv __le16 promiscuous_flags; 1049270346Sjfv __le16 valid_flags; 1050266423Sjfv/* flags used for both fields above */ 1051270346Sjfv#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1052270346Sjfv#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1053270346Sjfv#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1054270346Sjfv#define I40E_AQC_SET_VSI_DEFAULT 0x08 1055270346Sjfv#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1056270346Sjfv __le16 seid; 1057270346Sjfv#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1058270346Sjfv __le16 vlan_tag; 1059270346Sjfv#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1060270346Sjfv u8 reserved[8]; 1061266423Sjfv}; 1062266423Sjfv 1063266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1064266423Sjfv 1065266423Sjfv/* Add S/E-tag command (direct 0x0255) 1066266423Sjfv * Uses generic i40e_aqc_add_remove_tag_completion for completion 1067266423Sjfv */ 1068266423Sjfvstruct i40e_aqc_add_tag { 1069270346Sjfv __le16 flags; 1070270346Sjfv#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1071270346Sjfv __le16 seid; 1072270346Sjfv#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1073270346Sjfv#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1074266423Sjfv I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1075270346Sjfv __le16 tag; 1076270346Sjfv __le16 queue_number; 1077270346Sjfv u8 reserved[8]; 1078266423Sjfv}; 1079266423Sjfv 1080266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1081266423Sjfv 1082266423Sjfvstruct i40e_aqc_add_remove_tag_completion { 1083270346Sjfv u8 reserved[12]; 1084270346Sjfv __le16 tags_used; 1085270346Sjfv __le16 tags_free; 1086266423Sjfv}; 1087266423Sjfv 1088266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1089266423Sjfv 1090266423Sjfv/* Remove S/E-tag command (direct 0x0256) 1091266423Sjfv * Uses generic i40e_aqc_add_remove_tag_completion for completion 1092266423Sjfv */ 1093266423Sjfvstruct i40e_aqc_remove_tag { 1094270346Sjfv __le16 seid; 1095270346Sjfv#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1096270346Sjfv#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1097266423Sjfv I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1098270346Sjfv __le16 tag; 1099270346Sjfv u8 reserved[12]; 1100266423Sjfv}; 1101266423Sjfv 1102266423Sjfv/* Add multicast E-Tag (direct 0x0257) 1103266423Sjfv * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1104266423Sjfv * and no external data 1105266423Sjfv */ 1106266423Sjfvstruct i40e_aqc_add_remove_mcast_etag { 1107270346Sjfv __le16 pv_seid; 1108270346Sjfv __le16 etag; 1109270346Sjfv u8 num_unicast_etags; 1110270346Sjfv u8 reserved[3]; 1111270346Sjfv __le32 addr_high; /* address of array of 2-byte s-tags */ 1112270346Sjfv __le32 addr_low; 1113266423Sjfv}; 1114266423Sjfv 1115266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1116266423Sjfv 1117266423Sjfvstruct i40e_aqc_add_remove_mcast_etag_completion { 1118270346Sjfv u8 reserved[4]; 1119270346Sjfv __le16 mcast_etags_used; 1120270346Sjfv __le16 mcast_etags_free; 1121270346Sjfv __le32 addr_high; 1122270346Sjfv __le32 addr_low; 1123266423Sjfv 1124266423Sjfv}; 1125266423Sjfv 1126266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1127266423Sjfv 1128266423Sjfv/* Update S/E-Tag (direct 0x0259) */ 1129266423Sjfvstruct i40e_aqc_update_tag { 1130270346Sjfv __le16 seid; 1131270346Sjfv#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1132270346Sjfv#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1133266423Sjfv I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1134270346Sjfv __le16 old_tag; 1135270346Sjfv __le16 new_tag; 1136270346Sjfv u8 reserved[10]; 1137266423Sjfv}; 1138266423Sjfv 1139266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1140266423Sjfv 1141266423Sjfvstruct i40e_aqc_update_tag_completion { 1142270346Sjfv u8 reserved[12]; 1143270346Sjfv __le16 tags_used; 1144270346Sjfv __le16 tags_free; 1145266423Sjfv}; 1146266423Sjfv 1147266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1148266423Sjfv 1149266423Sjfv/* Add Control Packet filter (direct 0x025A) 1150266423Sjfv * Remove Control Packet filter (direct 0x025B) 1151266423Sjfv * uses the i40e_aqc_add_oveb_cloud, 1152266423Sjfv * and the generic direct completion structure 1153266423Sjfv */ 1154266423Sjfvstruct i40e_aqc_add_remove_control_packet_filter { 1155270346Sjfv u8 mac[6]; 1156270346Sjfv __le16 etype; 1157270346Sjfv __le16 flags; 1158270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1159270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1160270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1161270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1162270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1163270346Sjfv __le16 seid; 1164270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1165270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1166266423Sjfv I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1167270346Sjfv __le16 queue; 1168270346Sjfv u8 reserved[2]; 1169266423Sjfv}; 1170266423Sjfv 1171266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1172266423Sjfv 1173266423Sjfvstruct i40e_aqc_add_remove_control_packet_filter_completion { 1174270346Sjfv __le16 mac_etype_used; 1175270346Sjfv __le16 etype_used; 1176270346Sjfv __le16 mac_etype_free; 1177270346Sjfv __le16 etype_free; 1178270346Sjfv u8 reserved[8]; 1179266423Sjfv}; 1180266423Sjfv 1181266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1182266423Sjfv 1183266423Sjfv/* Add Cloud filters (indirect 0x025C) 1184266423Sjfv * Remove Cloud filters (indirect 0x025D) 1185266423Sjfv * uses the i40e_aqc_add_remove_cloud_filters, 1186266423Sjfv * and the generic indirect completion structure 1187266423Sjfv */ 1188266423Sjfvstruct i40e_aqc_add_remove_cloud_filters { 1189270346Sjfv u8 num_filters; 1190270346Sjfv u8 reserved; 1191270346Sjfv __le16 seid; 1192270346Sjfv#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1193270346Sjfv#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1194266423Sjfv I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1195270346Sjfv u8 reserved2[4]; 1196270346Sjfv __le32 addr_high; 1197270346Sjfv __le32 addr_low; 1198266423Sjfv}; 1199266423Sjfv 1200266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1201266423Sjfv 1202266423Sjfvstruct i40e_aqc_add_remove_cloud_filters_element_data { 1203270346Sjfv u8 outer_mac[6]; 1204270346Sjfv u8 inner_mac[6]; 1205270346Sjfv __le16 inner_vlan; 1206266423Sjfv union { 1207266423Sjfv struct { 1208266423Sjfv u8 reserved[12]; 1209266423Sjfv u8 data[4]; 1210266423Sjfv } v4; 1211266423Sjfv struct { 1212266423Sjfv u8 data[16]; 1213266423Sjfv } v6; 1214266423Sjfv } ipaddr; 1215270346Sjfv __le16 flags; 1216270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1217270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1218266423Sjfv I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1219266423Sjfv/* 0x0000 reserved */ 1220270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1221266423Sjfv/* 0x0002 reserved */ 1222270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1223270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1224266423Sjfv/* 0x0005 reserved */ 1225270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1226266423Sjfv/* 0x0007 reserved */ 1227266423Sjfv/* 0x0008 reserved */ 1228270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1229270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1230270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1231270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1232266423Sjfv 1233270346Sjfv#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1234270346Sjfv#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1235270346Sjfv#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1236270346Sjfv#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1237270346Sjfv#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1238266423Sjfv 1239270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1240270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1241270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0 1242270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1243270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2 1244270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1245266423Sjfv 1246270346Sjfv __le32 tenant_id; 1247270346Sjfv u8 reserved[4]; 1248270346Sjfv __le16 queue_number; 1249270346Sjfv#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1250270346Sjfv#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x3F << \ 1251270346Sjfv I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1252270346Sjfv u8 reserved2[14]; 1253266423Sjfv /* response section */ 1254270346Sjfv u8 allocation_result; 1255270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1256270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1257270346Sjfv u8 response_reserved[7]; 1258266423Sjfv}; 1259266423Sjfv 1260266423Sjfvstruct i40e_aqc_remove_cloud_filters_completion { 1261266423Sjfv __le16 perfect_ovlan_used; 1262266423Sjfv __le16 perfect_ovlan_free; 1263266423Sjfv __le16 vlan_used; 1264266423Sjfv __le16 vlan_free; 1265266423Sjfv __le32 addr_high; 1266266423Sjfv __le32 addr_low; 1267266423Sjfv}; 1268266423Sjfv 1269266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1270266423Sjfv 1271266423Sjfv/* Add Mirror Rule (indirect or direct 0x0260) 1272266423Sjfv * Delete Mirror Rule (indirect or direct 0x0261) 1273266423Sjfv * note: some rule types (4,5) do not use an external buffer. 1274266423Sjfv * take care to set the flags correctly. 1275266423Sjfv */ 1276266423Sjfvstruct i40e_aqc_add_delete_mirror_rule { 1277266423Sjfv __le16 seid; 1278266423Sjfv __le16 rule_type; 1279270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1280270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1281266423Sjfv I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1282270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1283270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1284270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1285270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1286270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1287266423Sjfv __le16 num_entries; 1288266423Sjfv __le16 destination; /* VSI for add, rule id for delete */ 1289266423Sjfv __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1290266423Sjfv __le32 addr_low; 1291266423Sjfv}; 1292266423Sjfv 1293266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1294266423Sjfv 1295266423Sjfvstruct i40e_aqc_add_delete_mirror_rule_completion { 1296270346Sjfv u8 reserved[2]; 1297270346Sjfv __le16 rule_id; /* only used on add */ 1298270346Sjfv __le16 mirror_rules_used; 1299270346Sjfv __le16 mirror_rules_free; 1300270346Sjfv __le32 addr_high; 1301270346Sjfv __le32 addr_low; 1302266423Sjfv}; 1303266423Sjfv 1304266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1305266423Sjfv 1306266423Sjfv/* DCB 0x03xx*/ 1307266423Sjfv 1308266423Sjfv/* PFC Ignore (direct 0x0301) 1309266423Sjfv * the command and response use the same descriptor structure 1310266423Sjfv */ 1311266423Sjfvstruct i40e_aqc_pfc_ignore { 1312270346Sjfv u8 tc_bitmap; 1313270346Sjfv u8 command_flags; /* unused on response */ 1314270346Sjfv#define I40E_AQC_PFC_IGNORE_SET 0x80 1315270346Sjfv#define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1316270346Sjfv u8 reserved[14]; 1317266423Sjfv}; 1318266423Sjfv 1319266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1320266423Sjfv 1321266423Sjfv/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1322266423Sjfv * with no parameters 1323266423Sjfv */ 1324266423Sjfv 1325266423Sjfv/* TX scheduler 0x04xx */ 1326266423Sjfv 1327266423Sjfv/* Almost all the indirect commands use 1328266423Sjfv * this generic struct to pass the SEID in param0 1329266423Sjfv */ 1330266423Sjfvstruct i40e_aqc_tx_sched_ind { 1331270346Sjfv __le16 vsi_seid; 1332270346Sjfv u8 reserved[6]; 1333270346Sjfv __le32 addr_high; 1334270346Sjfv __le32 addr_low; 1335266423Sjfv}; 1336266423Sjfv 1337266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1338266423Sjfv 1339266423Sjfv/* Several commands respond with a set of queue set handles */ 1340266423Sjfvstruct i40e_aqc_qs_handles_resp { 1341266423Sjfv __le16 qs_handles[8]; 1342266423Sjfv}; 1343266423Sjfv 1344266423Sjfv/* Configure VSI BW limits (direct 0x0400) */ 1345266423Sjfvstruct i40e_aqc_configure_vsi_bw_limit { 1346270346Sjfv __le16 vsi_seid; 1347270346Sjfv u8 reserved[2]; 1348270346Sjfv __le16 credit; 1349270346Sjfv u8 reserved1[2]; 1350270346Sjfv u8 max_credit; /* 0-3, limit = 2^max */ 1351270346Sjfv u8 reserved2[7]; 1352266423Sjfv}; 1353266423Sjfv 1354266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1355266423Sjfv 1356266423Sjfv/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1357266423Sjfv * responds with i40e_aqc_qs_handles_resp 1358266423Sjfv */ 1359266423Sjfvstruct i40e_aqc_configure_vsi_ets_sla_bw_data { 1360270346Sjfv u8 tc_valid_bits; 1361270346Sjfv u8 reserved[15]; 1362270346Sjfv __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1363266423Sjfv 1364266423Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1365270346Sjfv __le16 tc_bw_max[2]; 1366270346Sjfv u8 reserved1[28]; 1367266423Sjfv}; 1368266423Sjfv 1369266423Sjfv/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1370266423Sjfv * responds with i40e_aqc_qs_handles_resp 1371266423Sjfv */ 1372266423Sjfvstruct i40e_aqc_configure_vsi_tc_bw_data { 1373270346Sjfv u8 tc_valid_bits; 1374270346Sjfv u8 reserved[3]; 1375270346Sjfv u8 tc_bw_credits[8]; 1376270346Sjfv u8 reserved1[4]; 1377270346Sjfv __le16 qs_handles[8]; 1378266423Sjfv}; 1379266423Sjfv 1380266423Sjfv/* Query vsi bw configuration (indirect 0x0408) */ 1381266423Sjfvstruct i40e_aqc_query_vsi_bw_config_resp { 1382270346Sjfv u8 tc_valid_bits; 1383270346Sjfv u8 tc_suspended_bits; 1384270346Sjfv u8 reserved[14]; 1385270346Sjfv __le16 qs_handles[8]; 1386270346Sjfv u8 reserved1[4]; 1387270346Sjfv __le16 port_bw_limit; 1388270346Sjfv u8 reserved2[2]; 1389270346Sjfv u8 max_bw; /* 0-3, limit = 2^max */ 1390270346Sjfv u8 reserved3[23]; 1391266423Sjfv}; 1392266423Sjfv 1393266423Sjfv/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1394266423Sjfvstruct i40e_aqc_query_vsi_ets_sla_config_resp { 1395270346Sjfv u8 tc_valid_bits; 1396270346Sjfv u8 reserved[3]; 1397270346Sjfv u8 share_credits[8]; 1398270346Sjfv __le16 credits[8]; 1399266423Sjfv 1400266423Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1401270346Sjfv __le16 tc_bw_max[2]; 1402266423Sjfv}; 1403266423Sjfv 1404266423Sjfv/* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1405266423Sjfvstruct i40e_aqc_configure_switching_comp_bw_limit { 1406270346Sjfv __le16 seid; 1407270346Sjfv u8 reserved[2]; 1408270346Sjfv __le16 credit; 1409270346Sjfv u8 reserved1[2]; 1410270346Sjfv u8 max_bw; /* 0-3, limit = 2^max */ 1411270346Sjfv u8 reserved2[7]; 1412266423Sjfv}; 1413266423Sjfv 1414266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1415266423Sjfv 1416266423Sjfv/* Enable Physical Port ETS (indirect 0x0413) 1417266423Sjfv * Modify Physical Port ETS (indirect 0x0414) 1418266423Sjfv * Disable Physical Port ETS (indirect 0x0415) 1419266423Sjfv */ 1420266423Sjfvstruct i40e_aqc_configure_switching_comp_ets_data { 1421270346Sjfv u8 reserved[4]; 1422270346Sjfv u8 tc_valid_bits; 1423270346Sjfv u8 seepage; 1424270346Sjfv#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1425270346Sjfv u8 tc_strict_priority_flags; 1426270346Sjfv u8 reserved1[17]; 1427270346Sjfv u8 tc_bw_share_credits[8]; 1428270346Sjfv u8 reserved2[96]; 1429266423Sjfv}; 1430266423Sjfv 1431266423Sjfv/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1432266423Sjfvstruct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1433270346Sjfv u8 tc_valid_bits; 1434270346Sjfv u8 reserved[15]; 1435270346Sjfv __le16 tc_bw_credit[8]; 1436266423Sjfv 1437266423Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1438270346Sjfv __le16 tc_bw_max[2]; 1439270346Sjfv u8 reserved1[28]; 1440266423Sjfv}; 1441266423Sjfv 1442266423Sjfv/* Configure Switching Component Bandwidth Allocation per Tc 1443266423Sjfv * (indirect 0x0417) 1444266423Sjfv */ 1445266423Sjfvstruct i40e_aqc_configure_switching_comp_bw_config_data { 1446270346Sjfv u8 tc_valid_bits; 1447270346Sjfv u8 reserved[2]; 1448270346Sjfv u8 absolute_credits; /* bool */ 1449270346Sjfv u8 tc_bw_share_credits[8]; 1450270346Sjfv u8 reserved1[20]; 1451266423Sjfv}; 1452266423Sjfv 1453266423Sjfv/* Query Switching Component Configuration (indirect 0x0418) */ 1454266423Sjfvstruct i40e_aqc_query_switching_comp_ets_config_resp { 1455270346Sjfv u8 tc_valid_bits; 1456270346Sjfv u8 reserved[35]; 1457270346Sjfv __le16 port_bw_limit; 1458270346Sjfv u8 reserved1[2]; 1459270346Sjfv u8 tc_bw_max; /* 0-3, limit = 2^max */ 1460270346Sjfv u8 reserved2[23]; 1461266423Sjfv}; 1462266423Sjfv 1463266423Sjfv/* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1464266423Sjfvstruct i40e_aqc_query_port_ets_config_resp { 1465270346Sjfv u8 reserved[4]; 1466270346Sjfv u8 tc_valid_bits; 1467270346Sjfv u8 reserved1; 1468270346Sjfv u8 tc_strict_priority_bits; 1469270346Sjfv u8 reserved2; 1470270346Sjfv u8 tc_bw_share_credits[8]; 1471270346Sjfv __le16 tc_bw_limits[8]; 1472266423Sjfv 1473266423Sjfv /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1474270346Sjfv __le16 tc_bw_max[2]; 1475270346Sjfv u8 reserved3[32]; 1476266423Sjfv}; 1477266423Sjfv 1478266423Sjfv/* Query Switching Component Bandwidth Allocation per Traffic Type 1479266423Sjfv * (indirect 0x041A) 1480266423Sjfv */ 1481266423Sjfvstruct i40e_aqc_query_switching_comp_bw_config_resp { 1482270346Sjfv u8 tc_valid_bits; 1483270346Sjfv u8 reserved[2]; 1484270346Sjfv u8 absolute_credits_enable; /* bool */ 1485270346Sjfv u8 tc_bw_share_credits[8]; 1486270346Sjfv __le16 tc_bw_limits[8]; 1487266423Sjfv 1488266423Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1489270346Sjfv __le16 tc_bw_max[2]; 1490266423Sjfv}; 1491266423Sjfv 1492266423Sjfv/* Suspend/resume port TX traffic 1493266423Sjfv * (direct 0x041B and 0x041C) uses the generic SEID struct 1494266423Sjfv */ 1495266423Sjfv 1496266423Sjfv/* Configure partition BW 1497266423Sjfv * (indirect 0x041D) 1498266423Sjfv */ 1499266423Sjfvstruct i40e_aqc_configure_partition_bw_data { 1500270346Sjfv __le16 pf_valid_bits; 1501270346Sjfv u8 min_bw[16]; /* guaranteed bandwidth */ 1502270346Sjfv u8 max_bw[16]; /* bandwidth limit */ 1503266423Sjfv}; 1504266423Sjfv 1505266423Sjfv/* Get and set the active HMC resource profile and status. 1506266423Sjfv * (direct 0x0500) and (direct 0x0501) 1507266423Sjfv */ 1508266423Sjfvstruct i40e_aq_get_set_hmc_resource_profile { 1509270346Sjfv u8 pm_profile; 1510270346Sjfv u8 pe_vf_enabled; 1511270346Sjfv u8 reserved[14]; 1512266423Sjfv}; 1513266423Sjfv 1514266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1515266423Sjfv 1516266423Sjfvenum i40e_aq_hmc_profile { 1517266423Sjfv /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1518270346Sjfv I40E_HMC_PROFILE_DEFAULT = 1, 1519270346Sjfv I40E_HMC_PROFILE_FAVOR_VF = 2, 1520270346Sjfv I40E_HMC_PROFILE_EQUAL = 3, 1521266423Sjfv}; 1522266423Sjfv 1523270346Sjfv#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF 1524270346Sjfv#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F 1525266423Sjfv 1526266423Sjfv/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1527266423Sjfv 1528266423Sjfv/* set in param0 for get phy abilities to report qualified modules */ 1529270346Sjfv#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1530270346Sjfv#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1531266423Sjfv 1532266423Sjfvenum i40e_aq_phy_type { 1533266423Sjfv I40E_PHY_TYPE_SGMII = 0x0, 1534266423Sjfv I40E_PHY_TYPE_1000BASE_KX = 0x1, 1535266423Sjfv I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1536266423Sjfv I40E_PHY_TYPE_10GBASE_KR = 0x3, 1537266423Sjfv I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1538266423Sjfv I40E_PHY_TYPE_XAUI = 0x5, 1539266423Sjfv I40E_PHY_TYPE_XFI = 0x6, 1540266423Sjfv I40E_PHY_TYPE_SFI = 0x7, 1541266423Sjfv I40E_PHY_TYPE_XLAUI = 0x8, 1542266423Sjfv I40E_PHY_TYPE_XLPPI = 0x9, 1543266423Sjfv I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1544266423Sjfv I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1545266423Sjfv I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1546266423Sjfv I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1547266423Sjfv I40E_PHY_TYPE_100BASE_TX = 0x11, 1548266423Sjfv I40E_PHY_TYPE_1000BASE_T = 0x12, 1549266423Sjfv I40E_PHY_TYPE_10GBASE_T = 0x13, 1550266423Sjfv I40E_PHY_TYPE_10GBASE_SR = 0x14, 1551266423Sjfv I40E_PHY_TYPE_10GBASE_LR = 0x15, 1552266423Sjfv I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1553266423Sjfv I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1554266423Sjfv I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1555266423Sjfv I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1556266423Sjfv I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1557266423Sjfv I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1558266423Sjfv I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1559266423Sjfv I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1560266423Sjfv I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1561266423Sjfv I40E_PHY_TYPE_MAX 1562266423Sjfv}; 1563266423Sjfv 1564266423Sjfv#define I40E_LINK_SPEED_100MB_SHIFT 0x1 1565266423Sjfv#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1566266423Sjfv#define I40E_LINK_SPEED_10GB_SHIFT 0x3 1567266423Sjfv#define I40E_LINK_SPEED_40GB_SHIFT 0x4 1568266423Sjfv#define I40E_LINK_SPEED_20GB_SHIFT 0x5 1569266423Sjfv 1570266423Sjfvenum i40e_aq_link_speed { 1571266423Sjfv I40E_LINK_SPEED_UNKNOWN = 0, 1572266423Sjfv I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1573266423Sjfv I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1574266423Sjfv I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1575266423Sjfv I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1576266423Sjfv I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) 1577266423Sjfv}; 1578266423Sjfv 1579266423Sjfvstruct i40e_aqc_module_desc { 1580266423Sjfv u8 oui[3]; 1581266423Sjfv u8 reserved1; 1582266423Sjfv u8 part_number[16]; 1583266423Sjfv u8 revision[4]; 1584266423Sjfv u8 reserved2[8]; 1585266423Sjfv}; 1586266423Sjfv 1587266423Sjfvstruct i40e_aq_get_phy_abilities_resp { 1588270346Sjfv __le32 phy_type; /* bitmap using the above enum for offsets */ 1589270346Sjfv u8 link_speed; /* bitmap using the above enum bit patterns */ 1590270346Sjfv u8 abilities; 1591270346Sjfv#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1592270346Sjfv#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1593270346Sjfv#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1594270346Sjfv#define I40E_AQ_PHY_LINK_ENABLED 0x08 1595270346Sjfv#define I40E_AQ_PHY_AN_ENABLED 0x10 1596270346Sjfv#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1597270346Sjfv __le16 eee_capability; 1598270346Sjfv#define I40E_AQ_EEE_100BASE_TX 0x0002 1599270346Sjfv#define I40E_AQ_EEE_1000BASE_T 0x0004 1600270346Sjfv#define I40E_AQ_EEE_10GBASE_T 0x0008 1601270346Sjfv#define I40E_AQ_EEE_1000BASE_KX 0x0010 1602270346Sjfv#define I40E_AQ_EEE_10GBASE_KX4 0x0020 1603270346Sjfv#define I40E_AQ_EEE_10GBASE_KR 0x0040 1604270346Sjfv __le32 eeer_val; 1605270346Sjfv u8 d3_lpan; 1606270346Sjfv#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1607270346Sjfv u8 reserved[3]; 1608270346Sjfv u8 phy_id[4]; 1609270346Sjfv u8 module_type[3]; 1610270346Sjfv u8 qualified_module_count; 1611270346Sjfv#define I40E_AQ_PHY_MAX_QMS 16 1612270346Sjfv struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1613266423Sjfv}; 1614266423Sjfv 1615266423Sjfv/* Set PHY Config (direct 0x0601) */ 1616266423Sjfvstruct i40e_aq_set_phy_config { /* same bits as above in all */ 1617270346Sjfv __le32 phy_type; 1618270346Sjfv u8 link_speed; 1619270346Sjfv u8 abilities; 1620266423Sjfv/* bits 0-2 use the values from get_phy_abilities_resp */ 1621266423Sjfv#define I40E_AQ_PHY_ENABLE_LINK 0x08 1622266423Sjfv#define I40E_AQ_PHY_ENABLE_AN 0x10 1623266423Sjfv#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1624270346Sjfv __le16 eee_capability; 1625270346Sjfv __le32 eeer; 1626270346Sjfv u8 low_power_ctrl; 1627270346Sjfv u8 reserved[3]; 1628266423Sjfv}; 1629266423Sjfv 1630266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1631266423Sjfv 1632266423Sjfv/* Set MAC Config command data structure (direct 0x0603) */ 1633266423Sjfvstruct i40e_aq_set_mac_config { 1634270346Sjfv __le16 max_frame_size; 1635270346Sjfv u8 params; 1636270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1637270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1638270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1639270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1640270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1641270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1642270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1643270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1644270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1645270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1646270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1647270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1648270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1649270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1650270346Sjfv u8 tx_timer_priority; /* bitmap */ 1651270346Sjfv __le16 tx_timer_value; 1652270346Sjfv __le16 fc_refresh_threshold; 1653270346Sjfv u8 reserved[8]; 1654266423Sjfv}; 1655266423Sjfv 1656266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1657266423Sjfv 1658266423Sjfv/* Restart Auto-Negotiation (direct 0x605) */ 1659266423Sjfvstruct i40e_aqc_set_link_restart_an { 1660270346Sjfv u8 command; 1661270346Sjfv#define I40E_AQ_PHY_RESTART_AN 0x02 1662270346Sjfv#define I40E_AQ_PHY_LINK_ENABLE 0x04 1663270346Sjfv u8 reserved[15]; 1664266423Sjfv}; 1665266423Sjfv 1666266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1667266423Sjfv 1668266423Sjfv/* Get Link Status cmd & response data structure (direct 0x0607) */ 1669266423Sjfvstruct i40e_aqc_get_link_status { 1670270346Sjfv __le16 command_flags; /* only field set on command */ 1671270346Sjfv#define I40E_AQ_LSE_MASK 0x3 1672270346Sjfv#define I40E_AQ_LSE_NOP 0x0 1673270346Sjfv#define I40E_AQ_LSE_DISABLE 0x2 1674270346Sjfv#define I40E_AQ_LSE_ENABLE 0x3 1675266423Sjfv/* only response uses this flag */ 1676270346Sjfv#define I40E_AQ_LSE_IS_ENABLED 0x1 1677270346Sjfv u8 phy_type; /* i40e_aq_phy_type */ 1678270346Sjfv u8 link_speed; /* i40e_aq_link_speed */ 1679270346Sjfv u8 link_info; 1680270346Sjfv#define I40E_AQ_LINK_UP 0x01 1681270346Sjfv#define I40E_AQ_LINK_FAULT 0x02 1682270346Sjfv#define I40E_AQ_LINK_FAULT_TX 0x04 1683270346Sjfv#define I40E_AQ_LINK_FAULT_RX 0x08 1684270346Sjfv#define I40E_AQ_LINK_FAULT_REMOTE 0x10 1685270346Sjfv#define I40E_AQ_MEDIA_AVAILABLE 0x40 1686270346Sjfv#define I40E_AQ_SIGNAL_DETECT 0x80 1687270346Sjfv u8 an_info; 1688270346Sjfv#define I40E_AQ_AN_COMPLETED 0x01 1689270346Sjfv#define I40E_AQ_LP_AN_ABILITY 0x02 1690270346Sjfv#define I40E_AQ_PD_FAULT 0x04 1691270346Sjfv#define I40E_AQ_FEC_EN 0x08 1692270346Sjfv#define I40E_AQ_PHY_LOW_POWER 0x10 1693270346Sjfv#define I40E_AQ_LINK_PAUSE_TX 0x20 1694270346Sjfv#define I40E_AQ_LINK_PAUSE_RX 0x40 1695270346Sjfv#define I40E_AQ_QUALIFIED_MODULE 0x80 1696270346Sjfv u8 ext_info; 1697270346Sjfv#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1698270346Sjfv#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1699270346Sjfv#define I40E_AQ_LINK_TX_SHIFT 0x02 1700270346Sjfv#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1701270346Sjfv#define I40E_AQ_LINK_TX_ACTIVE 0x00 1702270346Sjfv#define I40E_AQ_LINK_TX_DRAINED 0x01 1703270346Sjfv#define I40E_AQ_LINK_TX_FLUSHED 0x03 1704270346Sjfv#define I40E_AQ_LINK_FORCED_40G 0x10 1705270346Sjfv u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1706270346Sjfv __le16 max_frame_size; 1707270346Sjfv u8 config; 1708270346Sjfv#define I40E_AQ_CONFIG_CRC_ENA 0x04 1709270346Sjfv#define I40E_AQ_CONFIG_PACING_MASK 0x78 1710270346Sjfv u8 reserved[5]; 1711266423Sjfv}; 1712266423Sjfv 1713266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1714266423Sjfv 1715266423Sjfv/* Set event mask command (direct 0x613) */ 1716266423Sjfvstruct i40e_aqc_set_phy_int_mask { 1717270346Sjfv u8 reserved[8]; 1718270346Sjfv __le16 event_mask; 1719270346Sjfv#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1720270346Sjfv#define I40E_AQ_EVENT_MEDIA_NA 0x0004 1721270346Sjfv#define I40E_AQ_EVENT_LINK_FAULT 0x0008 1722270346Sjfv#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1723270346Sjfv#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1724270346Sjfv#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1725270346Sjfv#define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1726270346Sjfv#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1727270346Sjfv#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1728270346Sjfv u8 reserved1[6]; 1729266423Sjfv}; 1730266423Sjfv 1731266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1732266423Sjfv 1733266423Sjfv/* Get Local AN advt register (direct 0x0614) 1734266423Sjfv * Set Local AN advt register (direct 0x0615) 1735266423Sjfv * Get Link Partner AN advt register (direct 0x0616) 1736266423Sjfv */ 1737266423Sjfvstruct i40e_aqc_an_advt_reg { 1738270346Sjfv __le32 local_an_reg0; 1739270346Sjfv __le16 local_an_reg1; 1740270346Sjfv u8 reserved[10]; 1741266423Sjfv}; 1742266423Sjfv 1743266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1744266423Sjfv 1745266423Sjfv/* Set Loopback mode (0x0618) */ 1746266423Sjfvstruct i40e_aqc_set_lb_mode { 1747270346Sjfv __le16 lb_mode; 1748270346Sjfv#define I40E_AQ_LB_PHY_LOCAL 0x01 1749270346Sjfv#define I40E_AQ_LB_PHY_REMOTE 0x02 1750270346Sjfv#define I40E_AQ_LB_MAC_LOCAL 0x04 1751270346Sjfv u8 reserved[14]; 1752266423Sjfv}; 1753266423Sjfv 1754266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1755266423Sjfv 1756266423Sjfv/* Set PHY Debug command (0x0622) */ 1757266423Sjfvstruct i40e_aqc_set_phy_debug { 1758270346Sjfv u8 command_flags; 1759266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1760266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1761270346Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1762270346Sjfv I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1763266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1764266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1765266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1766266423Sjfv#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1767270346Sjfv u8 reserved[15]; 1768266423Sjfv}; 1769266423Sjfv 1770266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1771266423Sjfv 1772266423Sjfvenum i40e_aq_phy_reg_type { 1773270346Sjfv I40E_AQC_PHY_REG_INTERNAL = 0x1, 1774270346Sjfv I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1775270346Sjfv I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1776266423Sjfv}; 1777266423Sjfv 1778266423Sjfv/* NVM Read command (indirect 0x0701) 1779266423Sjfv * NVM Erase commands (direct 0x0702) 1780266423Sjfv * NVM Update commands (indirect 0x0703) 1781266423Sjfv */ 1782266423Sjfvstruct i40e_aqc_nvm_update { 1783270346Sjfv u8 command_flags; 1784270346Sjfv#define I40E_AQ_NVM_LAST_CMD 0x01 1785270346Sjfv#define I40E_AQ_NVM_FLASH_ONLY 0x80 1786270346Sjfv u8 module_pointer; 1787270346Sjfv __le16 length; 1788270346Sjfv __le32 offset; 1789270346Sjfv __le32 addr_high; 1790270346Sjfv __le32 addr_low; 1791266423Sjfv}; 1792266423Sjfv 1793266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 1794266423Sjfv 1795266423Sjfv/* NVM Config Read (indirect 0x0704) */ 1796266423Sjfvstruct i40e_aqc_nvm_config_read { 1797270346Sjfv __le16 cmd_flags; 1798266423Sjfv#define ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 1799266423Sjfv#define ANVM_READ_SINGLE_FEATURE 0 1800266423Sjfv#define ANVM_READ_MULTIPLE_FEATURES 1 1801270346Sjfv __le16 element_count; 1802270346Sjfv __le16 element_id; /* Feature/field ID */ 1803270346Sjfv u8 reserved[2]; 1804270346Sjfv __le32 address_high; 1805270346Sjfv __le32 address_low; 1806266423Sjfv}; 1807266423Sjfv 1808266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 1809266423Sjfv 1810266423Sjfv/* NVM Config Write (indirect 0x0705) */ 1811266423Sjfvstruct i40e_aqc_nvm_config_write { 1812270346Sjfv __le16 cmd_flags; 1813270346Sjfv __le16 element_count; 1814270346Sjfv u8 reserved[4]; 1815270346Sjfv __le32 address_high; 1816270346Sjfv __le32 address_low; 1817266423Sjfv}; 1818266423Sjfv 1819266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 1820266423Sjfv 1821266423Sjfvstruct i40e_aqc_nvm_config_data_feature { 1822266423Sjfv __le16 feature_id; 1823266423Sjfv __le16 instance_id; 1824266423Sjfv __le16 feature_options; 1825266423Sjfv __le16 feature_selection; 1826266423Sjfv}; 1827266423Sjfv 1828266423Sjfvstruct i40e_aqc_nvm_config_data_immediate_field { 1829266423Sjfv#define ANVM_FEATURE_OR_IMMEDIATE_MASK 0x2 1830266423Sjfv __le16 field_id; 1831266423Sjfv __le16 instance_id; 1832266423Sjfv __le16 field_options; 1833266423Sjfv __le16 field_value; 1834266423Sjfv}; 1835266423Sjfv 1836266423Sjfv/* Send to PF command (indirect 0x0801) id is only used by PF 1837266423Sjfv * Send to VF command (indirect 0x0802) id is only used by PF 1838266423Sjfv * Send to Peer PF command (indirect 0x0803) 1839266423Sjfv */ 1840266423Sjfvstruct i40e_aqc_pf_vf_message { 1841270346Sjfv __le32 id; 1842270346Sjfv u8 reserved[4]; 1843270346Sjfv __le32 addr_high; 1844270346Sjfv __le32 addr_low; 1845266423Sjfv}; 1846266423Sjfv 1847266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 1848266423Sjfv 1849266423Sjfv/* Alternate structure */ 1850266423Sjfv 1851266423Sjfv/* Direct write (direct 0x0900) 1852266423Sjfv * Direct read (direct 0x0902) 1853266423Sjfv */ 1854266423Sjfvstruct i40e_aqc_alternate_write { 1855266423Sjfv __le32 address0; 1856266423Sjfv __le32 data0; 1857266423Sjfv __le32 address1; 1858266423Sjfv __le32 data1; 1859266423Sjfv}; 1860266423Sjfv 1861266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 1862266423Sjfv 1863266423Sjfv/* Indirect write (indirect 0x0901) 1864266423Sjfv * Indirect read (indirect 0x0903) 1865266423Sjfv */ 1866266423Sjfv 1867266423Sjfvstruct i40e_aqc_alternate_ind_write { 1868266423Sjfv __le32 address; 1869266423Sjfv __le32 length; 1870266423Sjfv __le32 addr_high; 1871266423Sjfv __le32 addr_low; 1872266423Sjfv}; 1873266423Sjfv 1874266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 1875266423Sjfv 1876266423Sjfv/* Done alternate write (direct 0x0904) 1877266423Sjfv * uses i40e_aq_desc 1878266423Sjfv */ 1879266423Sjfvstruct i40e_aqc_alternate_write_done { 1880270346Sjfv __le16 cmd_flags; 1881266423Sjfv#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 1882266423Sjfv#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 1883266423Sjfv#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 1884266423Sjfv#define I40E_AQ_ALTERNATE_RESET_NEEDED 2 1885270346Sjfv u8 reserved[14]; 1886266423Sjfv}; 1887266423Sjfv 1888266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 1889266423Sjfv 1890266423Sjfv/* Set OEM mode (direct 0x0905) */ 1891266423Sjfvstruct i40e_aqc_alternate_set_mode { 1892270346Sjfv __le32 mode; 1893266423Sjfv#define I40E_AQ_ALTERNATE_MODE_NONE 0 1894266423Sjfv#define I40E_AQ_ALTERNATE_MODE_OEM 1 1895270346Sjfv u8 reserved[12]; 1896266423Sjfv}; 1897266423Sjfv 1898266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 1899266423Sjfv 1900266423Sjfv/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 1901266423Sjfv 1902266423Sjfv/* async events 0x10xx */ 1903266423Sjfv 1904266423Sjfv/* Lan Queue Overflow Event (direct, 0x1001) */ 1905266423Sjfvstruct i40e_aqc_lan_overflow { 1906270346Sjfv __le32 prtdcb_rupto; 1907270346Sjfv __le32 otx_ctl; 1908270346Sjfv u8 reserved[8]; 1909266423Sjfv}; 1910266423Sjfv 1911266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 1912266423Sjfv 1913266423Sjfv/* Get LLDP MIB (indirect 0x0A00) */ 1914266423Sjfvstruct i40e_aqc_lldp_get_mib { 1915270346Sjfv u8 type; 1916270346Sjfv u8 reserved1; 1917270346Sjfv#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 1918270346Sjfv#define I40E_AQ_LLDP_MIB_LOCAL 0x0 1919270346Sjfv#define I40E_AQ_LLDP_MIB_REMOTE 0x1 1920270346Sjfv#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 1921270346Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 1922270346Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 1923270346Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 1924270346Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 1925270346Sjfv#define I40E_AQ_LLDP_TX_SHIFT 0x4 1926270346Sjfv#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 1927266423Sjfv/* TX pause flags use I40E_AQ_LINK_TX_* above */ 1928270346Sjfv __le16 local_len; 1929270346Sjfv __le16 remote_len; 1930270346Sjfv u8 reserved2[2]; 1931270346Sjfv __le32 addr_high; 1932270346Sjfv __le32 addr_low; 1933266423Sjfv}; 1934266423Sjfv 1935266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 1936266423Sjfv 1937266423Sjfv/* Configure LLDP MIB Change Event (direct 0x0A01) 1938266423Sjfv * also used for the event (with type in the command field) 1939266423Sjfv */ 1940266423Sjfvstruct i40e_aqc_lldp_update_mib { 1941270346Sjfv u8 command; 1942270346Sjfv#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1943270346Sjfv#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 1944270346Sjfv u8 reserved[7]; 1945270346Sjfv __le32 addr_high; 1946270346Sjfv __le32 addr_low; 1947266423Sjfv}; 1948266423Sjfv 1949266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 1950266423Sjfv 1951266423Sjfv/* Add LLDP TLV (indirect 0x0A02) 1952266423Sjfv * Delete LLDP TLV (indirect 0x0A04) 1953266423Sjfv */ 1954266423Sjfvstruct i40e_aqc_lldp_add_tlv { 1955270346Sjfv u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1956270346Sjfv u8 reserved1[1]; 1957270346Sjfv __le16 len; 1958270346Sjfv u8 reserved2[4]; 1959270346Sjfv __le32 addr_high; 1960270346Sjfv __le32 addr_low; 1961266423Sjfv}; 1962266423Sjfv 1963266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 1964266423Sjfv 1965266423Sjfv/* Update LLDP TLV (indirect 0x0A03) */ 1966266423Sjfvstruct i40e_aqc_lldp_update_tlv { 1967270346Sjfv u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1968270346Sjfv u8 reserved; 1969270346Sjfv __le16 old_len; 1970270346Sjfv __le16 new_offset; 1971270346Sjfv __le16 new_len; 1972270346Sjfv __le32 addr_high; 1973270346Sjfv __le32 addr_low; 1974266423Sjfv}; 1975266423Sjfv 1976266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 1977266423Sjfv 1978266423Sjfv/* Stop LLDP (direct 0x0A05) */ 1979266423Sjfvstruct i40e_aqc_lldp_stop { 1980270346Sjfv u8 command; 1981270346Sjfv#define I40E_AQ_LLDP_AGENT_STOP 0x0 1982270346Sjfv#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 1983270346Sjfv u8 reserved[15]; 1984266423Sjfv}; 1985266423Sjfv 1986266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 1987266423Sjfv 1988266423Sjfv/* Start LLDP (direct 0x0A06) */ 1989266423Sjfv 1990266423Sjfvstruct i40e_aqc_lldp_start { 1991270346Sjfv u8 command; 1992270346Sjfv#define I40E_AQ_LLDP_AGENT_START 0x1 1993270346Sjfv u8 reserved[15]; 1994266423Sjfv}; 1995266423Sjfv 1996266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 1997266423Sjfv 1998266423Sjfv/* Apply MIB changes (0x0A07) 1999266423Sjfv * uses the generic struc as it contains no data 2000266423Sjfv */ 2001266423Sjfv 2002266423Sjfv/* Add Udp Tunnel command and completion (direct 0x0B00) */ 2003266423Sjfvstruct i40e_aqc_add_udp_tunnel { 2004270346Sjfv __le16 udp_port; 2005270346Sjfv u8 reserved0[3]; 2006270346Sjfv u8 protocol_type; 2007266423Sjfv#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2008266423Sjfv#define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2009266423Sjfv#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2010270346Sjfv u8 reserved1[10]; 2011266423Sjfv}; 2012266423Sjfv 2013266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2014266423Sjfv 2015266423Sjfvstruct i40e_aqc_add_udp_tunnel_completion { 2016266423Sjfv __le16 udp_port; 2017266423Sjfv u8 filter_entry_index; 2018266423Sjfv u8 multiple_pfs; 2019270346Sjfv#define I40E_AQC_SINGLE_PF 0x0 2020270346Sjfv#define I40E_AQC_MULTIPLE_PFS 0x1 2021266423Sjfv u8 total_filters; 2022266423Sjfv u8 reserved[11]; 2023266423Sjfv}; 2024266423Sjfv 2025266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2026266423Sjfv 2027266423Sjfv/* remove UDP Tunnel command (0x0B01) */ 2028266423Sjfvstruct i40e_aqc_remove_udp_tunnel { 2029270346Sjfv u8 reserved[2]; 2030270346Sjfv u8 index; /* 0 to 15 */ 2031270346Sjfv u8 reserved2[13]; 2032266423Sjfv}; 2033266423Sjfv 2034266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2035266423Sjfv 2036266423Sjfvstruct i40e_aqc_del_udp_tunnel_completion { 2037270346Sjfv __le16 udp_port; 2038270346Sjfv u8 index; /* 0 to 15 */ 2039270346Sjfv u8 multiple_pfs; 2040270346Sjfv u8 total_filters_used; 2041270346Sjfv u8 reserved1[11]; 2042266423Sjfv}; 2043266423Sjfv 2044266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2045266423Sjfv 2046266423Sjfv/* tunnel key structure 0x0B10 */ 2047266423Sjfv 2048266423Sjfvstruct i40e_aqc_tunnel_key_structure { 2049266423Sjfv u8 key1_off; 2050266423Sjfv u8 key2_off; 2051266423Sjfv u8 key1_len; /* 0 to 15 */ 2052266423Sjfv u8 key2_len; /* 0 to 15 */ 2053266423Sjfv u8 flags; 2054270346Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2055266423Sjfv/* response flags */ 2056270346Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2057270346Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2058270346Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2059266423Sjfv u8 network_key_index; 2060266423Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2061266423Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2062266423Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2063266423Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2064266423Sjfv u8 reserved[10]; 2065266423Sjfv}; 2066266423Sjfv 2067266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2068266423Sjfv 2069266423Sjfv/* OEM mode commands (direct 0xFE0x) */ 2070266423Sjfvstruct i40e_aqc_oem_param_change { 2071270346Sjfv __le32 param_type; 2072270346Sjfv#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2073270346Sjfv#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2074270346Sjfv#define I40E_AQ_OEM_PARAM_MAC 2 2075270346Sjfv __le32 param_value1; 2076270346Sjfv u8 param_value2[8]; 2077266423Sjfv}; 2078266423Sjfv 2079266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2080266423Sjfv 2081266423Sjfvstruct i40e_aqc_oem_state_change { 2082270346Sjfv __le32 state; 2083270346Sjfv#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2084270346Sjfv#define I40E_AQ_OEM_STATE_LINK_UP 0x1 2085270346Sjfv u8 reserved[12]; 2086266423Sjfv}; 2087266423Sjfv 2088266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2089266423Sjfv 2090266423Sjfv/* debug commands */ 2091266423Sjfv 2092266423Sjfv/* get device id (0xFF00) uses the generic structure */ 2093266423Sjfv 2094266423Sjfv/* set test more (0xFF01, internal) */ 2095266423Sjfv 2096266423Sjfvstruct i40e_acq_set_test_mode { 2097270346Sjfv u8 mode; 2098270346Sjfv#define I40E_AQ_TEST_PARTIAL 0 2099270346Sjfv#define I40E_AQ_TEST_FULL 1 2100270346Sjfv#define I40E_AQ_TEST_NVM 2 2101270346Sjfv u8 reserved[3]; 2102270346Sjfv u8 command; 2103270346Sjfv#define I40E_AQ_TEST_OPEN 0 2104270346Sjfv#define I40E_AQ_TEST_CLOSE 1 2105270346Sjfv#define I40E_AQ_TEST_INC 2 2106270346Sjfv u8 reserved2[3]; 2107270346Sjfv __le32 address_high; 2108270346Sjfv __le32 address_low; 2109266423Sjfv}; 2110266423Sjfv 2111266423SjfvI40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2112266423Sjfv 2113266423Sjfv/* Debug Read Register command (0xFF03) 2114266423Sjfv * Debug Write Register command (0xFF04) 2115266423Sjfv */ 2116266423Sjfvstruct i40e_aqc_debug_reg_read_write { 2117266423Sjfv __le32 reserved; 2118266423Sjfv __le32 address; 2119266423Sjfv __le32 value_high; 2120266423Sjfv __le32 value_low; 2121266423Sjfv}; 2122266423Sjfv 2123266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2124266423Sjfv 2125266423Sjfv/* Scatter/gather Reg Read (indirect 0xFF05) 2126266423Sjfv * Scatter/gather Reg Write (indirect 0xFF06) 2127266423Sjfv */ 2128266423Sjfv 2129266423Sjfv/* i40e_aq_desc is used for the command */ 2130266423Sjfvstruct i40e_aqc_debug_reg_sg_element_data { 2131266423Sjfv __le32 address; 2132266423Sjfv __le32 value; 2133266423Sjfv}; 2134266423Sjfv 2135266423Sjfv/* Debug Modify register (direct 0xFF07) */ 2136266423Sjfvstruct i40e_aqc_debug_modify_reg { 2137266423Sjfv __le32 address; 2138266423Sjfv __le32 value; 2139266423Sjfv __le32 clear_mask; 2140266423Sjfv __le32 set_mask; 2141266423Sjfv}; 2142266423Sjfv 2143266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2144266423Sjfv 2145266423Sjfv/* dump internal data (0xFF08, indirect) */ 2146266423Sjfv 2147266423Sjfv#define I40E_AQ_CLUSTER_ID_AUX 0 2148266423Sjfv#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2149266423Sjfv#define I40E_AQ_CLUSTER_ID_TXSCHED 2 2150266423Sjfv#define I40E_AQ_CLUSTER_ID_HMC 3 2151266423Sjfv#define I40E_AQ_CLUSTER_ID_MAC0 4 2152266423Sjfv#define I40E_AQ_CLUSTER_ID_MAC1 5 2153266423Sjfv#define I40E_AQ_CLUSTER_ID_MAC2 6 2154266423Sjfv#define I40E_AQ_CLUSTER_ID_MAC3 7 2155266423Sjfv#define I40E_AQ_CLUSTER_ID_DCB 8 2156266423Sjfv#define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2157266423Sjfv#define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2158266423Sjfv#define I40E_AQ_CLUSTER_ID_ALTRAM 11 2159266423Sjfv 2160266423Sjfvstruct i40e_aqc_debug_dump_internals { 2161270346Sjfv u8 cluster_id; 2162270346Sjfv u8 table_id; 2163270346Sjfv __le16 data_size; 2164270346Sjfv __le32 idx; 2165270346Sjfv __le32 address_high; 2166270346Sjfv __le32 address_low; 2167266423Sjfv}; 2168266423Sjfv 2169266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2170266423Sjfv 2171266423Sjfvstruct i40e_aqc_debug_modify_internals { 2172270346Sjfv u8 cluster_id; 2173270346Sjfv u8 cluster_specific_params[7]; 2174270346Sjfv __le32 address_high; 2175270346Sjfv __le32 address_low; 2176266423Sjfv}; 2177266423Sjfv 2178266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2179266423Sjfv 2180266423Sjfv#endif 2181