i40e_adminq_cmd.h revision 266423
1/****************************************************************************** 2 3 Copyright (c) 2013-2014, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/i40e/i40e_adminq_cmd.h 266423 2014-05-19 01:21:02Z jfv $*/ 34 35#ifndef _I40E_ADMINQ_CMD_H_ 36#define _I40E_ADMINQ_CMD_H_ 37 38/* This header file defines the i40e Admin Queue commands and is shared between 39 * i40e Firmware and Software. 40 * 41 * This file needs to comply with the Linux Kernel coding style. 42 */ 43 44#define I40E_FW_API_VERSION_MAJOR 0x0001 45#define I40E_FW_API_VERSION_MINOR 0x0002 46#ifdef FORTVILLE_A0_SUPPORT 47#define I40E_FW_API_VERSION_A0_MINOR 0x0000 48#endif 49 50struct i40e_aq_desc { 51 __le16 flags; 52 __le16 opcode; 53 __le16 datalen; 54 __le16 retval; 55 __le32 cookie_high; 56 __le32 cookie_low; 57 union { 58 struct { 59 __le32 param0; 60 __le32 param1; 61 __le32 param2; 62 __le32 param3; 63 } internal; 64 struct { 65 __le32 param0; 66 __le32 param1; 67 __le32 addr_high; 68 __le32 addr_low; 69 } external; 70 u8 raw[16]; 71 } params; 72}; 73 74/* Flags sub-structure 75 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 76 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 77 */ 78 79/* command flags and offsets*/ 80#define I40E_AQ_FLAG_DD_SHIFT 0 81#define I40E_AQ_FLAG_CMP_SHIFT 1 82#define I40E_AQ_FLAG_ERR_SHIFT 2 83#define I40E_AQ_FLAG_VFE_SHIFT 3 84#define I40E_AQ_FLAG_LB_SHIFT 9 85#define I40E_AQ_FLAG_RD_SHIFT 10 86#define I40E_AQ_FLAG_VFC_SHIFT 11 87#define I40E_AQ_FLAG_BUF_SHIFT 12 88#define I40E_AQ_FLAG_SI_SHIFT 13 89#define I40E_AQ_FLAG_EI_SHIFT 14 90#define I40E_AQ_FLAG_FE_SHIFT 15 91 92#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 93#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 94#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 95#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 96#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 97#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 98#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 99#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 100#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 101#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 102#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 103 104/* error codes */ 105enum i40e_admin_queue_err { 106 I40E_AQ_RC_OK = 0, /* success */ 107 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 108 I40E_AQ_RC_ENOENT = 2, /* No such element */ 109 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 110 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 111 I40E_AQ_RC_EIO = 5, /* I/O error */ 112 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 113 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 114 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 115 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 116 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 117 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 118 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 119 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 120 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 121 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 122 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 123 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 124 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 125 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed because of prev cmd error */ 126 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 127 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 128 I40E_AQ_RC_EFBIG = 22, /* File too large */ 129}; 130 131/* Admin Queue command opcodes */ 132enum i40e_admin_queue_opc { 133 /* aq commands */ 134 i40e_aqc_opc_get_version = 0x0001, 135 i40e_aqc_opc_driver_version = 0x0002, 136 i40e_aqc_opc_queue_shutdown = 0x0003, 137 i40e_aqc_opc_set_pf_context = 0x0004, 138 139 /* resource ownership */ 140 i40e_aqc_opc_request_resource = 0x0008, 141 i40e_aqc_opc_release_resource = 0x0009, 142 143 i40e_aqc_opc_list_func_capabilities = 0x000A, 144 i40e_aqc_opc_list_dev_capabilities = 0x000B, 145 146 i40e_aqc_opc_set_cppm_configuration = 0x0103, 147 i40e_aqc_opc_set_arp_proxy_entry = 0x0104, 148 i40e_aqc_opc_set_ns_proxy_entry = 0x0105, 149 150 /* LAA */ 151 i40e_aqc_opc_mng_laa = 0x0106, /* AQ obsolete */ 152 i40e_aqc_opc_mac_address_read = 0x0107, 153 i40e_aqc_opc_mac_address_write = 0x0108, 154 155 /* PXE */ 156 i40e_aqc_opc_clear_pxe_mode = 0x0110, 157 158 /* internal switch commands */ 159 i40e_aqc_opc_get_switch_config = 0x0200, 160 i40e_aqc_opc_add_statistics = 0x0201, 161 i40e_aqc_opc_remove_statistics = 0x0202, 162 i40e_aqc_opc_set_port_parameters = 0x0203, 163 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 164 165 i40e_aqc_opc_add_vsi = 0x0210, 166 i40e_aqc_opc_update_vsi_parameters = 0x0211, 167 i40e_aqc_opc_get_vsi_parameters = 0x0212, 168 169 i40e_aqc_opc_add_pv = 0x0220, 170 i40e_aqc_opc_update_pv_parameters = 0x0221, 171 i40e_aqc_opc_get_pv_parameters = 0x0222, 172 173 i40e_aqc_opc_add_veb = 0x0230, 174 i40e_aqc_opc_update_veb_parameters = 0x0231, 175 i40e_aqc_opc_get_veb_parameters = 0x0232, 176 177 i40e_aqc_opc_delete_element = 0x0243, 178 179 i40e_aqc_opc_add_macvlan = 0x0250, 180 i40e_aqc_opc_remove_macvlan = 0x0251, 181 i40e_aqc_opc_add_vlan = 0x0252, 182 i40e_aqc_opc_remove_vlan = 0x0253, 183 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 184 i40e_aqc_opc_add_tag = 0x0255, 185 i40e_aqc_opc_remove_tag = 0x0256, 186 i40e_aqc_opc_add_multicast_etag = 0x0257, 187 i40e_aqc_opc_remove_multicast_etag = 0x0258, 188 i40e_aqc_opc_update_tag = 0x0259, 189 i40e_aqc_opc_add_control_packet_filter = 0x025A, 190 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 191 i40e_aqc_opc_add_cloud_filters = 0x025C, 192 i40e_aqc_opc_remove_cloud_filters = 0x025D, 193 194 i40e_aqc_opc_add_mirror_rule = 0x0260, 195 i40e_aqc_opc_delete_mirror_rule = 0x0261, 196 197 /* DCB commands */ 198 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 199 i40e_aqc_opc_dcb_updated = 0x0302, 200 201 /* TX scheduler */ 202 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 203 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 204 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 205 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 206 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 207 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 208 209 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 210 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 211 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 212 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 213 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 214 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 215 i40e_aqc_opc_query_port_ets_config = 0x0419, 216 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 217 i40e_aqc_opc_suspend_port_tx = 0x041B, 218 i40e_aqc_opc_resume_port_tx = 0x041C, 219 i40e_aqc_opc_configure_partition_bw = 0x041D, 220 221 /* hmc */ 222 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 223 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 224 225 /* phy commands*/ 226 i40e_aqc_opc_get_phy_abilities = 0x0600, 227 i40e_aqc_opc_set_phy_config = 0x0601, 228 i40e_aqc_opc_set_mac_config = 0x0603, 229 i40e_aqc_opc_set_link_restart_an = 0x0605, 230 i40e_aqc_opc_get_link_status = 0x0607, 231 i40e_aqc_opc_set_phy_int_mask = 0x0613, 232 i40e_aqc_opc_get_local_advt_reg = 0x0614, 233 i40e_aqc_opc_set_local_advt_reg = 0x0615, 234 i40e_aqc_opc_get_partner_advt = 0x0616, 235 i40e_aqc_opc_set_lb_modes = 0x0618, 236 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 237 i40e_aqc_opc_set_phy_debug = 0x0622, 238 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 239 240 /* NVM commands */ 241 i40e_aqc_opc_nvm_read = 0x0701, 242 i40e_aqc_opc_nvm_erase = 0x0702, 243 i40e_aqc_opc_nvm_update = 0x0703, 244 i40e_aqc_opc_nvm_config_read = 0x0704, 245 i40e_aqc_opc_nvm_config_write = 0x0705, 246 247 /* virtualization commands */ 248 i40e_aqc_opc_send_msg_to_pf = 0x0801, 249 i40e_aqc_opc_send_msg_to_vf = 0x0802, 250 i40e_aqc_opc_send_msg_to_peer = 0x0803, 251 252 /* alternate structure */ 253 i40e_aqc_opc_alternate_write = 0x0900, 254 i40e_aqc_opc_alternate_write_indirect = 0x0901, 255 i40e_aqc_opc_alternate_read = 0x0902, 256 i40e_aqc_opc_alternate_read_indirect = 0x0903, 257 i40e_aqc_opc_alternate_write_done = 0x0904, 258 i40e_aqc_opc_alternate_set_mode = 0x0905, 259 i40e_aqc_opc_alternate_clear_port = 0x0906, 260 261 /* LLDP commands */ 262 i40e_aqc_opc_lldp_get_mib = 0x0A00, 263 i40e_aqc_opc_lldp_update_mib = 0x0A01, 264 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 265 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 266 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 267 i40e_aqc_opc_lldp_stop = 0x0A05, 268 i40e_aqc_opc_lldp_start = 0x0A06, 269 270 /* Tunnel commands */ 271 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 272 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 273 i40e_aqc_opc_tunnel_key_structure = 0x0B10, 274 275 /* Async Events */ 276 i40e_aqc_opc_event_lan_overflow = 0x1001, 277 278 /* OEM commands */ 279 i40e_aqc_opc_oem_parameter_change = 0xFE00, 280 i40e_aqc_opc_oem_device_status_change = 0xFE01, 281 282 /* debug commands */ 283 i40e_aqc_opc_debug_get_deviceid = 0xFF00, 284 i40e_aqc_opc_debug_set_mode = 0xFF01, 285 i40e_aqc_opc_debug_read_reg = 0xFF03, 286 i40e_aqc_opc_debug_write_reg = 0xFF04, 287 i40e_aqc_opc_debug_modify_reg = 0xFF07, 288 i40e_aqc_opc_debug_dump_internals = 0xFF08, 289 i40e_aqc_opc_debug_modify_internals = 0xFF09, 290}; 291 292/* command structures and indirect data structures */ 293 294/* Structure naming conventions: 295 * - no suffix for direct command descriptor structures 296 * - _data for indirect sent data 297 * - _resp for indirect return data (data which is both will use _data) 298 * - _completion for direct return data 299 * - _element_ for repeated elements (may also be _data or _resp) 300 * 301 * Command structures are expected to overlay the params.raw member of the basic 302 * descriptor, and as such cannot exceed 16 bytes in length. 303 */ 304 305/* This macro is used to generate a compilation error if a structure 306 * is not exactly the correct length. It gives a divide by zero error if the 307 * structure is not of the correct size, otherwise it creates an enum that is 308 * never used. 309 */ 310#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 311 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 312 313/* This macro is used extensively to ensure that command structures are 16 314 * bytes in length as they have to map to the raw array of that size. 315 */ 316#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 317 318/* internal (0x00XX) commands */ 319 320/* Get version (direct 0x0001) */ 321struct i40e_aqc_get_version { 322 __le32 rom_ver; 323 __le32 fw_build; 324 __le16 fw_major; 325 __le16 fw_minor; 326 __le16 api_major; 327 __le16 api_minor; 328}; 329 330I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 331 332/* Send driver version (indirect 0x0002) */ 333struct i40e_aqc_driver_version { 334 u8 driver_major_ver; 335 u8 driver_minor_ver; 336 u8 driver_build_ver; 337 u8 driver_subbuild_ver; 338 u8 reserved[4]; 339 __le32 address_high; 340 __le32 address_low; 341}; 342 343I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 344 345/* Queue Shutdown (direct 0x0003) */ 346struct i40e_aqc_queue_shutdown { 347 __le32 driver_unloading; 348#define I40E_AQ_DRIVER_UNLOADING 0x1 349 u8 reserved[12]; 350}; 351 352I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 353 354/* Set PF context (0x0004, direct) */ 355struct i40e_aqc_set_pf_context { 356 u8 pf_id; 357 u8 reserved[15]; 358}; 359 360I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 361 362/* Request resource ownership (direct 0x0008) 363 * Release resource ownership (direct 0x0009) 364 */ 365#define I40E_AQ_RESOURCE_NVM 1 366#define I40E_AQ_RESOURCE_SDP 2 367#define I40E_AQ_RESOURCE_ACCESS_READ 1 368#define I40E_AQ_RESOURCE_ACCESS_WRITE 2 369#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 370#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 371 372struct i40e_aqc_request_resource { 373 __le16 resource_id; 374 __le16 access_type; 375 __le32 timeout; 376 __le32 resource_number; 377 u8 reserved[4]; 378}; 379 380I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 381 382/* Get function capabilities (indirect 0x000A) 383 * Get device capabilities (indirect 0x000B) 384 */ 385struct i40e_aqc_list_capabilites { 386 u8 command_flags; 387#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 388 u8 pf_index; 389 u8 reserved[2]; 390 __le32 count; 391 __le32 addr_high; 392 __le32 addr_low; 393}; 394 395I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 396 397struct i40e_aqc_list_capabilities_element_resp { 398 __le16 id; 399 u8 major_rev; 400 u8 minor_rev; 401 __le32 number; 402 __le32 logical_id; 403 __le32 phys_id; 404 u8 reserved[16]; 405}; 406 407/* list of caps */ 408 409#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 410#define I40E_AQ_CAP_ID_MNG_MODE 0x0002 411#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 412#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 413#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 414#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 415#define I40E_AQ_CAP_ID_SRIOV 0x0012 416#define I40E_AQ_CAP_ID_VF 0x0013 417#define I40E_AQ_CAP_ID_VMDQ 0x0014 418#define I40E_AQ_CAP_ID_8021QBG 0x0015 419#define I40E_AQ_CAP_ID_8021QBR 0x0016 420#define I40E_AQ_CAP_ID_VSI 0x0017 421#define I40E_AQ_CAP_ID_DCB 0x0018 422#define I40E_AQ_CAP_ID_FCOE 0x0021 423#define I40E_AQ_CAP_ID_RSS 0x0040 424#define I40E_AQ_CAP_ID_RXQ 0x0041 425#define I40E_AQ_CAP_ID_TXQ 0x0042 426#define I40E_AQ_CAP_ID_MSIX 0x0043 427#define I40E_AQ_CAP_ID_VF_MSIX 0x0044 428#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 429#define I40E_AQ_CAP_ID_1588 0x0046 430#define I40E_AQ_CAP_ID_IWARP 0x0051 431#define I40E_AQ_CAP_ID_LED 0x0061 432#define I40E_AQ_CAP_ID_SDP 0x0062 433#define I40E_AQ_CAP_ID_MDIO 0x0063 434#define I40E_AQ_CAP_ID_FLEX10 0x00F1 435#define I40E_AQ_CAP_ID_CEM 0x00F2 436 437/* Set CPPM Configuration (direct 0x0103) */ 438struct i40e_aqc_cppm_configuration { 439 __le16 command_flags; 440#define I40E_AQ_CPPM_EN_LTRC 0x0800 441#define I40E_AQ_CPPM_EN_DMCTH 0x1000 442#define I40E_AQ_CPPM_EN_DMCTLX 0x2000 443#define I40E_AQ_CPPM_EN_HPTC 0x4000 444#define I40E_AQ_CPPM_EN_DMARC 0x8000 445 __le16 ttlx; 446 __le32 dmacr; 447 __le16 dmcth; 448 u8 hptc; 449 u8 reserved; 450 __le32 pfltrc; 451}; 452 453I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 454 455/* Set ARP Proxy command / response (indirect 0x0104) */ 456struct i40e_aqc_arp_proxy_data { 457 __le16 command_flags; 458#define I40E_AQ_ARP_INIT_IPV4 0x0008 459#define I40E_AQ_ARP_UNSUP_CTL 0x0010 460#define I40E_AQ_ARP_ENA 0x0020 461#define I40E_AQ_ARP_ADD_IPV4 0x0040 462#define I40E_AQ_ARP_DEL_IPV4 0x0080 463 __le16 table_id; 464 __le32 pfpm_proxyfc; 465 __le32 ip_addr; 466 u8 mac_addr[6]; 467}; 468 469/* Set NS Proxy Table Entry Command (indirect 0x0105) */ 470struct i40e_aqc_ns_proxy_data { 471 __le16 table_idx_mac_addr_0; 472 __le16 table_idx_mac_addr_1; 473 __le16 table_idx_ipv6_0; 474 __le16 table_idx_ipv6_1; 475 __le16 control; 476#define I40E_AQ_NS_PROXY_ADD_0 0x0100 477#define I40E_AQ_NS_PROXY_DEL_0 0x0200 478#define I40E_AQ_NS_PROXY_ADD_1 0x0400 479#define I40E_AQ_NS_PROXY_DEL_1 0x0800 480#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 481#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 482#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 483#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 484#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 485#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 486#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 487 u8 mac_addr_0[6]; 488 u8 mac_addr_1[6]; 489 u8 local_mac_addr[6]; 490 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 491 u8 ipv6_addr_1[16]; 492}; 493 494/* Manage LAA Command (0x0106) - obsolete */ 495struct i40e_aqc_mng_laa { 496 __le16 command_flags; 497#define I40E_AQ_LAA_FLAG_WR 0x8000 498 u8 reserved[2]; 499 __le32 sal; 500 __le16 sah; 501 u8 reserved2[6]; 502}; 503 504/* Manage MAC Address Read Command (indirect 0x0107) */ 505struct i40e_aqc_mac_address_read { 506 __le16 command_flags; 507#define I40E_AQC_LAN_ADDR_VALID 0x10 508#define I40E_AQC_SAN_ADDR_VALID 0x20 509#define I40E_AQC_PORT_ADDR_VALID 0x40 510#define I40E_AQC_WOL_ADDR_VALID 0x80 511#define I40E_AQC_ADDR_VALID_MASK 0xf0 512 u8 reserved[6]; 513 __le32 addr_high; 514 __le32 addr_low; 515}; 516 517I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 518 519struct i40e_aqc_mac_address_read_data { 520 u8 pf_lan_mac[6]; 521 u8 pf_san_mac[6]; 522 u8 port_mac[6]; 523 u8 pf_wol_mac[6]; 524}; 525 526I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 527 528/* Manage MAC Address Write Command (0x0108) */ 529struct i40e_aqc_mac_address_write { 530 __le16 command_flags; 531#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 532#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 533#define I40E_AQC_WRITE_TYPE_PORT 0x8000 534#define I40E_AQC_WRITE_TYPE_MASK 0xc000 535 __le16 mac_sah; 536 __le32 mac_sal; 537 u8 reserved[8]; 538}; 539 540I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 541 542/* PXE commands (0x011x) */ 543 544/* Clear PXE Command and response (direct 0x0110) */ 545struct i40e_aqc_clear_pxe { 546 u8 rx_cnt; 547 u8 reserved[15]; 548}; 549 550I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 551 552/* Switch configuration commands (0x02xx) */ 553 554/* Used by many indirect commands that only pass an seid and a buffer in the 555 * command 556 */ 557struct i40e_aqc_switch_seid { 558 __le16 seid; 559 u8 reserved[6]; 560 __le32 addr_high; 561 __le32 addr_low; 562}; 563 564I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 565 566/* Get Switch Configuration command (indirect 0x0200) 567 * uses i40e_aqc_switch_seid for the descriptor 568 */ 569struct i40e_aqc_get_switch_config_header_resp { 570 __le16 num_reported; 571 __le16 num_total; 572 u8 reserved[12]; 573}; 574 575struct i40e_aqc_switch_config_element_resp { 576 u8 element_type; 577#define I40E_AQ_SW_ELEM_TYPE_MAC 1 578#define I40E_AQ_SW_ELEM_TYPE_PF 2 579#define I40E_AQ_SW_ELEM_TYPE_VF 3 580#define I40E_AQ_SW_ELEM_TYPE_EMP 4 581#define I40E_AQ_SW_ELEM_TYPE_BMC 5 582#define I40E_AQ_SW_ELEM_TYPE_PV 16 583#define I40E_AQ_SW_ELEM_TYPE_VEB 17 584#define I40E_AQ_SW_ELEM_TYPE_PA 18 585#define I40E_AQ_SW_ELEM_TYPE_VSI 19 586 u8 revision; 587#define I40E_AQ_SW_ELEM_REV_1 1 588 __le16 seid; 589 __le16 uplink_seid; 590 __le16 downlink_seid; 591 u8 reserved[3]; 592 u8 connection_type; 593#define I40E_AQ_CONN_TYPE_REGULAR 0x1 594#define I40E_AQ_CONN_TYPE_DEFAULT 0x2 595#define I40E_AQ_CONN_TYPE_CASCADED 0x3 596 __le16 scheduler_id; 597 __le16 element_info; 598}; 599 600/* Get Switch Configuration (indirect 0x0200) 601 * an array of elements are returned in the response buffer 602 * the first in the array is the header, remainder are elements 603 */ 604struct i40e_aqc_get_switch_config_resp { 605 struct i40e_aqc_get_switch_config_header_resp header; 606 struct i40e_aqc_switch_config_element_resp element[1]; 607}; 608 609/* Add Statistics (direct 0x0201) 610 * Remove Statistics (direct 0x0202) 611 */ 612struct i40e_aqc_add_remove_statistics { 613 __le16 seid; 614 __le16 vlan; 615 __le16 stat_index; 616 u8 reserved[10]; 617}; 618 619I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 620 621/* Set Port Parameters command (direct 0x0203) */ 622struct i40e_aqc_set_port_parameters { 623 __le16 command_flags; 624#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 625#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 626#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 627 __le16 bad_frame_vsi; 628 __le16 default_seid; /* reserved for command */ 629 u8 reserved[10]; 630}; 631 632I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 633 634/* Get Switch Resource Allocation (indirect 0x0204) */ 635struct i40e_aqc_get_switch_resource_alloc { 636 u8 num_entries; /* reserved for command */ 637 u8 reserved[7]; 638 __le32 addr_high; 639 __le32 addr_low; 640}; 641 642I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 643 644/* expect an array of these structs in the response buffer */ 645struct i40e_aqc_switch_resource_alloc_element_resp { 646 u8 resource_type; 647#define I40E_AQ_RESOURCE_TYPE_VEB 0x0 648#define I40E_AQ_RESOURCE_TYPE_VSI 0x1 649#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 650#define I40E_AQ_RESOURCE_TYPE_STAG 0x3 651#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 652#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 653#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 654#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 655#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 656#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 657#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 658#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 659#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 660#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 661#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 662#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 663#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 664#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 665#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 666 u8 reserved1; 667 __le16 guaranteed; 668 __le16 total; 669 __le16 used; 670 __le16 total_unalloced; 671 u8 reserved2[6]; 672}; 673 674/* Add VSI (indirect 0x0210) 675 * this indirect command uses struct i40e_aqc_vsi_properties_data 676 * as the indirect buffer (128 bytes) 677 * 678 * Update VSI (indirect 0x211) 679 * uses the same data structure as Add VSI 680 * 681 * Get VSI (indirect 0x0212) 682 * uses the same completion and data structure as Add VSI 683 */ 684struct i40e_aqc_add_get_update_vsi { 685 __le16 uplink_seid; 686 u8 connection_type; 687#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 688#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 689#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 690 u8 reserved1; 691 u8 vf_id; 692 u8 reserved2; 693 __le16 vsi_flags; 694#define I40E_AQ_VSI_TYPE_SHIFT 0x0 695#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 696#define I40E_AQ_VSI_TYPE_VF 0x0 697#define I40E_AQ_VSI_TYPE_VMDQ2 0x1 698#define I40E_AQ_VSI_TYPE_PF 0x2 699#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 700#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 701#ifdef FORTVILLE_A0_SUPPORT 702#define I40E_AQ_VSI_FLAG_CLOUD_VSI 0x8 703#endif 704 __le32 addr_high; 705 __le32 addr_low; 706}; 707 708I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 709 710struct i40e_aqc_add_get_update_vsi_completion { 711 __le16 seid; 712 __le16 vsi_number; 713 __le16 vsi_used; 714 __le16 vsi_free; 715 __le32 addr_high; 716 __le32 addr_low; 717}; 718 719I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 720 721struct i40e_aqc_vsi_properties_data { 722 /* first 96 byte are written by SW */ 723 __le16 valid_sections; 724#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 725#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 726#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 727#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 728#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 729#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 730#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 731#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 732#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 733#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 734 /* switch section */ 735 __le16 switch_id; /* 12bit id combined with flags below */ 736#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 737#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 738#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 739#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 740#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 741 u8 sw_reserved[2]; 742 /* security section */ 743 u8 sec_flags; 744#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 745#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 746#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 747 u8 sec_reserved; 748 /* VLAN section */ 749 __le16 pvid; /* VLANS include priority bits */ 750 __le16 fcoe_pvid; 751 u8 port_vlan_flags; 752#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 753#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 754 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 755#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 756#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 757#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 758#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 759#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 760#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 761 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 762#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 763#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 764#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 765#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 766 u8 pvlan_reserved[3]; 767 /* ingress egress up sections */ 768 __le32 ingress_table; /* bitmap, 3 bits per up */ 769#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 770#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 771 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 772#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 773#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 774 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 775#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 776#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 777 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 778#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 779#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 780 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 781#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 782#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 783 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 784#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 785#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 786 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 787#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 788#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 789 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 790#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 791#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 792 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 793 __le32 egress_table; /* same defines as for ingress table */ 794 /* cascaded PV section */ 795 __le16 cas_pv_tag; 796 u8 cas_pv_flags; 797#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 798#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 799 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 800#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 801#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 802#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 803#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 804#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 805#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 806 u8 cas_pv_reserved; 807 /* queue mapping section */ 808 __le16 mapping_flags; 809#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 810#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 811 __le16 queue_mapping[16]; 812#define I40E_AQ_VSI_QUEUE_SHIFT 0x0 813#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 814 __le16 tc_mapping[8]; 815#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 816#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 817 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 818#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 819#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 820 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 821 /* queueing option section */ 822 u8 queueing_opt_flags; 823#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 824#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 825 u8 queueing_opt_reserved[3]; 826 /* scheduler section */ 827 u8 up_enable_bits; 828 u8 sched_reserved; 829 /* outer up section */ 830 __le32 outer_up_table; /* same structure and defines as ingress table */ 831 u8 cmd_reserved[8]; 832 /* last 32 bytes are written by FW */ 833 __le16 qs_handle[8]; 834#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 835 __le16 stat_counter_idx; 836 __le16 sched_id; 837 u8 resp_reserved[12]; 838}; 839 840I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 841 842/* Add Port Virtualizer (direct 0x0220) 843 * also used for update PV (direct 0x0221) but only flags are used 844 * (IS_CTRL_PORT only works on add PV) 845 */ 846struct i40e_aqc_add_update_pv { 847 __le16 command_flags; 848#define I40E_AQC_PV_FLAG_PV_TYPE 0x1 849#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 850#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 851#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 852 __le16 uplink_seid; 853 __le16 connected_seid; 854 u8 reserved[10]; 855}; 856 857I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 858 859struct i40e_aqc_add_update_pv_completion { 860 /* reserved for update; for add also encodes error if rc == ENOSPC */ 861 __le16 pv_seid; 862#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 863#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 864#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 865#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 866 u8 reserved[14]; 867}; 868 869I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 870 871/* Get PV Params (direct 0x0222) 872 * uses i40e_aqc_switch_seid for the descriptor 873 */ 874 875struct i40e_aqc_get_pv_params_completion { 876 __le16 seid; 877 __le16 default_stag; 878 __le16 pv_flags; /* same flags as add_pv */ 879#define I40E_AQC_GET_PV_PV_TYPE 0x1 880#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 881#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 882 u8 reserved[8]; 883 __le16 default_port_seid; 884}; 885 886I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 887 888/* Add VEB (direct 0x0230) */ 889struct i40e_aqc_add_veb { 890 __le16 uplink_seid; 891 __le16 downlink_seid; 892 __le16 veb_flags; 893#define I40E_AQC_ADD_VEB_FLOATING 0x1 894#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 895#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 896 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 897#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 898#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 899#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 900 u8 enable_tcs; 901 u8 reserved[9]; 902}; 903 904I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 905 906struct i40e_aqc_add_veb_completion { 907 u8 reserved[6]; 908 __le16 switch_seid; 909 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 910 __le16 veb_seid; 911#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 912#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 913#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 914#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 915 __le16 statistic_index; 916 __le16 vebs_used; 917 __le16 vebs_free; 918}; 919 920I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 921 922/* Get VEB Parameters (direct 0x0232) 923 * uses i40e_aqc_switch_seid for the descriptor 924 */ 925struct i40e_aqc_get_veb_parameters_completion { 926 __le16 seid; 927 __le16 switch_id; 928 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 929 __le16 statistic_index; 930 __le16 vebs_used; 931 __le16 vebs_free; 932 u8 reserved[4]; 933}; 934 935I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 936 937/* Delete Element (direct 0x0243) 938 * uses the generic i40e_aqc_switch_seid 939 */ 940 941/* Add MAC-VLAN (indirect 0x0250) */ 942 943/* used for the command for most vlan commands */ 944struct i40e_aqc_macvlan { 945 __le16 num_addresses; 946 __le16 seid[3]; 947#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 948#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 949 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 950#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 951 __le32 addr_high; 952 __le32 addr_low; 953}; 954 955I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 956 957/* indirect data for command and response */ 958struct i40e_aqc_add_macvlan_element_data { 959 u8 mac_addr[6]; 960 __le16 vlan_tag; 961 __le16 flags; 962#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 963#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 964#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 965#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 966 __le16 queue_number; 967#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 968#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 969 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 970 /* response section */ 971 u8 match_method; 972#define I40E_AQC_MM_PERFECT_MATCH 0x01 973#define I40E_AQC_MM_HASH_MATCH 0x02 974#define I40E_AQC_MM_ERR_NO_RES 0xFF 975 u8 reserved1[3]; 976}; 977 978struct i40e_aqc_add_remove_macvlan_completion { 979 __le16 perfect_mac_used; 980 __le16 perfect_mac_free; 981 __le16 unicast_hash_free; 982 __le16 multicast_hash_free; 983 __le32 addr_high; 984 __le32 addr_low; 985}; 986 987I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 988 989/* Remove MAC-VLAN (indirect 0x0251) 990 * uses i40e_aqc_macvlan for the descriptor 991 * data points to an array of num_addresses of elements 992 */ 993 994struct i40e_aqc_remove_macvlan_element_data { 995 u8 mac_addr[6]; 996 __le16 vlan_tag; 997 u8 flags; 998#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 999#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1000#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1001#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1002 u8 reserved[3]; 1003 /* reply section */ 1004 u8 error_code; 1005#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1006#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1007 u8 reply_reserved[3]; 1008}; 1009 1010/* Add VLAN (indirect 0x0252) 1011 * Remove VLAN (indirect 0x0253) 1012 * use the generic i40e_aqc_macvlan for the command 1013 */ 1014struct i40e_aqc_add_remove_vlan_element_data { 1015 __le16 vlan_tag; 1016 u8 vlan_flags; 1017/* flags for add VLAN */ 1018#define I40E_AQC_ADD_VLAN_LOCAL 0x1 1019#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1020#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << \ 1021 I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1022#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1023#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1024#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1025#define I40E_AQC_VLAN_PTYPE_SHIFT 3 1026#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1027#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1028#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1029#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1030#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1031/* flags for remove VLAN */ 1032#define I40E_AQC_REMOVE_VLAN_ALL 0x1 1033 u8 reserved; 1034 u8 result; 1035/* flags for add VLAN */ 1036#define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1037#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1038#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1039/* flags for remove VLAN */ 1040#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1041#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1042 u8 reserved1[3]; 1043}; 1044 1045struct i40e_aqc_add_remove_vlan_completion { 1046 u8 reserved[4]; 1047 __le16 vlans_used; 1048 __le16 vlans_free; 1049 __le32 addr_high; 1050 __le32 addr_low; 1051}; 1052 1053/* Set VSI Promiscuous Modes (direct 0x0254) */ 1054struct i40e_aqc_set_vsi_promiscuous_modes { 1055 __le16 promiscuous_flags; 1056 __le16 valid_flags; 1057/* flags used for both fields above */ 1058#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1059#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1060#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1061#define I40E_AQC_SET_VSI_DEFAULT 0x08 1062#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1063 __le16 seid; 1064#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1065 __le16 vlan_tag; 1066#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1067 u8 reserved[8]; 1068}; 1069 1070I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1071 1072/* Add S/E-tag command (direct 0x0255) 1073 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1074 */ 1075struct i40e_aqc_add_tag { 1076 __le16 flags; 1077#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1078 __le16 seid; 1079#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1080#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1081 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1082 __le16 tag; 1083 __le16 queue_number; 1084 u8 reserved[8]; 1085}; 1086 1087I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1088 1089struct i40e_aqc_add_remove_tag_completion { 1090 u8 reserved[12]; 1091 __le16 tags_used; 1092 __le16 tags_free; 1093}; 1094 1095I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1096 1097/* Remove S/E-tag command (direct 0x0256) 1098 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1099 */ 1100struct i40e_aqc_remove_tag { 1101 __le16 seid; 1102#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1103#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1104 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1105 __le16 tag; 1106 u8 reserved[12]; 1107}; 1108 1109/* Add multicast E-Tag (direct 0x0257) 1110 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1111 * and no external data 1112 */ 1113struct i40e_aqc_add_remove_mcast_etag { 1114 __le16 pv_seid; 1115 __le16 etag; 1116 u8 num_unicast_etags; 1117 u8 reserved[3]; 1118 __le32 addr_high; /* address of array of 2-byte s-tags */ 1119 __le32 addr_low; 1120}; 1121 1122I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1123 1124struct i40e_aqc_add_remove_mcast_etag_completion { 1125 u8 reserved[4]; 1126 __le16 mcast_etags_used; 1127 __le16 mcast_etags_free; 1128 __le32 addr_high; 1129 __le32 addr_low; 1130 1131}; 1132 1133I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1134 1135/* Update S/E-Tag (direct 0x0259) */ 1136struct i40e_aqc_update_tag { 1137 __le16 seid; 1138#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1139#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1140 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1141 __le16 old_tag; 1142 __le16 new_tag; 1143 u8 reserved[10]; 1144}; 1145 1146I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1147 1148struct i40e_aqc_update_tag_completion { 1149 u8 reserved[12]; 1150 __le16 tags_used; 1151 __le16 tags_free; 1152}; 1153 1154I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1155 1156/* Add Control Packet filter (direct 0x025A) 1157 * Remove Control Packet filter (direct 0x025B) 1158 * uses the i40e_aqc_add_oveb_cloud, 1159 * and the generic direct completion structure 1160 */ 1161struct i40e_aqc_add_remove_control_packet_filter { 1162 u8 mac[6]; 1163 __le16 etype; 1164 __le16 flags; 1165#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1166#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1167#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1168#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1169#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1170 __le16 seid; 1171#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1172#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1173 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1174 __le16 queue; 1175 u8 reserved[2]; 1176}; 1177 1178I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1179 1180struct i40e_aqc_add_remove_control_packet_filter_completion { 1181 __le16 mac_etype_used; 1182 __le16 etype_used; 1183 __le16 mac_etype_free; 1184 __le16 etype_free; 1185 u8 reserved[8]; 1186}; 1187 1188I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1189 1190/* Add Cloud filters (indirect 0x025C) 1191 * Remove Cloud filters (indirect 0x025D) 1192 * uses the i40e_aqc_add_remove_cloud_filters, 1193 * and the generic indirect completion structure 1194 */ 1195struct i40e_aqc_add_remove_cloud_filters { 1196 u8 num_filters; 1197 u8 reserved; 1198 __le16 seid; 1199#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1200#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1201 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1202 u8 reserved2[4]; 1203 __le32 addr_high; 1204 __le32 addr_low; 1205}; 1206 1207I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1208 1209struct i40e_aqc_add_remove_cloud_filters_element_data { 1210 u8 outer_mac[6]; 1211 u8 inner_mac[6]; 1212 __le16 inner_vlan; 1213 union { 1214 struct { 1215 u8 reserved[12]; 1216 u8 data[4]; 1217 } v4; 1218 struct { 1219 u8 data[16]; 1220 } v6; 1221 } ipaddr; 1222 __le16 flags; 1223#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1224#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1225 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1226#ifdef FORTVILLE_A0_SUPPORT 1227#define I40E_AQC_ADD_CLOUD_FILTER_OIP_GRE 0x0002 1228#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_GRE 0x0004 1229#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_VNL 0x0007 1230#endif 1231/* 0x0000 reserved */ 1232#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1233/* 0x0002 reserved */ 1234#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1235#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1236/* 0x0005 reserved */ 1237#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1238/* 0x0007 reserved */ 1239/* 0x0008 reserved */ 1240#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1241#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1242#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1243#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1244 1245#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1246#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1247#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1248#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1249#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1250 1251#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1252#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1253#define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0 1254#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1255#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2 1256#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1257 1258 __le32 tenant_id; 1259 u8 reserved[4]; 1260 __le16 queue_number; 1261#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1262#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x3F << \ 1263 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1264 u8 reserved2[14]; 1265 /* response section */ 1266 u8 allocation_result; 1267#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1268#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1269 u8 response_reserved[7]; 1270}; 1271 1272struct i40e_aqc_remove_cloud_filters_completion { 1273 __le16 perfect_ovlan_used; 1274 __le16 perfect_ovlan_free; 1275 __le16 vlan_used; 1276 __le16 vlan_free; 1277 __le32 addr_high; 1278 __le32 addr_low; 1279}; 1280 1281I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1282 1283/* Add Mirror Rule (indirect or direct 0x0260) 1284 * Delete Mirror Rule (indirect or direct 0x0261) 1285 * note: some rule types (4,5) do not use an external buffer. 1286 * take care to set the flags correctly. 1287 */ 1288struct i40e_aqc_add_delete_mirror_rule { 1289 __le16 seid; 1290 __le16 rule_type; 1291#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1292#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1293 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1294#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1295#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1296#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1297#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1298#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1299 __le16 num_entries; 1300 __le16 destination; /* VSI for add, rule id for delete */ 1301 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1302 __le32 addr_low; 1303}; 1304 1305I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1306 1307struct i40e_aqc_add_delete_mirror_rule_completion { 1308 u8 reserved[2]; 1309 __le16 rule_id; /* only used on add */ 1310 __le16 mirror_rules_used; 1311 __le16 mirror_rules_free; 1312 __le32 addr_high; 1313 __le32 addr_low; 1314}; 1315 1316I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1317 1318/* DCB 0x03xx*/ 1319 1320/* PFC Ignore (direct 0x0301) 1321 * the command and response use the same descriptor structure 1322 */ 1323struct i40e_aqc_pfc_ignore { 1324 u8 tc_bitmap; 1325 u8 command_flags; /* unused on response */ 1326#define I40E_AQC_PFC_IGNORE_SET 0x80 1327#define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1328 u8 reserved[14]; 1329}; 1330 1331I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1332 1333/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1334 * with no parameters 1335 */ 1336 1337/* TX scheduler 0x04xx */ 1338 1339/* Almost all the indirect commands use 1340 * this generic struct to pass the SEID in param0 1341 */ 1342struct i40e_aqc_tx_sched_ind { 1343 __le16 vsi_seid; 1344 u8 reserved[6]; 1345 __le32 addr_high; 1346 __le32 addr_low; 1347}; 1348 1349I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1350 1351/* Several commands respond with a set of queue set handles */ 1352struct i40e_aqc_qs_handles_resp { 1353 __le16 qs_handles[8]; 1354}; 1355 1356/* Configure VSI BW limits (direct 0x0400) */ 1357struct i40e_aqc_configure_vsi_bw_limit { 1358 __le16 vsi_seid; 1359 u8 reserved[2]; 1360 __le16 credit; 1361 u8 reserved1[2]; 1362 u8 max_credit; /* 0-3, limit = 2^max */ 1363 u8 reserved2[7]; 1364}; 1365 1366I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1367 1368/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1369 * responds with i40e_aqc_qs_handles_resp 1370 */ 1371struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1372 u8 tc_valid_bits; 1373 u8 reserved[15]; 1374 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1375 1376 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1377 __le16 tc_bw_max[2]; 1378 u8 reserved1[28]; 1379}; 1380 1381/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1382 * responds with i40e_aqc_qs_handles_resp 1383 */ 1384struct i40e_aqc_configure_vsi_tc_bw_data { 1385 u8 tc_valid_bits; 1386 u8 reserved[3]; 1387 u8 tc_bw_credits[8]; 1388 u8 reserved1[4]; 1389 __le16 qs_handles[8]; 1390}; 1391 1392/* Query vsi bw configuration (indirect 0x0408) */ 1393struct i40e_aqc_query_vsi_bw_config_resp { 1394 u8 tc_valid_bits; 1395 u8 tc_suspended_bits; 1396 u8 reserved[14]; 1397 __le16 qs_handles[8]; 1398 u8 reserved1[4]; 1399 __le16 port_bw_limit; 1400 u8 reserved2[2]; 1401 u8 max_bw; /* 0-3, limit = 2^max */ 1402 u8 reserved3[23]; 1403}; 1404 1405/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1406struct i40e_aqc_query_vsi_ets_sla_config_resp { 1407 u8 tc_valid_bits; 1408 u8 reserved[3]; 1409 u8 share_credits[8]; 1410 __le16 credits[8]; 1411 1412 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1413 __le16 tc_bw_max[2]; 1414}; 1415 1416/* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1417struct i40e_aqc_configure_switching_comp_bw_limit { 1418 __le16 seid; 1419 u8 reserved[2]; 1420 __le16 credit; 1421 u8 reserved1[2]; 1422 u8 max_bw; /* 0-3, limit = 2^max */ 1423 u8 reserved2[7]; 1424}; 1425 1426I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1427 1428/* Enable Physical Port ETS (indirect 0x0413) 1429 * Modify Physical Port ETS (indirect 0x0414) 1430 * Disable Physical Port ETS (indirect 0x0415) 1431 */ 1432struct i40e_aqc_configure_switching_comp_ets_data { 1433 u8 reserved[4]; 1434 u8 tc_valid_bits; 1435 u8 seepage; 1436#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1437 u8 tc_strict_priority_flags; 1438 u8 reserved1[17]; 1439 u8 tc_bw_share_credits[8]; 1440 u8 reserved2[96]; 1441}; 1442 1443/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1444struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1445 u8 tc_valid_bits; 1446 u8 reserved[15]; 1447 __le16 tc_bw_credit[8]; 1448 1449 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1450 __le16 tc_bw_max[2]; 1451 u8 reserved1[28]; 1452}; 1453 1454/* Configure Switching Component Bandwidth Allocation per Tc 1455 * (indirect 0x0417) 1456 */ 1457struct i40e_aqc_configure_switching_comp_bw_config_data { 1458 u8 tc_valid_bits; 1459 u8 reserved[2]; 1460 u8 absolute_credits; /* bool */ 1461 u8 tc_bw_share_credits[8]; 1462 u8 reserved1[20]; 1463}; 1464 1465/* Query Switching Component Configuration (indirect 0x0418) */ 1466struct i40e_aqc_query_switching_comp_ets_config_resp { 1467 u8 tc_valid_bits; 1468 u8 reserved[35]; 1469 __le16 port_bw_limit; 1470 u8 reserved1[2]; 1471 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1472 u8 reserved2[23]; 1473}; 1474 1475/* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1476struct i40e_aqc_query_port_ets_config_resp { 1477 u8 reserved[4]; 1478 u8 tc_valid_bits; 1479 u8 reserved1; 1480 u8 tc_strict_priority_bits; 1481 u8 reserved2; 1482 u8 tc_bw_share_credits[8]; 1483 __le16 tc_bw_limits[8]; 1484 1485 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1486 __le16 tc_bw_max[2]; 1487 u8 reserved3[32]; 1488}; 1489 1490/* Query Switching Component Bandwidth Allocation per Traffic Type 1491 * (indirect 0x041A) 1492 */ 1493struct i40e_aqc_query_switching_comp_bw_config_resp { 1494 u8 tc_valid_bits; 1495 u8 reserved[2]; 1496 u8 absolute_credits_enable; /* bool */ 1497 u8 tc_bw_share_credits[8]; 1498 __le16 tc_bw_limits[8]; 1499 1500 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1501 __le16 tc_bw_max[2]; 1502}; 1503 1504/* Suspend/resume port TX traffic 1505 * (direct 0x041B and 0x041C) uses the generic SEID struct 1506 */ 1507 1508/* Configure partition BW 1509 * (indirect 0x041D) 1510 */ 1511struct i40e_aqc_configure_partition_bw_data { 1512 __le16 pf_valid_bits; 1513 u8 min_bw[16]; /* guaranteed bandwidth */ 1514 u8 max_bw[16]; /* bandwidth limit */ 1515}; 1516 1517/* Get and set the active HMC resource profile and status. 1518 * (direct 0x0500) and (direct 0x0501) 1519 */ 1520struct i40e_aq_get_set_hmc_resource_profile { 1521 u8 pm_profile; 1522 u8 pe_vf_enabled; 1523 u8 reserved[14]; 1524}; 1525 1526I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1527 1528enum i40e_aq_hmc_profile { 1529 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1530 I40E_HMC_PROFILE_DEFAULT = 1, 1531 I40E_HMC_PROFILE_FAVOR_VF = 2, 1532 I40E_HMC_PROFILE_EQUAL = 3, 1533}; 1534 1535#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF 1536#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F 1537 1538/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1539 1540/* set in param0 for get phy abilities to report qualified modules */ 1541#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1542#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1543 1544enum i40e_aq_phy_type { 1545 I40E_PHY_TYPE_SGMII = 0x0, 1546 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1547 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1548 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1549 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1550 I40E_PHY_TYPE_XAUI = 0x5, 1551 I40E_PHY_TYPE_XFI = 0x6, 1552 I40E_PHY_TYPE_SFI = 0x7, 1553 I40E_PHY_TYPE_XLAUI = 0x8, 1554 I40E_PHY_TYPE_XLPPI = 0x9, 1555 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1556 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1557 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1558 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1559 I40E_PHY_TYPE_100BASE_TX = 0x11, 1560 I40E_PHY_TYPE_1000BASE_T = 0x12, 1561 I40E_PHY_TYPE_10GBASE_T = 0x13, 1562 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1563 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1564 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1565 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1566 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1567 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1568 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1569 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1570 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1571 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1572 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1573 I40E_PHY_TYPE_MAX 1574}; 1575 1576#define I40E_LINK_SPEED_100MB_SHIFT 0x1 1577#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1578#define I40E_LINK_SPEED_10GB_SHIFT 0x3 1579#define I40E_LINK_SPEED_40GB_SHIFT 0x4 1580#define I40E_LINK_SPEED_20GB_SHIFT 0x5 1581 1582enum i40e_aq_link_speed { 1583 I40E_LINK_SPEED_UNKNOWN = 0, 1584 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1585 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1586 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1587 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1588 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) 1589}; 1590 1591struct i40e_aqc_module_desc { 1592 u8 oui[3]; 1593 u8 reserved1; 1594 u8 part_number[16]; 1595 u8 revision[4]; 1596 u8 reserved2[8]; 1597}; 1598 1599struct i40e_aq_get_phy_abilities_resp { 1600 __le32 phy_type; /* bitmap using the above enum for offsets */ 1601 u8 link_speed; /* bitmap using the above enum bit patterns */ 1602 u8 abilities; 1603#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1604#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1605#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1606#define I40E_AQ_PHY_LINK_ENABLED 0x08 1607#define I40E_AQ_PHY_AN_ENABLED 0x10 1608#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1609 __le16 eee_capability; 1610#define I40E_AQ_EEE_100BASE_TX 0x0002 1611#define I40E_AQ_EEE_1000BASE_T 0x0004 1612#define I40E_AQ_EEE_10GBASE_T 0x0008 1613#define I40E_AQ_EEE_1000BASE_KX 0x0010 1614#define I40E_AQ_EEE_10GBASE_KX4 0x0020 1615#define I40E_AQ_EEE_10GBASE_KR 0x0040 1616 __le32 eeer_val; 1617 u8 d3_lpan; 1618#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1619 u8 reserved[3]; 1620 u8 phy_id[4]; 1621 u8 module_type[3]; 1622 u8 qualified_module_count; 1623#define I40E_AQ_PHY_MAX_QMS 16 1624 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1625}; 1626 1627/* Set PHY Config (direct 0x0601) */ 1628struct i40e_aq_set_phy_config { /* same bits as above in all */ 1629 __le32 phy_type; 1630 u8 link_speed; 1631 u8 abilities; 1632/* bits 0-2 use the values from get_phy_abilities_resp */ 1633#define I40E_AQ_PHY_ENABLE_LINK 0x08 1634#define I40E_AQ_PHY_ENABLE_AN 0x10 1635#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1636 __le16 eee_capability; 1637 __le32 eeer; 1638 u8 low_power_ctrl; 1639 u8 reserved[3]; 1640}; 1641 1642I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1643 1644/* Set MAC Config command data structure (direct 0x0603) */ 1645struct i40e_aq_set_mac_config { 1646 __le16 max_frame_size; 1647 u8 params; 1648#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1649#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1650#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1651#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1652#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1653#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1654#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1655#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1656#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1657#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1658#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1659#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1660#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1661#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1662 u8 tx_timer_priority; /* bitmap */ 1663 __le16 tx_timer_value; 1664 __le16 fc_refresh_threshold; 1665 u8 reserved[8]; 1666}; 1667 1668I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1669 1670/* Restart Auto-Negotiation (direct 0x605) */ 1671struct i40e_aqc_set_link_restart_an { 1672 u8 command; 1673#define I40E_AQ_PHY_RESTART_AN 0x02 1674#define I40E_AQ_PHY_LINK_ENABLE 0x04 1675 u8 reserved[15]; 1676}; 1677 1678I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1679 1680/* Get Link Status cmd & response data structure (direct 0x0607) */ 1681struct i40e_aqc_get_link_status { 1682 __le16 command_flags; /* only field set on command */ 1683#define I40E_AQ_LSE_MASK 0x3 1684#define I40E_AQ_LSE_NOP 0x0 1685#define I40E_AQ_LSE_DISABLE 0x2 1686#define I40E_AQ_LSE_ENABLE 0x3 1687/* only response uses this flag */ 1688#define I40E_AQ_LSE_IS_ENABLED 0x1 1689 u8 phy_type; /* i40e_aq_phy_type */ 1690 u8 link_speed; /* i40e_aq_link_speed */ 1691 u8 link_info; 1692#define I40E_AQ_LINK_UP 0x01 1693#define I40E_AQ_LINK_FAULT 0x02 1694#define I40E_AQ_LINK_FAULT_TX 0x04 1695#define I40E_AQ_LINK_FAULT_RX 0x08 1696#define I40E_AQ_LINK_FAULT_REMOTE 0x10 1697#define I40E_AQ_MEDIA_AVAILABLE 0x40 1698#define I40E_AQ_SIGNAL_DETECT 0x80 1699 u8 an_info; 1700#define I40E_AQ_AN_COMPLETED 0x01 1701#define I40E_AQ_LP_AN_ABILITY 0x02 1702#define I40E_AQ_PD_FAULT 0x04 1703#define I40E_AQ_FEC_EN 0x08 1704#define I40E_AQ_PHY_LOW_POWER 0x10 1705#define I40E_AQ_LINK_PAUSE_TX 0x20 1706#define I40E_AQ_LINK_PAUSE_RX 0x40 1707#define I40E_AQ_QUALIFIED_MODULE 0x80 1708 u8 ext_info; 1709#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1710#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1711#define I40E_AQ_LINK_TX_SHIFT 0x02 1712#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1713#define I40E_AQ_LINK_TX_ACTIVE 0x00 1714#define I40E_AQ_LINK_TX_DRAINED 0x01 1715#define I40E_AQ_LINK_TX_FLUSHED 0x03 1716#define I40E_AQ_LINK_FORCED_40G 0x10 1717 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1718 __le16 max_frame_size; 1719 u8 config; 1720#define I40E_AQ_CONFIG_CRC_ENA 0x04 1721#define I40E_AQ_CONFIG_PACING_MASK 0x78 1722 u8 reserved[5]; 1723}; 1724 1725I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1726 1727/* Set event mask command (direct 0x613) */ 1728struct i40e_aqc_set_phy_int_mask { 1729 u8 reserved[8]; 1730 __le16 event_mask; 1731#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1732#define I40E_AQ_EVENT_MEDIA_NA 0x0004 1733#define I40E_AQ_EVENT_LINK_FAULT 0x0008 1734#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1735#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1736#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1737#define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1738#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1739#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1740 u8 reserved1[6]; 1741}; 1742 1743I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1744 1745/* Get Local AN advt register (direct 0x0614) 1746 * Set Local AN advt register (direct 0x0615) 1747 * Get Link Partner AN advt register (direct 0x0616) 1748 */ 1749struct i40e_aqc_an_advt_reg { 1750 __le32 local_an_reg0; 1751 __le16 local_an_reg1; 1752 u8 reserved[10]; 1753}; 1754 1755I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1756 1757/* Set Loopback mode (0x0618) */ 1758struct i40e_aqc_set_lb_mode { 1759 __le16 lb_mode; 1760#define I40E_AQ_LB_PHY_LOCAL 0x01 1761#define I40E_AQ_LB_PHY_REMOTE 0x02 1762#define I40E_AQ_LB_MAC_LOCAL 0x04 1763 u8 reserved[14]; 1764}; 1765 1766I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1767 1768/* Set PHY Debug command (0x0622) */ 1769struct i40e_aqc_set_phy_debug { 1770 u8 command_flags; 1771#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1772#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1773#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1774#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1775#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1776#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1777#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1778 u8 reserved[15]; 1779}; 1780 1781I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1782 1783enum i40e_aq_phy_reg_type { 1784 I40E_AQC_PHY_REG_INTERNAL = 0x1, 1785 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1786 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1787}; 1788 1789/* NVM Read command (indirect 0x0701) 1790 * NVM Erase commands (direct 0x0702) 1791 * NVM Update commands (indirect 0x0703) 1792 */ 1793struct i40e_aqc_nvm_update { 1794 u8 command_flags; 1795#define I40E_AQ_NVM_LAST_CMD 0x01 1796#define I40E_AQ_NVM_FLASH_ONLY 0x80 1797 u8 module_pointer; 1798 __le16 length; 1799 __le32 offset; 1800 __le32 addr_high; 1801 __le32 addr_low; 1802}; 1803 1804I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 1805 1806/* NVM Config Read (indirect 0x0704) */ 1807struct i40e_aqc_nvm_config_read { 1808 __le16 cmd_flags; 1809#define ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 1810#define ANVM_READ_SINGLE_FEATURE 0 1811#define ANVM_READ_MULTIPLE_FEATURES 1 1812 __le16 element_count; 1813 __le16 element_id; /* Feature/field ID */ 1814 u8 reserved[2]; 1815 __le32 address_high; 1816 __le32 address_low; 1817}; 1818 1819I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 1820 1821/* NVM Config Write (indirect 0x0705) */ 1822struct i40e_aqc_nvm_config_write { 1823 __le16 cmd_flags; 1824 __le16 element_count; 1825 u8 reserved[4]; 1826 __le32 address_high; 1827 __le32 address_low; 1828}; 1829 1830I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 1831 1832struct i40e_aqc_nvm_config_data_feature { 1833 __le16 feature_id; 1834 __le16 instance_id; 1835 __le16 feature_options; 1836 __le16 feature_selection; 1837}; 1838 1839struct i40e_aqc_nvm_config_data_immediate_field { 1840#define ANVM_FEATURE_OR_IMMEDIATE_MASK 0x2 1841 __le16 field_id; 1842 __le16 instance_id; 1843 __le16 field_options; 1844 __le16 field_value; 1845}; 1846 1847/* Send to PF command (indirect 0x0801) id is only used by PF 1848 * Send to VF command (indirect 0x0802) id is only used by PF 1849 * Send to Peer PF command (indirect 0x0803) 1850 */ 1851struct i40e_aqc_pf_vf_message { 1852 __le32 id; 1853 u8 reserved[4]; 1854 __le32 addr_high; 1855 __le32 addr_low; 1856}; 1857 1858I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 1859 1860/* Alternate structure */ 1861 1862/* Direct write (direct 0x0900) 1863 * Direct read (direct 0x0902) 1864 */ 1865struct i40e_aqc_alternate_write { 1866 __le32 address0; 1867 __le32 data0; 1868 __le32 address1; 1869 __le32 data1; 1870}; 1871 1872I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 1873 1874/* Indirect write (indirect 0x0901) 1875 * Indirect read (indirect 0x0903) 1876 */ 1877 1878struct i40e_aqc_alternate_ind_write { 1879 __le32 address; 1880 __le32 length; 1881 __le32 addr_high; 1882 __le32 addr_low; 1883}; 1884 1885I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 1886 1887/* Done alternate write (direct 0x0904) 1888 * uses i40e_aq_desc 1889 */ 1890struct i40e_aqc_alternate_write_done { 1891 __le16 cmd_flags; 1892#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 1893#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 1894#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 1895#define I40E_AQ_ALTERNATE_RESET_NEEDED 2 1896 u8 reserved[14]; 1897}; 1898 1899I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 1900 1901/* Set OEM mode (direct 0x0905) */ 1902struct i40e_aqc_alternate_set_mode { 1903 __le32 mode; 1904#define I40E_AQ_ALTERNATE_MODE_NONE 0 1905#define I40E_AQ_ALTERNATE_MODE_OEM 1 1906 u8 reserved[12]; 1907}; 1908 1909I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 1910 1911/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 1912 1913/* async events 0x10xx */ 1914 1915/* Lan Queue Overflow Event (direct, 0x1001) */ 1916struct i40e_aqc_lan_overflow { 1917 __le32 prtdcb_rupto; 1918 __le32 otx_ctl; 1919 u8 reserved[8]; 1920}; 1921 1922I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 1923 1924/* Get LLDP MIB (indirect 0x0A00) */ 1925struct i40e_aqc_lldp_get_mib { 1926 u8 type; 1927 u8 reserved1; 1928#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 1929#define I40E_AQ_LLDP_MIB_LOCAL 0x0 1930#define I40E_AQ_LLDP_MIB_REMOTE 0x1 1931#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 1932#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 1933#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 1934#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 1935#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 1936#define I40E_AQ_LLDP_TX_SHIFT 0x4 1937#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 1938/* TX pause flags use I40E_AQ_LINK_TX_* above */ 1939 __le16 local_len; 1940 __le16 remote_len; 1941 u8 reserved2[2]; 1942 __le32 addr_high; 1943 __le32 addr_low; 1944}; 1945 1946I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 1947 1948/* Configure LLDP MIB Change Event (direct 0x0A01) 1949 * also used for the event (with type in the command field) 1950 */ 1951struct i40e_aqc_lldp_update_mib { 1952 u8 command; 1953#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1954#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 1955 u8 reserved[7]; 1956 __le32 addr_high; 1957 __le32 addr_low; 1958}; 1959 1960I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 1961 1962/* Add LLDP TLV (indirect 0x0A02) 1963 * Delete LLDP TLV (indirect 0x0A04) 1964 */ 1965struct i40e_aqc_lldp_add_tlv { 1966 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1967 u8 reserved1[1]; 1968 __le16 len; 1969 u8 reserved2[4]; 1970 __le32 addr_high; 1971 __le32 addr_low; 1972}; 1973 1974I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 1975 1976/* Update LLDP TLV (indirect 0x0A03) */ 1977struct i40e_aqc_lldp_update_tlv { 1978 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1979 u8 reserved; 1980 __le16 old_len; 1981 __le16 new_offset; 1982 __le16 new_len; 1983 __le32 addr_high; 1984 __le32 addr_low; 1985}; 1986 1987I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 1988 1989/* Stop LLDP (direct 0x0A05) */ 1990struct i40e_aqc_lldp_stop { 1991 u8 command; 1992#define I40E_AQ_LLDP_AGENT_STOP 0x0 1993#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 1994 u8 reserved[15]; 1995}; 1996 1997I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 1998 1999/* Start LLDP (direct 0x0A06) */ 2000 2001struct i40e_aqc_lldp_start { 2002 u8 command; 2003#define I40E_AQ_LLDP_AGENT_START 0x1 2004 u8 reserved[15]; 2005}; 2006 2007I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2008 2009/* Apply MIB changes (0x0A07) 2010 * uses the generic struc as it contains no data 2011 */ 2012 2013/* Add Udp Tunnel command and completion (direct 0x0B00) */ 2014struct i40e_aqc_add_udp_tunnel { 2015#ifdef FORTVILLE_A0_SUPPORT 2016 __le16 udp_port; 2017 u8 header_len; /* in DWords, 1 to 15 */ 2018 u8 protocol_type; 2019#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x0 2020#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x2 2021#define I40E_AQC_TUNNEL_TYPE_NGE 0x3 2022 u8 variable_udp_length; 2023#define I40E_AQC_TUNNEL_FIXED_UDP_LENGTH 0x0 2024#define I40E_AQC_TUNNEL_VARIABLE_UDP_LENGTH 0x1 2025 u8 udp_key_index; 2026#define I40E_AQC_TUNNEL_KEY_INDEX_VXLAN 0x0 2027#define I40E_AQC_TUNNEL_KEY_INDEX_NGE 0x1 2028#define I40E_AQC_TUNNEL_KEY_INDEX_PROPRIETARY_UDP 0x2 2029 u8 reserved[10]; 2030#else 2031 __le16 udp_port; 2032 u8 reserved0[3]; 2033 u8 protocol_type; 2034#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2035#define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2036#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2037 u8 reserved1[10]; 2038#endif 2039}; 2040 2041I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2042 2043struct i40e_aqc_add_udp_tunnel_completion { 2044 __le16 udp_port; 2045 u8 filter_entry_index; 2046 u8 multiple_pfs; 2047#define I40E_AQC_SINGLE_PF 0x0 2048#define I40E_AQC_MULTIPLE_PFS 0x1 2049 u8 total_filters; 2050 u8 reserved[11]; 2051}; 2052 2053I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2054 2055/* remove UDP Tunnel command (0x0B01) */ 2056struct i40e_aqc_remove_udp_tunnel { 2057 u8 reserved[2]; 2058 u8 index; /* 0 to 15 */ 2059#ifdef FORTVILLE_A0_SUPPORT 2060 u8 pf_filters; 2061 u8 total_filters; 2062 u8 reserved2[11]; 2063#else 2064 u8 reserved2[13]; 2065#endif 2066}; 2067 2068I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2069 2070struct i40e_aqc_del_udp_tunnel_completion { 2071 __le16 udp_port; 2072 u8 index; /* 0 to 15 */ 2073 u8 multiple_pfs; 2074 u8 total_filters_used; 2075#ifdef FORTVILLE_A0_SUPPORT 2076 u8 reserved; 2077 u8 tunnels_free; 2078 u8 reserved1[9]; 2079#else 2080 u8 reserved1[11]; 2081#endif 2082}; 2083 2084I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2085 2086/* tunnel key structure 0x0B10 */ 2087 2088#ifdef FORTVILLE_A0_SUPPORT 2089struct i40e_aqc_tunnel_key_structure_A0 { 2090 __le16 key1_off; 2091 __le16 key1_len; 2092 __le16 key2_off; 2093 __le16 key2_len; 2094 __le16 flags; 2095#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2096/* response flags */ 2097#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2098#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2099#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2100 u8 resreved[6]; 2101}; 2102 2103I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure_A0); 2104 2105#endif 2106struct i40e_aqc_tunnel_key_structure { 2107 u8 key1_off; 2108 u8 key2_off; 2109 u8 key1_len; /* 0 to 15 */ 2110 u8 key2_len; /* 0 to 15 */ 2111 u8 flags; 2112#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2113/* response flags */ 2114#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2115#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2116#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2117 u8 network_key_index; 2118#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2119#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2120#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2121#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2122 u8 reserved[10]; 2123}; 2124 2125I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2126 2127/* OEM mode commands (direct 0xFE0x) */ 2128struct i40e_aqc_oem_param_change { 2129 __le32 param_type; 2130#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2131#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2132#define I40E_AQ_OEM_PARAM_MAC 2 2133 __le32 param_value1; 2134 u8 param_value2[8]; 2135}; 2136 2137I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2138 2139struct i40e_aqc_oem_state_change { 2140 __le32 state; 2141#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2142#define I40E_AQ_OEM_STATE_LINK_UP 0x1 2143 u8 reserved[12]; 2144}; 2145 2146I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2147 2148/* debug commands */ 2149 2150/* get device id (0xFF00) uses the generic structure */ 2151 2152/* set test more (0xFF01, internal) */ 2153 2154struct i40e_acq_set_test_mode { 2155 u8 mode; 2156#define I40E_AQ_TEST_PARTIAL 0 2157#define I40E_AQ_TEST_FULL 1 2158#define I40E_AQ_TEST_NVM 2 2159 u8 reserved[3]; 2160 u8 command; 2161#define I40E_AQ_TEST_OPEN 0 2162#define I40E_AQ_TEST_CLOSE 1 2163#define I40E_AQ_TEST_INC 2 2164 u8 reserved2[3]; 2165 __le32 address_high; 2166 __le32 address_low; 2167}; 2168 2169I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2170 2171/* Debug Read Register command (0xFF03) 2172 * Debug Write Register command (0xFF04) 2173 */ 2174struct i40e_aqc_debug_reg_read_write { 2175 __le32 reserved; 2176 __le32 address; 2177 __le32 value_high; 2178 __le32 value_low; 2179}; 2180 2181I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2182 2183/* Scatter/gather Reg Read (indirect 0xFF05) 2184 * Scatter/gather Reg Write (indirect 0xFF06) 2185 */ 2186 2187/* i40e_aq_desc is used for the command */ 2188struct i40e_aqc_debug_reg_sg_element_data { 2189 __le32 address; 2190 __le32 value; 2191}; 2192 2193/* Debug Modify register (direct 0xFF07) */ 2194struct i40e_aqc_debug_modify_reg { 2195 __le32 address; 2196 __le32 value; 2197 __le32 clear_mask; 2198 __le32 set_mask; 2199}; 2200 2201I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2202 2203/* dump internal data (0xFF08, indirect) */ 2204 2205#define I40E_AQ_CLUSTER_ID_AUX 0 2206#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2207#define I40E_AQ_CLUSTER_ID_TXSCHED 2 2208#define I40E_AQ_CLUSTER_ID_HMC 3 2209#define I40E_AQ_CLUSTER_ID_MAC0 4 2210#define I40E_AQ_CLUSTER_ID_MAC1 5 2211#define I40E_AQ_CLUSTER_ID_MAC2 6 2212#define I40E_AQ_CLUSTER_ID_MAC3 7 2213#define I40E_AQ_CLUSTER_ID_DCB 8 2214#define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2215#define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2216#define I40E_AQ_CLUSTER_ID_ALTRAM 11 2217 2218struct i40e_aqc_debug_dump_internals { 2219 u8 cluster_id; 2220 u8 table_id; 2221 __le16 data_size; 2222 __le32 idx; 2223 __le32 address_high; 2224 __le32 address_low; 2225}; 2226 2227I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2228 2229struct i40e_aqc_debug_modify_internals { 2230 u8 cluster_id; 2231 u8 cluster_specific_params[7]; 2232 __le32 address_high; 2233 __le32 address_low; 2234}; 2235 2236I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2237 2238#endif 2239