1266423Sjfv/****************************************************************************** 2266423Sjfv 3349163Serj Copyright (c) 2013-2019, Intel Corporation 4266423Sjfv All rights reserved. 5349163Serj 6266423Sjfv Redistribution and use in source and binary forms, with or without 7266423Sjfv modification, are permitted provided that the following conditions are met: 8266423Sjfv 9266423Sjfv 1. Redistributions of source code must retain the above copyright notice, 10266423Sjfv this list of conditions and the following disclaimer. 11266423Sjfv 12266423Sjfv 2. Redistributions in binary form must reproduce the above copyright 13266423Sjfv notice, this list of conditions and the following disclaimer in the 14266423Sjfv documentation and/or other materials provided with the distribution. 15266423Sjfv 16266423Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17266423Sjfv contributors may be used to endorse or promote products derived from 18266423Sjfv this software without specific prior written permission. 19266423Sjfv 20266423Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21266423Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22266423Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23266423Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24266423Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25266423Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26266423Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27266423Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28266423Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29266423Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30266423Sjfv POSSIBILITY OF SUCH DAMAGE. 31266423Sjfv 32266423Sjfv******************************************************************************/ 33266423Sjfv/*$FreeBSD: stable/11/sys/dev/ixl/i40e_adminq_cmd.h 349163 2019-06-18 00:08:02Z erj $*/ 34266423Sjfv 35266423Sjfv#ifndef _I40E_ADMINQ_CMD_H_ 36266423Sjfv#define _I40E_ADMINQ_CMD_H_ 37266423Sjfv 38266423Sjfv/* This header file defines the i40e Admin Queue commands and is shared between 39266423Sjfv * i40e Firmware and Software. 40266423Sjfv * 41266423Sjfv * This file needs to comply with the Linux Kernel coding style. 42266423Sjfv */ 43266423Sjfv 44333343Serj 45270346Sjfv#define I40E_FW_API_VERSION_MAJOR 0x0001 46349163Serj#define I40E_FW_API_VERSION_MINOR_X722 0x0008 47349163Serj#define I40E_FW_API_VERSION_MINOR_X710 0x0008 48266423Sjfv 49333343Serj#define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \ 50333343Serj I40E_FW_API_VERSION_MINOR_X710 : \ 51333343Serj I40E_FW_API_VERSION_MINOR_X722) 52333343Serj 53333343Serj/* API version 1.7 implements additional link and PHY-specific APIs */ 54333343Serj#define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007 55349163Serj/* API version 1.6 for X722 devices adds ability to stop FW LLDP agent */ 56349163Serj#define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006 57333343Serj 58266423Sjfvstruct i40e_aq_desc { 59266423Sjfv __le16 flags; 60266423Sjfv __le16 opcode; 61266423Sjfv __le16 datalen; 62266423Sjfv __le16 retval; 63266423Sjfv __le32 cookie_high; 64266423Sjfv __le32 cookie_low; 65266423Sjfv union { 66266423Sjfv struct { 67266423Sjfv __le32 param0; 68266423Sjfv __le32 param1; 69266423Sjfv __le32 param2; 70266423Sjfv __le32 param3; 71266423Sjfv } internal; 72266423Sjfv struct { 73266423Sjfv __le32 param0; 74266423Sjfv __le32 param1; 75266423Sjfv __le32 addr_high; 76266423Sjfv __le32 addr_low; 77266423Sjfv } external; 78266423Sjfv u8 raw[16]; 79266423Sjfv } params; 80266423Sjfv}; 81266423Sjfv 82266423Sjfv/* Flags sub-structure 83266423Sjfv * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 84266423Sjfv * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 85266423Sjfv */ 86266423Sjfv 87266423Sjfv/* command flags and offsets*/ 88270346Sjfv#define I40E_AQ_FLAG_DD_SHIFT 0 89270346Sjfv#define I40E_AQ_FLAG_CMP_SHIFT 1 90270346Sjfv#define I40E_AQ_FLAG_ERR_SHIFT 2 91270346Sjfv#define I40E_AQ_FLAG_VFE_SHIFT 3 92270346Sjfv#define I40E_AQ_FLAG_LB_SHIFT 9 93270346Sjfv#define I40E_AQ_FLAG_RD_SHIFT 10 94270346Sjfv#define I40E_AQ_FLAG_VFC_SHIFT 11 95270346Sjfv#define I40E_AQ_FLAG_BUF_SHIFT 12 96270346Sjfv#define I40E_AQ_FLAG_SI_SHIFT 13 97270346Sjfv#define I40E_AQ_FLAG_EI_SHIFT 14 98270346Sjfv#define I40E_AQ_FLAG_FE_SHIFT 15 99266423Sjfv 100270346Sjfv#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 101270346Sjfv#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 102270346Sjfv#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 103270346Sjfv#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 104270346Sjfv#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 105270346Sjfv#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 106270346Sjfv#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 107270346Sjfv#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 108270346Sjfv#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 109270346Sjfv#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 110270346Sjfv#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 111266423Sjfv 112266423Sjfv/* error codes */ 113266423Sjfvenum i40e_admin_queue_err { 114270346Sjfv I40E_AQ_RC_OK = 0, /* success */ 115270346Sjfv I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 116270346Sjfv I40E_AQ_RC_ENOENT = 2, /* No such element */ 117270346Sjfv I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 118270346Sjfv I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 119270346Sjfv I40E_AQ_RC_EIO = 5, /* I/O error */ 120270346Sjfv I40E_AQ_RC_ENXIO = 6, /* No such resource */ 121270346Sjfv I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 122270346Sjfv I40E_AQ_RC_EAGAIN = 8, /* Try again */ 123270346Sjfv I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 124270346Sjfv I40E_AQ_RC_EACCES = 10, /* Permission denied */ 125270346Sjfv I40E_AQ_RC_EFAULT = 11, /* Bad address */ 126270346Sjfv I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 127270346Sjfv I40E_AQ_RC_EEXIST = 13, /* object already exists */ 128270346Sjfv I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 129270346Sjfv I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 130270346Sjfv I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 131270346Sjfv I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 132270346Sjfv I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 133270346Sjfv I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 134270346Sjfv I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 135270346Sjfv I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 136270346Sjfv I40E_AQ_RC_EFBIG = 22, /* File too large */ 137266423Sjfv}; 138266423Sjfv 139266423Sjfv/* Admin Queue command opcodes */ 140266423Sjfvenum i40e_admin_queue_opc { 141266423Sjfv /* aq commands */ 142270346Sjfv i40e_aqc_opc_get_version = 0x0001, 143270346Sjfv i40e_aqc_opc_driver_version = 0x0002, 144270346Sjfv i40e_aqc_opc_queue_shutdown = 0x0003, 145270346Sjfv i40e_aqc_opc_set_pf_context = 0x0004, 146266423Sjfv 147266423Sjfv /* resource ownership */ 148270346Sjfv i40e_aqc_opc_request_resource = 0x0008, 149270346Sjfv i40e_aqc_opc_release_resource = 0x0009, 150266423Sjfv 151270346Sjfv i40e_aqc_opc_list_func_capabilities = 0x000A, 152270346Sjfv i40e_aqc_opc_list_dev_capabilities = 0x000B, 153266423Sjfv 154303967Ssbruno /* Proxy commands */ 155303967Ssbruno i40e_aqc_opc_set_proxy_config = 0x0104, 156303967Ssbruno i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, 157303967Ssbruno 158266423Sjfv /* LAA */ 159270346Sjfv i40e_aqc_opc_mac_address_read = 0x0107, 160270346Sjfv i40e_aqc_opc_mac_address_write = 0x0108, 161266423Sjfv 162266423Sjfv /* PXE */ 163270346Sjfv i40e_aqc_opc_clear_pxe_mode = 0x0110, 164266423Sjfv 165303967Ssbruno /* WoL commands */ 166303967Ssbruno i40e_aqc_opc_set_wol_filter = 0x0120, 167303967Ssbruno i40e_aqc_opc_get_wake_reason = 0x0121, 168318357Serj i40e_aqc_opc_clear_all_wol_filters = 0x025E, 169303967Ssbruno 170266423Sjfv /* internal switch commands */ 171270346Sjfv i40e_aqc_opc_get_switch_config = 0x0200, 172270346Sjfv i40e_aqc_opc_add_statistics = 0x0201, 173270346Sjfv i40e_aqc_opc_remove_statistics = 0x0202, 174270346Sjfv i40e_aqc_opc_set_port_parameters = 0x0203, 175270346Sjfv i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 176299549Serj i40e_aqc_opc_set_switch_config = 0x0205, 177299555Serj i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 178299555Serj i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 179266423Sjfv 180270346Sjfv i40e_aqc_opc_add_vsi = 0x0210, 181270346Sjfv i40e_aqc_opc_update_vsi_parameters = 0x0211, 182270346Sjfv i40e_aqc_opc_get_vsi_parameters = 0x0212, 183266423Sjfv 184270346Sjfv i40e_aqc_opc_add_pv = 0x0220, 185270346Sjfv i40e_aqc_opc_update_pv_parameters = 0x0221, 186270346Sjfv i40e_aqc_opc_get_pv_parameters = 0x0222, 187266423Sjfv 188270346Sjfv i40e_aqc_opc_add_veb = 0x0230, 189270346Sjfv i40e_aqc_opc_update_veb_parameters = 0x0231, 190270346Sjfv i40e_aqc_opc_get_veb_parameters = 0x0232, 191266423Sjfv 192270346Sjfv i40e_aqc_opc_delete_element = 0x0243, 193266423Sjfv 194270346Sjfv i40e_aqc_opc_add_macvlan = 0x0250, 195270346Sjfv i40e_aqc_opc_remove_macvlan = 0x0251, 196270346Sjfv i40e_aqc_opc_add_vlan = 0x0252, 197270346Sjfv i40e_aqc_opc_remove_vlan = 0x0253, 198270346Sjfv i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 199270346Sjfv i40e_aqc_opc_add_tag = 0x0255, 200270346Sjfv i40e_aqc_opc_remove_tag = 0x0256, 201270346Sjfv i40e_aqc_opc_add_multicast_etag = 0x0257, 202270346Sjfv i40e_aqc_opc_remove_multicast_etag = 0x0258, 203270346Sjfv i40e_aqc_opc_update_tag = 0x0259, 204270346Sjfv i40e_aqc_opc_add_control_packet_filter = 0x025A, 205270346Sjfv i40e_aqc_opc_remove_control_packet_filter = 0x025B, 206270346Sjfv i40e_aqc_opc_add_cloud_filters = 0x025C, 207270346Sjfv i40e_aqc_opc_remove_cloud_filters = 0x025D, 208303967Ssbruno i40e_aqc_opc_clear_wol_switch_filters = 0x025E, 209266423Sjfv 210270346Sjfv i40e_aqc_opc_add_mirror_rule = 0x0260, 211270346Sjfv i40e_aqc_opc_delete_mirror_rule = 0x0261, 212266423Sjfv 213266423Sjfv /* DCB commands */ 214270346Sjfv i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 215270346Sjfv i40e_aqc_opc_dcb_updated = 0x0302, 216333343Serj i40e_aqc_opc_set_dcb_parameters = 0x0303, 217266423Sjfv 218266423Sjfv /* TX scheduler */ 219270346Sjfv i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 220270346Sjfv i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 221270346Sjfv i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 222270346Sjfv i40e_aqc_opc_query_vsi_bw_config = 0x0408, 223270346Sjfv i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 224270346Sjfv i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 225266423Sjfv 226270346Sjfv i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 227270346Sjfv i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 228270346Sjfv i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 229270346Sjfv i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 230270346Sjfv i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 231270346Sjfv i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 232270346Sjfv i40e_aqc_opc_query_port_ets_config = 0x0419, 233270346Sjfv i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 234270346Sjfv i40e_aqc_opc_suspend_port_tx = 0x041B, 235270346Sjfv i40e_aqc_opc_resume_port_tx = 0x041C, 236270346Sjfv i40e_aqc_opc_configure_partition_bw = 0x041D, 237266423Sjfv /* hmc */ 238270346Sjfv i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 239270346Sjfv i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 240266423Sjfv 241266423Sjfv /* phy commands*/ 242270346Sjfv i40e_aqc_opc_get_phy_abilities = 0x0600, 243270346Sjfv i40e_aqc_opc_set_phy_config = 0x0601, 244270346Sjfv i40e_aqc_opc_set_mac_config = 0x0603, 245270346Sjfv i40e_aqc_opc_set_link_restart_an = 0x0605, 246270346Sjfv i40e_aqc_opc_get_link_status = 0x0607, 247270346Sjfv i40e_aqc_opc_set_phy_int_mask = 0x0613, 248270346Sjfv i40e_aqc_opc_get_local_advt_reg = 0x0614, 249270346Sjfv i40e_aqc_opc_set_local_advt_reg = 0x0615, 250270346Sjfv i40e_aqc_opc_get_partner_advt = 0x0616, 251270346Sjfv i40e_aqc_opc_set_lb_modes = 0x0618, 252270346Sjfv i40e_aqc_opc_get_phy_wol_caps = 0x0621, 253270346Sjfv i40e_aqc_opc_set_phy_debug = 0x0622, 254270346Sjfv i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 255299549Serj i40e_aqc_opc_run_phy_activity = 0x0626, 256333343Serj i40e_aqc_opc_set_phy_register = 0x0628, 257333343Serj i40e_aqc_opc_get_phy_register = 0x0629, 258266423Sjfv 259266423Sjfv /* NVM commands */ 260270346Sjfv i40e_aqc_opc_nvm_read = 0x0701, 261270346Sjfv i40e_aqc_opc_nvm_erase = 0x0702, 262270346Sjfv i40e_aqc_opc_nvm_update = 0x0703, 263270346Sjfv i40e_aqc_opc_nvm_config_read = 0x0704, 264270346Sjfv i40e_aqc_opc_nvm_config_write = 0x0705, 265333343Serj i40e_aqc_opc_nvm_progress = 0x0706, 266284049Sjfv i40e_aqc_opc_oem_post_update = 0x0720, 267299549Serj i40e_aqc_opc_thermal_sensor = 0x0721, 268266423Sjfv 269266423Sjfv /* virtualization commands */ 270270346Sjfv i40e_aqc_opc_send_msg_to_pf = 0x0801, 271270346Sjfv i40e_aqc_opc_send_msg_to_vf = 0x0802, 272270346Sjfv i40e_aqc_opc_send_msg_to_peer = 0x0803, 273266423Sjfv 274266423Sjfv /* alternate structure */ 275270346Sjfv i40e_aqc_opc_alternate_write = 0x0900, 276270346Sjfv i40e_aqc_opc_alternate_write_indirect = 0x0901, 277270346Sjfv i40e_aqc_opc_alternate_read = 0x0902, 278270346Sjfv i40e_aqc_opc_alternate_read_indirect = 0x0903, 279270346Sjfv i40e_aqc_opc_alternate_write_done = 0x0904, 280270346Sjfv i40e_aqc_opc_alternate_set_mode = 0x0905, 281270346Sjfv i40e_aqc_opc_alternate_clear_port = 0x0906, 282266423Sjfv 283266423Sjfv /* LLDP commands */ 284270346Sjfv i40e_aqc_opc_lldp_get_mib = 0x0A00, 285270346Sjfv i40e_aqc_opc_lldp_update_mib = 0x0A01, 286270346Sjfv i40e_aqc_opc_lldp_add_tlv = 0x0A02, 287270346Sjfv i40e_aqc_opc_lldp_update_tlv = 0x0A03, 288270346Sjfv i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 289270346Sjfv i40e_aqc_opc_lldp_stop = 0x0A05, 290270346Sjfv i40e_aqc_opc_lldp_start = 0x0A06, 291277082Sjfv i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 292277082Sjfv i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 293277082Sjfv i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 294349163Serj i40e_aqc_opc_lldp_restore = 0x0A0A, 295266423Sjfv 296266423Sjfv /* Tunnel commands */ 297270346Sjfv i40e_aqc_opc_add_udp_tunnel = 0x0B00, 298270346Sjfv i40e_aqc_opc_del_udp_tunnel = 0x0B01, 299303967Ssbruno i40e_aqc_opc_set_rss_key = 0x0B02, 300303967Ssbruno i40e_aqc_opc_set_rss_lut = 0x0B03, 301303967Ssbruno i40e_aqc_opc_get_rss_key = 0x0B04, 302303967Ssbruno i40e_aqc_opc_get_rss_lut = 0x0B05, 303266423Sjfv 304266423Sjfv /* Async Events */ 305270346Sjfv i40e_aqc_opc_event_lan_overflow = 0x1001, 306266423Sjfv 307266423Sjfv /* OEM commands */ 308270346Sjfv i40e_aqc_opc_oem_parameter_change = 0xFE00, 309270346Sjfv i40e_aqc_opc_oem_device_status_change = 0xFE01, 310277082Sjfv i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 311277082Sjfv i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 312266423Sjfv 313266423Sjfv /* debug commands */ 314270346Sjfv i40e_aqc_opc_debug_read_reg = 0xFF03, 315270346Sjfv i40e_aqc_opc_debug_write_reg = 0xFF04, 316270346Sjfv i40e_aqc_opc_debug_modify_reg = 0xFF07, 317270346Sjfv i40e_aqc_opc_debug_dump_internals = 0xFF08, 318266423Sjfv}; 319266423Sjfv 320266423Sjfv/* command structures and indirect data structures */ 321266423Sjfv 322266423Sjfv/* Structure naming conventions: 323266423Sjfv * - no suffix for direct command descriptor structures 324266423Sjfv * - _data for indirect sent data 325266423Sjfv * - _resp for indirect return data (data which is both will use _data) 326266423Sjfv * - _completion for direct return data 327266423Sjfv * - _element_ for repeated elements (may also be _data or _resp) 328266423Sjfv * 329266423Sjfv * Command structures are expected to overlay the params.raw member of the basic 330266423Sjfv * descriptor, and as such cannot exceed 16 bytes in length. 331266423Sjfv */ 332266423Sjfv 333266423Sjfv/* This macro is used to generate a compilation error if a structure 334266423Sjfv * is not exactly the correct length. It gives a divide by zero error if the 335266423Sjfv * structure is not of the correct size, otherwise it creates an enum that is 336266423Sjfv * never used. 337266423Sjfv */ 338266423Sjfv#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 339266423Sjfv { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 340266423Sjfv 341266423Sjfv/* This macro is used extensively to ensure that command structures are 16 342266423Sjfv * bytes in length as they have to map to the raw array of that size. 343266423Sjfv */ 344270346Sjfv#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 345266423Sjfv 346266423Sjfv/* internal (0x00XX) commands */ 347266423Sjfv 348266423Sjfv/* Get version (direct 0x0001) */ 349266423Sjfvstruct i40e_aqc_get_version { 350266423Sjfv __le32 rom_ver; 351266423Sjfv __le32 fw_build; 352266423Sjfv __le16 fw_major; 353266423Sjfv __le16 fw_minor; 354266423Sjfv __le16 api_major; 355266423Sjfv __le16 api_minor; 356266423Sjfv}; 357266423Sjfv 358266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 359266423Sjfv 360266423Sjfv/* Send driver version (indirect 0x0002) */ 361266423Sjfvstruct i40e_aqc_driver_version { 362270346Sjfv u8 driver_major_ver; 363270346Sjfv u8 driver_minor_ver; 364270346Sjfv u8 driver_build_ver; 365270346Sjfv u8 driver_subbuild_ver; 366270346Sjfv u8 reserved[4]; 367270346Sjfv __le32 address_high; 368270346Sjfv __le32 address_low; 369266423Sjfv}; 370266423Sjfv 371266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 372266423Sjfv 373266423Sjfv/* Queue Shutdown (direct 0x0003) */ 374266423Sjfvstruct i40e_aqc_queue_shutdown { 375270346Sjfv __le32 driver_unloading; 376270346Sjfv#define I40E_AQ_DRIVER_UNLOADING 0x1 377270346Sjfv u8 reserved[12]; 378266423Sjfv}; 379266423Sjfv 380266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 381266423Sjfv 382266423Sjfv/* Set PF context (0x0004, direct) */ 383266423Sjfvstruct i40e_aqc_set_pf_context { 384266423Sjfv u8 pf_id; 385266423Sjfv u8 reserved[15]; 386266423Sjfv}; 387266423Sjfv 388266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 389266423Sjfv 390266423Sjfv/* Request resource ownership (direct 0x0008) 391266423Sjfv * Release resource ownership (direct 0x0009) 392266423Sjfv */ 393270346Sjfv#define I40E_AQ_RESOURCE_NVM 1 394270346Sjfv#define I40E_AQ_RESOURCE_SDP 2 395270346Sjfv#define I40E_AQ_RESOURCE_ACCESS_READ 1 396270346Sjfv#define I40E_AQ_RESOURCE_ACCESS_WRITE 2 397270346Sjfv#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 398270346Sjfv#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 399266423Sjfv 400266423Sjfvstruct i40e_aqc_request_resource { 401270346Sjfv __le16 resource_id; 402270346Sjfv __le16 access_type; 403270346Sjfv __le32 timeout; 404270346Sjfv __le32 resource_number; 405270346Sjfv u8 reserved[4]; 406266423Sjfv}; 407266423Sjfv 408266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 409266423Sjfv 410266423Sjfv/* Get function capabilities (indirect 0x000A) 411266423Sjfv * Get device capabilities (indirect 0x000B) 412266423Sjfv */ 413266423Sjfvstruct i40e_aqc_list_capabilites { 414266423Sjfv u8 command_flags; 415270346Sjfv#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 416266423Sjfv u8 pf_index; 417266423Sjfv u8 reserved[2]; 418266423Sjfv __le32 count; 419266423Sjfv __le32 addr_high; 420266423Sjfv __le32 addr_low; 421266423Sjfv}; 422266423Sjfv 423266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 424266423Sjfv 425266423Sjfvstruct i40e_aqc_list_capabilities_element_resp { 426270346Sjfv __le16 id; 427270346Sjfv u8 major_rev; 428270346Sjfv u8 minor_rev; 429270346Sjfv __le32 number; 430270346Sjfv __le32 logical_id; 431270346Sjfv __le32 phys_id; 432270346Sjfv u8 reserved[16]; 433266423Sjfv}; 434266423Sjfv 435266423Sjfv/* list of caps */ 436266423Sjfv 437270346Sjfv#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 438270346Sjfv#define I40E_AQ_CAP_ID_MNG_MODE 0x0002 439270346Sjfv#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 440270346Sjfv#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 441270346Sjfv#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 442270346Sjfv#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 443299548Serj#define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 444270346Sjfv#define I40E_AQ_CAP_ID_SRIOV 0x0012 445270346Sjfv#define I40E_AQ_CAP_ID_VF 0x0013 446270346Sjfv#define I40E_AQ_CAP_ID_VMDQ 0x0014 447270346Sjfv#define I40E_AQ_CAP_ID_8021QBG 0x0015 448270346Sjfv#define I40E_AQ_CAP_ID_8021QBR 0x0016 449270346Sjfv#define I40E_AQ_CAP_ID_VSI 0x0017 450270346Sjfv#define I40E_AQ_CAP_ID_DCB 0x0018 451270346Sjfv#define I40E_AQ_CAP_ID_FCOE 0x0021 452277082Sjfv#define I40E_AQ_CAP_ID_ISCSI 0x0022 453270346Sjfv#define I40E_AQ_CAP_ID_RSS 0x0040 454270346Sjfv#define I40E_AQ_CAP_ID_RXQ 0x0041 455270346Sjfv#define I40E_AQ_CAP_ID_TXQ 0x0042 456270346Sjfv#define I40E_AQ_CAP_ID_MSIX 0x0043 457270346Sjfv#define I40E_AQ_CAP_ID_VF_MSIX 0x0044 458270346Sjfv#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 459270346Sjfv#define I40E_AQ_CAP_ID_1588 0x0046 460270346Sjfv#define I40E_AQ_CAP_ID_IWARP 0x0051 461270346Sjfv#define I40E_AQ_CAP_ID_LED 0x0061 462270346Sjfv#define I40E_AQ_CAP_ID_SDP 0x0062 463270346Sjfv#define I40E_AQ_CAP_ID_MDIO 0x0063 464299548Serj#define I40E_AQ_CAP_ID_WSR_PROT 0x0064 465303967Ssbruno#define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 466270346Sjfv#define I40E_AQ_CAP_ID_FLEX10 0x00F1 467270346Sjfv#define I40E_AQ_CAP_ID_CEM 0x00F2 468266423Sjfv 469266423Sjfv/* Set CPPM Configuration (direct 0x0103) */ 470266423Sjfvstruct i40e_aqc_cppm_configuration { 471270346Sjfv __le16 command_flags; 472270346Sjfv#define I40E_AQ_CPPM_EN_LTRC 0x0800 473270346Sjfv#define I40E_AQ_CPPM_EN_DMCTH 0x1000 474270346Sjfv#define I40E_AQ_CPPM_EN_DMCTLX 0x2000 475270346Sjfv#define I40E_AQ_CPPM_EN_HPTC 0x4000 476270346Sjfv#define I40E_AQ_CPPM_EN_DMARC 0x8000 477270346Sjfv __le16 ttlx; 478270346Sjfv __le32 dmacr; 479270346Sjfv __le16 dmcth; 480270346Sjfv u8 hptc; 481270346Sjfv u8 reserved; 482270346Sjfv __le32 pfltrc; 483266423Sjfv}; 484266423Sjfv 485266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 486266423Sjfv 487266423Sjfv/* Set ARP Proxy command / response (indirect 0x0104) */ 488266423Sjfvstruct i40e_aqc_arp_proxy_data { 489270346Sjfv __le16 command_flags; 490303967Ssbruno#define I40E_AQ_ARP_INIT_IPV4 0x0800 491303967Ssbruno#define I40E_AQ_ARP_UNSUP_CTL 0x1000 492303967Ssbruno#define I40E_AQ_ARP_ENA 0x2000 493303967Ssbruno#define I40E_AQ_ARP_ADD_IPV4 0x4000 494303967Ssbruno#define I40E_AQ_ARP_DEL_IPV4 0x8000 495270346Sjfv __le16 table_id; 496303967Ssbruno __le32 enabled_offloads; 497303967Ssbruno#define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 498303967Ssbruno#define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 499270346Sjfv __le32 ip_addr; 500270346Sjfv u8 mac_addr[6]; 501277082Sjfv u8 reserved[2]; 502266423Sjfv}; 503266423Sjfv 504277082SjfvI40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 505277082Sjfv 506266423Sjfv/* Set NS Proxy Table Entry Command (indirect 0x0105) */ 507266423Sjfvstruct i40e_aqc_ns_proxy_data { 508270346Sjfv __le16 table_idx_mac_addr_0; 509270346Sjfv __le16 table_idx_mac_addr_1; 510270346Sjfv __le16 table_idx_ipv6_0; 511270346Sjfv __le16 table_idx_ipv6_1; 512270346Sjfv __le16 control; 513303967Ssbruno#define I40E_AQ_NS_PROXY_ADD_0 0x0001 514303967Ssbruno#define I40E_AQ_NS_PROXY_DEL_0 0x0002 515303967Ssbruno#define I40E_AQ_NS_PROXY_ADD_1 0x0004 516303967Ssbruno#define I40E_AQ_NS_PROXY_DEL_1 0x0008 517303967Ssbruno#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 518303967Ssbruno#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 519303967Ssbruno#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 520303967Ssbruno#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 521303967Ssbruno#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 522303967Ssbruno#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 523303967Ssbruno#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 524303967Ssbruno#define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 525303967Ssbruno#define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 526270346Sjfv u8 mac_addr_0[6]; 527270346Sjfv u8 mac_addr_1[6]; 528270346Sjfv u8 local_mac_addr[6]; 529270346Sjfv u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 530270346Sjfv u8 ipv6_addr_1[16]; 531266423Sjfv}; 532266423Sjfv 533277082SjfvI40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 534277082Sjfv 535266423Sjfv/* Manage LAA Command (0x0106) - obsolete */ 536266423Sjfvstruct i40e_aqc_mng_laa { 537266423Sjfv __le16 command_flags; 538270346Sjfv#define I40E_AQ_LAA_FLAG_WR 0x8000 539270346Sjfv u8 reserved[2]; 540270346Sjfv __le32 sal; 541270346Sjfv __le16 sah; 542270346Sjfv u8 reserved2[6]; 543266423Sjfv}; 544266423Sjfv 545277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 546277082Sjfv 547266423Sjfv/* Manage MAC Address Read Command (indirect 0x0107) */ 548266423Sjfvstruct i40e_aqc_mac_address_read { 549266423Sjfv __le16 command_flags; 550270346Sjfv#define I40E_AQC_LAN_ADDR_VALID 0x10 551270346Sjfv#define I40E_AQC_SAN_ADDR_VALID 0x20 552270346Sjfv#define I40E_AQC_PORT_ADDR_VALID 0x40 553270346Sjfv#define I40E_AQC_WOL_ADDR_VALID 0x80 554284049Sjfv#define I40E_AQC_MC_MAG_EN_VALID 0x100 555318357Serj#define I40E_AQC_WOL_PRESERVE_STATUS 0x200 556318357Serj#define I40E_AQC_ADDR_VALID_MASK 0x3F0 557270346Sjfv u8 reserved[6]; 558270346Sjfv __le32 addr_high; 559270346Sjfv __le32 addr_low; 560266423Sjfv}; 561266423Sjfv 562266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 563266423Sjfv 564266423Sjfvstruct i40e_aqc_mac_address_read_data { 565266423Sjfv u8 pf_lan_mac[6]; 566266423Sjfv u8 pf_san_mac[6]; 567266423Sjfv u8 port_mac[6]; 568266423Sjfv u8 pf_wol_mac[6]; 569266423Sjfv}; 570266423Sjfv 571266423SjfvI40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 572266423Sjfv 573266423Sjfv/* Manage MAC Address Write Command (0x0108) */ 574266423Sjfvstruct i40e_aqc_mac_address_write { 575270346Sjfv __le16 command_flags; 576303967Ssbruno#define I40E_AQC_MC_MAG_EN 0x0100 577318357Serj#define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200 578270346Sjfv#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 579270346Sjfv#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 580270346Sjfv#define I40E_AQC_WRITE_TYPE_PORT 0x8000 581284049Sjfv#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 582284049Sjfv#define I40E_AQC_WRITE_TYPE_MASK 0xC000 583284049Sjfv 584270346Sjfv __le16 mac_sah; 585270346Sjfv __le32 mac_sal; 586270346Sjfv u8 reserved[8]; 587266423Sjfv}; 588266423Sjfv 589266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 590266423Sjfv 591266423Sjfv/* PXE commands (0x011x) */ 592266423Sjfv 593266423Sjfv/* Clear PXE Command and response (direct 0x0110) */ 594266423Sjfvstruct i40e_aqc_clear_pxe { 595266423Sjfv u8 rx_cnt; 596266423Sjfv u8 reserved[15]; 597266423Sjfv}; 598266423Sjfv 599266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 600266423Sjfv 601303967Ssbruno/* Set WoL Filter (0x0120) */ 602303967Ssbruno 603303967Ssbrunostruct i40e_aqc_set_wol_filter { 604303967Ssbruno __le16 filter_index; 605303967Ssbruno#define I40E_AQC_MAX_NUM_WOL_FILTERS 8 606303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 607303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ 608303967Ssbruno I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) 609303967Ssbruno 610303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 611303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ 612303967Ssbruno I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) 613303967Ssbruno __le16 cmd_flags; 614303967Ssbruno#define I40E_AQC_SET_WOL_FILTER 0x8000 615303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 616318357Serj#define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000 617303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 618303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 619303967Ssbruno __le16 valid_flags; 620303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 621303967Ssbruno#define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 622303967Ssbruno u8 reserved[2]; 623303967Ssbruno __le32 address_high; 624303967Ssbruno __le32 address_low; 625303967Ssbruno}; 626303967Ssbruno 627303967SsbrunoI40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); 628303967Ssbruno 629303967Ssbrunostruct i40e_aqc_set_wol_filter_data { 630303967Ssbruno u8 filter[128]; 631303967Ssbruno u8 mask[16]; 632303967Ssbruno}; 633303967Ssbruno 634303967SsbrunoI40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); 635303967Ssbruno 636303967Ssbruno/* Get Wake Reason (0x0121) */ 637303967Ssbruno 638303967Ssbrunostruct i40e_aqc_get_wake_reason_completion { 639303967Ssbruno u8 reserved_1[2]; 640303967Ssbruno __le16 wake_reason; 641303967Ssbruno#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 642303967Ssbruno#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ 643303967Ssbruno I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) 644303967Ssbruno#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 645303967Ssbruno#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ 646303967Ssbruno I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) 647303967Ssbruno u8 reserved_2[12]; 648303967Ssbruno}; 649303967Ssbruno 650303967SsbrunoI40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); 651303967Ssbruno 652266423Sjfv/* Switch configuration commands (0x02xx) */ 653266423Sjfv 654266423Sjfv/* Used by many indirect commands that only pass an seid and a buffer in the 655266423Sjfv * command 656266423Sjfv */ 657266423Sjfvstruct i40e_aqc_switch_seid { 658270346Sjfv __le16 seid; 659270346Sjfv u8 reserved[6]; 660270346Sjfv __le32 addr_high; 661270346Sjfv __le32 addr_low; 662266423Sjfv}; 663266423Sjfv 664266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 665266423Sjfv 666266423Sjfv/* Get Switch Configuration command (indirect 0x0200) 667266423Sjfv * uses i40e_aqc_switch_seid for the descriptor 668266423Sjfv */ 669266423Sjfvstruct i40e_aqc_get_switch_config_header_resp { 670270346Sjfv __le16 num_reported; 671270346Sjfv __le16 num_total; 672270346Sjfv u8 reserved[12]; 673266423Sjfv}; 674266423Sjfv 675277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 676277082Sjfv 677266423Sjfvstruct i40e_aqc_switch_config_element_resp { 678270346Sjfv u8 element_type; 679270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_MAC 1 680270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_PF 2 681270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_VF 3 682270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_EMP 4 683270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_BMC 5 684270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_PV 16 685270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_VEB 17 686270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_PA 18 687270346Sjfv#define I40E_AQ_SW_ELEM_TYPE_VSI 19 688270346Sjfv u8 revision; 689270346Sjfv#define I40E_AQ_SW_ELEM_REV_1 1 690270346Sjfv __le16 seid; 691270346Sjfv __le16 uplink_seid; 692270346Sjfv __le16 downlink_seid; 693270346Sjfv u8 reserved[3]; 694270346Sjfv u8 connection_type; 695270346Sjfv#define I40E_AQ_CONN_TYPE_REGULAR 0x1 696270346Sjfv#define I40E_AQ_CONN_TYPE_DEFAULT 0x2 697270346Sjfv#define I40E_AQ_CONN_TYPE_CASCADED 0x3 698270346Sjfv __le16 scheduler_id; 699270346Sjfv __le16 element_info; 700266423Sjfv}; 701266423Sjfv 702277082SjfvI40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 703277082Sjfv 704266423Sjfv/* Get Switch Configuration (indirect 0x0200) 705266423Sjfv * an array of elements are returned in the response buffer 706266423Sjfv * the first in the array is the header, remainder are elements 707266423Sjfv */ 708266423Sjfvstruct i40e_aqc_get_switch_config_resp { 709270346Sjfv struct i40e_aqc_get_switch_config_header_resp header; 710270346Sjfv struct i40e_aqc_switch_config_element_resp element[1]; 711266423Sjfv}; 712266423Sjfv 713277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 714277082Sjfv 715266423Sjfv/* Add Statistics (direct 0x0201) 716266423Sjfv * Remove Statistics (direct 0x0202) 717266423Sjfv */ 718266423Sjfvstruct i40e_aqc_add_remove_statistics { 719270346Sjfv __le16 seid; 720270346Sjfv __le16 vlan; 721270346Sjfv __le16 stat_index; 722270346Sjfv u8 reserved[10]; 723266423Sjfv}; 724266423Sjfv 725266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 726266423Sjfv 727266423Sjfv/* Set Port Parameters command (direct 0x0203) */ 728266423Sjfvstruct i40e_aqc_set_port_parameters { 729270346Sjfv __le16 command_flags; 730270346Sjfv#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 731270346Sjfv#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 732270346Sjfv#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 733270346Sjfv __le16 bad_frame_vsi; 734303967Ssbruno#define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 735303967Ssbruno#define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF 736270346Sjfv __le16 default_seid; /* reserved for command */ 737270346Sjfv u8 reserved[10]; 738266423Sjfv}; 739266423Sjfv 740266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 741266423Sjfv 742266423Sjfv/* Get Switch Resource Allocation (indirect 0x0204) */ 743266423Sjfvstruct i40e_aqc_get_switch_resource_alloc { 744270346Sjfv u8 num_entries; /* reserved for command */ 745270346Sjfv u8 reserved[7]; 746270346Sjfv __le32 addr_high; 747270346Sjfv __le32 addr_low; 748266423Sjfv}; 749266423Sjfv 750266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 751266423Sjfv 752266423Sjfv/* expect an array of these structs in the response buffer */ 753266423Sjfvstruct i40e_aqc_switch_resource_alloc_element_resp { 754270346Sjfv u8 resource_type; 755270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VEB 0x0 756270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VSI 0x1 757270346Sjfv#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 758270346Sjfv#define I40E_AQ_RESOURCE_TYPE_STAG 0x3 759270346Sjfv#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 760270346Sjfv#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 761270346Sjfv#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 762270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 763270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 764270346Sjfv#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 765270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 766270346Sjfv#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 767270346Sjfv#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 768270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 769270346Sjfv#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 770270346Sjfv#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 771270346Sjfv#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 772270346Sjfv#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 773270346Sjfv#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 774270346Sjfv u8 reserved1; 775270346Sjfv __le16 guaranteed; 776270346Sjfv __le16 total; 777270346Sjfv __le16 used; 778270346Sjfv __le16 total_unalloced; 779270346Sjfv u8 reserved2[6]; 780266423Sjfv}; 781266423Sjfv 782277082SjfvI40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 783277082Sjfv 784299549Serj/* Set Switch Configuration (direct 0x0205) */ 785299549Serjstruct i40e_aqc_set_switch_config { 786299549Serj __le16 flags; 787303967Ssbruno/* flags used for both fields below */ 788299549Serj#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 789299549Serj#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 790333343Serj#define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT 0x0004 791299549Serj __le16 valid_flags; 792333343Serj /* The ethertype in switch_tag is dropped on ingress and used 793333343Serj * internally by the switch. Set this to zero for the default 794333343Serj * of 0x88a8 (802.1ad). Should be zero for firmware API 795333343Serj * versions lower than 1.7. 796333343Serj */ 797333343Serj __le16 switch_tag; 798333343Serj /* The ethertypes in first_tag and second_tag are used to 799333343Serj * match the outer and inner VLAN tags (respectively) when HW 800333343Serj * double VLAN tagging is enabled via the set port parameters 801333343Serj * AQ command. Otherwise these are both ignored. Set them to 802333343Serj * zero for their defaults of 0x8100 (802.1Q). Should be zero 803333343Serj * for firmware API versions lower than 1.7. 804333343Serj */ 805333343Serj __le16 first_tag; 806333343Serj __le16 second_tag; 807333343Serj /* Next byte is split into following: 808333343Serj * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0 809333343Serj * Bit 6 : 0 : Destination Port, 1: source port 810333343Serj * Bit 5..4 : L4 type 811333343Serj * 0: rsvd 812333343Serj * 1: TCP 813333343Serj * 2: UDP 814333343Serj * 3: Both TCP and UDP 815333343Serj * Bits 3:0 Mode 816333343Serj * 0: default mode 817333343Serj * 1: L4 port only mode 818333343Serj * 2: non-tunneled mode 819333343Serj * 3: tunneled mode 820333343Serj */ 821333343Serj#define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80 822333343Serj 823333343Serj#define I40E_AQ_SET_SWITCH_L4_SRC_PORT 0x40 824333343Serj 825333343Serj#define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD 0x00 826333343Serj#define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10 827333343Serj#define I40E_AQ_SET_SWITCH_L4_TYPE_UDP 0x20 828333343Serj#define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH 0x30 829333343Serj 830333343Serj#define I40E_AQ_SET_SWITCH_MODE_DEFAULT 0x00 831333343Serj#define I40E_AQ_SET_SWITCH_MODE_L4_PORT 0x01 832333343Serj#define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02 833333343Serj#define I40E_AQ_SET_SWITCH_MODE_TUNNEL 0x03 834333343Serj u8 mode; 835333343Serj u8 rsvd5[5]; 836299549Serj}; 837299549Serj 838299549SerjI40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 839299549Serj 840299555Serj/* Read Receive control registers (direct 0x0206) 841299555Serj * Write Receive control registers (direct 0x0207) 842299555Serj * used for accessing Rx control registers that can be 843299555Serj * slow and need special handling when under high Rx load 844299555Serj */ 845299555Serjstruct i40e_aqc_rx_ctl_reg_read_write { 846299555Serj __le32 reserved1; 847299555Serj __le32 address; 848299555Serj __le32 reserved2; 849299555Serj __le32 value; 850299555Serj}; 851299555Serj 852299555SerjI40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 853299555Serj 854266423Sjfv/* Add VSI (indirect 0x0210) 855266423Sjfv * this indirect command uses struct i40e_aqc_vsi_properties_data 856266423Sjfv * as the indirect buffer (128 bytes) 857266423Sjfv * 858266423Sjfv * Update VSI (indirect 0x211) 859266423Sjfv * uses the same data structure as Add VSI 860266423Sjfv * 861266423Sjfv * Get VSI (indirect 0x0212) 862266423Sjfv * uses the same completion and data structure as Add VSI 863266423Sjfv */ 864266423Sjfvstruct i40e_aqc_add_get_update_vsi { 865270346Sjfv __le16 uplink_seid; 866270346Sjfv u8 connection_type; 867270346Sjfv#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 868270346Sjfv#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 869270346Sjfv#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 870270346Sjfv u8 reserved1; 871270346Sjfv u8 vf_id; 872270346Sjfv u8 reserved2; 873270346Sjfv __le16 vsi_flags; 874270346Sjfv#define I40E_AQ_VSI_TYPE_SHIFT 0x0 875270346Sjfv#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 876270346Sjfv#define I40E_AQ_VSI_TYPE_VF 0x0 877270346Sjfv#define I40E_AQ_VSI_TYPE_VMDQ2 0x1 878270346Sjfv#define I40E_AQ_VSI_TYPE_PF 0x2 879270346Sjfv#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 880270346Sjfv#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 881270346Sjfv __le32 addr_high; 882270346Sjfv __le32 addr_low; 883266423Sjfv}; 884266423Sjfv 885266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 886266423Sjfv 887266423Sjfvstruct i40e_aqc_add_get_update_vsi_completion { 888266423Sjfv __le16 seid; 889266423Sjfv __le16 vsi_number; 890266423Sjfv __le16 vsi_used; 891266423Sjfv __le16 vsi_free; 892266423Sjfv __le32 addr_high; 893266423Sjfv __le32 addr_low; 894266423Sjfv}; 895266423Sjfv 896266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 897266423Sjfv 898266423Sjfvstruct i40e_aqc_vsi_properties_data { 899266423Sjfv /* first 96 byte are written by SW */ 900270346Sjfv __le16 valid_sections; 901270346Sjfv#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 902270346Sjfv#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 903270346Sjfv#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 904270346Sjfv#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 905270346Sjfv#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 906270346Sjfv#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 907270346Sjfv#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 908270346Sjfv#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 909270346Sjfv#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 910270346Sjfv#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 911266423Sjfv /* switch section */ 912270346Sjfv __le16 switch_id; /* 12bit id combined with flags below */ 913270346Sjfv#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 914270346Sjfv#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 915270346Sjfv#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 916270346Sjfv#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 917270346Sjfv#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 918270346Sjfv u8 sw_reserved[2]; 919266423Sjfv /* security section */ 920270346Sjfv u8 sec_flags; 921270346Sjfv#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 922270346Sjfv#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 923270346Sjfv#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 924270346Sjfv u8 sec_reserved; 925266423Sjfv /* VLAN section */ 926270346Sjfv __le16 pvid; /* VLANS include priority bits */ 927270346Sjfv __le16 fcoe_pvid; 928270346Sjfv u8 port_vlan_flags; 929270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 930270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 931270346Sjfv I40E_AQ_VSI_PVLAN_MODE_SHIFT) 932270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 933270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 934270346Sjfv#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 935270346Sjfv#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 936270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 937270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 938270346Sjfv I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 939270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 940270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 941270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 942270346Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 943270346Sjfv u8 pvlan_reserved[3]; 944266423Sjfv /* ingress egress up sections */ 945270346Sjfv __le32 ingress_table; /* bitmap, 3 bits per up */ 946270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 947270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 948270346Sjfv I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 949270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 950270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 951270346Sjfv I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 952270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 953270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 954270346Sjfv I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 955270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 956270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 957270346Sjfv I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 958270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 959270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 960270346Sjfv I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 961270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 962270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 963270346Sjfv I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 964270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 965270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 966270346Sjfv I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 967270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 968270346Sjfv#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 969270346Sjfv I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 970270346Sjfv __le32 egress_table; /* same defines as for ingress table */ 971266423Sjfv /* cascaded PV section */ 972270346Sjfv __le16 cas_pv_tag; 973270346Sjfv u8 cas_pv_flags; 974270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 975270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 976270346Sjfv I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 977270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 978270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 979270346Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 980270346Sjfv#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 981270346Sjfv#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 982270346Sjfv#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 983270346Sjfv u8 cas_pv_reserved; 984266423Sjfv /* queue mapping section */ 985270346Sjfv __le16 mapping_flags; 986270346Sjfv#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 987270346Sjfv#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 988270346Sjfv __le16 queue_mapping[16]; 989270346Sjfv#define I40E_AQ_VSI_QUEUE_SHIFT 0x0 990270346Sjfv#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 991270346Sjfv __le16 tc_mapping[8]; 992270346Sjfv#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 993270346Sjfv#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 994270346Sjfv I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 995270346Sjfv#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 996270346Sjfv#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 997270346Sjfv I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 998266423Sjfv /* queueing option section */ 999270346Sjfv u8 queueing_opt_flags; 1000303967Ssbruno#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 1001303967Ssbruno#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 1002270346Sjfv#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 1003270346Sjfv#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 1004303967Ssbruno#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 1005303967Ssbruno#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 1006270346Sjfv u8 queueing_opt_reserved[3]; 1007266423Sjfv /* scheduler section */ 1008270346Sjfv u8 up_enable_bits; 1009270346Sjfv u8 sched_reserved; 1010266423Sjfv /* outer up section */ 1011299555Serj __le32 outer_up_table; /* same structure and defines as ingress tbl */ 1012270346Sjfv u8 cmd_reserved[8]; 1013266423Sjfv /* last 32 bytes are written by FW */ 1014270346Sjfv __le16 qs_handle[8]; 1015266423Sjfv#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 1016270346Sjfv __le16 stat_counter_idx; 1017270346Sjfv __le16 sched_id; 1018270346Sjfv u8 resp_reserved[12]; 1019266423Sjfv}; 1020266423Sjfv 1021266423SjfvI40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 1022266423Sjfv 1023266423Sjfv/* Add Port Virtualizer (direct 0x0220) 1024266423Sjfv * also used for update PV (direct 0x0221) but only flags are used 1025266423Sjfv * (IS_CTRL_PORT only works on add PV) 1026266423Sjfv */ 1027266423Sjfvstruct i40e_aqc_add_update_pv { 1028270346Sjfv __le16 command_flags; 1029270346Sjfv#define I40E_AQC_PV_FLAG_PV_TYPE 0x1 1030270346Sjfv#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 1031270346Sjfv#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 1032270346Sjfv#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 1033270346Sjfv __le16 uplink_seid; 1034270346Sjfv __le16 connected_seid; 1035270346Sjfv u8 reserved[10]; 1036266423Sjfv}; 1037266423Sjfv 1038266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 1039266423Sjfv 1040266423Sjfvstruct i40e_aqc_add_update_pv_completion { 1041266423Sjfv /* reserved for update; for add also encodes error if rc == ENOSPC */ 1042270346Sjfv __le16 pv_seid; 1043270346Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 1044270346Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 1045270346Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 1046270346Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 1047270346Sjfv u8 reserved[14]; 1048266423Sjfv}; 1049266423Sjfv 1050266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 1051266423Sjfv 1052266423Sjfv/* Get PV Params (direct 0x0222) 1053266423Sjfv * uses i40e_aqc_switch_seid for the descriptor 1054266423Sjfv */ 1055266423Sjfv 1056266423Sjfvstruct i40e_aqc_get_pv_params_completion { 1057270346Sjfv __le16 seid; 1058270346Sjfv __le16 default_stag; 1059270346Sjfv __le16 pv_flags; /* same flags as add_pv */ 1060270346Sjfv#define I40E_AQC_GET_PV_PV_TYPE 0x1 1061270346Sjfv#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 1062270346Sjfv#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 1063270346Sjfv u8 reserved[8]; 1064270346Sjfv __le16 default_port_seid; 1065266423Sjfv}; 1066266423Sjfv 1067266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 1068266423Sjfv 1069266423Sjfv/* Add VEB (direct 0x0230) */ 1070266423Sjfvstruct i40e_aqc_add_veb { 1071270346Sjfv __le16 uplink_seid; 1072270346Sjfv __le16 downlink_seid; 1073270346Sjfv __le16 veb_flags; 1074270346Sjfv#define I40E_AQC_ADD_VEB_FLOATING 0x1 1075270346Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 1076270346Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 1077266423Sjfv I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 1078270346Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 1079270346Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 1080299549Serj#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 1081299549Serj#define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 1082270346Sjfv u8 enable_tcs; 1083270346Sjfv u8 reserved[9]; 1084266423Sjfv}; 1085266423Sjfv 1086266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 1087266423Sjfv 1088266423Sjfvstruct i40e_aqc_add_veb_completion { 1089270346Sjfv u8 reserved[6]; 1090270346Sjfv __le16 switch_seid; 1091266423Sjfv /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 1092270346Sjfv __le16 veb_seid; 1093270346Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 1094270346Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 1095270346Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 1096270346Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 1097270346Sjfv __le16 statistic_index; 1098270346Sjfv __le16 vebs_used; 1099270346Sjfv __le16 vebs_free; 1100266423Sjfv}; 1101266423Sjfv 1102266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 1103266423Sjfv 1104266423Sjfv/* Get VEB Parameters (direct 0x0232) 1105266423Sjfv * uses i40e_aqc_switch_seid for the descriptor 1106266423Sjfv */ 1107266423Sjfvstruct i40e_aqc_get_veb_parameters_completion { 1108270346Sjfv __le16 seid; 1109270346Sjfv __le16 switch_id; 1110270346Sjfv __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 1111270346Sjfv __le16 statistic_index; 1112270346Sjfv __le16 vebs_used; 1113270346Sjfv __le16 vebs_free; 1114270346Sjfv u8 reserved[4]; 1115266423Sjfv}; 1116266423Sjfv 1117266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 1118266423Sjfv 1119266423Sjfv/* Delete Element (direct 0x0243) 1120266423Sjfv * uses the generic i40e_aqc_switch_seid 1121266423Sjfv */ 1122266423Sjfv 1123266423Sjfv/* Add MAC-VLAN (indirect 0x0250) */ 1124266423Sjfv 1125266423Sjfv/* used for the command for most vlan commands */ 1126266423Sjfvstruct i40e_aqc_macvlan { 1127270346Sjfv __le16 num_addresses; 1128270346Sjfv __le16 seid[3]; 1129270346Sjfv#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 1130270346Sjfv#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 1131266423Sjfv I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1132270346Sjfv#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 1133270346Sjfv __le32 addr_high; 1134270346Sjfv __le32 addr_low; 1135266423Sjfv}; 1136266423Sjfv 1137266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 1138266423Sjfv 1139266423Sjfv/* indirect data for command and response */ 1140266423Sjfvstruct i40e_aqc_add_macvlan_element_data { 1141270346Sjfv u8 mac_addr[6]; 1142270346Sjfv __le16 vlan_tag; 1143270346Sjfv __le16 flags; 1144270346Sjfv#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 1145270346Sjfv#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 1146270346Sjfv#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 1147270346Sjfv#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 1148299549Serj#define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 1149270346Sjfv __le16 queue_number; 1150270346Sjfv#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 1151270346Sjfv#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 1152266423Sjfv I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1153266423Sjfv /* response section */ 1154270346Sjfv u8 match_method; 1155270346Sjfv#define I40E_AQC_MM_PERFECT_MATCH 0x01 1156270346Sjfv#define I40E_AQC_MM_HASH_MATCH 0x02 1157270346Sjfv#define I40E_AQC_MM_ERR_NO_RES 0xFF 1158270346Sjfv u8 reserved1[3]; 1159266423Sjfv}; 1160266423Sjfv 1161266423Sjfvstruct i40e_aqc_add_remove_macvlan_completion { 1162266423Sjfv __le16 perfect_mac_used; 1163266423Sjfv __le16 perfect_mac_free; 1164266423Sjfv __le16 unicast_hash_free; 1165266423Sjfv __le16 multicast_hash_free; 1166266423Sjfv __le32 addr_high; 1167266423Sjfv __le32 addr_low; 1168266423Sjfv}; 1169266423Sjfv 1170266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1171266423Sjfv 1172266423Sjfv/* Remove MAC-VLAN (indirect 0x0251) 1173266423Sjfv * uses i40e_aqc_macvlan for the descriptor 1174266423Sjfv * data points to an array of num_addresses of elements 1175266423Sjfv */ 1176266423Sjfv 1177266423Sjfvstruct i40e_aqc_remove_macvlan_element_data { 1178270346Sjfv u8 mac_addr[6]; 1179270346Sjfv __le16 vlan_tag; 1180270346Sjfv u8 flags; 1181270346Sjfv#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1182270346Sjfv#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1183270346Sjfv#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1184270346Sjfv#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1185270346Sjfv u8 reserved[3]; 1186266423Sjfv /* reply section */ 1187270346Sjfv u8 error_code; 1188270346Sjfv#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1189270346Sjfv#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1190270346Sjfv u8 reply_reserved[3]; 1191266423Sjfv}; 1192266423Sjfv 1193266423Sjfv/* Add VLAN (indirect 0x0252) 1194266423Sjfv * Remove VLAN (indirect 0x0253) 1195266423Sjfv * use the generic i40e_aqc_macvlan for the command 1196266423Sjfv */ 1197266423Sjfvstruct i40e_aqc_add_remove_vlan_element_data { 1198270346Sjfv __le16 vlan_tag; 1199270346Sjfv u8 vlan_flags; 1200266423Sjfv/* flags for add VLAN */ 1201270346Sjfv#define I40E_AQC_ADD_VLAN_LOCAL 0x1 1202270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1203270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1204270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1205270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1206270346Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1207270346Sjfv#define I40E_AQC_VLAN_PTYPE_SHIFT 3 1208270346Sjfv#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1209270346Sjfv#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1210270346Sjfv#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1211270346Sjfv#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1212270346Sjfv#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1213266423Sjfv/* flags for remove VLAN */ 1214270346Sjfv#define I40E_AQC_REMOVE_VLAN_ALL 0x1 1215270346Sjfv u8 reserved; 1216270346Sjfv u8 result; 1217266423Sjfv/* flags for add VLAN */ 1218270346Sjfv#define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1219270346Sjfv#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1220270346Sjfv#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1221266423Sjfv/* flags for remove VLAN */ 1222270346Sjfv#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1223270346Sjfv#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1224270346Sjfv u8 reserved1[3]; 1225266423Sjfv}; 1226266423Sjfv 1227266423Sjfvstruct i40e_aqc_add_remove_vlan_completion { 1228270346Sjfv u8 reserved[4]; 1229270346Sjfv __le16 vlans_used; 1230270346Sjfv __le16 vlans_free; 1231270346Sjfv __le32 addr_high; 1232270346Sjfv __le32 addr_low; 1233266423Sjfv}; 1234266423Sjfv 1235266423Sjfv/* Set VSI Promiscuous Modes (direct 0x0254) */ 1236266423Sjfvstruct i40e_aqc_set_vsi_promiscuous_modes { 1237270346Sjfv __le16 promiscuous_flags; 1238270346Sjfv __le16 valid_flags; 1239266423Sjfv/* flags used for both fields above */ 1240270346Sjfv#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1241270346Sjfv#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1242270346Sjfv#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1243270346Sjfv#define I40E_AQC_SET_VSI_DEFAULT 0x08 1244270346Sjfv#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1245299554Serj#define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 1246270346Sjfv __le16 seid; 1247270346Sjfv#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1248270346Sjfv __le16 vlan_tag; 1249284049Sjfv#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1250270346Sjfv#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1251270346Sjfv u8 reserved[8]; 1252266423Sjfv}; 1253266423Sjfv 1254266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1255266423Sjfv 1256266423Sjfv/* Add S/E-tag command (direct 0x0255) 1257266423Sjfv * Uses generic i40e_aqc_add_remove_tag_completion for completion 1258266423Sjfv */ 1259266423Sjfvstruct i40e_aqc_add_tag { 1260270346Sjfv __le16 flags; 1261270346Sjfv#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1262270346Sjfv __le16 seid; 1263270346Sjfv#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1264270346Sjfv#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1265266423Sjfv I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1266270346Sjfv __le16 tag; 1267270346Sjfv __le16 queue_number; 1268270346Sjfv u8 reserved[8]; 1269266423Sjfv}; 1270266423Sjfv 1271266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1272266423Sjfv 1273266423Sjfvstruct i40e_aqc_add_remove_tag_completion { 1274270346Sjfv u8 reserved[12]; 1275270346Sjfv __le16 tags_used; 1276270346Sjfv __le16 tags_free; 1277266423Sjfv}; 1278266423Sjfv 1279266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1280266423Sjfv 1281266423Sjfv/* Remove S/E-tag command (direct 0x0256) 1282266423Sjfv * Uses generic i40e_aqc_add_remove_tag_completion for completion 1283266423Sjfv */ 1284266423Sjfvstruct i40e_aqc_remove_tag { 1285270346Sjfv __le16 seid; 1286270346Sjfv#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1287270346Sjfv#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1288266423Sjfv I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1289270346Sjfv __le16 tag; 1290270346Sjfv u8 reserved[12]; 1291266423Sjfv}; 1292266423Sjfv 1293277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1294277082Sjfv 1295266423Sjfv/* Add multicast E-Tag (direct 0x0257) 1296266423Sjfv * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1297266423Sjfv * and no external data 1298266423Sjfv */ 1299266423Sjfvstruct i40e_aqc_add_remove_mcast_etag { 1300270346Sjfv __le16 pv_seid; 1301270346Sjfv __le16 etag; 1302270346Sjfv u8 num_unicast_etags; 1303270346Sjfv u8 reserved[3]; 1304270346Sjfv __le32 addr_high; /* address of array of 2-byte s-tags */ 1305270346Sjfv __le32 addr_low; 1306266423Sjfv}; 1307266423Sjfv 1308266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1309266423Sjfv 1310266423Sjfvstruct i40e_aqc_add_remove_mcast_etag_completion { 1311270346Sjfv u8 reserved[4]; 1312270346Sjfv __le16 mcast_etags_used; 1313270346Sjfv __le16 mcast_etags_free; 1314270346Sjfv __le32 addr_high; 1315270346Sjfv __le32 addr_low; 1316266423Sjfv 1317266423Sjfv}; 1318266423Sjfv 1319266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1320266423Sjfv 1321266423Sjfv/* Update S/E-Tag (direct 0x0259) */ 1322266423Sjfvstruct i40e_aqc_update_tag { 1323270346Sjfv __le16 seid; 1324270346Sjfv#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1325270346Sjfv#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1326266423Sjfv I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1327270346Sjfv __le16 old_tag; 1328270346Sjfv __le16 new_tag; 1329270346Sjfv u8 reserved[10]; 1330266423Sjfv}; 1331266423Sjfv 1332266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1333266423Sjfv 1334266423Sjfvstruct i40e_aqc_update_tag_completion { 1335270346Sjfv u8 reserved[12]; 1336270346Sjfv __le16 tags_used; 1337270346Sjfv __le16 tags_free; 1338266423Sjfv}; 1339266423Sjfv 1340266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1341266423Sjfv 1342266423Sjfv/* Add Control Packet filter (direct 0x025A) 1343266423Sjfv * Remove Control Packet filter (direct 0x025B) 1344266423Sjfv * uses the i40e_aqc_add_oveb_cloud, 1345266423Sjfv * and the generic direct completion structure 1346266423Sjfv */ 1347266423Sjfvstruct i40e_aqc_add_remove_control_packet_filter { 1348270346Sjfv u8 mac[6]; 1349270346Sjfv __le16 etype; 1350270346Sjfv __le16 flags; 1351270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1352270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1353270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1354270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1355270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1356270346Sjfv __le16 seid; 1357270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1358270346Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1359266423Sjfv I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1360270346Sjfv __le16 queue; 1361270346Sjfv u8 reserved[2]; 1362266423Sjfv}; 1363266423Sjfv 1364266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1365266423Sjfv 1366266423Sjfvstruct i40e_aqc_add_remove_control_packet_filter_completion { 1367270346Sjfv __le16 mac_etype_used; 1368270346Sjfv __le16 etype_used; 1369270346Sjfv __le16 mac_etype_free; 1370270346Sjfv __le16 etype_free; 1371270346Sjfv u8 reserved[8]; 1372266423Sjfv}; 1373266423Sjfv 1374266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1375266423Sjfv 1376266423Sjfv/* Add Cloud filters (indirect 0x025C) 1377266423Sjfv * Remove Cloud filters (indirect 0x025D) 1378266423Sjfv * uses the i40e_aqc_add_remove_cloud_filters, 1379266423Sjfv * and the generic indirect completion structure 1380266423Sjfv */ 1381266423Sjfvstruct i40e_aqc_add_remove_cloud_filters { 1382270346Sjfv u8 num_filters; 1383270346Sjfv u8 reserved; 1384270346Sjfv __le16 seid; 1385270346Sjfv#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1386270346Sjfv#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1387266423Sjfv I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1388270346Sjfv u8 reserved2[4]; 1389270346Sjfv __le32 addr_high; 1390270346Sjfv __le32 addr_low; 1391266423Sjfv}; 1392266423Sjfv 1393266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1394266423Sjfv 1395266423Sjfvstruct i40e_aqc_add_remove_cloud_filters_element_data { 1396270346Sjfv u8 outer_mac[6]; 1397270346Sjfv u8 inner_mac[6]; 1398270346Sjfv __le16 inner_vlan; 1399266423Sjfv union { 1400266423Sjfv struct { 1401266423Sjfv u8 reserved[12]; 1402266423Sjfv u8 data[4]; 1403266423Sjfv } v4; 1404266423Sjfv struct { 1405266423Sjfv u8 data[16]; 1406266423Sjfv } v6; 1407266423Sjfv } ipaddr; 1408270346Sjfv __le16 flags; 1409270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1410277082Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1411266423Sjfv I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1412266423Sjfv/* 0x0000 reserved */ 1413270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1414266423Sjfv/* 0x0002 reserved */ 1415270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1416270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1417266423Sjfv/* 0x0005 reserved */ 1418270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1419266423Sjfv/* 0x0007 reserved */ 1420266423Sjfv/* 0x0008 reserved */ 1421270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1422270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1423270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1424270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1425266423Sjfv 1426270346Sjfv#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1427270346Sjfv#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1428270346Sjfv#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1429270346Sjfv#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1430270346Sjfv#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1431266423Sjfv 1432270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1433270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1434299549Serj#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1435270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1436299549Serj#define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1437270346Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1438299549Serj#define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1439299549Serj#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1440266423Sjfv 1441299549Serj#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1442299549Serj#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1443299549Serj#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1444299549Serj 1445270346Sjfv __le32 tenant_id; 1446270346Sjfv u8 reserved[4]; 1447270346Sjfv __le16 queue_number; 1448270346Sjfv#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1449277082Sjfv#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1450270346Sjfv I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1451270346Sjfv u8 reserved2[14]; 1452266423Sjfv /* response section */ 1453270346Sjfv u8 allocation_result; 1454270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1455270346Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1456270346Sjfv u8 response_reserved[7]; 1457266423Sjfv}; 1458266423Sjfv 1459266423Sjfvstruct i40e_aqc_remove_cloud_filters_completion { 1460266423Sjfv __le16 perfect_ovlan_used; 1461266423Sjfv __le16 perfect_ovlan_free; 1462266423Sjfv __le16 vlan_used; 1463266423Sjfv __le16 vlan_free; 1464266423Sjfv __le32 addr_high; 1465266423Sjfv __le32 addr_low; 1466266423Sjfv}; 1467266423Sjfv 1468266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1469266423Sjfv 1470266423Sjfv/* Add Mirror Rule (indirect or direct 0x0260) 1471266423Sjfv * Delete Mirror Rule (indirect or direct 0x0261) 1472266423Sjfv * note: some rule types (4,5) do not use an external buffer. 1473266423Sjfv * take care to set the flags correctly. 1474266423Sjfv */ 1475266423Sjfvstruct i40e_aqc_add_delete_mirror_rule { 1476266423Sjfv __le16 seid; 1477266423Sjfv __le16 rule_type; 1478270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1479270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1480266423Sjfv I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1481270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1482270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1483270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1484270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1485270346Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1486266423Sjfv __le16 num_entries; 1487266423Sjfv __le16 destination; /* VSI for add, rule id for delete */ 1488266423Sjfv __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1489266423Sjfv __le32 addr_low; 1490266423Sjfv}; 1491266423Sjfv 1492266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1493266423Sjfv 1494266423Sjfvstruct i40e_aqc_add_delete_mirror_rule_completion { 1495270346Sjfv u8 reserved[2]; 1496270346Sjfv __le16 rule_id; /* only used on add */ 1497270346Sjfv __le16 mirror_rules_used; 1498270346Sjfv __le16 mirror_rules_free; 1499270346Sjfv __le32 addr_high; 1500270346Sjfv __le32 addr_low; 1501266423Sjfv}; 1502266423Sjfv 1503266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1504266423Sjfv 1505266423Sjfv/* DCB 0x03xx*/ 1506266423Sjfv 1507266423Sjfv/* PFC Ignore (direct 0x0301) 1508266423Sjfv * the command and response use the same descriptor structure 1509266423Sjfv */ 1510266423Sjfvstruct i40e_aqc_pfc_ignore { 1511270346Sjfv u8 tc_bitmap; 1512270346Sjfv u8 command_flags; /* unused on response */ 1513270346Sjfv#define I40E_AQC_PFC_IGNORE_SET 0x80 1514270346Sjfv#define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1515270346Sjfv u8 reserved[14]; 1516266423Sjfv}; 1517266423Sjfv 1518266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1519266423Sjfv 1520266423Sjfv/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1521266423Sjfv * with no parameters 1522266423Sjfv */ 1523266423Sjfv 1524266423Sjfv/* TX scheduler 0x04xx */ 1525266423Sjfv 1526266423Sjfv/* Almost all the indirect commands use 1527266423Sjfv * this generic struct to pass the SEID in param0 1528266423Sjfv */ 1529266423Sjfvstruct i40e_aqc_tx_sched_ind { 1530270346Sjfv __le16 vsi_seid; 1531270346Sjfv u8 reserved[6]; 1532270346Sjfv __le32 addr_high; 1533270346Sjfv __le32 addr_low; 1534266423Sjfv}; 1535266423Sjfv 1536266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1537266423Sjfv 1538266423Sjfv/* Several commands respond with a set of queue set handles */ 1539266423Sjfvstruct i40e_aqc_qs_handles_resp { 1540266423Sjfv __le16 qs_handles[8]; 1541266423Sjfv}; 1542266423Sjfv 1543266423Sjfv/* Configure VSI BW limits (direct 0x0400) */ 1544266423Sjfvstruct i40e_aqc_configure_vsi_bw_limit { 1545270346Sjfv __le16 vsi_seid; 1546270346Sjfv u8 reserved[2]; 1547270346Sjfv __le16 credit; 1548270346Sjfv u8 reserved1[2]; 1549270346Sjfv u8 max_credit; /* 0-3, limit = 2^max */ 1550270346Sjfv u8 reserved2[7]; 1551266423Sjfv}; 1552266423Sjfv 1553266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1554266423Sjfv 1555266423Sjfv/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1556266423Sjfv * responds with i40e_aqc_qs_handles_resp 1557266423Sjfv */ 1558266423Sjfvstruct i40e_aqc_configure_vsi_ets_sla_bw_data { 1559270346Sjfv u8 tc_valid_bits; 1560270346Sjfv u8 reserved[15]; 1561270346Sjfv __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1562266423Sjfv 1563266423Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1564270346Sjfv __le16 tc_bw_max[2]; 1565270346Sjfv u8 reserved1[28]; 1566266423Sjfv}; 1567266423Sjfv 1568277082SjfvI40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1569277082Sjfv 1570266423Sjfv/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1571266423Sjfv * responds with i40e_aqc_qs_handles_resp 1572266423Sjfv */ 1573266423Sjfvstruct i40e_aqc_configure_vsi_tc_bw_data { 1574270346Sjfv u8 tc_valid_bits; 1575270346Sjfv u8 reserved[3]; 1576270346Sjfv u8 tc_bw_credits[8]; 1577270346Sjfv u8 reserved1[4]; 1578270346Sjfv __le16 qs_handles[8]; 1579266423Sjfv}; 1580266423Sjfv 1581277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1582277082Sjfv 1583266423Sjfv/* Query vsi bw configuration (indirect 0x0408) */ 1584266423Sjfvstruct i40e_aqc_query_vsi_bw_config_resp { 1585270346Sjfv u8 tc_valid_bits; 1586270346Sjfv u8 tc_suspended_bits; 1587270346Sjfv u8 reserved[14]; 1588270346Sjfv __le16 qs_handles[8]; 1589270346Sjfv u8 reserved1[4]; 1590270346Sjfv __le16 port_bw_limit; 1591270346Sjfv u8 reserved2[2]; 1592270346Sjfv u8 max_bw; /* 0-3, limit = 2^max */ 1593270346Sjfv u8 reserved3[23]; 1594266423Sjfv}; 1595266423Sjfv 1596277082SjfvI40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1597277082Sjfv 1598266423Sjfv/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1599266423Sjfvstruct i40e_aqc_query_vsi_ets_sla_config_resp { 1600270346Sjfv u8 tc_valid_bits; 1601270346Sjfv u8 reserved[3]; 1602270346Sjfv u8 share_credits[8]; 1603270346Sjfv __le16 credits[8]; 1604266423Sjfv 1605266423Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1606270346Sjfv __le16 tc_bw_max[2]; 1607266423Sjfv}; 1608266423Sjfv 1609277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1610277082Sjfv 1611266423Sjfv/* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1612266423Sjfvstruct i40e_aqc_configure_switching_comp_bw_limit { 1613270346Sjfv __le16 seid; 1614270346Sjfv u8 reserved[2]; 1615270346Sjfv __le16 credit; 1616270346Sjfv u8 reserved1[2]; 1617270346Sjfv u8 max_bw; /* 0-3, limit = 2^max */ 1618270346Sjfv u8 reserved2[7]; 1619266423Sjfv}; 1620266423Sjfv 1621266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1622266423Sjfv 1623266423Sjfv/* Enable Physical Port ETS (indirect 0x0413) 1624266423Sjfv * Modify Physical Port ETS (indirect 0x0414) 1625266423Sjfv * Disable Physical Port ETS (indirect 0x0415) 1626266423Sjfv */ 1627266423Sjfvstruct i40e_aqc_configure_switching_comp_ets_data { 1628270346Sjfv u8 reserved[4]; 1629270346Sjfv u8 tc_valid_bits; 1630270346Sjfv u8 seepage; 1631270346Sjfv#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1632270346Sjfv u8 tc_strict_priority_flags; 1633270346Sjfv u8 reserved1[17]; 1634270346Sjfv u8 tc_bw_share_credits[8]; 1635270346Sjfv u8 reserved2[96]; 1636266423Sjfv}; 1637266423Sjfv 1638277082SjfvI40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1639277082Sjfv 1640266423Sjfv/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1641266423Sjfvstruct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1642270346Sjfv u8 tc_valid_bits; 1643270346Sjfv u8 reserved[15]; 1644270346Sjfv __le16 tc_bw_credit[8]; 1645266423Sjfv 1646266423Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1647270346Sjfv __le16 tc_bw_max[2]; 1648270346Sjfv u8 reserved1[28]; 1649266423Sjfv}; 1650266423Sjfv 1651299555SerjI40E_CHECK_STRUCT_LEN(0x40, 1652299555Serj i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1653277082Sjfv 1654266423Sjfv/* Configure Switching Component Bandwidth Allocation per Tc 1655266423Sjfv * (indirect 0x0417) 1656266423Sjfv */ 1657266423Sjfvstruct i40e_aqc_configure_switching_comp_bw_config_data { 1658270346Sjfv u8 tc_valid_bits; 1659270346Sjfv u8 reserved[2]; 1660270346Sjfv u8 absolute_credits; /* bool */ 1661270346Sjfv u8 tc_bw_share_credits[8]; 1662270346Sjfv u8 reserved1[20]; 1663266423Sjfv}; 1664266423Sjfv 1665277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1666277082Sjfv 1667266423Sjfv/* Query Switching Component Configuration (indirect 0x0418) */ 1668266423Sjfvstruct i40e_aqc_query_switching_comp_ets_config_resp { 1669270346Sjfv u8 tc_valid_bits; 1670270346Sjfv u8 reserved[35]; 1671270346Sjfv __le16 port_bw_limit; 1672270346Sjfv u8 reserved1[2]; 1673270346Sjfv u8 tc_bw_max; /* 0-3, limit = 2^max */ 1674270346Sjfv u8 reserved2[23]; 1675266423Sjfv}; 1676266423Sjfv 1677277082SjfvI40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1678277082Sjfv 1679266423Sjfv/* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1680266423Sjfvstruct i40e_aqc_query_port_ets_config_resp { 1681270346Sjfv u8 reserved[4]; 1682270346Sjfv u8 tc_valid_bits; 1683270346Sjfv u8 reserved1; 1684270346Sjfv u8 tc_strict_priority_bits; 1685270346Sjfv u8 reserved2; 1686270346Sjfv u8 tc_bw_share_credits[8]; 1687270346Sjfv __le16 tc_bw_limits[8]; 1688266423Sjfv 1689266423Sjfv /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1690270346Sjfv __le16 tc_bw_max[2]; 1691270346Sjfv u8 reserved3[32]; 1692266423Sjfv}; 1693266423Sjfv 1694277082SjfvI40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1695277082Sjfv 1696266423Sjfv/* Query Switching Component Bandwidth Allocation per Traffic Type 1697266423Sjfv * (indirect 0x041A) 1698266423Sjfv */ 1699266423Sjfvstruct i40e_aqc_query_switching_comp_bw_config_resp { 1700270346Sjfv u8 tc_valid_bits; 1701270346Sjfv u8 reserved[2]; 1702270346Sjfv u8 absolute_credits_enable; /* bool */ 1703270346Sjfv u8 tc_bw_share_credits[8]; 1704270346Sjfv __le16 tc_bw_limits[8]; 1705266423Sjfv 1706266423Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1707270346Sjfv __le16 tc_bw_max[2]; 1708266423Sjfv}; 1709266423Sjfv 1710277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1711277082Sjfv 1712266423Sjfv/* Suspend/resume port TX traffic 1713266423Sjfv * (direct 0x041B and 0x041C) uses the generic SEID struct 1714266423Sjfv */ 1715266423Sjfv 1716266423Sjfv/* Configure partition BW 1717266423Sjfv * (indirect 0x041D) 1718266423Sjfv */ 1719266423Sjfvstruct i40e_aqc_configure_partition_bw_data { 1720270346Sjfv __le16 pf_valid_bits; 1721270346Sjfv u8 min_bw[16]; /* guaranteed bandwidth */ 1722270346Sjfv u8 max_bw[16]; /* bandwidth limit */ 1723266423Sjfv}; 1724266423Sjfv 1725277082SjfvI40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1726277082Sjfv 1727266423Sjfv/* Get and set the active HMC resource profile and status. 1728266423Sjfv * (direct 0x0500) and (direct 0x0501) 1729266423Sjfv */ 1730266423Sjfvstruct i40e_aq_get_set_hmc_resource_profile { 1731270346Sjfv u8 pm_profile; 1732270346Sjfv u8 pe_vf_enabled; 1733270346Sjfv u8 reserved[14]; 1734266423Sjfv}; 1735266423Sjfv 1736266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1737266423Sjfv 1738266423Sjfvenum i40e_aq_hmc_profile { 1739303967Ssbruno /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1740270346Sjfv I40E_HMC_PROFILE_DEFAULT = 1, 1741270346Sjfv I40E_HMC_PROFILE_FAVOR_VF = 2, 1742270346Sjfv I40E_HMC_PROFILE_EQUAL = 3, 1743266423Sjfv}; 1744266423Sjfv 1745266423Sjfv/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1746266423Sjfv 1747266423Sjfv/* set in param0 for get phy abilities to report qualified modules */ 1748270346Sjfv#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1749270346Sjfv#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1750266423Sjfv 1751266423Sjfvenum i40e_aq_phy_type { 1752266423Sjfv I40E_PHY_TYPE_SGMII = 0x0, 1753266423Sjfv I40E_PHY_TYPE_1000BASE_KX = 0x1, 1754266423Sjfv I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1755266423Sjfv I40E_PHY_TYPE_10GBASE_KR = 0x3, 1756266423Sjfv I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1757266423Sjfv I40E_PHY_TYPE_XAUI = 0x5, 1758266423Sjfv I40E_PHY_TYPE_XFI = 0x6, 1759266423Sjfv I40E_PHY_TYPE_SFI = 0x7, 1760266423Sjfv I40E_PHY_TYPE_XLAUI = 0x8, 1761266423Sjfv I40E_PHY_TYPE_XLPPI = 0x9, 1762266423Sjfv I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1763266423Sjfv I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1764266423Sjfv I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1765266423Sjfv I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1766333343Serj I40E_PHY_TYPE_UNRECOGNIZED = 0xE, 1767333343Serj I40E_PHY_TYPE_UNSUPPORTED = 0xF, 1768266423Sjfv I40E_PHY_TYPE_100BASE_TX = 0x11, 1769266423Sjfv I40E_PHY_TYPE_1000BASE_T = 0x12, 1770266423Sjfv I40E_PHY_TYPE_10GBASE_T = 0x13, 1771266423Sjfv I40E_PHY_TYPE_10GBASE_SR = 0x14, 1772266423Sjfv I40E_PHY_TYPE_10GBASE_LR = 0x15, 1773266423Sjfv I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1774266423Sjfv I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1775266423Sjfv I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1776266423Sjfv I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1777266423Sjfv I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1778266423Sjfv I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1779266423Sjfv I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1780266423Sjfv I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1781266423Sjfv I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1782303967Ssbruno I40E_PHY_TYPE_25GBASE_KR = 0x1F, 1783303967Ssbruno I40E_PHY_TYPE_25GBASE_CR = 0x20, 1784303967Ssbruno I40E_PHY_TYPE_25GBASE_SR = 0x21, 1785303967Ssbruno I40E_PHY_TYPE_25GBASE_LR = 0x22, 1786333343Serj I40E_PHY_TYPE_25GBASE_AOC = 0x23, 1787333343Serj I40E_PHY_TYPE_25GBASE_ACC = 0x24, 1788349163Serj I40E_PHY_TYPE_2_5GBASE_T = 0x30, 1789349163Serj I40E_PHY_TYPE_5GBASE_T = 0x31, 1790333343Serj I40E_PHY_TYPE_MAX, 1791333343Serj I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD, 1792333343Serj I40E_PHY_TYPE_EMPTY = 0xFE, 1793333343Serj I40E_PHY_TYPE_DEFAULT = 0xFF, 1794266423Sjfv}; 1795266423Sjfv 1796333343Serj#define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \ 1797333343Serj BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \ 1798333343Serj BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \ 1799333343Serj BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \ 1800333343Serj BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \ 1801333343Serj BIT_ULL(I40E_PHY_TYPE_XAUI) | \ 1802333343Serj BIT_ULL(I40E_PHY_TYPE_XFI) | \ 1803333343Serj BIT_ULL(I40E_PHY_TYPE_SFI) | \ 1804333343Serj BIT_ULL(I40E_PHY_TYPE_XLAUI) | \ 1805333343Serj BIT_ULL(I40E_PHY_TYPE_XLPPI) | \ 1806333343Serj BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \ 1807333343Serj BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \ 1808333343Serj BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \ 1809333343Serj BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \ 1810333343Serj BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \ 1811333343Serj BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \ 1812333343Serj BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \ 1813333343Serj BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \ 1814333343Serj BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \ 1815333343Serj BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \ 1816333343Serj BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \ 1817333343Serj BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \ 1818333343Serj BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \ 1819333343Serj BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \ 1820333343Serj BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \ 1821333343Serj BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \ 1822333343Serj BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \ 1823333343Serj BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \ 1824333343Serj BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \ 1825333343Serj BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \ 1826333343Serj BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \ 1827333343Serj BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \ 1828333343Serj BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \ 1829333343Serj BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \ 1830333343Serj BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \ 1831349163Serj BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \ 1832349163Serj BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \ 1833349163Serj BIT_ULL(I40E_PHY_TYPE_5GBASE_T)) 1834333343Serj 1835349163Serj#define I40E_LINK_SPEED_2_5GB_SHIFT 0x0 1836266423Sjfv#define I40E_LINK_SPEED_100MB_SHIFT 0x1 1837266423Sjfv#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1838266423Sjfv#define I40E_LINK_SPEED_10GB_SHIFT 0x3 1839266423Sjfv#define I40E_LINK_SPEED_40GB_SHIFT 0x4 1840266423Sjfv#define I40E_LINK_SPEED_20GB_SHIFT 0x5 1841303967Ssbruno#define I40E_LINK_SPEED_25GB_SHIFT 0x6 1842349163Serj#define I40E_LINK_SPEED_5GB_SHIFT 0x7 1843266423Sjfv 1844266423Sjfvenum i40e_aq_link_speed { 1845266423Sjfv I40E_LINK_SPEED_UNKNOWN = 0, 1846266423Sjfv I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1847266423Sjfv I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1848349163Serj I40E_LINK_SPEED_2_5GB = (1 << I40E_LINK_SPEED_2_5GB_SHIFT), 1849349163Serj I40E_LINK_SPEED_5GB = (1 << I40E_LINK_SPEED_5GB_SHIFT), 1850266423Sjfv I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1851266423Sjfv I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1852303967Ssbruno I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT), 1853303967Ssbruno I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT), 1854266423Sjfv}; 1855266423Sjfv 1856266423Sjfvstruct i40e_aqc_module_desc { 1857266423Sjfv u8 oui[3]; 1858266423Sjfv u8 reserved1; 1859266423Sjfv u8 part_number[16]; 1860266423Sjfv u8 revision[4]; 1861266423Sjfv u8 reserved2[8]; 1862266423Sjfv}; 1863266423Sjfv 1864277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1865277082Sjfv 1866266423Sjfvstruct i40e_aq_get_phy_abilities_resp { 1867270346Sjfv __le32 phy_type; /* bitmap using the above enum for offsets */ 1868270346Sjfv u8 link_speed; /* bitmap using the above enum bit patterns */ 1869270346Sjfv u8 abilities; 1870270346Sjfv#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1871270346Sjfv#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1872270346Sjfv#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1873270346Sjfv#define I40E_AQ_PHY_LINK_ENABLED 0x08 1874270346Sjfv#define I40E_AQ_PHY_AN_ENABLED 0x10 1875270346Sjfv#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1876318357Serj#define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 1877318357Serj#define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 1878270346Sjfv __le16 eee_capability; 1879349163Serj#define I40E_AQ_EEE_AUTO 0x0001 1880270346Sjfv#define I40E_AQ_EEE_100BASE_TX 0x0002 1881270346Sjfv#define I40E_AQ_EEE_1000BASE_T 0x0004 1882270346Sjfv#define I40E_AQ_EEE_10GBASE_T 0x0008 1883270346Sjfv#define I40E_AQ_EEE_1000BASE_KX 0x0010 1884270346Sjfv#define I40E_AQ_EEE_10GBASE_KX4 0x0020 1885270346Sjfv#define I40E_AQ_EEE_10GBASE_KR 0x0040 1886349163Serj#define I40E_AQ_EEE_2_5GBASE_T 0x0100 1887349163Serj#define I40E_AQ_EEE_5GBASE_T 0x0200 1888270346Sjfv __le32 eeer_val; 1889270346Sjfv u8 d3_lpan; 1890270346Sjfv#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1891303967Ssbruno u8 phy_type_ext; 1892318357Serj#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01 1893318357Serj#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02 1894303967Ssbruno#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 1895303967Ssbruno#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 1896333343Serj#define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10 1897333343Serj#define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20 1898349163Serj#define I40E_AQ_PHY_TYPE_EXT_2_5GBASE_T 0x40 1899349163Serj#define I40E_AQ_PHY_TYPE_EXT_5GBASE_T 0x80 1900318357Serj u8 fec_cfg_curr_mod_ext_info; 1901318357Serj#define I40E_AQ_ENABLE_FEC_KR 0x01 1902318357Serj#define I40E_AQ_ENABLE_FEC_RS 0x02 1903318357Serj#define I40E_AQ_REQUEST_FEC_KR 0x04 1904318357Serj#define I40E_AQ_REQUEST_FEC_RS 0x08 1905318357Serj#define I40E_AQ_ENABLE_FEC_AUTO 0x10 1906318357Serj#define I40E_AQ_FEC 1907318357Serj#define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 1908318357Serj#define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5 1909318357Serj 1910303967Ssbruno u8 ext_comp_code; 1911270346Sjfv u8 phy_id[4]; 1912270346Sjfv u8 module_type[3]; 1913270346Sjfv u8 qualified_module_count; 1914270346Sjfv#define I40E_AQ_PHY_MAX_QMS 16 1915270346Sjfv struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1916266423Sjfv}; 1917266423Sjfv 1918277082SjfvI40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1919277082Sjfv 1920266423Sjfv/* Set PHY Config (direct 0x0601) */ 1921266423Sjfvstruct i40e_aq_set_phy_config { /* same bits as above in all */ 1922270346Sjfv __le32 phy_type; 1923270346Sjfv u8 link_speed; 1924270346Sjfv u8 abilities; 1925266423Sjfv/* bits 0-2 use the values from get_phy_abilities_resp */ 1926266423Sjfv#define I40E_AQ_PHY_ENABLE_LINK 0x08 1927266423Sjfv#define I40E_AQ_PHY_ENABLE_AN 0x10 1928266423Sjfv#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1929270346Sjfv __le16 eee_capability; 1930270346Sjfv __le32 eeer; 1931270346Sjfv u8 low_power_ctrl; 1932303967Ssbruno u8 phy_type_ext; 1933318357Serj u8 fec_config; 1934318357Serj#define I40E_AQ_SET_FEC_ABILITY_KR BIT(0) 1935318357Serj#define I40E_AQ_SET_FEC_ABILITY_RS BIT(1) 1936318357Serj#define I40E_AQ_SET_FEC_REQUEST_KR BIT(2) 1937318357Serj#define I40E_AQ_SET_FEC_REQUEST_RS BIT(3) 1938318357Serj#define I40E_AQ_SET_FEC_AUTO BIT(4) 1939318357Serj#define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0 1940318357Serj#define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT) 1941318357Serj u8 reserved; 1942266423Sjfv}; 1943266423Sjfv 1944266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1945266423Sjfv 1946266423Sjfv/* Set MAC Config command data structure (direct 0x0603) */ 1947266423Sjfvstruct i40e_aq_set_mac_config { 1948270346Sjfv __le16 max_frame_size; 1949270346Sjfv u8 params; 1950270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1951270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1952270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1953270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1954270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1955270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1956270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1957270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1958270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1959270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1960270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1961270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1962270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1963270346Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1964270346Sjfv u8 tx_timer_priority; /* bitmap */ 1965270346Sjfv __le16 tx_timer_value; 1966270346Sjfv __le16 fc_refresh_threshold; 1967270346Sjfv u8 reserved[8]; 1968266423Sjfv}; 1969266423Sjfv 1970266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1971266423Sjfv 1972266423Sjfv/* Restart Auto-Negotiation (direct 0x605) */ 1973266423Sjfvstruct i40e_aqc_set_link_restart_an { 1974270346Sjfv u8 command; 1975270346Sjfv#define I40E_AQ_PHY_RESTART_AN 0x02 1976270346Sjfv#define I40E_AQ_PHY_LINK_ENABLE 0x04 1977270346Sjfv u8 reserved[15]; 1978266423Sjfv}; 1979266423Sjfv 1980266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1981266423Sjfv 1982266423Sjfv/* Get Link Status cmd & response data structure (direct 0x0607) */ 1983266423Sjfvstruct i40e_aqc_get_link_status { 1984270346Sjfv __le16 command_flags; /* only field set on command */ 1985270346Sjfv#define I40E_AQ_LSE_MASK 0x3 1986270346Sjfv#define I40E_AQ_LSE_NOP 0x0 1987270346Sjfv#define I40E_AQ_LSE_DISABLE 0x2 1988270346Sjfv#define I40E_AQ_LSE_ENABLE 0x3 1989266423Sjfv/* only response uses this flag */ 1990270346Sjfv#define I40E_AQ_LSE_IS_ENABLED 0x1 1991270346Sjfv u8 phy_type; /* i40e_aq_phy_type */ 1992270346Sjfv u8 link_speed; /* i40e_aq_link_speed */ 1993270346Sjfv u8 link_info; 1994284049Sjfv#define I40E_AQ_LINK_UP 0x01 /* obsolete */ 1995284049Sjfv#define I40E_AQ_LINK_UP_FUNCTION 0x01 1996270346Sjfv#define I40E_AQ_LINK_FAULT 0x02 1997270346Sjfv#define I40E_AQ_LINK_FAULT_TX 0x04 1998270346Sjfv#define I40E_AQ_LINK_FAULT_RX 0x08 1999270346Sjfv#define I40E_AQ_LINK_FAULT_REMOTE 0x10 2000284049Sjfv#define I40E_AQ_LINK_UP_PORT 0x20 2001270346Sjfv#define I40E_AQ_MEDIA_AVAILABLE 0x40 2002270346Sjfv#define I40E_AQ_SIGNAL_DETECT 0x80 2003270346Sjfv u8 an_info; 2004270346Sjfv#define I40E_AQ_AN_COMPLETED 0x01 2005270346Sjfv#define I40E_AQ_LP_AN_ABILITY 0x02 2006270346Sjfv#define I40E_AQ_PD_FAULT 0x04 2007270346Sjfv#define I40E_AQ_FEC_EN 0x08 2008270346Sjfv#define I40E_AQ_PHY_LOW_POWER 0x10 2009270346Sjfv#define I40E_AQ_LINK_PAUSE_TX 0x20 2010270346Sjfv#define I40E_AQ_LINK_PAUSE_RX 0x40 2011270346Sjfv#define I40E_AQ_QUALIFIED_MODULE 0x80 2012270346Sjfv u8 ext_info; 2013270346Sjfv#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 2014270346Sjfv#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 2015270346Sjfv#define I40E_AQ_LINK_TX_SHIFT 0x02 2016270346Sjfv#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 2017270346Sjfv#define I40E_AQ_LINK_TX_ACTIVE 0x00 2018270346Sjfv#define I40E_AQ_LINK_TX_DRAINED 0x01 2019270346Sjfv#define I40E_AQ_LINK_TX_FLUSHED 0x03 2020270346Sjfv#define I40E_AQ_LINK_FORCED_40G 0x10 2021303967Ssbruno/* 25G Error Codes */ 2022303967Ssbruno#define I40E_AQ_25G_NO_ERR 0X00 2023303967Ssbruno#define I40E_AQ_25G_NOT_PRESENT 0X01 2024303967Ssbruno#define I40E_AQ_25G_NVM_CRC_ERR 0X02 2025303967Ssbruno#define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 2026303967Ssbruno#define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 2027303967Ssbruno#define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 2028270346Sjfv u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 2029333343Serj/* Since firmware API 1.7 loopback field keeps power class info as well */ 2030333343Serj#define I40E_AQ_LOOPBACK_MASK 0x07 2031333343Serj#define I40E_AQ_PWR_CLASS_SHIFT_LB 6 2032333343Serj#define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB) 2033270346Sjfv __le16 max_frame_size; 2034270346Sjfv u8 config; 2035318357Serj#define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 2036318357Serj#define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 2037270346Sjfv#define I40E_AQ_CONFIG_CRC_ENA 0x04 2038270346Sjfv#define I40E_AQ_CONFIG_PACING_MASK 0x78 2039333343Serj union { 2040333343Serj struct { 2041333343Serj u8 power_desc; 2042299549Serj#define I40E_AQ_LINK_POWER_CLASS_1 0x00 2043299549Serj#define I40E_AQ_LINK_POWER_CLASS_2 0x01 2044299549Serj#define I40E_AQ_LINK_POWER_CLASS_3 0x02 2045299549Serj#define I40E_AQ_LINK_POWER_CLASS_4 0x03 2046303967Ssbruno#define I40E_AQ_PWR_CLASS_MASK 0x03 2047333343Serj u8 reserved[4]; 2048333343Serj }; 2049333343Serj struct { 2050333343Serj u8 link_type[4]; 2051333343Serj u8 link_type_ext; 2052333343Serj }; 2053333343Serj }; 2054266423Sjfv}; 2055266423Sjfv 2056266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 2057266423Sjfv 2058266423Sjfv/* Set event mask command (direct 0x613) */ 2059266423Sjfvstruct i40e_aqc_set_phy_int_mask { 2060270346Sjfv u8 reserved[8]; 2061270346Sjfv __le16 event_mask; 2062270346Sjfv#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 2063270346Sjfv#define I40E_AQ_EVENT_MEDIA_NA 0x0004 2064270346Sjfv#define I40E_AQ_EVENT_LINK_FAULT 0x0008 2065270346Sjfv#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 2066270346Sjfv#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 2067270346Sjfv#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 2068270346Sjfv#define I40E_AQ_EVENT_AN_COMPLETED 0x0080 2069270346Sjfv#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 2070270346Sjfv#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 2071270346Sjfv u8 reserved1[6]; 2072266423Sjfv}; 2073266423Sjfv 2074266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 2075266423Sjfv 2076266423Sjfv/* Get Local AN advt register (direct 0x0614) 2077266423Sjfv * Set Local AN advt register (direct 0x0615) 2078266423Sjfv * Get Link Partner AN advt register (direct 0x0616) 2079266423Sjfv */ 2080266423Sjfvstruct i40e_aqc_an_advt_reg { 2081270346Sjfv __le32 local_an_reg0; 2082270346Sjfv __le16 local_an_reg1; 2083270346Sjfv u8 reserved[10]; 2084266423Sjfv}; 2085266423Sjfv 2086266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 2087266423Sjfv 2088266423Sjfv/* Set Loopback mode (0x0618) */ 2089266423Sjfvstruct i40e_aqc_set_lb_mode { 2090333343Serj u8 lb_level; 2091333343Serj#define I40E_AQ_LB_NONE 0 2092333343Serj#define I40E_AQ_LB_MAC 1 2093333343Serj#define I40E_AQ_LB_SERDES 2 2094333343Serj#define I40E_AQ_LB_PHY_INT 3 2095333343Serj#define I40E_AQ_LB_PHY_EXT 4 2096333343Serj#define I40E_AQ_LB_CPVL_PCS 5 2097333343Serj#define I40E_AQ_LB_CPVL_EXT 6 2098270346Sjfv#define I40E_AQ_LB_PHY_LOCAL 0x01 2099270346Sjfv#define I40E_AQ_LB_PHY_REMOTE 0x02 2100270346Sjfv#define I40E_AQ_LB_MAC_LOCAL 0x04 2101333343Serj u8 lb_type; 2102333343Serj#define I40E_AQ_LB_LOCAL 0 2103333343Serj#define I40E_AQ_LB_FAR 0x01 2104333343Serj u8 speed; 2105333343Serj#define I40E_AQ_LB_SPEED_NONE 0 2106333343Serj#define I40E_AQ_LB_SPEED_1G 1 2107333343Serj#define I40E_AQ_LB_SPEED_10G 2 2108333343Serj#define I40E_AQ_LB_SPEED_40G 3 2109333343Serj#define I40E_AQ_LB_SPEED_20G 4 2110333343Serj u8 force_speed; 2111333343Serj u8 reserved[12]; 2112266423Sjfv}; 2113266423Sjfv 2114266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 2115266423Sjfv 2116266423Sjfv/* Set PHY Debug command (0x0622) */ 2117266423Sjfvstruct i40e_aqc_set_phy_debug { 2118270346Sjfv u8 command_flags; 2119266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 2120266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 2121270346Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 2122270346Sjfv I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 2123266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 2124266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 2125266423Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 2126303967Ssbruno/* Disable link manageability on a single port */ 2127266423Sjfv#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 2128303967Ssbruno/* Disable link manageability on all ports needs both bits 4 and 5 */ 2129303967Ssbruno#define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 2130270346Sjfv u8 reserved[15]; 2131266423Sjfv}; 2132266423Sjfv 2133266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 2134266423Sjfv 2135266423Sjfvenum i40e_aq_phy_reg_type { 2136270346Sjfv I40E_AQC_PHY_REG_INTERNAL = 0x1, 2137270346Sjfv I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 2138270346Sjfv I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 2139266423Sjfv}; 2140266423Sjfv 2141349163Serj#pragma pack(1) 2142299549Serj/* Run PHY Activity (0x0626) */ 2143299549Serjstruct i40e_aqc_run_phy_activity { 2144349163Serj u8 cmd_flags; 2145349163Serj __le16 activity_id; 2146349163Serj#define I40E_AQ_RUN_PHY_ACTIVITY_ACTIVITY_ID_USER_DEFINED 0x10 2147349163Serj u8 reserved; 2148349163Serj union { 2149349163Serj struct { 2150349163Serj __le32 dnl_opcode; 2151349163Serj#define I40E_AQ_RUN_PHY_ACTIVITY_DNL_OPCODE_GET_EEE_STATISTICS 0x801b 2152349163Serj __le32 data; 2153349163Serj u8 reserved2[4]; 2154349163Serj } cmd; 2155349163Serj struct { 2156349163Serj __le32 cmd_status; 2157349163Serj#define I40E_AQ_RUN_PHY_ACTIVITY_CMD_STATUS_SUCCESS 0x4 2158349163Serj __le32 data0; 2159349163Serj __le32 data1; 2160349163Serj } resp; 2161349163Serj } params; 2162299549Serj}; 2163349163Serj#pragma pack() 2164299549Serj 2165299549SerjI40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 2166299549Serj 2167333343Serj/* Set PHY Register command (0x0628) */ 2168333343Serj/* Get PHY Register command (0x0629) */ 2169333343Serjstruct i40e_aqc_phy_register_access { 2170333343Serj u8 phy_interface; 2171333343Serj#define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0 2172333343Serj#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1 2173333343Serj#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2 2174333343Serj u8 dev_addres; 2175349163Serj u8 cmd_flags; 2176349163Serj#define I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE 1 2177349163Serj u8 reserved1; 2178333343Serj __le32 reg_address; 2179333343Serj __le32 reg_value; 2180333343Serj u8 reserved2[4]; 2181333343Serj}; 2182333343Serj 2183333343SerjI40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access); 2184333343Serj 2185266423Sjfv/* NVM Read command (indirect 0x0701) 2186266423Sjfv * NVM Erase commands (direct 0x0702) 2187266423Sjfv * NVM Update commands (indirect 0x0703) 2188266423Sjfv */ 2189266423Sjfvstruct i40e_aqc_nvm_update { 2190270346Sjfv u8 command_flags; 2191333343Serj#define I40E_AQ_NVM_LAST_CMD 0x01 2192349163Serj#define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20 2193349163Serj#define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40 2194333343Serj#define I40E_AQ_NVM_FLASH_ONLY 0x80 2195333343Serj#define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1 2196333343Serj#define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03 2197333343Serj#define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03 2198333343Serj#define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01 2199270346Sjfv u8 module_pointer; 2200270346Sjfv __le16 length; 2201270346Sjfv __le32 offset; 2202270346Sjfv __le32 addr_high; 2203270346Sjfv __le32 addr_low; 2204266423Sjfv}; 2205266423Sjfv 2206266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 2207266423Sjfv 2208266423Sjfv/* NVM Config Read (indirect 0x0704) */ 2209266423Sjfvstruct i40e_aqc_nvm_config_read { 2210270346Sjfv __le16 cmd_flags; 2211277082Sjfv#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 2212277082Sjfv#define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 2213277082Sjfv#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 2214270346Sjfv __le16 element_count; 2215299555Serj __le16 element_id; /* Feature/field ID */ 2216277082Sjfv __le16 element_id_msw; /* MSWord of field ID */ 2217270346Sjfv __le32 address_high; 2218270346Sjfv __le32 address_low; 2219266423Sjfv}; 2220266423Sjfv 2221266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 2222266423Sjfv 2223266423Sjfv/* NVM Config Write (indirect 0x0705) */ 2224266423Sjfvstruct i40e_aqc_nvm_config_write { 2225270346Sjfv __le16 cmd_flags; 2226270346Sjfv __le16 element_count; 2227270346Sjfv u8 reserved[4]; 2228270346Sjfv __le32 address_high; 2229270346Sjfv __le32 address_low; 2230266423Sjfv}; 2231266423Sjfv 2232266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 2233266423Sjfv 2234277082Sjfv/* Used for 0x0704 as well as for 0x0705 commands */ 2235277082Sjfv#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 2236299555Serj#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 2237299555Serj (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 2238299555Serj#define I40E_AQ_ANVM_FEATURE 0 2239299555Serj#define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 2240266423Sjfvstruct i40e_aqc_nvm_config_data_feature { 2241266423Sjfv __le16 feature_id; 2242277082Sjfv#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 2243277082Sjfv#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 2244277082Sjfv#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 2245266423Sjfv __le16 feature_options; 2246266423Sjfv __le16 feature_selection; 2247266423Sjfv}; 2248266423Sjfv 2249277082SjfvI40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 2250277082Sjfv 2251266423Sjfvstruct i40e_aqc_nvm_config_data_immediate_field { 2252277082Sjfv __le32 field_id; 2253277082Sjfv __le32 field_value; 2254266423Sjfv __le16 field_options; 2255277082Sjfv __le16 reserved; 2256266423Sjfv}; 2257266423Sjfv 2258277082SjfvI40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 2259277082Sjfv 2260284049Sjfv/* OEM Post Update (indirect 0x0720) 2261284049Sjfv * no command data struct used 2262284049Sjfv */ 2263299555Serjstruct i40e_aqc_nvm_oem_post_update { 2264284049Sjfv#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 2265284049Sjfv u8 sel_data; 2266284049Sjfv u8 reserved[7]; 2267284049Sjfv}; 2268284049Sjfv 2269284049SjfvI40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 2270284049Sjfv 2271284049Sjfvstruct i40e_aqc_nvm_oem_post_update_buffer { 2272284049Sjfv u8 str_len; 2273284049Sjfv u8 dev_addr; 2274284049Sjfv __le16 eeprom_addr; 2275284049Sjfv u8 data[36]; 2276284049Sjfv}; 2277284049Sjfv 2278284049SjfvI40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 2279284049Sjfv 2280299549Serj/* Thermal Sensor (indirect 0x0721) 2281299549Serj * read or set thermal sensor configs and values 2282299549Serj * takes a sensor and command specific data buffer, not detailed here 2283299549Serj */ 2284299549Serjstruct i40e_aqc_thermal_sensor { 2285299549Serj u8 sensor_action; 2286299549Serj#define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 2287299549Serj#define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 2288299549Serj#define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 2289299549Serj u8 reserved[7]; 2290299549Serj __le32 addr_high; 2291299549Serj __le32 addr_low; 2292299549Serj}; 2293299549Serj 2294299549SerjI40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 2295299549Serj 2296266423Sjfv/* Send to PF command (indirect 0x0801) id is only used by PF 2297266423Sjfv * Send to VF command (indirect 0x0802) id is only used by PF 2298266423Sjfv * Send to Peer PF command (indirect 0x0803) 2299266423Sjfv */ 2300266423Sjfvstruct i40e_aqc_pf_vf_message { 2301270346Sjfv __le32 id; 2302270346Sjfv u8 reserved[4]; 2303270346Sjfv __le32 addr_high; 2304270346Sjfv __le32 addr_low; 2305266423Sjfv}; 2306266423Sjfv 2307266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 2308266423Sjfv 2309266423Sjfv/* Alternate structure */ 2310266423Sjfv 2311266423Sjfv/* Direct write (direct 0x0900) 2312266423Sjfv * Direct read (direct 0x0902) 2313266423Sjfv */ 2314266423Sjfvstruct i40e_aqc_alternate_write { 2315266423Sjfv __le32 address0; 2316266423Sjfv __le32 data0; 2317266423Sjfv __le32 address1; 2318266423Sjfv __le32 data1; 2319266423Sjfv}; 2320266423Sjfv 2321266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 2322266423Sjfv 2323266423Sjfv/* Indirect write (indirect 0x0901) 2324266423Sjfv * Indirect read (indirect 0x0903) 2325266423Sjfv */ 2326266423Sjfv 2327266423Sjfvstruct i40e_aqc_alternate_ind_write { 2328266423Sjfv __le32 address; 2329266423Sjfv __le32 length; 2330266423Sjfv __le32 addr_high; 2331266423Sjfv __le32 addr_low; 2332266423Sjfv}; 2333266423Sjfv 2334266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 2335266423Sjfv 2336266423Sjfv/* Done alternate write (direct 0x0904) 2337266423Sjfv * uses i40e_aq_desc 2338266423Sjfv */ 2339266423Sjfvstruct i40e_aqc_alternate_write_done { 2340270346Sjfv __le16 cmd_flags; 2341266423Sjfv#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 2342266423Sjfv#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 2343266423Sjfv#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 2344266423Sjfv#define I40E_AQ_ALTERNATE_RESET_NEEDED 2 2345270346Sjfv u8 reserved[14]; 2346266423Sjfv}; 2347266423Sjfv 2348266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2349266423Sjfv 2350266423Sjfv/* Set OEM mode (direct 0x0905) */ 2351266423Sjfvstruct i40e_aqc_alternate_set_mode { 2352270346Sjfv __le32 mode; 2353266423Sjfv#define I40E_AQ_ALTERNATE_MODE_NONE 0 2354266423Sjfv#define I40E_AQ_ALTERNATE_MODE_OEM 1 2355270346Sjfv u8 reserved[12]; 2356266423Sjfv}; 2357266423Sjfv 2358266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2359266423Sjfv 2360266423Sjfv/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2361266423Sjfv 2362266423Sjfv/* async events 0x10xx */ 2363266423Sjfv 2364266423Sjfv/* Lan Queue Overflow Event (direct, 0x1001) */ 2365266423Sjfvstruct i40e_aqc_lan_overflow { 2366270346Sjfv __le32 prtdcb_rupto; 2367270346Sjfv __le32 otx_ctl; 2368270346Sjfv u8 reserved[8]; 2369266423Sjfv}; 2370266423Sjfv 2371266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2372266423Sjfv 2373266423Sjfv/* Get LLDP MIB (indirect 0x0A00) */ 2374266423Sjfvstruct i40e_aqc_lldp_get_mib { 2375270346Sjfv u8 type; 2376270346Sjfv u8 reserved1; 2377270346Sjfv#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2378270346Sjfv#define I40E_AQ_LLDP_MIB_LOCAL 0x0 2379270346Sjfv#define I40E_AQ_LLDP_MIB_REMOTE 0x1 2380270346Sjfv#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2381270346Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2382270346Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2383270346Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2384270346Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2385270346Sjfv#define I40E_AQ_LLDP_TX_SHIFT 0x4 2386270346Sjfv#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2387266423Sjfv/* TX pause flags use I40E_AQ_LINK_TX_* above */ 2388270346Sjfv __le16 local_len; 2389270346Sjfv __le16 remote_len; 2390270346Sjfv u8 reserved2[2]; 2391270346Sjfv __le32 addr_high; 2392270346Sjfv __le32 addr_low; 2393266423Sjfv}; 2394266423Sjfv 2395266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2396266423Sjfv 2397266423Sjfv/* Configure LLDP MIB Change Event (direct 0x0A01) 2398266423Sjfv * also used for the event (with type in the command field) 2399266423Sjfv */ 2400266423Sjfvstruct i40e_aqc_lldp_update_mib { 2401270346Sjfv u8 command; 2402270346Sjfv#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2403270346Sjfv#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2404270346Sjfv u8 reserved[7]; 2405270346Sjfv __le32 addr_high; 2406270346Sjfv __le32 addr_low; 2407266423Sjfv}; 2408266423Sjfv 2409266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2410266423Sjfv 2411266423Sjfv/* Add LLDP TLV (indirect 0x0A02) 2412266423Sjfv * Delete LLDP TLV (indirect 0x0A04) 2413266423Sjfv */ 2414266423Sjfvstruct i40e_aqc_lldp_add_tlv { 2415270346Sjfv u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2416270346Sjfv u8 reserved1[1]; 2417270346Sjfv __le16 len; 2418270346Sjfv u8 reserved2[4]; 2419270346Sjfv __le32 addr_high; 2420270346Sjfv __le32 addr_low; 2421266423Sjfv}; 2422266423Sjfv 2423266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2424266423Sjfv 2425266423Sjfv/* Update LLDP TLV (indirect 0x0A03) */ 2426266423Sjfvstruct i40e_aqc_lldp_update_tlv { 2427270346Sjfv u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2428270346Sjfv u8 reserved; 2429270346Sjfv __le16 old_len; 2430270346Sjfv __le16 new_offset; 2431270346Sjfv __le16 new_len; 2432270346Sjfv __le32 addr_high; 2433270346Sjfv __le32 addr_low; 2434266423Sjfv}; 2435266423Sjfv 2436266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2437266423Sjfv 2438266423Sjfv/* Stop LLDP (direct 0x0A05) */ 2439266423Sjfvstruct i40e_aqc_lldp_stop { 2440270346Sjfv u8 command; 2441349163Serj#define I40E_AQ_LLDP_AGENT_STOP 0x0 2442349163Serj#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2443349163Serj#define I40E_AQ_LLDP_AGENT_STOP_PERSIST 0x2 2444270346Sjfv u8 reserved[15]; 2445266423Sjfv}; 2446266423Sjfv 2447266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2448266423Sjfv 2449266423Sjfv/* Start LLDP (direct 0x0A06) */ 2450266423Sjfvstruct i40e_aqc_lldp_start { 2451270346Sjfv u8 command; 2452349163Serj#define I40E_AQ_LLDP_AGENT_START 0x1 2453349163Serj#define I40E_AQ_LLDP_AGENT_START_PERSIST 0x2 2454270346Sjfv u8 reserved[15]; 2455266423Sjfv}; 2456266423Sjfv 2457266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2458266423Sjfv 2459333343Serj/* Set DCB (direct 0x0303) */ 2460333343Serjstruct i40e_aqc_set_dcb_parameters { 2461333343Serj u8 command; 2462333343Serj#define I40E_AQ_DCB_SET_AGENT 0x1 2463333343Serj#define I40E_DCB_VALID 0x1 2464333343Serj u8 valid_flags; 2465333343Serj u8 reserved[14]; 2466333343Serj}; 2467333343Serj 2468333343SerjI40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters); 2469333343Serj 2470277082Sjfv/* Get CEE DCBX Oper Config (0x0A07) 2471277082Sjfv * uses the generic descriptor struct 2472277082Sjfv * returns below as indirect response 2473266423Sjfv */ 2474266423Sjfv 2475277082Sjfv#define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2476277082Sjfv#define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2477277082Sjfv#define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2478277082Sjfv#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2479277082Sjfv#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2480277082Sjfv#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2481284049Sjfv 2482277082Sjfv#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2483277082Sjfv#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2484277082Sjfv#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2485277082Sjfv#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2486277082Sjfv#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2487277082Sjfv#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2488284049Sjfv#define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2489284049Sjfv#define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2490284049Sjfv#define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2491284049Sjfv#define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2492284049Sjfv#define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2493284049Sjfv#define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2494284049Sjfv 2495284049Sjfv/* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2496284049Sjfv * word boundary layout issues, which the Linux compilers silently deal 2497284049Sjfv * with by adding padding, making the actual struct larger than designed. 2498284049Sjfv * However, the FW compiler for the NIC is less lenient and complains 2499284049Sjfv * about the struct. Hence, the struct defined here has an extra byte in 2500284049Sjfv * fields reserved3 and reserved4 to directly acknowledge that padding, 2501284049Sjfv * and the new length is used in the length check macro. 2502284049Sjfv */ 2503277082Sjfvstruct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2504277082Sjfv u8 reserved1; 2505277082Sjfv u8 oper_num_tc; 2506277082Sjfv u8 oper_prio_tc[4]; 2507277082Sjfv u8 reserved2; 2508277082Sjfv u8 oper_tc_bw[8]; 2509277082Sjfv u8 oper_pfc_en; 2510284049Sjfv u8 reserved3[2]; 2511277082Sjfv __le16 oper_app_prio; 2512284049Sjfv u8 reserved4[2]; 2513277082Sjfv __le16 tlv_status; 2514277082Sjfv}; 2515277082Sjfv 2516277082SjfvI40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2517277082Sjfv 2518277082Sjfvstruct i40e_aqc_get_cee_dcb_cfg_resp { 2519277082Sjfv u8 oper_num_tc; 2520277082Sjfv u8 oper_prio_tc[4]; 2521277082Sjfv u8 oper_tc_bw[8]; 2522277082Sjfv u8 oper_pfc_en; 2523277082Sjfv __le16 oper_app_prio; 2524277082Sjfv __le32 tlv_status; 2525277082Sjfv u8 reserved[12]; 2526277082Sjfv}; 2527277082Sjfv 2528277082SjfvI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2529277082Sjfv 2530277082Sjfv/* Set Local LLDP MIB (indirect 0x0A08) 2531277082Sjfv * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2532277082Sjfv */ 2533277082Sjfvstruct i40e_aqc_lldp_set_local_mib { 2534277082Sjfv#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2535299545Serj#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \ 2536299545Serj SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2537299545Serj#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2538299545Serj#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2539299545Serj#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \ 2540299545Serj SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2541299545Serj#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2542277082Sjfv u8 type; 2543277082Sjfv u8 reserved0; 2544277082Sjfv __le16 length; 2545277082Sjfv u8 reserved1[4]; 2546277082Sjfv __le32 address_high; 2547277082Sjfv __le32 address_low; 2548277082Sjfv}; 2549277082Sjfv 2550277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2551277082Sjfv 2552299547Serjstruct i40e_aqc_lldp_set_local_mib_resp { 2553299547Serj#define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01 2554299547Serj u8 status; 2555299547Serj u8 reserved[15]; 2556299547Serj}; 2557299547Serj 2558299547SerjI40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp); 2559299547Serj 2560277082Sjfv/* Stop/Start LLDP Agent (direct 0x0A09) 2561277082Sjfv * Used for stopping/starting specific LLDP agent. e.g. DCBx 2562277082Sjfv */ 2563277082Sjfvstruct i40e_aqc_lldp_stop_start_specific_agent { 2564277082Sjfv#define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2565299555Serj#define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2566299555Serj (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2567277082Sjfv u8 command; 2568277082Sjfv u8 reserved[15]; 2569277082Sjfv}; 2570277082Sjfv 2571277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2572277082Sjfv 2573349163Serj/* Restore LLDP Agent factory settings (direct 0x0A0A) */ 2574349163Serjstruct i40e_aqc_lldp_restore { 2575349163Serj u8 command; 2576349163Serj#define I40E_AQ_LLDP_AGENT_RESTORE_NOT 0x0 2577349163Serj#define I40E_AQ_LLDP_AGENT_RESTORE 0x1 2578349163Serj u8 reserved[15]; 2579349163Serj}; 2580349163Serj 2581349163SerjI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_restore); 2582349163Serj 2583266423Sjfv/* Add Udp Tunnel command and completion (direct 0x0B00) */ 2584266423Sjfvstruct i40e_aqc_add_udp_tunnel { 2585270346Sjfv __le16 udp_port; 2586270346Sjfv u8 reserved0[3]; 2587270346Sjfv u8 protocol_type; 2588266423Sjfv#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2589266423Sjfv#define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2590266423Sjfv#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2591299549Serj#define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2592270346Sjfv u8 reserved1[10]; 2593266423Sjfv}; 2594266423Sjfv 2595266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2596266423Sjfv 2597266423Sjfvstruct i40e_aqc_add_udp_tunnel_completion { 2598299555Serj __le16 udp_port; 2599266423Sjfv u8 filter_entry_index; 2600266423Sjfv u8 multiple_pfs; 2601270346Sjfv#define I40E_AQC_SINGLE_PF 0x0 2602270346Sjfv#define I40E_AQC_MULTIPLE_PFS 0x1 2603266423Sjfv u8 total_filters; 2604266423Sjfv u8 reserved[11]; 2605266423Sjfv}; 2606266423Sjfv 2607266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2608266423Sjfv 2609266423Sjfv/* remove UDP Tunnel command (0x0B01) */ 2610266423Sjfvstruct i40e_aqc_remove_udp_tunnel { 2611270346Sjfv u8 reserved[2]; 2612270346Sjfv u8 index; /* 0 to 15 */ 2613270346Sjfv u8 reserved2[13]; 2614266423Sjfv}; 2615266423Sjfv 2616266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2617266423Sjfv 2618266423Sjfvstruct i40e_aqc_del_udp_tunnel_completion { 2619270346Sjfv __le16 udp_port; 2620270346Sjfv u8 index; /* 0 to 15 */ 2621270346Sjfv u8 multiple_pfs; 2622270346Sjfv u8 total_filters_used; 2623270346Sjfv u8 reserved1[11]; 2624266423Sjfv}; 2625266423Sjfv 2626266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2627266423Sjfv 2628303967Ssbrunostruct i40e_aqc_get_set_rss_key { 2629303967Ssbruno#define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15) 2630303967Ssbruno#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2631303967Ssbruno#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2632303967Ssbruno I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2633303967Ssbruno __le16 vsi_id; 2634303967Ssbruno u8 reserved[6]; 2635303967Ssbruno __le32 addr_high; 2636303967Ssbruno __le32 addr_low; 2637303967Ssbruno}; 2638303967Ssbruno 2639303967SsbrunoI40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2640303967Ssbruno 2641303967Ssbrunostruct i40e_aqc_get_set_rss_key_data { 2642303967Ssbruno u8 standard_rss_key[0x28]; 2643303967Ssbruno u8 extended_hash_key[0xc]; 2644303967Ssbruno}; 2645303967Ssbruno 2646303967SsbrunoI40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2647303967Ssbruno 2648303967Ssbrunostruct i40e_aqc_get_set_rss_lut { 2649303967Ssbruno#define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15) 2650303967Ssbruno#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2651303967Ssbruno#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2652303967Ssbruno I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2653303967Ssbruno __le16 vsi_id; 2654303967Ssbruno#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2655303967Ssbruno#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \ 2656303967Ssbruno I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2657303967Ssbruno 2658303967Ssbruno#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2659303967Ssbruno#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2660303967Ssbruno __le16 flags; 2661303967Ssbruno u8 reserved[4]; 2662303967Ssbruno __le32 addr_high; 2663303967Ssbruno __le32 addr_low; 2664303967Ssbruno}; 2665303967Ssbruno 2666303967SsbrunoI40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2667303967Ssbruno 2668266423Sjfv/* tunnel key structure 0x0B10 */ 2669266423Sjfv 2670266423Sjfvstruct i40e_aqc_tunnel_key_structure { 2671266423Sjfv u8 key1_off; 2672266423Sjfv u8 key2_off; 2673266423Sjfv u8 key1_len; /* 0 to 15 */ 2674266423Sjfv u8 key2_len; /* 0 to 15 */ 2675266423Sjfv u8 flags; 2676270346Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2677266423Sjfv/* response flags */ 2678270346Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2679270346Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2680270346Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2681266423Sjfv u8 network_key_index; 2682266423Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2683266423Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2684266423Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2685266423Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2686266423Sjfv u8 reserved[10]; 2687266423Sjfv}; 2688266423Sjfv 2689266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2690266423Sjfv 2691266423Sjfv/* OEM mode commands (direct 0xFE0x) */ 2692266423Sjfvstruct i40e_aqc_oem_param_change { 2693270346Sjfv __le32 param_type; 2694270346Sjfv#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2695270346Sjfv#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2696270346Sjfv#define I40E_AQ_OEM_PARAM_MAC 2 2697270346Sjfv __le32 param_value1; 2698277082Sjfv __le16 param_value2; 2699277082Sjfv u8 reserved[6]; 2700266423Sjfv}; 2701266423Sjfv 2702266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2703266423Sjfv 2704266423Sjfvstruct i40e_aqc_oem_state_change { 2705270346Sjfv __le32 state; 2706270346Sjfv#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2707270346Sjfv#define I40E_AQ_OEM_STATE_LINK_UP 0x1 2708270346Sjfv u8 reserved[12]; 2709266423Sjfv}; 2710266423Sjfv 2711266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2712266423Sjfv 2713277082Sjfv/* Initialize OCSD (0xFE02, direct) */ 2714277082Sjfvstruct i40e_aqc_opc_oem_ocsd_initialize { 2715277082Sjfv u8 type_status; 2716277082Sjfv u8 reserved1[3]; 2717277082Sjfv __le32 ocsd_memory_block_addr_high; 2718277082Sjfv __le32 ocsd_memory_block_addr_low; 2719277082Sjfv __le32 requested_update_interval; 2720277082Sjfv}; 2721277082Sjfv 2722277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2723277082Sjfv 2724277082Sjfv/* Initialize OCBB (0xFE03, direct) */ 2725277082Sjfvstruct i40e_aqc_opc_oem_ocbb_initialize { 2726277082Sjfv u8 type_status; 2727277082Sjfv u8 reserved1[3]; 2728277082Sjfv __le32 ocbb_memory_block_addr_high; 2729277082Sjfv __le32 ocbb_memory_block_addr_low; 2730277082Sjfv u8 reserved2[4]; 2731277082Sjfv}; 2732277082Sjfv 2733277082SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2734277082Sjfv 2735266423Sjfv/* debug commands */ 2736266423Sjfv 2737266423Sjfv/* get device id (0xFF00) uses the generic structure */ 2738266423Sjfv 2739266423Sjfv/* set test more (0xFF01, internal) */ 2740266423Sjfv 2741266423Sjfvstruct i40e_acq_set_test_mode { 2742270346Sjfv u8 mode; 2743270346Sjfv#define I40E_AQ_TEST_PARTIAL 0 2744270346Sjfv#define I40E_AQ_TEST_FULL 1 2745270346Sjfv#define I40E_AQ_TEST_NVM 2 2746270346Sjfv u8 reserved[3]; 2747270346Sjfv u8 command; 2748270346Sjfv#define I40E_AQ_TEST_OPEN 0 2749270346Sjfv#define I40E_AQ_TEST_CLOSE 1 2750270346Sjfv#define I40E_AQ_TEST_INC 2 2751270346Sjfv u8 reserved2[3]; 2752270346Sjfv __le32 address_high; 2753270346Sjfv __le32 address_low; 2754266423Sjfv}; 2755266423Sjfv 2756266423SjfvI40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2757266423Sjfv 2758266423Sjfv/* Debug Read Register command (0xFF03) 2759266423Sjfv * Debug Write Register command (0xFF04) 2760266423Sjfv */ 2761266423Sjfvstruct i40e_aqc_debug_reg_read_write { 2762266423Sjfv __le32 reserved; 2763266423Sjfv __le32 address; 2764266423Sjfv __le32 value_high; 2765266423Sjfv __le32 value_low; 2766266423Sjfv}; 2767266423Sjfv 2768266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2769266423Sjfv 2770266423Sjfv/* Scatter/gather Reg Read (indirect 0xFF05) 2771266423Sjfv * Scatter/gather Reg Write (indirect 0xFF06) 2772266423Sjfv */ 2773266423Sjfv 2774266423Sjfv/* i40e_aq_desc is used for the command */ 2775266423Sjfvstruct i40e_aqc_debug_reg_sg_element_data { 2776266423Sjfv __le32 address; 2777266423Sjfv __le32 value; 2778266423Sjfv}; 2779266423Sjfv 2780266423Sjfv/* Debug Modify register (direct 0xFF07) */ 2781266423Sjfvstruct i40e_aqc_debug_modify_reg { 2782266423Sjfv __le32 address; 2783266423Sjfv __le32 value; 2784266423Sjfv __le32 clear_mask; 2785266423Sjfv __le32 set_mask; 2786266423Sjfv}; 2787266423Sjfv 2788266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2789266423Sjfv 2790266423Sjfv/* dump internal data (0xFF08, indirect) */ 2791266423Sjfv 2792266423Sjfv#define I40E_AQ_CLUSTER_ID_AUX 0 2793266423Sjfv#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2794266423Sjfv#define I40E_AQ_CLUSTER_ID_TXSCHED 2 2795266423Sjfv#define I40E_AQ_CLUSTER_ID_HMC 3 2796266423Sjfv#define I40E_AQ_CLUSTER_ID_MAC0 4 2797266423Sjfv#define I40E_AQ_CLUSTER_ID_MAC1 5 2798266423Sjfv#define I40E_AQ_CLUSTER_ID_MAC2 6 2799266423Sjfv#define I40E_AQ_CLUSTER_ID_MAC3 7 2800266423Sjfv#define I40E_AQ_CLUSTER_ID_DCB 8 2801266423Sjfv#define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2802266423Sjfv#define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2803266423Sjfv#define I40E_AQ_CLUSTER_ID_ALTRAM 11 2804266423Sjfv 2805266423Sjfvstruct i40e_aqc_debug_dump_internals { 2806270346Sjfv u8 cluster_id; 2807270346Sjfv u8 table_id; 2808270346Sjfv __le16 data_size; 2809270346Sjfv __le32 idx; 2810270346Sjfv __le32 address_high; 2811270346Sjfv __le32 address_low; 2812266423Sjfv}; 2813266423Sjfv 2814266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2815266423Sjfv 2816266423Sjfvstruct i40e_aqc_debug_modify_internals { 2817270346Sjfv u8 cluster_id; 2818270346Sjfv u8 cluster_specific_params[7]; 2819270346Sjfv __le32 address_high; 2820270346Sjfv __le32 address_low; 2821266423Sjfv}; 2822266423Sjfv 2823266423SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2824266423Sjfv 2825299547Serj#endif /* _I40E_ADMINQ_CMD_H_ */ 2826