ixgbe_x540.c revision 320897
1/****************************************************************************** 2 3 Copyright (c) 2001-2017, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: stable/11/sys/dev/ixgbe/ixgbe_x540.c 320897 2017-07-11 21:25:07Z erj $*/ 34 35#include "ixgbe_x540.h" 36#include "ixgbe_type.h" 37#include "ixgbe_api.h" 38#include "ixgbe_common.h" 39#include "ixgbe_phy.h" 40 41#define IXGBE_X540_MAX_TX_QUEUES 128 42#define IXGBE_X540_MAX_RX_QUEUES 128 43#define IXGBE_X540_RAR_ENTRIES 128 44#define IXGBE_X540_MC_TBL_SIZE 128 45#define IXGBE_X540_VFT_TBL_SIZE 128 46#define IXGBE_X540_RX_PB_SIZE 384 47 48static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); 49static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); 50static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); 51 52/** 53 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type 54 * @hw: pointer to hardware structure 55 * 56 * Initialize the function pointers and assign the MAC type for X540. 57 * Does not touch the hardware. 58 **/ 59s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) 60{ 61 struct ixgbe_mac_info *mac = &hw->mac; 62 struct ixgbe_phy_info *phy = &hw->phy; 63 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 64 s32 ret_val; 65 66 DEBUGFUNC("ixgbe_init_ops_X540"); 67 68 ret_val = ixgbe_init_phy_ops_generic(hw); 69 ret_val = ixgbe_init_ops_generic(hw); 70 71 72 /* EEPROM */ 73 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540; 74 eeprom->ops.read = ixgbe_read_eerd_X540; 75 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_X540; 76 eeprom->ops.write = ixgbe_write_eewr_X540; 77 eeprom->ops.write_buffer = ixgbe_write_eewr_buffer_X540; 78 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X540; 79 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X540; 80 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X540; 81 82 /* PHY */ 83 phy->ops.init = ixgbe_init_phy_ops_generic; 84 phy->ops.reset = NULL; 85 phy->ops.set_phy_power = ixgbe_set_copper_phy_power; 86 87 /* MAC */ 88 mac->ops.reset_hw = ixgbe_reset_hw_X540; 89 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2; 90 mac->ops.get_media_type = ixgbe_get_media_type_X540; 91 mac->ops.get_supported_physical_layer = 92 ixgbe_get_supported_physical_layer_X540; 93 mac->ops.read_analog_reg8 = NULL; 94 mac->ops.write_analog_reg8 = NULL; 95 mac->ops.start_hw = ixgbe_start_hw_X540; 96 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic; 97 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic; 98 mac->ops.get_device_caps = ixgbe_get_device_caps_generic; 99 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic; 100 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic; 101 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540; 102 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X540; 103 mac->ops.init_swfw_sync = ixgbe_init_swfw_sync_X540; 104 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic; 105 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic; 106 107 /* RAR, Multicast, VLAN */ 108 mac->ops.set_vmdq = ixgbe_set_vmdq_generic; 109 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic; 110 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic; 111 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic; 112 mac->rar_highwater = 1; 113 mac->ops.set_vfta = ixgbe_set_vfta_generic; 114 mac->ops.set_vlvf = ixgbe_set_vlvf_generic; 115 mac->ops.clear_vfta = ixgbe_clear_vfta_generic; 116 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic; 117 mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing; 118 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing; 119 120 /* Link */ 121 mac->ops.get_link_capabilities = 122 ixgbe_get_copper_link_capabilities_generic; 123 mac->ops.setup_link = ixgbe_setup_mac_link_X540; 124 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic; 125 mac->ops.check_link = ixgbe_check_mac_link_generic; 126 mac->ops.bypass_rw = ixgbe_bypass_rw_generic; 127 mac->ops.bypass_valid_rd = ixgbe_bypass_valid_rd_generic; 128 mac->ops.bypass_set = ixgbe_bypass_set_generic; 129 mac->ops.bypass_rd_eep = ixgbe_bypass_rd_eep_generic; 130 131 132 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE; 133 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE; 134 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES; 135 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE; 136 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES; 137 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES; 138 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 139 140 /* 141 * FWSM register 142 * ARC supported; valid only if manageability features are 143 * enabled. 144 */ 145 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)) 146 & IXGBE_FWSM_MODE_MASK); 147 148 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 149 150 /* LEDs */ 151 mac->ops.blink_led_start = ixgbe_blink_led_start_X540; 152 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540; 153 154 /* Manageability interface */ 155 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic; 156 157 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; 158 159 return ret_val; 160} 161 162/** 163 * ixgbe_get_link_capabilities_X540 - Determines link capabilities 164 * @hw: pointer to hardware structure 165 * @speed: pointer to link speed 166 * @autoneg: TRUE when autoneg or autotry is enabled 167 * 168 * Determines the link capabilities by reading the AUTOC register. 169 **/ 170s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw, 171 ixgbe_link_speed *speed, 172 bool *autoneg) 173{ 174 ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg); 175 176 return IXGBE_SUCCESS; 177} 178 179/** 180 * ixgbe_get_media_type_X540 - Get media type 181 * @hw: pointer to hardware structure 182 * 183 * Returns the media type (fiber, copper, backplane) 184 **/ 185enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) 186{ 187 UNREFERENCED_1PARAMETER(hw); 188 return ixgbe_media_type_copper; 189} 190 191/** 192 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities 193 * @hw: pointer to hardware structure 194 * @speed: new link speed 195 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 196 **/ 197s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, 198 ixgbe_link_speed speed, 199 bool autoneg_wait_to_complete) 200{ 201 DEBUGFUNC("ixgbe_setup_mac_link_X540"); 202 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete); 203} 204 205/** 206 * ixgbe_reset_hw_X540 - Perform hardware reset 207 * @hw: pointer to hardware structure 208 * 209 * Resets the hardware by resetting the transmit and receive units, masks 210 * and clears all interrupts, and perform a reset. 211 **/ 212s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw) 213{ 214 s32 status; 215 u32 ctrl, i; 216 u32 swfw_mask = hw->phy.phy_semaphore_mask; 217 218 DEBUGFUNC("ixgbe_reset_hw_X540"); 219 220 /* Call adapter stop to disable tx/rx and clear interrupts */ 221 status = hw->mac.ops.stop_adapter(hw); 222 if (status != IXGBE_SUCCESS) 223 goto reset_hw_out; 224 225 /* flush pending Tx transactions */ 226 ixgbe_clear_tx_pending(hw); 227 228mac_reset_top: 229 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 230 if (status != IXGBE_SUCCESS) { 231 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 232 "semaphore failed with %d", status); 233 return IXGBE_ERR_SWFW_SYNC; 234 } 235 ctrl = IXGBE_CTRL_RST; 236 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 237 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 238 IXGBE_WRITE_FLUSH(hw); 239 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 240 241 /* Poll for reset bit to self-clear indicating reset is complete */ 242 for (i = 0; i < 10; i++) { 243 usec_delay(1); 244 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 245 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 246 break; 247 } 248 249 if (ctrl & IXGBE_CTRL_RST_MASK) { 250 status = IXGBE_ERR_RESET_FAILED; 251 ERROR_REPORT1(IXGBE_ERROR_POLLING, 252 "Reset polling failed to complete.\n"); 253 } 254 msec_delay(100); 255 256 /* 257 * Double resets are required for recovery from certain error 258 * conditions. Between resets, it is necessary to stall to allow time 259 * for any pending HW events to complete. 260 */ 261 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 262 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 263 goto mac_reset_top; 264 } 265 266 /* Set the Rx packet buffer size. */ 267 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT); 268 269 /* Store the permanent mac address */ 270 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 271 272 /* 273 * Store MAC address from RAR0, clear receive address registers, and 274 * clear the multicast table. Also reset num_rar_entries to 128, 275 * since we modify this value when programming the SAN MAC address. 276 */ 277 hw->mac.num_rar_entries = 128; 278 hw->mac.ops.init_rx_addrs(hw); 279 280 /* Store the permanent SAN mac address */ 281 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 282 283 /* Add the SAN MAC address to the RAR only if it's a valid address */ 284 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 285 /* Save the SAN MAC RAR index */ 286 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 287 288 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index, 289 hw->mac.san_addr, 0, IXGBE_RAH_AV); 290 291 /* clear VMDq pool/queue selection for this RAR */ 292 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index, 293 IXGBE_CLEAR_VMDQ_ALL); 294 295 /* Reserve the last RAR for the SAN MAC address */ 296 hw->mac.num_rar_entries--; 297 } 298 299 /* Store the alternative WWNN/WWPN prefix */ 300 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 301 &hw->mac.wwpn_prefix); 302 303reset_hw_out: 304 return status; 305} 306 307/** 308 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx 309 * @hw: pointer to hardware structure 310 * 311 * Starts the hardware using the generic start_hw function 312 * and the generation start_hw function. 313 * Then performs revision-specific operations, if any. 314 **/ 315s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw) 316{ 317 s32 ret_val = IXGBE_SUCCESS; 318 319 DEBUGFUNC("ixgbe_start_hw_X540"); 320 321 ret_val = ixgbe_start_hw_generic(hw); 322 if (ret_val != IXGBE_SUCCESS) 323 goto out; 324 325 ret_val = ixgbe_start_hw_gen2(hw); 326 327out: 328 return ret_val; 329} 330 331/** 332 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type 333 * @hw: pointer to hardware structure 334 * 335 * Determines physical layer capabilities of the current configuration. 336 **/ 337u64 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw) 338{ 339 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 340 u16 ext_ability = 0; 341 342 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540"); 343 344 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 345 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 346 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 347 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 348 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 349 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 350 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 351 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 352 353 return physical_layer; 354} 355 356/** 357 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params 358 * @hw: pointer to hardware structure 359 * 360 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 361 * ixgbe_hw struct in order to set up EEPROM access. 362 **/ 363s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) 364{ 365 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 366 u32 eec; 367 u16 eeprom_size; 368 369 DEBUGFUNC("ixgbe_init_eeprom_params_X540"); 370 371 if (eeprom->type == ixgbe_eeprom_uninitialized) { 372 eeprom->semaphore_delay = 10; 373 eeprom->type = ixgbe_flash; 374 375 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 376 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 377 IXGBE_EEC_SIZE_SHIFT); 378 eeprom->word_size = 1 << (eeprom_size + 379 IXGBE_EEPROM_WORD_SIZE_SHIFT); 380 381 DEBUGOUT2("Eeprom params: type = %d, size = %d\n", 382 eeprom->type, eeprom->word_size); 383 } 384 385 return IXGBE_SUCCESS; 386} 387 388/** 389 * ixgbe_read_eerd_X540- Read EEPROM word using EERD 390 * @hw: pointer to hardware structure 391 * @offset: offset of word in the EEPROM to read 392 * @data: word read from the EEPROM 393 * 394 * Reads a 16 bit word from the EEPROM using the EERD register. 395 **/ 396s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) 397{ 398 s32 status = IXGBE_SUCCESS; 399 400 DEBUGFUNC("ixgbe_read_eerd_X540"); 401 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 402 IXGBE_SUCCESS) { 403 status = ixgbe_read_eerd_generic(hw, offset, data); 404 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 405 } else { 406 status = IXGBE_ERR_SWFW_SYNC; 407 } 408 409 return status; 410} 411 412/** 413 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD 414 * @hw: pointer to hardware structure 415 * @offset: offset of word in the EEPROM to read 416 * @words: number of words 417 * @data: word(s) read from the EEPROM 418 * 419 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 420 **/ 421s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, 422 u16 offset, u16 words, u16 *data) 423{ 424 s32 status = IXGBE_SUCCESS; 425 426 DEBUGFUNC("ixgbe_read_eerd_buffer_X540"); 427 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 428 IXGBE_SUCCESS) { 429 status = ixgbe_read_eerd_buffer_generic(hw, offset, 430 words, data); 431 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 432 } else { 433 status = IXGBE_ERR_SWFW_SYNC; 434 } 435 436 return status; 437} 438 439/** 440 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR 441 * @hw: pointer to hardware structure 442 * @offset: offset of word in the EEPROM to write 443 * @data: word write to the EEPROM 444 * 445 * Write a 16 bit word to the EEPROM using the EEWR register. 446 **/ 447s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data) 448{ 449 s32 status = IXGBE_SUCCESS; 450 451 DEBUGFUNC("ixgbe_write_eewr_X540"); 452 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 453 IXGBE_SUCCESS) { 454 status = ixgbe_write_eewr_generic(hw, offset, data); 455 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 456 } else { 457 status = IXGBE_ERR_SWFW_SYNC; 458 } 459 460 return status; 461} 462 463/** 464 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR 465 * @hw: pointer to hardware structure 466 * @offset: offset of word in the EEPROM to write 467 * @words: number of words 468 * @data: word(s) write to the EEPROM 469 * 470 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 471 **/ 472s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, 473 u16 offset, u16 words, u16 *data) 474{ 475 s32 status = IXGBE_SUCCESS; 476 477 DEBUGFUNC("ixgbe_write_eewr_buffer_X540"); 478 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 479 IXGBE_SUCCESS) { 480 status = ixgbe_write_eewr_buffer_generic(hw, offset, 481 words, data); 482 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 483 } else { 484 status = IXGBE_ERR_SWFW_SYNC; 485 } 486 487 return status; 488} 489 490/** 491 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum 492 * 493 * This function does not use synchronization for EERD and EEWR. It can 494 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540. 495 * 496 * @hw: pointer to hardware structure 497 * 498 * Returns a negative error code on error, or the 16-bit checksum 499 **/ 500s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) 501{ 502 u16 i, j; 503 u16 checksum = 0; 504 u16 length = 0; 505 u16 pointer = 0; 506 u16 word = 0; 507 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR; 508 509 /* Do not use hw->eeprom.ops.read because we do not want to take 510 * the synchronization semaphores here. Instead use 511 * ixgbe_read_eerd_generic 512 */ 513 514 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540"); 515 516 /* Include 0x0 up to IXGBE_EEPROM_CHECKSUM; do not include the 517 * checksum itself 518 */ 519 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 520 if (ixgbe_read_eerd_generic(hw, i, &word)) { 521 DEBUGOUT("EEPROM read failed\n"); 522 return IXGBE_ERR_EEPROM; 523 } 524 checksum += word; 525 } 526 527 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the 528 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 529 */ 530 for (i = ptr_start; i < IXGBE_FW_PTR; i++) { 531 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 532 continue; 533 534 if (ixgbe_read_eerd_generic(hw, i, &pointer)) { 535 DEBUGOUT("EEPROM read failed\n"); 536 return IXGBE_ERR_EEPROM; 537 } 538 539 /* Skip pointer section if the pointer is invalid. */ 540 if (pointer == 0xFFFF || pointer == 0 || 541 pointer >= hw->eeprom.word_size) 542 continue; 543 544 if (ixgbe_read_eerd_generic(hw, pointer, &length)) { 545 DEBUGOUT("EEPROM read failed\n"); 546 return IXGBE_ERR_EEPROM; 547 } 548 549 /* Skip pointer section if length is invalid. */ 550 if (length == 0xFFFF || length == 0 || 551 (pointer + length) >= hw->eeprom.word_size) 552 continue; 553 554 for (j = pointer + 1; j <= pointer + length; j++) { 555 if (ixgbe_read_eerd_generic(hw, j, &word)) { 556 DEBUGOUT("EEPROM read failed\n"); 557 return IXGBE_ERR_EEPROM; 558 } 559 checksum += word; 560 } 561 } 562 563 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 564 565 return (s32)checksum; 566} 567 568/** 569 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum 570 * @hw: pointer to hardware structure 571 * @checksum_val: calculated checksum 572 * 573 * Performs checksum calculation and validates the EEPROM checksum. If the 574 * caller does not need checksum_val, the value can be NULL. 575 **/ 576s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, 577 u16 *checksum_val) 578{ 579 s32 status; 580 u16 checksum; 581 u16 read_checksum = 0; 582 583 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540"); 584 585 /* Read the first word from the EEPROM. If this times out or fails, do 586 * not continue or we could be in for a very long wait while every 587 * EEPROM read fails 588 */ 589 status = hw->eeprom.ops.read(hw, 0, &checksum); 590 if (status) { 591 DEBUGOUT("EEPROM read failed\n"); 592 return status; 593 } 594 595 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 596 return IXGBE_ERR_SWFW_SYNC; 597 598 status = hw->eeprom.ops.calc_checksum(hw); 599 if (status < 0) 600 goto out; 601 602 checksum = (u16)(status & 0xffff); 603 604 /* Do not use hw->eeprom.ops.read because we do not want to take 605 * the synchronization semaphores twice here. 606 */ 607 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM, 608 &read_checksum); 609 if (status) 610 goto out; 611 612 /* Verify read checksum from EEPROM is the same as 613 * calculated checksum 614 */ 615 if (read_checksum != checksum) { 616 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 617 "Invalid EEPROM checksum"); 618 status = IXGBE_ERR_EEPROM_CHECKSUM; 619 } 620 621 /* If the user cares, return the calculated checksum */ 622 if (checksum_val) 623 *checksum_val = checksum; 624 625out: 626 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 627 628 return status; 629} 630 631/** 632 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash 633 * @hw: pointer to hardware structure 634 * 635 * After writing EEPROM to shadow RAM using EEWR register, software calculates 636 * checksum and updates the EEPROM and instructs the hardware to update 637 * the flash. 638 **/ 639s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) 640{ 641 s32 status; 642 u16 checksum; 643 644 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540"); 645 646 /* Read the first word from the EEPROM. If this times out or fails, do 647 * not continue or we could be in for a very long wait while every 648 * EEPROM read fails 649 */ 650 status = hw->eeprom.ops.read(hw, 0, &checksum); 651 if (status) { 652 DEBUGOUT("EEPROM read failed\n"); 653 return status; 654 } 655 656 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 657 return IXGBE_ERR_SWFW_SYNC; 658 659 status = hw->eeprom.ops.calc_checksum(hw); 660 if (status < 0) 661 goto out; 662 663 checksum = (u16)(status & 0xffff); 664 665 /* Do not use hw->eeprom.ops.write because we do not want to 666 * take the synchronization semaphores twice here. 667 */ 668 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum); 669 if (status) 670 goto out; 671 672 status = ixgbe_update_flash_X540(hw); 673 674out: 675 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 676 677 return status; 678} 679 680/** 681 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device 682 * @hw: pointer to hardware structure 683 * 684 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy 685 * EEPROM from shadow RAM to the flash device. 686 **/ 687s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) 688{ 689 u32 flup; 690 s32 status; 691 692 DEBUGFUNC("ixgbe_update_flash_X540"); 693 694 status = ixgbe_poll_flash_update_done_X540(hw); 695 if (status == IXGBE_ERR_EEPROM) { 696 DEBUGOUT("Flash update time out\n"); 697 goto out; 698 } 699 700 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)) | IXGBE_EEC_FLUP; 701 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup); 702 703 status = ixgbe_poll_flash_update_done_X540(hw); 704 if (status == IXGBE_SUCCESS) 705 DEBUGOUT("Flash update complete\n"); 706 else 707 DEBUGOUT("Flash update time out\n"); 708 709 if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) { 710 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 711 712 if (flup & IXGBE_EEC_SEC1VAL) { 713 flup |= IXGBE_EEC_FLUP; 714 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup); 715 } 716 717 status = ixgbe_poll_flash_update_done_X540(hw); 718 if (status == IXGBE_SUCCESS) 719 DEBUGOUT("Flash update complete\n"); 720 else 721 DEBUGOUT("Flash update time out\n"); 722 } 723out: 724 return status; 725} 726 727/** 728 * ixgbe_poll_flash_update_done_X540 - Poll flash update status 729 * @hw: pointer to hardware structure 730 * 731 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the 732 * flash update is done. 733 **/ 734static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) 735{ 736 u32 i; 737 u32 reg; 738 s32 status = IXGBE_ERR_EEPROM; 739 740 DEBUGFUNC("ixgbe_poll_flash_update_done_X540"); 741 742 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) { 743 reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 744 if (reg & IXGBE_EEC_FLUDONE) { 745 status = IXGBE_SUCCESS; 746 break; 747 } 748 msec_delay(5); 749 } 750 751 if (i == IXGBE_FLUDONE_ATTEMPTS) 752 ERROR_REPORT1(IXGBE_ERROR_POLLING, 753 "Flash update status polling timed out"); 754 755 return status; 756} 757 758/** 759 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore 760 * @hw: pointer to hardware structure 761 * @mask: Mask to specify which semaphore to acquire 762 * 763 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for 764 * the specified function (CSR, PHY0, PHY1, NVM, Flash) 765 **/ 766s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) 767{ 768 u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK; 769 u32 fwmask = swmask << 5; 770 u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK; 771 u32 timeout = 200; 772 u32 hwmask = 0; 773 u32 swfw_sync; 774 u32 i; 775 776 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540"); 777 778 if (swmask & IXGBE_GSSR_EEP_SM) 779 hwmask |= IXGBE_GSSR_FLASH_SM; 780 781 /* SW only mask doesn't have FW bit pair */ 782 if (mask & IXGBE_GSSR_SW_MNG_SM) 783 swmask |= IXGBE_GSSR_SW_MNG_SM; 784 785 swmask |= swi2c_mask; 786 fwmask |= swi2c_mask << 2; 787 for (i = 0; i < timeout; i++) { 788 /* SW NVM semaphore bit is used for access to all 789 * SW_FW_SYNC bits (not just NVM) 790 */ 791 if (ixgbe_get_swfw_sync_semaphore(hw)) { 792 DEBUGOUT("Failed to get NVM access and register semaphore, returning IXGBE_ERR_SWFW_SYNC\n"); 793 return IXGBE_ERR_SWFW_SYNC; 794 } 795 796 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 797 if (!(swfw_sync & (fwmask | swmask | hwmask))) { 798 swfw_sync |= swmask; 799 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), 800 swfw_sync); 801 ixgbe_release_swfw_sync_semaphore(hw); 802 return IXGBE_SUCCESS; 803 } 804 /* Firmware currently using resource (fwmask), hardware 805 * currently using resource (hwmask), or other software 806 * thread currently using resource (swmask) 807 */ 808 ixgbe_release_swfw_sync_semaphore(hw); 809 msec_delay(5); 810 } 811 812 /* If the resource is not released by the FW/HW the SW can assume that 813 * the FW/HW malfunctions. In that case the SW should set the SW bit(s) 814 * of the requested resource(s) while ignoring the corresponding FW/HW 815 * bits in the SW_FW_SYNC register. 816 */ 817 if (ixgbe_get_swfw_sync_semaphore(hw)) { 818 DEBUGOUT("Failed to get NVM sempahore and register semaphore while forcefully ignoring FW sempahore bit(s) and setting SW semaphore bit(s), returning IXGBE_ERR_SWFW_SYNC\n"); 819 return IXGBE_ERR_SWFW_SYNC; 820 } 821 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 822 if (swfw_sync & (fwmask | hwmask)) { 823 swfw_sync |= swmask; 824 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync); 825 ixgbe_release_swfw_sync_semaphore(hw); 826 msec_delay(5); 827 return IXGBE_SUCCESS; 828 } 829 /* If the resource is not released by other SW the SW can assume that 830 * the other SW malfunctions. In that case the SW should clear all SW 831 * flags that it does not own and then repeat the whole process once 832 * again. 833 */ 834 if (swfw_sync & swmask) { 835 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM | 836 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM | 837 IXGBE_GSSR_SW_MNG_SM; 838 839 if (swi2c_mask) 840 rmask |= IXGBE_GSSR_I2C_MASK; 841 ixgbe_release_swfw_sync_X540(hw, rmask); 842 ixgbe_release_swfw_sync_semaphore(hw); 843 DEBUGOUT("Resource not released by other SW, returning IXGBE_ERR_SWFW_SYNC\n"); 844 return IXGBE_ERR_SWFW_SYNC; 845 } 846 ixgbe_release_swfw_sync_semaphore(hw); 847 DEBUGOUT("Returning error IXGBE_ERR_SWFW_SYNC\n"); 848 849 return IXGBE_ERR_SWFW_SYNC; 850} 851 852/** 853 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore 854 * @hw: pointer to hardware structure 855 * @mask: Mask to specify which semaphore to release 856 * 857 * Releases the SWFW semaphore through the SW_FW_SYNC register 858 * for the specified function (CSR, PHY0, PHY1, EVM, Flash) 859 **/ 860void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) 861{ 862 u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM); 863 u32 swfw_sync; 864 865 DEBUGFUNC("ixgbe_release_swfw_sync_X540"); 866 867 if (mask & IXGBE_GSSR_I2C_MASK) 868 swmask |= mask & IXGBE_GSSR_I2C_MASK; 869 ixgbe_get_swfw_sync_semaphore(hw); 870 871 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 872 swfw_sync &= ~swmask; 873 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync); 874 875 ixgbe_release_swfw_sync_semaphore(hw); 876 msec_delay(2); 877} 878 879/** 880 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore 881 * @hw: pointer to hardware structure 882 * 883 * Sets the hardware semaphores so SW/FW can gain control of shared resources 884 **/ 885static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) 886{ 887 s32 status = IXGBE_ERR_EEPROM; 888 u32 timeout = 2000; 889 u32 i; 890 u32 swsm; 891 892 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore"); 893 894 /* Get SMBI software semaphore between device drivers first */ 895 for (i = 0; i < timeout; i++) { 896 /* 897 * If the SMBI bit is 0 when we read it, then the bit will be 898 * set and we have the semaphore 899 */ 900 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 901 if (!(swsm & IXGBE_SWSM_SMBI)) { 902 status = IXGBE_SUCCESS; 903 break; 904 } 905 usec_delay(50); 906 } 907 908 /* Now get the semaphore between SW/FW through the REGSMP bit */ 909 if (status == IXGBE_SUCCESS) { 910 for (i = 0; i < timeout; i++) { 911 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 912 if (!(swsm & IXGBE_SWFW_REGSMP)) 913 break; 914 915 usec_delay(50); 916 } 917 918 /* 919 * Release semaphores and return error if SW NVM semaphore 920 * was not granted because we don't have access to the EEPROM 921 */ 922 if (i >= timeout) { 923 ERROR_REPORT1(IXGBE_ERROR_POLLING, 924 "REGSMP Software NVM semaphore not granted.\n"); 925 ixgbe_release_swfw_sync_semaphore(hw); 926 status = IXGBE_ERR_EEPROM; 927 } 928 } else { 929 ERROR_REPORT1(IXGBE_ERROR_POLLING, 930 "Software semaphore SMBI between device drivers " 931 "not granted.\n"); 932 } 933 934 return status; 935} 936 937/** 938 * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore 939 * @hw: pointer to hardware structure 940 * 941 * This function clears hardware semaphore bits. 942 **/ 943static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) 944{ 945 u32 swsm; 946 947 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore"); 948 949 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */ 950 951 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 952 swsm &= ~IXGBE_SWFW_REGSMP; 953 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swsm); 954 955 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 956 swsm &= ~IXGBE_SWSM_SMBI; 957 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); 958 959 IXGBE_WRITE_FLUSH(hw); 960} 961 962/** 963 * ixgbe_init_swfw_sync_X540 - Release hardware semaphore 964 * @hw: pointer to hardware structure 965 * 966 * This function reset hardware semaphore bits for a semaphore that may 967 * have be left locked due to a catastrophic failure. 968 **/ 969void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw) 970{ 971 u32 rmask; 972 973 /* First try to grab the semaphore but we don't need to bother 974 * looking to see whether we got the lock or not since we do 975 * the same thing regardless of whether we got the lock or not. 976 * We got the lock - we release it. 977 * We timeout trying to get the lock - we force its release. 978 */ 979 ixgbe_get_swfw_sync_semaphore(hw); 980 ixgbe_release_swfw_sync_semaphore(hw); 981 982 /* Acquire and release all software resources. */ 983 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM | 984 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM | 985 IXGBE_GSSR_SW_MNG_SM; 986 987 rmask |= IXGBE_GSSR_I2C_MASK; 988 ixgbe_acquire_swfw_sync_X540(hw, rmask); 989 ixgbe_release_swfw_sync_X540(hw, rmask); 990} 991 992/** 993 * ixgbe_blink_led_start_X540 - Blink LED based on index. 994 * @hw: pointer to hardware structure 995 * @index: led number to blink 996 * 997 * Devices that implement the version 2 interface: 998 * X540 999 **/ 1000s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index) 1001{ 1002 u32 macc_reg; 1003 u32 ledctl_reg; 1004 ixgbe_link_speed speed; 1005 bool link_up; 1006 1007 DEBUGFUNC("ixgbe_blink_led_start_X540"); 1008 1009 if (index > 3) 1010 return IXGBE_ERR_PARAM; 1011 1012 /* 1013 * Link should be up in order for the blink bit in the LED control 1014 * register to work. Force link and speed in the MAC if link is down. 1015 * This will be reversed when we stop the blinking. 1016 */ 1017 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 1018 if (link_up == FALSE) { 1019 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 1020 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS; 1021 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 1022 } 1023 /* Set the LED to LINK_UP + BLINK. */ 1024 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1025 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 1026 ledctl_reg |= IXGBE_LED_BLINK(index); 1027 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 1028 IXGBE_WRITE_FLUSH(hw); 1029 1030 return IXGBE_SUCCESS; 1031} 1032 1033/** 1034 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index. 1035 * @hw: pointer to hardware structure 1036 * @index: led number to stop blinking 1037 * 1038 * Devices that implement the version 2 interface: 1039 * X540 1040 **/ 1041s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index) 1042{ 1043 u32 macc_reg; 1044 u32 ledctl_reg; 1045 1046 if (index > 3) 1047 return IXGBE_ERR_PARAM; 1048 1049 DEBUGFUNC("ixgbe_blink_led_stop_X540"); 1050 1051 /* Restore the LED to its default value. */ 1052 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1053 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 1054 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 1055 ledctl_reg &= ~IXGBE_LED_BLINK(index); 1056 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 1057 1058 /* Unforce link and speed in the MAC. */ 1059 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 1060 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS); 1061 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 1062 IXGBE_WRITE_FLUSH(hw); 1063 1064 return IXGBE_SUCCESS; 1065} 1066