ixgbe_x540.c revision 295093
1/****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_x540.c 295093 2016-01-31 15:14:23Z smh $*/ 34 35#include "ixgbe_x540.h" 36#include "ixgbe_type.h" 37#include "ixgbe_api.h" 38#include "ixgbe_common.h" 39#include "ixgbe_phy.h" 40 41#define IXGBE_X540_MAX_TX_QUEUES 128 42#define IXGBE_X540_MAX_RX_QUEUES 128 43#define IXGBE_X540_RAR_ENTRIES 128 44#define IXGBE_X540_MC_TBL_SIZE 128 45#define IXGBE_X540_VFT_TBL_SIZE 128 46#define IXGBE_X540_RX_PB_SIZE 384 47 48static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); 49static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); 50static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); 51 52/** 53 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type 54 * @hw: pointer to hardware structure 55 * 56 * Initialize the function pointers and assign the MAC type for X540. 57 * Does not touch the hardware. 58 **/ 59s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) 60{ 61 struct ixgbe_mac_info *mac = &hw->mac; 62 struct ixgbe_phy_info *phy = &hw->phy; 63 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 64 s32 ret_val; 65 66 DEBUGFUNC("ixgbe_init_ops_X540"); 67 68 ret_val = ixgbe_init_phy_ops_generic(hw); 69 ret_val = ixgbe_init_ops_generic(hw); 70 71 72 /* EEPROM */ 73 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540; 74 eeprom->ops.read = ixgbe_read_eerd_X540; 75 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_X540; 76 eeprom->ops.write = ixgbe_write_eewr_X540; 77 eeprom->ops.write_buffer = ixgbe_write_eewr_buffer_X540; 78 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X540; 79 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X540; 80 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X540; 81 82 /* PHY */ 83 phy->ops.init = ixgbe_init_phy_ops_generic; 84 phy->ops.reset = NULL; 85 phy->ops.set_phy_power = ixgbe_set_copper_phy_power; 86 87 /* MAC */ 88 mac->ops.reset_hw = ixgbe_reset_hw_X540; 89 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2; 90 mac->ops.get_media_type = ixgbe_get_media_type_X540; 91 mac->ops.get_supported_physical_layer = 92 ixgbe_get_supported_physical_layer_X540; 93 mac->ops.read_analog_reg8 = NULL; 94 mac->ops.write_analog_reg8 = NULL; 95 mac->ops.start_hw = ixgbe_start_hw_X540; 96 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic; 97 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic; 98 mac->ops.get_device_caps = ixgbe_get_device_caps_generic; 99 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic; 100 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic; 101 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540; 102 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X540; 103 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic; 104 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic; 105 106 /* RAR, Multicast, VLAN */ 107 mac->ops.set_vmdq = ixgbe_set_vmdq_generic; 108 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic; 109 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic; 110 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic; 111 mac->rar_highwater = 1; 112 mac->ops.set_vfta = ixgbe_set_vfta_generic; 113 mac->ops.set_vlvf = ixgbe_set_vlvf_generic; 114 mac->ops.clear_vfta = ixgbe_clear_vfta_generic; 115 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic; 116 mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing; 117 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing; 118 119 /* Link */ 120 mac->ops.get_link_capabilities = 121 ixgbe_get_copper_link_capabilities_generic; 122 mac->ops.setup_link = ixgbe_setup_mac_link_X540; 123 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic; 124 mac->ops.check_link = ixgbe_check_mac_link_generic; 125 126 127 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE; 128 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE; 129 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES; 130 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE; 131 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES; 132 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES; 133 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 134 135 /* 136 * FWSM register 137 * ARC supported; valid only if manageability features are 138 * enabled. 139 */ 140 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)) 141 & IXGBE_FWSM_MODE_MASK); 142 143 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 144 145 /* LEDs */ 146 mac->ops.blink_led_start = ixgbe_blink_led_start_X540; 147 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540; 148 149 /* Manageability interface */ 150 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic; 151 152 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; 153 154 return ret_val; 155} 156 157/** 158 * ixgbe_get_link_capabilities_X540 - Determines link capabilities 159 * @hw: pointer to hardware structure 160 * @speed: pointer to link speed 161 * @autoneg: TRUE when autoneg or autotry is enabled 162 * 163 * Determines the link capabilities by reading the AUTOC register. 164 **/ 165s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw, 166 ixgbe_link_speed *speed, 167 bool *autoneg) 168{ 169 ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg); 170 171 return IXGBE_SUCCESS; 172} 173 174/** 175 * ixgbe_get_media_type_X540 - Get media type 176 * @hw: pointer to hardware structure 177 * 178 * Returns the media type (fiber, copper, backplane) 179 **/ 180enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) 181{ 182 UNREFERENCED_1PARAMETER(hw); 183 return ixgbe_media_type_copper; 184} 185 186/** 187 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities 188 * @hw: pointer to hardware structure 189 * @speed: new link speed 190 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 191 **/ 192s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, 193 ixgbe_link_speed speed, 194 bool autoneg_wait_to_complete) 195{ 196 DEBUGFUNC("ixgbe_setup_mac_link_X540"); 197 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete); 198} 199 200/** 201 * ixgbe_reset_hw_X540 - Perform hardware reset 202 * @hw: pointer to hardware structure 203 * 204 * Resets the hardware by resetting the transmit and receive units, masks 205 * and clears all interrupts, and perform a reset. 206 **/ 207s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw) 208{ 209 s32 status; 210 u32 ctrl, i; 211 212 DEBUGFUNC("ixgbe_reset_hw_X540"); 213 214 /* Call adapter stop to disable tx/rx and clear interrupts */ 215 status = hw->mac.ops.stop_adapter(hw); 216 if (status != IXGBE_SUCCESS) 217 goto reset_hw_out; 218 219 /* flush pending Tx transactions */ 220 ixgbe_clear_tx_pending(hw); 221 222mac_reset_top: 223 ctrl = IXGBE_CTRL_RST; 224 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 225 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 226 IXGBE_WRITE_FLUSH(hw); 227 228 /* Poll for reset bit to self-clear indicating reset is complete */ 229 for (i = 0; i < 10; i++) { 230 usec_delay(1); 231 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 232 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 233 break; 234 } 235 236 if (ctrl & IXGBE_CTRL_RST_MASK) { 237 status = IXGBE_ERR_RESET_FAILED; 238 ERROR_REPORT1(IXGBE_ERROR_POLLING, 239 "Reset polling failed to complete.\n"); 240 } 241 msec_delay(100); 242 243 /* 244 * Double resets are required for recovery from certain error 245 * conditions. Between resets, it is necessary to stall to allow time 246 * for any pending HW events to complete. 247 */ 248 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 249 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 250 goto mac_reset_top; 251 } 252 253 /* Set the Rx packet buffer size. */ 254 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT); 255 256 /* Store the permanent mac address */ 257 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 258 259 /* 260 * Store MAC address from RAR0, clear receive address registers, and 261 * clear the multicast table. Also reset num_rar_entries to 128, 262 * since we modify this value when programming the SAN MAC address. 263 */ 264 hw->mac.num_rar_entries = 128; 265 hw->mac.ops.init_rx_addrs(hw); 266 267 /* Store the permanent SAN mac address */ 268 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 269 270 /* Add the SAN MAC address to the RAR only if it's a valid address */ 271 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 272 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, 273 hw->mac.san_addr, 0, IXGBE_RAH_AV); 274 275 /* Save the SAN MAC RAR index */ 276 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 277 278 /* Reserve the last RAR for the SAN MAC address */ 279 hw->mac.num_rar_entries--; 280 } 281 282 /* Store the alternative WWNN/WWPN prefix */ 283 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 284 &hw->mac.wwpn_prefix); 285 286reset_hw_out: 287 return status; 288} 289 290/** 291 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx 292 * @hw: pointer to hardware structure 293 * 294 * Starts the hardware using the generic start_hw function 295 * and the generation start_hw function. 296 * Then performs revision-specific operations, if any. 297 **/ 298s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw) 299{ 300 s32 ret_val = IXGBE_SUCCESS; 301 302 DEBUGFUNC("ixgbe_start_hw_X540"); 303 304 ret_val = ixgbe_start_hw_generic(hw); 305 if (ret_val != IXGBE_SUCCESS) 306 goto out; 307 308 ret_val = ixgbe_start_hw_gen2(hw); 309 310out: 311 return ret_val; 312} 313 314/** 315 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type 316 * @hw: pointer to hardware structure 317 * 318 * Determines physical layer capabilities of the current configuration. 319 **/ 320u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw) 321{ 322 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 323 u16 ext_ability = 0; 324 325 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540"); 326 327 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 328 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 329 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 330 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 331 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 332 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 333 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 334 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 335 336 return physical_layer; 337} 338 339/** 340 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params 341 * @hw: pointer to hardware structure 342 * 343 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 344 * ixgbe_hw struct in order to set up EEPROM access. 345 **/ 346s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) 347{ 348 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 349 u32 eec; 350 u16 eeprom_size; 351 352 DEBUGFUNC("ixgbe_init_eeprom_params_X540"); 353 354 if (eeprom->type == ixgbe_eeprom_uninitialized) { 355 eeprom->semaphore_delay = 10; 356 eeprom->type = ixgbe_flash; 357 358 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 359 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 360 IXGBE_EEC_SIZE_SHIFT); 361 eeprom->word_size = 1 << (eeprom_size + 362 IXGBE_EEPROM_WORD_SIZE_SHIFT); 363 364 DEBUGOUT2("Eeprom params: type = %d, size = %d\n", 365 eeprom->type, eeprom->word_size); 366 } 367 368 return IXGBE_SUCCESS; 369} 370 371/** 372 * ixgbe_read_eerd_X540- Read EEPROM word using EERD 373 * @hw: pointer to hardware structure 374 * @offset: offset of word in the EEPROM to read 375 * @data: word read from the EEPROM 376 * 377 * Reads a 16 bit word from the EEPROM using the EERD register. 378 **/ 379s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) 380{ 381 s32 status = IXGBE_SUCCESS; 382 383 DEBUGFUNC("ixgbe_read_eerd_X540"); 384 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 385 IXGBE_SUCCESS) { 386 status = ixgbe_read_eerd_generic(hw, offset, data); 387 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 388 } else { 389 status = IXGBE_ERR_SWFW_SYNC; 390 } 391 392 return status; 393} 394 395/** 396 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD 397 * @hw: pointer to hardware structure 398 * @offset: offset of word in the EEPROM to read 399 * @words: number of words 400 * @data: word(s) read from the EEPROM 401 * 402 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 403 **/ 404s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, 405 u16 offset, u16 words, u16 *data) 406{ 407 s32 status = IXGBE_SUCCESS; 408 409 DEBUGFUNC("ixgbe_read_eerd_buffer_X540"); 410 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 411 IXGBE_SUCCESS) { 412 status = ixgbe_read_eerd_buffer_generic(hw, offset, 413 words, data); 414 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 415 } else { 416 status = IXGBE_ERR_SWFW_SYNC; 417 } 418 419 return status; 420} 421 422/** 423 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR 424 * @hw: pointer to hardware structure 425 * @offset: offset of word in the EEPROM to write 426 * @data: word write to the EEPROM 427 * 428 * Write a 16 bit word to the EEPROM using the EEWR register. 429 **/ 430s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data) 431{ 432 s32 status = IXGBE_SUCCESS; 433 434 DEBUGFUNC("ixgbe_write_eewr_X540"); 435 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 436 IXGBE_SUCCESS) { 437 status = ixgbe_write_eewr_generic(hw, offset, data); 438 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 439 } else { 440 status = IXGBE_ERR_SWFW_SYNC; 441 } 442 443 return status; 444} 445 446/** 447 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR 448 * @hw: pointer to hardware structure 449 * @offset: offset of word in the EEPROM to write 450 * @words: number of words 451 * @data: word(s) write to the EEPROM 452 * 453 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 454 **/ 455s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, 456 u16 offset, u16 words, u16 *data) 457{ 458 s32 status = IXGBE_SUCCESS; 459 460 DEBUGFUNC("ixgbe_write_eewr_buffer_X540"); 461 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 462 IXGBE_SUCCESS) { 463 status = ixgbe_write_eewr_buffer_generic(hw, offset, 464 words, data); 465 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 466 } else { 467 status = IXGBE_ERR_SWFW_SYNC; 468 } 469 470 return status; 471} 472 473/** 474 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum 475 * 476 * This function does not use synchronization for EERD and EEWR. It can 477 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540. 478 * 479 * @hw: pointer to hardware structure 480 * 481 * Returns a negative error code on error, or the 16-bit checksum 482 **/ 483s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) 484{ 485 u16 i, j; 486 u16 checksum = 0; 487 u16 length = 0; 488 u16 pointer = 0; 489 u16 word = 0; 490 u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM; 491 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR; 492 493 /* Do not use hw->eeprom.ops.read because we do not want to take 494 * the synchronization semaphores here. Instead use 495 * ixgbe_read_eerd_generic 496 */ 497 498 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540"); 499 500 /* Include 0x0-0x3F in the checksum */ 501 for (i = 0; i <= checksum_last_word; i++) { 502 if (ixgbe_read_eerd_generic(hw, i, &word)) { 503 DEBUGOUT("EEPROM read failed\n"); 504 return IXGBE_ERR_EEPROM; 505 } 506 if (i != IXGBE_EEPROM_CHECKSUM) 507 checksum += word; 508 } 509 510 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the 511 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 512 */ 513 for (i = ptr_start; i < IXGBE_FW_PTR; i++) { 514 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 515 continue; 516 517 if (ixgbe_read_eerd_generic(hw, i, &pointer)) { 518 DEBUGOUT("EEPROM read failed\n"); 519 return IXGBE_ERR_EEPROM; 520 } 521 522 /* Skip pointer section if the pointer is invalid. */ 523 if (pointer == 0xFFFF || pointer == 0 || 524 pointer >= hw->eeprom.word_size) 525 continue; 526 527 if (ixgbe_read_eerd_generic(hw, pointer, &length)) { 528 DEBUGOUT("EEPROM read failed\n"); 529 return IXGBE_ERR_EEPROM; 530 } 531 532 /* Skip pointer section if length is invalid. */ 533 if (length == 0xFFFF || length == 0 || 534 (pointer + length) >= hw->eeprom.word_size) 535 continue; 536 537 for (j = pointer + 1; j <= pointer + length; j++) { 538 if (ixgbe_read_eerd_generic(hw, j, &word)) { 539 DEBUGOUT("EEPROM read failed\n"); 540 return IXGBE_ERR_EEPROM; 541 } 542 checksum += word; 543 } 544 } 545 546 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 547 548 return (s32)checksum; 549} 550 551/** 552 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum 553 * @hw: pointer to hardware structure 554 * @checksum_val: calculated checksum 555 * 556 * Performs checksum calculation and validates the EEPROM checksum. If the 557 * caller does not need checksum_val, the value can be NULL. 558 **/ 559s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, 560 u16 *checksum_val) 561{ 562 s32 status; 563 u16 checksum; 564 u16 read_checksum = 0; 565 566 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540"); 567 568 /* Read the first word from the EEPROM. If this times out or fails, do 569 * not continue or we could be in for a very long wait while every 570 * EEPROM read fails 571 */ 572 status = hw->eeprom.ops.read(hw, 0, &checksum); 573 if (status) { 574 DEBUGOUT("EEPROM read failed\n"); 575 return status; 576 } 577 578 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 579 return IXGBE_ERR_SWFW_SYNC; 580 581 status = hw->eeprom.ops.calc_checksum(hw); 582 if (status < 0) 583 goto out; 584 585 checksum = (u16)(status & 0xffff); 586 587 /* Do not use hw->eeprom.ops.read because we do not want to take 588 * the synchronization semaphores twice here. 589 */ 590 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM, 591 &read_checksum); 592 if (status) 593 goto out; 594 595 /* Verify read checksum from EEPROM is the same as 596 * calculated checksum 597 */ 598 if (read_checksum != checksum) { 599 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 600 "Invalid EEPROM checksum"); 601 status = IXGBE_ERR_EEPROM_CHECKSUM; 602 } 603 604 /* If the user cares, return the calculated checksum */ 605 if (checksum_val) 606 *checksum_val = checksum; 607 608out: 609 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 610 611 return status; 612} 613 614/** 615 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash 616 * @hw: pointer to hardware structure 617 * 618 * After writing EEPROM to shadow RAM using EEWR register, software calculates 619 * checksum and updates the EEPROM and instructs the hardware to update 620 * the flash. 621 **/ 622s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) 623{ 624 s32 status; 625 u16 checksum; 626 627 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540"); 628 629 /* Read the first word from the EEPROM. If this times out or fails, do 630 * not continue or we could be in for a very long wait while every 631 * EEPROM read fails 632 */ 633 status = hw->eeprom.ops.read(hw, 0, &checksum); 634 if (status) { 635 DEBUGOUT("EEPROM read failed\n"); 636 return status; 637 } 638 639 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 640 return IXGBE_ERR_SWFW_SYNC; 641 642 status = hw->eeprom.ops.calc_checksum(hw); 643 if (status < 0) 644 goto out; 645 646 checksum = (u16)(status & 0xffff); 647 648 /* Do not use hw->eeprom.ops.write because we do not want to 649 * take the synchronization semaphores twice here. 650 */ 651 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum); 652 if (status) 653 goto out; 654 655 status = ixgbe_update_flash_X540(hw); 656 657out: 658 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 659 660 return status; 661} 662 663/** 664 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device 665 * @hw: pointer to hardware structure 666 * 667 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy 668 * EEPROM from shadow RAM to the flash device. 669 **/ 670s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) 671{ 672 u32 flup; 673 s32 status; 674 675 DEBUGFUNC("ixgbe_update_flash_X540"); 676 677 status = ixgbe_poll_flash_update_done_X540(hw); 678 if (status == IXGBE_ERR_EEPROM) { 679 DEBUGOUT("Flash update time out\n"); 680 goto out; 681 } 682 683 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)) | IXGBE_EEC_FLUP; 684 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup); 685 686 status = ixgbe_poll_flash_update_done_X540(hw); 687 if (status == IXGBE_SUCCESS) 688 DEBUGOUT("Flash update complete\n"); 689 else 690 DEBUGOUT("Flash update time out\n"); 691 692 if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) { 693 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 694 695 if (flup & IXGBE_EEC_SEC1VAL) { 696 flup |= IXGBE_EEC_FLUP; 697 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup); 698 } 699 700 status = ixgbe_poll_flash_update_done_X540(hw); 701 if (status == IXGBE_SUCCESS) 702 DEBUGOUT("Flash update complete\n"); 703 else 704 DEBUGOUT("Flash update time out\n"); 705 } 706out: 707 return status; 708} 709 710/** 711 * ixgbe_poll_flash_update_done_X540 - Poll flash update status 712 * @hw: pointer to hardware structure 713 * 714 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the 715 * flash update is done. 716 **/ 717static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) 718{ 719 u32 i; 720 u32 reg; 721 s32 status = IXGBE_ERR_EEPROM; 722 723 DEBUGFUNC("ixgbe_poll_flash_update_done_X540"); 724 725 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) { 726 reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 727 if (reg & IXGBE_EEC_FLUDONE) { 728 status = IXGBE_SUCCESS; 729 break; 730 } 731 msec_delay(5); 732 } 733 734 if (i == IXGBE_FLUDONE_ATTEMPTS) 735 ERROR_REPORT1(IXGBE_ERROR_POLLING, 736 "Flash update status polling timed out"); 737 738 return status; 739} 740 741/** 742 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore 743 * @hw: pointer to hardware structure 744 * @mask: Mask to specify which semaphore to acquire 745 * 746 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for 747 * the specified function (CSR, PHY0, PHY1, NVM, Flash) 748 **/ 749s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) 750{ 751 u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK; 752 u32 fwmask = swmask << 5; 753 u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK; 754 u32 timeout = 200; 755 u32 hwmask = 0; 756 u32 swfw_sync; 757 u32 i; 758 759 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540"); 760 761 if (swmask & IXGBE_GSSR_EEP_SM) 762 hwmask |= IXGBE_GSSR_FLASH_SM; 763 764 /* SW only mask doesn't have FW bit pair */ 765 if (mask & IXGBE_GSSR_SW_MNG_SM) 766 swmask |= IXGBE_GSSR_SW_MNG_SM; 767 768 swmask |= swi2c_mask; 769 fwmask |= swi2c_mask << 2; 770 for (i = 0; i < timeout; i++) { 771 /* SW NVM semaphore bit is used for access to all 772 * SW_FW_SYNC bits (not just NVM) 773 */ 774 if (ixgbe_get_swfw_sync_semaphore(hw)) 775 return IXGBE_ERR_SWFW_SYNC; 776 777 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 778 if (!(swfw_sync & (fwmask | swmask | hwmask))) { 779 swfw_sync |= swmask; 780 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), 781 swfw_sync); 782 ixgbe_release_swfw_sync_semaphore(hw); 783 msec_delay(5); 784 return IXGBE_SUCCESS; 785 } 786 /* Firmware currently using resource (fwmask), hardware 787 * currently using resource (hwmask), or other software 788 * thread currently using resource (swmask) 789 */ 790 ixgbe_release_swfw_sync_semaphore(hw); 791 msec_delay(5); 792 } 793 794 /* Failed to get SW only semaphore */ 795 if (swmask == IXGBE_GSSR_SW_MNG_SM) { 796 ERROR_REPORT1(IXGBE_ERROR_POLLING, 797 "Failed to get SW only semaphore"); 798 return IXGBE_ERR_SWFW_SYNC; 799 } 800 801 /* If the resource is not released by the FW/HW the SW can assume that 802 * the FW/HW malfunctions. In that case the SW should set the SW bit(s) 803 * of the requested resource(s) while ignoring the corresponding FW/HW 804 * bits in the SW_FW_SYNC register. 805 */ 806 if (ixgbe_get_swfw_sync_semaphore(hw)) 807 return IXGBE_ERR_SWFW_SYNC; 808 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 809 if (swfw_sync & (fwmask | hwmask)) { 810 swfw_sync |= swmask; 811 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync); 812 ixgbe_release_swfw_sync_semaphore(hw); 813 msec_delay(5); 814 return IXGBE_SUCCESS; 815 } 816 /* If the resource is not released by other SW the SW can assume that 817 * the other SW malfunctions. In that case the SW should clear all SW 818 * flags that it does not own and then repeat the whole process once 819 * again. 820 */ 821 if (swfw_sync & swmask) { 822 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM | 823 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM; 824 825 if (swi2c_mask) 826 rmask |= IXGBE_GSSR_I2C_MASK; 827 ixgbe_release_swfw_sync_X540(hw, rmask); 828 ixgbe_release_swfw_sync_semaphore(hw); 829 return IXGBE_ERR_SWFW_SYNC; 830 } 831 ixgbe_release_swfw_sync_semaphore(hw); 832 833 return IXGBE_ERR_SWFW_SYNC; 834} 835 836/** 837 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore 838 * @hw: pointer to hardware structure 839 * @mask: Mask to specify which semaphore to release 840 * 841 * Releases the SWFW semaphore through the SW_FW_SYNC register 842 * for the specified function (CSR, PHY0, PHY1, EVM, Flash) 843 **/ 844void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) 845{ 846 u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM); 847 u32 swfw_sync; 848 849 DEBUGFUNC("ixgbe_release_swfw_sync_X540"); 850 851 if (mask & IXGBE_GSSR_I2C_MASK) 852 swmask |= mask & IXGBE_GSSR_I2C_MASK; 853 ixgbe_get_swfw_sync_semaphore(hw); 854 855 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 856 swfw_sync &= ~swmask; 857 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync); 858 859 ixgbe_release_swfw_sync_semaphore(hw); 860 msec_delay(5); 861} 862 863/** 864 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore 865 * @hw: pointer to hardware structure 866 * 867 * Sets the hardware semaphores so SW/FW can gain control of shared resources 868 **/ 869static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) 870{ 871 s32 status = IXGBE_ERR_EEPROM; 872 u32 timeout = 2000; 873 u32 i; 874 u32 swsm; 875 876 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore"); 877 878 /* Get SMBI software semaphore between device drivers first */ 879 for (i = 0; i < timeout; i++) { 880 /* 881 * If the SMBI bit is 0 when we read it, then the bit will be 882 * set and we have the semaphore 883 */ 884 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 885 if (!(swsm & IXGBE_SWSM_SMBI)) { 886 status = IXGBE_SUCCESS; 887 break; 888 } 889 usec_delay(50); 890 } 891 892 /* Now get the semaphore between SW/FW through the REGSMP bit */ 893 if (status == IXGBE_SUCCESS) { 894 for (i = 0; i < timeout; i++) { 895 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 896 if (!(swsm & IXGBE_SWFW_REGSMP)) 897 break; 898 899 usec_delay(50); 900 } 901 902 /* 903 * Release semaphores and return error if SW NVM semaphore 904 * was not granted because we don't have access to the EEPROM 905 */ 906 if (i >= timeout) { 907 ERROR_REPORT1(IXGBE_ERROR_POLLING, 908 "REGSMP Software NVM semaphore not granted.\n"); 909 ixgbe_release_swfw_sync_semaphore(hw); 910 status = IXGBE_ERR_EEPROM; 911 } 912 } else { 913 ERROR_REPORT1(IXGBE_ERROR_POLLING, 914 "Software semaphore SMBI between device drivers " 915 "not granted.\n"); 916 } 917 918 return status; 919} 920 921/** 922 * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore 923 * @hw: pointer to hardware structure 924 * 925 * This function clears hardware semaphore bits. 926 **/ 927static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) 928{ 929 u32 swsm; 930 931 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore"); 932 933 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */ 934 935 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 936 swsm &= ~IXGBE_SWFW_REGSMP; 937 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swsm); 938 939 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 940 swsm &= ~IXGBE_SWSM_SMBI; 941 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); 942 943 IXGBE_WRITE_FLUSH(hw); 944} 945 946/** 947 * ixgbe_blink_led_start_X540 - Blink LED based on index. 948 * @hw: pointer to hardware structure 949 * @index: led number to blink 950 * 951 * Devices that implement the version 2 interface: 952 * X540 953 **/ 954s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index) 955{ 956 u32 macc_reg; 957 u32 ledctl_reg; 958 ixgbe_link_speed speed; 959 bool link_up; 960 961 DEBUGFUNC("ixgbe_blink_led_start_X540"); 962 963 /* 964 * Link should be up in order for the blink bit in the LED control 965 * register to work. Force link and speed in the MAC if link is down. 966 * This will be reversed when we stop the blinking. 967 */ 968 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 969 if (link_up == FALSE) { 970 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 971 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS; 972 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 973 } 974 /* Set the LED to LINK_UP + BLINK. */ 975 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 976 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 977 ledctl_reg |= IXGBE_LED_BLINK(index); 978 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 979 IXGBE_WRITE_FLUSH(hw); 980 981 return IXGBE_SUCCESS; 982} 983 984/** 985 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index. 986 * @hw: pointer to hardware structure 987 * @index: led number to stop blinking 988 * 989 * Devices that implement the version 2 interface: 990 * X540 991 **/ 992s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index) 993{ 994 u32 macc_reg; 995 u32 ledctl_reg; 996 997 DEBUGFUNC("ixgbe_blink_led_stop_X540"); 998 999 /* Restore the LED to its default value. */ 1000 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1001 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 1002 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 1003 ledctl_reg &= ~IXGBE_LED_BLINK(index); 1004 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 1005 1006 /* Unforce link and speed in the MAC. */ 1007 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 1008 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS); 1009 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 1010 IXGBE_WRITE_FLUSH(hw); 1011 1012 return IXGBE_SUCCESS; 1013} 1014