ixgbe_x540.c revision 230775
1/****************************************************************************** 2 3 Copyright (c) 2001-2012, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_x540.c 230775 2012-01-30 16:42:02Z jfv $*/ 34 35#include "ixgbe_x540.h" 36#include "ixgbe_type.h" 37#include "ixgbe_api.h" 38#include "ixgbe_common.h" 39#include "ixgbe_phy.h" 40 41static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw); 42static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); 43static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); 44static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); 45 46/** 47 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type 48 * @hw: pointer to hardware structure 49 * 50 * Initialize the function pointers and assign the MAC type for X540. 51 * Does not touch the hardware. 52 **/ 53s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) 54{ 55 struct ixgbe_mac_info *mac = &hw->mac; 56 struct ixgbe_phy_info *phy = &hw->phy; 57 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 58 s32 ret_val; 59 60 DEBUGFUNC("ixgbe_init_ops_X540"); 61 62 ret_val = ixgbe_init_phy_ops_generic(hw); 63 ret_val = ixgbe_init_ops_generic(hw); 64 65 66 /* EEPROM */ 67 eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540; 68 eeprom->ops.read = &ixgbe_read_eerd_X540; 69 eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540; 70 eeprom->ops.write = &ixgbe_write_eewr_X540; 71 eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540; 72 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540; 73 eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540; 74 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540; 75 76 /* PHY */ 77 phy->ops.init = &ixgbe_init_phy_ops_generic; 78 phy->ops.reset = NULL; 79 80 /* MAC */ 81 mac->ops.reset_hw = &ixgbe_reset_hw_X540; 82 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2; 83 mac->ops.get_media_type = &ixgbe_get_media_type_X540; 84 mac->ops.get_supported_physical_layer = 85 &ixgbe_get_supported_physical_layer_X540; 86 mac->ops.read_analog_reg8 = NULL; 87 mac->ops.write_analog_reg8 = NULL; 88 mac->ops.start_hw = &ixgbe_start_hw_X540; 89 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic; 90 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic; 91 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic; 92 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic; 93 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic; 94 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540; 95 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540; 96 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic; 97 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic; 98 99 /* RAR, Multicast, VLAN */ 100 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic; 101 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic; 102 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic; 103 mac->rar_highwater = 1; 104 mac->ops.set_vfta = &ixgbe_set_vfta_generic; 105 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic; 106 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic; 107 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic; 108 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing; 109 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing; 110 111 /* Link */ 112 mac->ops.get_link_capabilities = 113 &ixgbe_get_copper_link_capabilities_generic; 114 mac->ops.setup_link = &ixgbe_setup_mac_link_X540; 115 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic; 116 mac->ops.check_link = &ixgbe_check_mac_link_generic; 117 118 mac->mcft_size = 128; 119 mac->vft_size = 128; 120 mac->num_rar_entries = 128; 121 mac->rx_pb_size = 384; 122 mac->max_tx_queues = 128; 123 mac->max_rx_queues = 128; 124 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 125 126 /* 127 * FWSM register 128 * ARC supported; valid only if manageability features are 129 * enabled. 130 */ 131 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) & 132 IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE; 133 134 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 135 136 /* LEDs */ 137 mac->ops.blink_led_start = ixgbe_blink_led_start_X540; 138 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540; 139 140 /* Manageability interface */ 141 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic; 142 143 return ret_val; 144} 145 146/** 147 * ixgbe_get_link_capabilities_X540 - Determines link capabilities 148 * @hw: pointer to hardware structure 149 * @speed: pointer to link speed 150 * @autoneg: TRUE when autoneg or autotry is enabled 151 * 152 * Determines the link capabilities by reading the AUTOC register. 153 **/ 154s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw, 155 ixgbe_link_speed *speed, 156 bool *autoneg) 157{ 158 ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg); 159 160 return IXGBE_SUCCESS; 161} 162 163/** 164 * ixgbe_get_media_type_X540 - Get media type 165 * @hw: pointer to hardware structure 166 * 167 * Returns the media type (fiber, copper, backplane) 168 **/ 169enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) 170{ 171 UNREFERENCED_1PARAMETER(hw); 172 return ixgbe_media_type_copper; 173} 174 175/** 176 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities 177 * @hw: pointer to hardware structure 178 * @speed: new link speed 179 * @autoneg: TRUE if autonegotiation enabled 180 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 181 **/ 182s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, 183 ixgbe_link_speed speed, bool autoneg, 184 bool autoneg_wait_to_complete) 185{ 186 DEBUGFUNC("ixgbe_setup_mac_link_X540"); 187 return hw->phy.ops.setup_link_speed(hw, speed, autoneg, 188 autoneg_wait_to_complete); 189} 190 191/** 192 * ixgbe_reset_hw_X540 - Perform hardware reset 193 * @hw: pointer to hardware structure 194 * 195 * Resets the hardware by resetting the transmit and receive units, masks 196 * and clears all interrupts, and perform a reset. 197 **/ 198s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw) 199{ 200 s32 status; 201 u32 ctrl, i; 202 203 DEBUGFUNC("ixgbe_reset_hw_X540"); 204 205 /* Call adapter stop to disable tx/rx and clear interrupts */ 206 status = hw->mac.ops.stop_adapter(hw); 207 if (status != IXGBE_SUCCESS) 208 goto reset_hw_out; 209 210 /* flush pending Tx transactions */ 211 ixgbe_clear_tx_pending(hw); 212 213mac_reset_top: 214 ctrl = IXGBE_CTRL_RST; 215 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 216 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 217 IXGBE_WRITE_FLUSH(hw); 218 219 /* Poll for reset bit to self-clear indicating reset is complete */ 220 for (i = 0; i < 10; i++) { 221 usec_delay(1); 222 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 223 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 224 break; 225 } 226 227 if (ctrl & IXGBE_CTRL_RST_MASK) { 228 status = IXGBE_ERR_RESET_FAILED; 229 DEBUGOUT("Reset polling failed to complete.\n"); 230 } 231 msec_delay(100); 232 233 /* 234 * Double resets are required for recovery from certain error 235 * conditions. Between resets, it is necessary to stall to allow time 236 * for any pending HW events to complete. 237 */ 238 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 239 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 240 goto mac_reset_top; 241 } 242 243 /* Set the Rx packet buffer size. */ 244 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT); 245 246 /* Store the permanent mac address */ 247 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 248 249 /* 250 * Store MAC address from RAR0, clear receive address registers, and 251 * clear the multicast table. Also reset num_rar_entries to 128, 252 * since we modify this value when programming the SAN MAC address. 253 */ 254 hw->mac.num_rar_entries = 128; 255 hw->mac.ops.init_rx_addrs(hw); 256 257 /* Store the permanent SAN mac address */ 258 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 259 260 /* Add the SAN MAC address to the RAR only if it's a valid address */ 261 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 262 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, 263 hw->mac.san_addr, 0, IXGBE_RAH_AV); 264 265 /* Reserve the last RAR for the SAN MAC address */ 266 hw->mac.num_rar_entries--; 267 } 268 269 /* Store the alternative WWNN/WWPN prefix */ 270 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 271 &hw->mac.wwpn_prefix); 272 273reset_hw_out: 274 return status; 275} 276 277/** 278 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx 279 * @hw: pointer to hardware structure 280 * 281 * Starts the hardware using the generic start_hw function 282 * and the generation start_hw function. 283 * Then performs revision-specific operations, if any. 284 **/ 285s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw) 286{ 287 s32 ret_val = IXGBE_SUCCESS; 288 289 DEBUGFUNC("ixgbe_start_hw_X540"); 290 291 ret_val = ixgbe_start_hw_generic(hw); 292 if (ret_val != IXGBE_SUCCESS) 293 goto out; 294 295 ret_val = ixgbe_start_hw_gen2(hw); 296 297out: 298 return ret_val; 299} 300 301/** 302 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type 303 * @hw: pointer to hardware structure 304 * 305 * Determines physical layer capabilities of the current configuration. 306 **/ 307u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw) 308{ 309 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 310 u16 ext_ability = 0; 311 312 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540"); 313 314 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 315 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 316 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 317 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 318 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 319 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 320 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 321 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 322 323 return physical_layer; 324} 325 326/** 327 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params 328 * @hw: pointer to hardware structure 329 * 330 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 331 * ixgbe_hw struct in order to set up EEPROM access. 332 **/ 333s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) 334{ 335 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 336 u32 eec; 337 u16 eeprom_size; 338 339 DEBUGFUNC("ixgbe_init_eeprom_params_X540"); 340 341 if (eeprom->type == ixgbe_eeprom_uninitialized) { 342 eeprom->semaphore_delay = 10; 343 eeprom->type = ixgbe_flash; 344 345 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 346 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 347 IXGBE_EEC_SIZE_SHIFT); 348 eeprom->word_size = 1 << (eeprom_size + 349 IXGBE_EEPROM_WORD_SIZE_SHIFT); 350 351 DEBUGOUT2("Eeprom params: type = %d, size = %d\n", 352 eeprom->type, eeprom->word_size); 353 } 354 355 return IXGBE_SUCCESS; 356} 357 358/** 359 * ixgbe_read_eerd_X540- Read EEPROM word using EERD 360 * @hw: pointer to hardware structure 361 * @offset: offset of word in the EEPROM to read 362 * @data: word read from the EEPROM 363 * 364 * Reads a 16 bit word from the EEPROM using the EERD register. 365 **/ 366s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) 367{ 368 s32 status = IXGBE_SUCCESS; 369 370 DEBUGFUNC("ixgbe_read_eerd_X540"); 371 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 372 IXGBE_SUCCESS) 373 status = ixgbe_read_eerd_generic(hw, offset, data); 374 else 375 status = IXGBE_ERR_SWFW_SYNC; 376 377 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 378 return status; 379} 380 381/** 382 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD 383 * @hw: pointer to hardware structure 384 * @offset: offset of word in the EEPROM to read 385 * @words: number of words 386 * @data: word(s) read from the EEPROM 387 * 388 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 389 **/ 390s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, 391 u16 offset, u16 words, u16 *data) 392{ 393 s32 status = IXGBE_SUCCESS; 394 395 DEBUGFUNC("ixgbe_read_eerd_buffer_X540"); 396 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 397 IXGBE_SUCCESS) 398 status = ixgbe_read_eerd_buffer_generic(hw, offset, 399 words, data); 400 else 401 status = IXGBE_ERR_SWFW_SYNC; 402 403 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 404 return status; 405} 406 407/** 408 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR 409 * @hw: pointer to hardware structure 410 * @offset: offset of word in the EEPROM to write 411 * @data: word write to the EEPROM 412 * 413 * Write a 16 bit word to the EEPROM using the EEWR register. 414 **/ 415s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data) 416{ 417 s32 status = IXGBE_SUCCESS; 418 419 DEBUGFUNC("ixgbe_write_eewr_X540"); 420 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 421 IXGBE_SUCCESS) 422 status = ixgbe_write_eewr_generic(hw, offset, data); 423 else 424 status = IXGBE_ERR_SWFW_SYNC; 425 426 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 427 return status; 428} 429 430/** 431 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR 432 * @hw: pointer to hardware structure 433 * @offset: offset of word in the EEPROM to write 434 * @words: number of words 435 * @data: word(s) write to the EEPROM 436 * 437 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 438 **/ 439s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, 440 u16 offset, u16 words, u16 *data) 441{ 442 s32 status = IXGBE_SUCCESS; 443 444 DEBUGFUNC("ixgbe_write_eewr_buffer_X540"); 445 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 446 IXGBE_SUCCESS) 447 status = ixgbe_write_eewr_buffer_generic(hw, offset, 448 words, data); 449 else 450 status = IXGBE_ERR_SWFW_SYNC; 451 452 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 453 return status; 454} 455 456/** 457 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum 458 * 459 * This function does not use synchronization for EERD and EEWR. It can 460 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540. 461 * 462 * @hw: pointer to hardware structure 463 **/ 464u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) 465{ 466 u16 i; 467 u16 j; 468 u16 checksum = 0; 469 u16 length = 0; 470 u16 pointer = 0; 471 u16 word = 0; 472 473 /* 474 * Do not use hw->eeprom.ops.read because we do not want to take 475 * the synchronization semaphores here. Instead use 476 * ixgbe_read_eerd_generic 477 */ 478 479 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540"); 480 481 /* Include 0x0-0x3F in the checksum */ 482 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 483 if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) { 484 DEBUGOUT("EEPROM read failed\n"); 485 break; 486 } 487 checksum += word; 488 } 489 490 /* 491 * Include all data from pointers 0x3, 0x6-0xE. This excludes the 492 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 493 */ 494 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 495 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 496 continue; 497 498 if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) { 499 DEBUGOUT("EEPROM read failed\n"); 500 break; 501 } 502 503 /* Skip pointer section if the pointer is invalid. */ 504 if (pointer == 0xFFFF || pointer == 0 || 505 pointer >= hw->eeprom.word_size) 506 continue; 507 508 if (ixgbe_read_eerd_generic(hw, pointer, &length) != 509 IXGBE_SUCCESS) { 510 DEBUGOUT("EEPROM read failed\n"); 511 break; 512 } 513 514 /* Skip pointer section if length is invalid. */ 515 if (length == 0xFFFF || length == 0 || 516 (pointer + length) >= hw->eeprom.word_size) 517 continue; 518 519 for (j = pointer+1; j <= pointer+length; j++) { 520 if (ixgbe_read_eerd_generic(hw, j, &word) != 521 IXGBE_SUCCESS) { 522 DEBUGOUT("EEPROM read failed\n"); 523 break; 524 } 525 checksum += word; 526 } 527 } 528 529 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 530 531 return checksum; 532} 533 534/** 535 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum 536 * @hw: pointer to hardware structure 537 * @checksum_val: calculated checksum 538 * 539 * Performs checksum calculation and validates the EEPROM checksum. If the 540 * caller does not need checksum_val, the value can be NULL. 541 **/ 542s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, 543 u16 *checksum_val) 544{ 545 s32 status; 546 u16 checksum; 547 u16 read_checksum = 0; 548 549 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540"); 550 551 /* 552 * Read the first word from the EEPROM. If this times out or fails, do 553 * not continue or we could be in for a very long wait while every 554 * EEPROM read fails 555 */ 556 status = hw->eeprom.ops.read(hw, 0, &checksum); 557 558 if (status != IXGBE_SUCCESS) { 559 DEBUGOUT("EEPROM read failed\n"); 560 goto out; 561 } 562 563 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 564 IXGBE_SUCCESS) { 565 checksum = hw->eeprom.ops.calc_checksum(hw); 566 567 /* 568 * Do not use hw->eeprom.ops.read because we do not want to take 569 * the synchronization semaphores twice here. 570 */ 571 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM, 572 &read_checksum); 573 574 /* 575 * Verify read checksum from EEPROM is the same as 576 * calculated checksum 577 */ 578 if (read_checksum != checksum) 579 status = IXGBE_ERR_EEPROM_CHECKSUM; 580 581 /* If the user cares, return the calculated checksum */ 582 if (checksum_val) 583 *checksum_val = checksum; 584 } else { 585 status = IXGBE_ERR_SWFW_SYNC; 586 } 587 588 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 589out: 590 return status; 591} 592 593/** 594 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash 595 * @hw: pointer to hardware structure 596 * 597 * After writing EEPROM to shadow RAM using EEWR register, software calculates 598 * checksum and updates the EEPROM and instructs the hardware to update 599 * the flash. 600 **/ 601s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) 602{ 603 s32 status; 604 u16 checksum; 605 606 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540"); 607 608 /* 609 * Read the first word from the EEPROM. If this times out or fails, do 610 * not continue or we could be in for a very long wait while every 611 * EEPROM read fails 612 */ 613 status = hw->eeprom.ops.read(hw, 0, &checksum); 614 615 if (status != IXGBE_SUCCESS) 616 DEBUGOUT("EEPROM read failed\n"); 617 618 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 619 IXGBE_SUCCESS) { 620 checksum = hw->eeprom.ops.calc_checksum(hw); 621 622 /* 623 * Do not use hw->eeprom.ops.write because we do not want to 624 * take the synchronization semaphores twice here. 625 */ 626 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, 627 checksum); 628 629 if (status == IXGBE_SUCCESS) 630 status = ixgbe_update_flash_X540(hw); 631 else 632 status = IXGBE_ERR_SWFW_SYNC; 633 } 634 635 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 636 637 return status; 638} 639 640/** 641 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device 642 * @hw: pointer to hardware structure 643 * 644 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy 645 * EEPROM from shadow RAM to the flash device. 646 **/ 647static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) 648{ 649 u32 flup; 650 s32 status = IXGBE_ERR_EEPROM; 651 652 DEBUGFUNC("ixgbe_update_flash_X540"); 653 654 status = ixgbe_poll_flash_update_done_X540(hw); 655 if (status == IXGBE_ERR_EEPROM) { 656 DEBUGOUT("Flash update time out\n"); 657 goto out; 658 } 659 660 flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP; 661 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); 662 663 status = ixgbe_poll_flash_update_done_X540(hw); 664 if (status == IXGBE_SUCCESS) 665 DEBUGOUT("Flash update complete\n"); 666 else 667 DEBUGOUT("Flash update time out\n"); 668 669 if (hw->revision_id == 0) { 670 flup = IXGBE_READ_REG(hw, IXGBE_EEC); 671 672 if (flup & IXGBE_EEC_SEC1VAL) { 673 flup |= IXGBE_EEC_FLUP; 674 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); 675 } 676 677 status = ixgbe_poll_flash_update_done_X540(hw); 678 if (status == IXGBE_SUCCESS) 679 DEBUGOUT("Flash update complete\n"); 680 else 681 DEBUGOUT("Flash update time out\n"); 682 } 683out: 684 return status; 685} 686 687/** 688 * ixgbe_poll_flash_update_done_X540 - Poll flash update status 689 * @hw: pointer to hardware structure 690 * 691 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the 692 * flash update is done. 693 **/ 694static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) 695{ 696 u32 i; 697 u32 reg; 698 s32 status = IXGBE_ERR_EEPROM; 699 700 DEBUGFUNC("ixgbe_poll_flash_update_done_X540"); 701 702 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) { 703 reg = IXGBE_READ_REG(hw, IXGBE_EEC); 704 if (reg & IXGBE_EEC_FLUDONE) { 705 status = IXGBE_SUCCESS; 706 break; 707 } 708 usec_delay(5); 709 } 710 return status; 711} 712 713/** 714 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore 715 * @hw: pointer to hardware structure 716 * @mask: Mask to specify which semaphore to acquire 717 * 718 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for 719 * the specified function (CSR, PHY0, PHY1, NVM, Flash) 720 **/ 721s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) 722{ 723 u32 swfw_sync; 724 u32 swmask = mask; 725 u32 fwmask = mask << 5; 726 u32 hwmask = 0; 727 u32 timeout = 200; 728 u32 i; 729 s32 ret_val = IXGBE_SUCCESS; 730 731 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540"); 732 733 if (swmask == IXGBE_GSSR_EEP_SM) 734 hwmask = IXGBE_GSSR_FLASH_SM; 735 736 /* SW only mask doesn't have FW bit pair */ 737 if (swmask == IXGBE_GSSR_SW_MNG_SM) 738 fwmask = 0; 739 740 for (i = 0; i < timeout; i++) { 741 /* 742 * SW NVM semaphore bit is used for access to all 743 * SW_FW_SYNC bits (not just NVM) 744 */ 745 if (ixgbe_get_swfw_sync_semaphore(hw)) { 746 ret_val = IXGBE_ERR_SWFW_SYNC; 747 goto out; 748 } 749 750 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 751 if (!(swfw_sync & (fwmask | swmask | hwmask))) { 752 swfw_sync |= swmask; 753 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 754 ixgbe_release_swfw_sync_semaphore(hw); 755 msec_delay(5); 756 goto out; 757 } else { 758 /* 759 * Firmware currently using resource (fwmask), hardware 760 * currently using resource (hwmask), or other software 761 * thread currently using resource (swmask) 762 */ 763 ixgbe_release_swfw_sync_semaphore(hw); 764 msec_delay(5); 765 } 766 } 767 768 /* Failed to get SW only semaphore */ 769 if (swmask == IXGBE_GSSR_SW_MNG_SM) { 770 ret_val = IXGBE_ERR_SWFW_SYNC; 771 goto out; 772 } 773 774 /* If the resource is not released by the FW/HW the SW can assume that 775 * the FW/HW malfunctions. In that case the SW should sets the SW bit(s) 776 * of the requested resource(s) while ignoring the corresponding FW/HW 777 * bits in the SW_FW_SYNC register. 778 */ 779 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 780 if (swfw_sync & (fwmask | hwmask)) { 781 if (ixgbe_get_swfw_sync_semaphore(hw)) { 782 ret_val = IXGBE_ERR_SWFW_SYNC; 783 goto out; 784 } 785 786 swfw_sync |= swmask; 787 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 788 ixgbe_release_swfw_sync_semaphore(hw); 789 msec_delay(5); 790 } 791 792out: 793 return ret_val; 794} 795 796/** 797 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore 798 * @hw: pointer to hardware structure 799 * @mask: Mask to specify which semaphore to release 800 * 801 * Releases the SWFW semaphore throught the SW_FW_SYNC register 802 * for the specified function (CSR, PHY0, PHY1, EVM, Flash) 803 **/ 804void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) 805{ 806 u32 swfw_sync; 807 u32 swmask = mask; 808 809 DEBUGFUNC("ixgbe_release_swfw_sync_X540"); 810 811 ixgbe_get_swfw_sync_semaphore(hw); 812 813 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 814 swfw_sync &= ~swmask; 815 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); 816 817 ixgbe_release_swfw_sync_semaphore(hw); 818 msec_delay(5); 819} 820 821/** 822 * ixgbe_get_nvm_semaphore - Get hardware semaphore 823 * @hw: pointer to hardware structure 824 * 825 * Sets the hardware semaphores so SW/FW can gain control of shared resources 826 **/ 827static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) 828{ 829 s32 status = IXGBE_ERR_EEPROM; 830 u32 timeout = 2000; 831 u32 i; 832 u32 swsm; 833 834 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore"); 835 836 /* Get SMBI software semaphore between device drivers first */ 837 for (i = 0; i < timeout; i++) { 838 /* 839 * If the SMBI bit is 0 when we read it, then the bit will be 840 * set and we have the semaphore 841 */ 842 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 843 if (!(swsm & IXGBE_SWSM_SMBI)) { 844 status = IXGBE_SUCCESS; 845 break; 846 } 847 usec_delay(50); 848 } 849 850 /* Now get the semaphore between SW/FW through the REGSMP bit */ 851 if (status == IXGBE_SUCCESS) { 852 for (i = 0; i < timeout; i++) { 853 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 854 if (!(swsm & IXGBE_SWFW_REGSMP)) 855 break; 856 857 usec_delay(50); 858 } 859 860 /* 861 * Release semaphores and return error if SW NVM semaphore 862 * was not granted because we don't have access to the EEPROM 863 */ 864 if (i >= timeout) { 865 DEBUGOUT("REGSMP Software NVM semaphore not " 866 "granted.\n"); 867 ixgbe_release_swfw_sync_semaphore(hw); 868 status = IXGBE_ERR_EEPROM; 869 } 870 } else { 871 DEBUGOUT("Software semaphore SMBI between device drivers " 872 "not granted.\n"); 873 } 874 875 return status; 876} 877 878/** 879 * ixgbe_release_nvm_semaphore - Release hardware semaphore 880 * @hw: pointer to hardware structure 881 * 882 * This function clears hardware semaphore bits. 883 **/ 884static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) 885{ 886 u32 swsm; 887 888 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore"); 889 890 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */ 891 892 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 893 swsm &= ~IXGBE_SWSM_SMBI; 894 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 895 896 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); 897 swsm &= ~IXGBE_SWFW_REGSMP; 898 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm); 899 900 IXGBE_WRITE_FLUSH(hw); 901} 902 903/** 904 * ixgbe_blink_led_start_X540 - Blink LED based on index. 905 * @hw: pointer to hardware structure 906 * @index: led number to blink 907 * 908 * Devices that implement the version 2 interface: 909 * X540 910 **/ 911s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index) 912{ 913 u32 macc_reg; 914 u32 ledctl_reg; 915 ixgbe_link_speed speed; 916 bool link_up; 917 918 DEBUGFUNC("ixgbe_blink_led_start_X540"); 919 920 /* 921 * Link should be up in order for the blink bit in the LED control 922 * register to work. Force link and speed in the MAC if link is down. 923 * This will be reversed when we stop the blinking. 924 */ 925 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 926 if (link_up == FALSE) { 927 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 928 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS; 929 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 930 } 931 /* Set the LED to LINK_UP + BLINK. */ 932 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 933 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 934 ledctl_reg |= IXGBE_LED_BLINK(index); 935 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 936 IXGBE_WRITE_FLUSH(hw); 937 938 return IXGBE_SUCCESS; 939} 940 941/** 942 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index. 943 * @hw: pointer to hardware structure 944 * @index: led number to stop blinking 945 * 946 * Devices that implement the version 2 interface: 947 * X540 948 **/ 949s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index) 950{ 951 u32 macc_reg; 952 u32 ledctl_reg; 953 954 DEBUGFUNC("ixgbe_blink_led_stop_X540"); 955 956 /* Restore the LED to its default value. */ 957 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 958 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 959 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 960 ledctl_reg &= ~IXGBE_LED_BLINK(index); 961 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 962 963 /* Unforce link and speed in the MAC. */ 964 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 965 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS); 966 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 967 IXGBE_WRITE_FLUSH(hw); 968 969 return IXGBE_SUCCESS; 970} 971 972