if_iwnreg.h revision 271246
118334Speter/* $FreeBSD: head/sys/dev/iwn/if_iwnreg.h 271246 2014-09-08 03:12:42Z adrian $ */ 2169689Skan/* $OpenBSD: if_iwnreg.h,v 1.40 2010/05/05 19:41:57 damien Exp $ */ 3169689Skan 4169689Skan/*- 518334Speter * Copyright (c) 2007, 2008 690075Sobrien * Damien Bergamini <damien.bergamini@free.fr> 718334Speter * 890075Sobrien * Permission to use, copy, modify, and distribute this software for any 990075Sobrien * purpose with or without fee is hereby granted, provided that the above 1090075Sobrien * copyright notice and this permission notice appear in all copies. 1190075Sobrien * 1218334Speter * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 1390075Sobrien * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 1490075Sobrien * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 1590075Sobrien * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 1690075Sobrien * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 1718334Speter * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 1818334Speter * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 1990075Sobrien */ 20169689Skan#ifndef __IF_IWNREG_H__ 21169689Skan#define __IF_IWNREG_H__ 2218334Speter 2318334Speter#define IWN_CT_KILL_THRESHOLD 114 /* in Celsius */ 2418334Speter#define IWN_CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */ 2518334Speter 2618334Speter#define IWN_TX_RING_COUNT 256 27169689Skan#define IWN_TX_RING_LOMARK 192 2818334Speter#define IWN_TX_RING_HIMARK 224 2918334Speter#define IWN_RX_RING_COUNT_LOG 6 3050397Sobrien#define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 31132718Skan 32132718Skan#define IWN4965_NTXQUEUES 16 3390075Sobrien#define IWN5000_NTXQUEUES 20 3418334Speter 35169689Skan#define IWN4965_FIRSTAGGQUEUE 7 3618334Speter#define IWN5000_FIRSTAGGQUEUE 10 3790075Sobrien 3818334Speter#define IWN4965_NDMACHNLS 7 3918334Speter#define IWN5000_NDMACHNLS 8 4050397Sobrien 4150397Sobrien#define IWN_SRVC_DMACHNL 9 4252284Sobrien 4390075Sobrien#define IWN_ICT_SIZE 4096 4490075Sobrien#define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 45169689Skan 46169689Skan/* For cards with PAN command, default is IWN_CMD_QUEUE_NUM */ 47169689Skan#define IWN_CMD_QUEUE_NUM 4 4818334Speter#define IWN_PAN_CMD_QUEUE 9 49169689Skan 50169689Skan/* Maximum number of DMA segments for TX. */ 51169689Skan#define IWN_MAX_SCATTER 20 52169689Skan 53169689Skan/* RX buffers must be large enough to hold a full 4K A-MPDU. */ 54169689Skan#define IWN_RBUF_SIZE (4 * 1024) 55169689Skan 56169689Skan#if defined(__LP64__) 57169689Skan/* HW supports 36-bit DMA addresses. */ 58169689Skan#define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 59169689Skan#define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 60169689Skan#else 61169689Skan#define IWN_LOADDR(paddr) (paddr) 62169689Skan#define IWN_HIADDR(paddr) (0) 63169689Skan#endif 64169689Skan 65169689Skan/* 66169689Skan * Control and status registers. 67169689Skan */ 68169689Skan#define IWN_HW_IF_CONFIG 0x000 69169689Skan#define IWN_INT_COALESCING 0x004 70169689Skan#define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 7118334Speter#define IWN_INT 0x008 7218334Speter#define IWN_INT_MASK 0x00c 7318334Speter#define IWN_FH_INT 0x010 7418334Speter#define IWN_GPIO_IN 0x018 /* read external chip pins */ 75132718Skan#define IWN_RESET 0x020 76132718Skan#define IWN_GP_CNTRL 0x024 7790075Sobrien#define IWN_HW_REV 0x028 78260311Spfg#define IWN_EEPROM 0x02c 79260311Spfg#define IWN_EEPROM_GP 0x030 80260311Spfg#define IWN_OTP_GP 0x034 81260311Spfg#define IWN_GIO 0x03c 82169689Skan#define IWN_GP_UCODE 0x048 83132718Skan#define IWN_GP_DRIVER 0x050 84169689Skan#define IWN_UCODE_GP1 0x054 85169689Skan#define IWN_UCODE_GP1_SET 0x058 86169689Skan#define IWN_UCODE_GP1_CLR 0x05c 87169689Skan#define IWN_UCODE_GP2 0x060 88132718Skan#define IWN_LED 0x094 89132718Skan#define IWN_DRAM_INT_TBL 0x0a0 90132718Skan#define IWN_SHADOW_REG_CTRL 0x0a8 91132718Skan#define IWN_GIO_CHICKEN 0x100 92169689Skan#define IWN_ANA_PLL 0x20c 93132718Skan#define IWN_HW_REV_WA 0x22c 94132718Skan#define IWN_DBG_HPET_MEM 0x240 95132718Skan#define IWN_DBG_LINK_PWR_MGMT 0x250 96132718Skan/* Need nic_lock for use above */ 97132718Skan#define IWN_MEM_RADDR 0x40c 98132718Skan#define IWN_MEM_WADDR 0x410 99132718Skan#define IWN_MEM_WDATA 0x418 100169689Skan#define IWN_MEM_RDATA 0x41c 101169689Skan#define IWN_TARG_MBX_C 0x430 102132718Skan#define IWN_PRPH_WADDR 0x444 103132718Skan#define IWN_PRPH_RADDR 0x448 104132718Skan#define IWN_PRPH_WDATA 0x44c 105132718Skan#define IWN_PRPH_RDATA 0x450 106132718Skan#define IWN_HBUS_TARG_WRPTR 0x460 107132718Skan 108132718Skan/* 109169689Skan * Flow-Handler registers. 110169689Skan */ 111169689Skan#define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 112169689Skan#define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 113169689Skan#define IWN_FH_KW_ADDR 0x197c 11418334Speter#define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 115169689Skan#define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 116169689Skan#define IWN_FH_STATUS_WPTR 0x1bc0 117169689Skan#define IWN_FH_RX_BASE 0x1bc4 118169689Skan#define IWN_FH_RX_WPTR 0x1bc8 119169689Skan#define IWN_FH_RX_CONFIG 0x1c00 120169689Skan#define IWN_FH_RX_STATUS 0x1c44 121169689Skan#define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 122169689Skan#define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 123169689Skan#define IWN_FH_TX_CHICKEN 0x1e98 124169689Skan#define IWN_FH_TX_STATUS 0x1eb0 125169689Skan 126169689Skan/* 127169689Skan * TX scheduler registers. 128169689Skan */ 129169689Skan#define IWN_SCHED_BASE 0xa02c00 130169689Skan#define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 131169689Skan#define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 132169689Skan#define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 133169689Skan#define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 134169689Skan#define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 135169689Skan#define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 136169689Skan#define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 137169689Skan#define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 138169689Skan#define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 139169689Skan#define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 140169689Skan#define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 141169689Skan#define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 142169689Skan#define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 143169689Skan#define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 144169689Skan 14518334Speter/* 14618334Speter * Offsets in TX scheduler's SRAM. 14718334Speter */ 14818334Speter#define IWN4965_SCHED_CTX_OFF 0x380 149132718Skan#define IWN4965_SCHED_CTX_LEN 416 15018334Speter#define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 15118334Speter#define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 15218334Speter#define IWN5000_SCHED_CTX_OFF 0x600 15390075Sobrien#define IWN5000_SCHED_CTX_LEN 520 15452284Sobrien#define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 15552284Sobrien#define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 15618334Speter 15790075Sobrien/* 15818334Speter * NIC internal memory offsets. 15918334Speter */ 160117395Skan#define IWN_APMG_CLK_CTRL 0x3000 16118334Speter#define IWN_APMG_CLK_EN 0x3004 16218334Speter#define IWN_APMG_CLK_DIS 0x3008 16318334Speter#define IWN_APMG_PS 0x300c 16418334Speter#define IWN_APMG_DIGITAL_SVR 0x3058 16518334Speter#define IWN_APMG_ANALOG_SVR 0x306c 16618334Speter#define IWN_APMG_PCI_STT 0x3010 16718334Speter#define IWN_BSM_WR_CTRL 0x3400 16818334Speter#define IWN_BSM_WR_MEM_SRC 0x3404 169132718Skan#define IWN_BSM_WR_MEM_DST 0x3408 17018334Speter#define IWN_BSM_WR_DWCOUNT 0x340c 17152284Sobrien#define IWN_BSM_DRAM_TEXT_ADDR 0x3490 17218334Speter#define IWN_BSM_DRAM_TEXT_SIZE 0x3494 17318334Speter#define IWN_BSM_DRAM_DATA_ADDR 0x3498 17418334Speter#define IWN_BSM_DRAM_DATA_SIZE 0x349c 17518334Speter#define IWN_BSM_SRAM_BASE 0x3800 17618334Speter 17718334Speter/* Possible flags for register IWN_HW_IF_CONFIG. */ 17818334Speter#define IWN_HW_IF_CONFIG_4965_R (1 << 4) 179169689Skan#define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 18018334Speter#define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 18118334Speter#define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 18218334Speter#define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 18318334Speter#define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 18418334Speter#define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 18518334Speter#define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 18618334Speter 18718334Speter/* Possible values for register IWN_INT_PERIODIC. */ 18852284Sobrien#define IWN_INT_PERIODIC_DIS 0x00 18918334Speter#define IWN_INT_PERIODIC_ENA 0xff 19018334Speter 19118334Speter/* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 19252284Sobrien#define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 19318334Speter 19418334Speter/* Possible values for IWN_BSM_WR_MEM_DST. */ 19518334Speter#define IWN_FW_TEXT_BASE 0x00000000 19652284Sobrien#define IWN_FW_DATA_BASE 0x00800000 19718334Speter 19818334Speter/* Possible flags for register IWN_RESET. */ 19918334Speter#define IWN_RESET_NEVO (1 << 0) 20018334Speter#define IWN_RESET_SW (1 << 7) 20118334Speter#define IWN_RESET_MASTER_DISABLED (1 << 8) 20218334Speter#define IWN_RESET_STOP_MASTER (1 << 9) 20318334Speter#define IWN_RESET_LINK_PWR_MGMT_DIS (1U << 31) 20418334Speter 20518334Speter/* Possible flags for register IWN_GP_CNTRL. */ 20696263Sobrien#define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 20796263Sobrien#define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 20896263Sobrien#define IWN_GP_CNTRL_INIT_DONE (1 << 2) 20996263Sobrien#define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 21096263Sobrien#define IWN_GP_CNTRL_SLEEP (1 << 4) 21118334Speter#define IWN_GP_CNTRL_RFKILL (1 << 27) 21218334Speter 21318334Speter/* Possible flags for register IWN_GIO_CHICKEN. */ 21418334Speter#define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 21518334Speter#define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 21618334Speter 21718334Speter/* Possible flags for register IWN_GIO. */ 218169689Skan#define IWN_GIO_L0S_ENA (1 << 1) 21918334Speter 22018334Speter/* Possible flags for register IWN_GP_DRIVER. */ 22118334Speter#define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 222169689Skan#define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 223169689Skan#define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 22418334Speter#define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 22518334Speter#define IWN_GP_DRIVER_6050_1X2 (1 << 3) 226169689Skan#define IWN_GP_DRIVER_REG_BIT_RADIO_IQ_INVERT (1 << 7) 22718334Speter#define IWN_GP_DRIVER_NONE 0 22818334Speter 22918334Speter/* Possible flags for register IWN_UCODE_GP1_CLR. */ 230117395Skan#define IWN_UCODE_GP1_RFKILL (1 << 1) 231117395Skan#define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 232117395Skan#define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 233117395Skan#define IWN_UCODE_GP1_CFG_COMPLETE (1 << 5) 234132718Skan 235117395Skan/* Possible flags/values for register IWN_LED. */ 236117395Skan#define IWN_LED_BSM_CTRL (1 << 5) 237117395Skan#define IWN_LED_OFF 0x00000038 238117395Skan#define IWN_LED_ON 0x00000078 239117395Skan 240117395Skan#define IWN_MAX_BLINK_TBL 10 241117395Skan#define IWN_LED_STATIC_ON 0 242169689Skan#define IWN_LED_STATIC_OFF 1 243169689Skan#define IWN_LED_SLOW_BLINK 2 244169689Skan#define IWN_LED_INT_BLINK 3 245117395Skan#define IWN_LED_UNIT 0x1388 /* 5 ms */ 246117395Skan 247117395Skanstatic const struct { 248117395Skan uint16_t tpt; /* Mb/s */ 249117395Skan uint8_t on_time; 250117395Skan uint8_t off_time; 25118334Speter} blink_tbl[] = 25218334Speter{ 25318334Speter {300, 5, 5}, 25418334Speter {200, 8, 8}, 255132718Skan {100, 11, 11}, 25618334Speter {70, 13, 13}, 257132718Skan {50, 15, 15}, 25852750Sobrien {20, 17, 17}, 25918334Speter {10, 19, 19}, 260169689Skan {5, 22, 22}, 261169689Skan {1, 26, 26}, 262169689Skan {0, 33, 33}, 263169689Skan /* SOLID_ON */ 264169689Skan}; 265169689Skan 266169689Skan/* Possible flags for register IWN_DRAM_INT_TBL. */ 267169689Skan#define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) 268169689Skan#define IWN_DRAM_INT_TBL_ENABLE (1U << 31) 269169689Skan 270169689Skan/* Possible values for register IWN_ANA_PLL. */ 27118334Speter#define IWN_ANA_PLL_INIT 0x00880300 272169689Skan 27318334Speter/* Possible flags for register IWN_FH_RX_STATUS. */ 274169689Skan#define IWN_FH_RX_STATUS_IDLE (1 << 24) 275169689Skan 276169689Skan/* Possible flags for register IWN_BSM_WR_CTRL. */ 27718334Speter#define IWN_BSM_WR_CTRL_START_EN (1 << 30) 27818334Speter#define IWN_BSM_WR_CTRL_START (1U << 31) 279169689Skan 28018334Speter/* Possible flags for register IWN_INT. */ 28190075Sobrien#define IWN_INT_ALIVE (1 << 0) 28290075Sobrien#define IWN_INT_WAKEUP (1 << 1) 28318334Speter#define IWN_INT_SW_RX (1 << 3) 28418334Speter#define IWN_INT_CT_REACHED (1 << 6) 28518334Speter#define IWN_INT_RF_TOGGLED (1 << 7) 28618334Speter#define IWN_INT_SW_ERR (1 << 25) 28718334Speter#define IWN_INT_SCHED (1 << 26) 28818334Speter#define IWN_INT_FH_TX (1 << 27) 28918334Speter#define IWN_INT_RX_PERIODIC (1 << 28) 29018334Speter#define IWN_INT_HW_ERR (1 << 29) 29118334Speter#define IWN_INT_FH_RX (1U << 31) 29218334Speter 29318334Speter/* Shortcut. */ 29418334Speter#define IWN_INT_MASK_DEF \ 295169689Skan (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 296169689Skan IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 297169689Skan IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 29850397Sobrien 299169689Skan/* Possible flags for register IWN_FH_INT. */ 30018334Speter#define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 301169689Skan#define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 302169689Skan#define IWN_FH_INT_HI_PRIOR (1 << 30) 303169689Skan/* Shortcuts for the above. */ 304169689Skan#define IWN_FH_INT_TX \ 30518334Speter (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 306169689Skan#define IWN_FH_INT_RX \ 307169689Skan (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 308169689Skan 309169689Skan/* Possible flags/values for register IWN_FH_TX_CONFIG. */ 31018334Speter#define IWN_FH_TX_CONFIG_DMA_PAUSE 0 311169689Skan#define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 31218334Speter#define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20) 31318334Speter 31418334Speter/* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 31518334Speter#define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 316169689Skan#define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 31718334Speter#define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 31852284Sobrien 31952284Sobrien/* Possible flags for register IWN_FH_TX_CHICKEN. */ 320169689Skan#define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 321169689Skan 322169689Skan/* Possible flags for register IWN_FH_TX_STATUS. */ 323169689Skan#define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16)) 32418334Speter 32518334Speter/* Possible flags for register IWN_FH_RX_CONFIG. */ 32618334Speter#define IWN_FH_RX_CONFIG_ENA (1U << 31) 32718334Speter#define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 328169689Skan#define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16) 329169689Skan#define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15) 330169689Skan#define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 331169689Skan#define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 332169689Skan#define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2) 333169689Skan 334169689Skan/* Possible flags for register IWN_FH_TX_CONFIG. */ 335169689Skan#define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 336169689Skan#define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3) 337169689Skan 338169689Skan/* Possible flags for register IWN_EEPROM. */ 339169689Skan#define IWN_EEPROM_READ_VALID (1 << 0) 340169689Skan#define IWN_EEPROM_CMD (1 << 1) 341169689Skan 342169689Skan/* Possible flags for register IWN_EEPROM_GP. */ 343169689Skan#define IWN_EEPROM_GP_IF_OWNER 0x00000180 344169689Skan 345169689Skan/* Possible flags for register IWN_OTP_GP. */ 346169689Skan#define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 347169689Skan#define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 348169689Skan#define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 349169689Skan#define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 350169689Skan 35118334Speter/* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 352169689Skan#define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 353169689Skan#define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 35418334Speter#define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 355169689Skan#define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 356169689Skan#define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 35718334Speter#define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 358169689Skan#define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 359169689Skan 360169689Skan/* Possible flags for registers IWN_APMG_CLK_*. */ 361169689Skan#define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 362169689Skan#define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 363169689Skan 364169689Skan/* Possible flags for register IWN_APMG_PS. */ 365169689Skan#define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 366169689Skan#define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 367169689Skan#define IWN_APMG_PS_PWR_SRC_VMAIN 0 368169689Skan#define IWN_APMG_PS_PWR_SRC_VAUX 2 369169689Skan#define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 370169689Skan#define IWN_APMG_PS_RESET_REQ (1 << 26) 371169689Skan 372169689Skan/* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 373169689Skan#define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 374169689Skan#define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 375169689Skan IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 376169689Skan#define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 377169689Skan IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 378169689Skan 37918334Speter/* Possible flags for IWN_APMG_PCI_STT. */ 38018334Speter#define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 38118334Speter 382169689Skan/* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 383169689Skan#define IWN_FW_UPDATED (1U << 31) 384169689Skan 385169689Skan#define IWN_SCHED_WINSZ 64 386169689Skan#define IWN_SCHED_LIMIT 64 387169689Skan#define IWN4965_SCHED_COUNT 512 388169689Skan#define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 389169689Skan#define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 390169689Skan#define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 391169689Skan 392169689Skanstruct iwn_tx_desc { 393169689Skan uint8_t reserved1[3]; 394169689Skan uint8_t nsegs; 39518334Speter struct { 39618334Speter uint32_t addr; 39718334Speter uint16_t len; 39818334Speter } __packed segs[IWN_MAX_SCATTER]; 399169689Skan /* Pad to 128 bytes. */ 40018334Speter uint32_t reserved2; 40118334Speter} __packed; 40218334Speter 40318334Speterstruct iwn_rx_status { 40418334Speter uint16_t closed_count; 40518334Speter uint16_t closed_rx_count; 40618334Speter uint16_t finished_count; 407169689Skan uint16_t finished_rx_count; 40818334Speter uint32_t reserved[2]; 409169689Skan} __packed; 41018334Speter 41118334Speterstruct iwn_rx_desc { 41218334Speter /* 41318334Speter * The first 4 bytes of the RX frame header contain both the RX frame 41418334Speter * size and some flags. 415169689Skan * Bit fields: 416169689Skan * 31: flag flush RB request 417169689Skan * 30: flag ignore TC (terminal counter) request 41818334Speter * 29: flag fast IRQ request 41918334Speter * 28-14: Reserved 42018334Speter * 13-00: RX frame size 42118334Speter */ 422169689Skan uint32_t len; 423169689Skan uint8_t type; 42418334Speter#define IWN_UC_READY 1 42518334Speter#define IWN_ADD_NODE_DONE 24 42618334Speter#define IWN_TX_DONE 28 42718334Speter#define IWN_REPLY_LED_CMD 72 428169689Skan#define IWN5000_CALIBRATION_RESULT 102 429169689Skan#define IWN5000_CALIBRATION_DONE 103 430169689Skan#define IWN_START_SCAN 130 43118334Speter#define IWN_NOTIF_SCAN_RESULT 131 43218334Speter#define IWN_STOP_SCAN 132 43318334Speter#define IWN_RX_STATISTICS 156 43418334Speter#define IWN_BEACON_STATISTICS 157 43518334Speter#define IWN_STATE_CHANGED 161 43618334Speter#define IWN_BEACON_MISSED 162 43718334Speter#define IWN_RX_PHY 192 43818334Speter#define IWN_MPDU_RX_DONE 193 43918334Speter#define IWN_RX_DONE 195 44018334Speter#define IWN_RX_COMPRESSED_BA 197 44118334Speter 44218334Speter uint8_t flags; /* 0:5 reserved, 6 abort, 7 internal */ 44318334Speter uint8_t idx; /* position within TX queue */ 44418334Speter uint8_t qid; 44518334Speter /* 0:4 TX queue id - 5:6 reserved - 7 unsolicited RX 44618334Speter * or uCode-originated notification 44718334Speter */ 44818334Speter} __packed; 44918334Speter 45018334Speter#define IWN_RX_DESC_QID_MSK 0x1F 45118334Speter#define IWN_UNSOLICITED_RX_NOTIF 0x80 45218334Speter 45318334Speter/* CARD_STATE_NOTIFICATION */ 45418334Speter#define IWN_STATE_CHANGE_HW_CARD_DISABLED 0x01 455132718Skan#define IWN_STATE_CHANGE_SW_CARD_DISABLED 0x02 45618334Speter#define IWN_STATE_CHANGE_CT_CARD_DISABLED 0x04 45718334Speter#define IWN_STATE_CHANGE_RXON_CARD_DISABLED 0x10 45818334Speter 45918334Speter/* Possible RX status flags. */ 46018334Speter#define IWN_RX_NO_CRC_ERR (1 << 0) 46118334Speter#define IWN_RX_NO_OVFL_ERR (1 << 1) 46218334Speter/* Shortcut for the above. */ 463169689Skan#define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 464169689Skan#define IWN_RX_MPDU_MIC_OK (1 << 6) 465169689Skan#define IWN_RX_CIPHER_MASK (7 << 8) 466169689Skan#define IWN_RX_CIPHER_CCMP (2 << 8) 46718334Speter#define IWN_RX_MPDU_DEC (1 << 11) 46818334Speter#define IWN_RX_DECRYPT_MASK (3 << 11) 469169689Skan#define IWN_RX_DECRYPT_OK (3 << 11) 470169689Skan 471169689Skanstruct iwn_tx_cmd { 472169689Skan uint8_t code; 473169689Skan#define IWN_CMD_RXON 16 474169689Skan#define IWN_CMD_RXON_ASSOC 17 475169689Skan#define IWN_CMD_EDCA_PARAMS 19 476169689Skan#define IWN_CMD_TIMING 20 477169689Skan#define IWN_CMD_ADD_NODE 24 478169689Skan#define IWN_CMD_TX_DATA 28 479169689Skan#define IWN_CMD_LINK_QUALITY 78 480169689Skan#define IWN_CMD_SET_LED 72 481169689Skan#define IWN5000_CMD_WIMAX_COEX 90 482169689Skan#define IWN_TEMP_NOTIFICATION 98 48318334Speter#define IWN5000_CMD_CALIB_CONFIG 101 48418334Speter#define IWN5000_CMD_CALIB_RESULT 102 48518334Speter#define IWN5000_CMD_CALIB_COMPLETE 103 48618334Speter#define IWN_CMD_SET_POWER_MODE 119 48718334Speter#define IWN_CMD_SCAN 128 488169689Skan#define IWN_CMD_SCAN_RESULTS 131 489169689Skan#define IWN_CMD_TXPOWER_DBM 149 490169689Skan#define IWN_CMD_TXPOWER 151 491169689Skan#define IWN5000_CMD_TX_ANT_CONFIG 152 49218334Speter#define IWN_CMD_TXPOWER_DBM_V1 152 49318334Speter#define IWN_CMD_BT_COEX 155 494169689Skan#define IWN_CMD_GET_STATISTICS 156 495169689Skan#define IWN_CMD_SET_CRITICAL_TEMP 164 496169689Skan#define IWN_CMD_SET_SENSITIVITY 168 497169689Skan#define IWN_CMD_PHY_CALIB 176 498169689Skan#define IWN_CMD_BT_COEX_PRIOTABLE 204 499169689Skan#define IWN_CMD_BT_COEX_PROT 205 500169689Skan#define IWN_CMD_BT_COEX_NOTIF 206 501169689Skan/* PAN commands */ 502169689Skan#define IWN_CMD_WIPAN_PARAMS 0xb2 503169689Skan#define IWN_CMD_WIPAN_RXON 0xb3 504169689Skan#define IWN_CMD_WIPAN_RXON_TIMING 0xb4 505169689Skan#define IWN_CMD_WIPAN_RXON_ASSOC 0xb6 506169689Skan#define IWN_CMD_WIPAN_QOS_PARAM 0xb7 507169689Skan#define IWN_CMD_WIPAN_WEPKEY 0xb8 50818334Speter#define IWN_CMD_WIPAN_P2P_CHANNEL_SWITCH 0xb9 509169689Skan#define IWN_CMD_WIPAN_NOA_NOTIFICATION 0xbc 51018334Speter#define IWN_CMD_WIPAN_DEACTIVATION_COMPLETE 0xbd 51118334Speter 51218334Speter uint8_t flags; 513169689Skan uint8_t idx; 51418334Speter uint8_t qid; 515169689Skan uint8_t data[136]; 51650397Sobrien} __packed; 51718334Speter 51818334Speter/* 51918334Speter * Structure for IWN_CMD_GET_STATISTICS = (0x9c) 156 52018334Speter * all devices identical. 52118334Speter * 52218334Speter * This command triggers an immediate response containing uCode statistics. 52318334Speter * The response is in the same format as IWN_BEACON_STATISTICS (0x9d) 157. 524169689Skan * 525169689Skan * If the CLEAR_STATS configuration flag is set, uCode will clear its 526169689Skan * internal copy of the statistics (counters) after issuing the response. 527169689Skan * This flag does not affect IWN_BEACON_STATISTICS after beacons (see below). 528169689Skan * 529169689Skan * If the DISABLE_NOTIF configuration flag is set, uCode will not issue 530169689Skan * IWN_BEACON_STATISTICS after received beacons. This flag 531169689Skan * does not affect the response to the IWN_CMD_GET_STATISTICS 0x9c itself. 532169689Skan */ 533169689Skanstruct iwn_statistics_cmd { 534169689Skan uint32_t configuration_flags; 535169689Skan#define IWN_STATS_CONF_CLEAR_STATS htole32(0x1) 536169689Skan#define IWN_STATS_CONF_DISABLE_NOTIF htole32(0x2) 537169689Skan} __packed; 538169689Skan 539169689Skan/* Antenna flags, used in various commands. */ 540169689Skan#define IWN_ANT_A (1 << 0) 541169689Skan#define IWN_ANT_B (1 << 1) 542169689Skan#define IWN_ANT_C (1 << 2) 543169689Skan/* Shortcuts. */ 544169689Skan#define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 545169689Skan#define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 546169689Skan#define IWN_ANT_AC (IWN_ANT_A | IWN_ANT_C) 547169689Skan#define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 548169689Skan 549260311Spfg/* Structure for command IWN_CMD_RXON. */ 550260311Spfgstruct iwn_rxon { 551260311Spfg uint8_t myaddr[IEEE80211_ADDR_LEN]; 552260311Spfg uint16_t reserved1; 553260311Spfg uint8_t bssid[IEEE80211_ADDR_LEN]; 554260311Spfg uint16_t reserved2; 555169689Skan uint8_t wlap[IEEE80211_ADDR_LEN]; 556169689Skan uint16_t reserved3; 557169689Skan uint8_t mode; 558169689Skan#define IWN_MODE_HOSTAP 1 559169689Skan#define IWN_MODE_STA 3 560169689Skan#define IWN_MODE_IBSS 4 561169689Skan#define IWN_MODE_MONITOR 6 562169689Skan#define IWN_MODE_2STA 8 563169689Skan#define IWN_MODE_P2P 9 564169689Skan 565169689Skan uint8_t air; 566169689Skan uint16_t rxchain; 567169689Skan#define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 568169689Skan#define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 569260311Spfg#define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 570260311Spfg#define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 571260311Spfg#define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 572260311Spfg#define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 573260311Spfg#define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 574260311Spfg 575260311Spfg uint8_t ofdm_mask; 576260311Spfg uint8_t cck_mask; 577260311Spfg uint16_t associd; 578169689Skan uint32_t flags; 579169689Skan#define IWN_RXON_24GHZ (1 << 0) 580169689Skan#define IWN_RXON_CCK (1 << 1) 581169689Skan#define IWN_RXON_AUTO (1 << 2) 582169689Skan#define IWN_RXON_SHSLOT (1 << 4) 583169689Skan#define IWN_RXON_SHPREAMBLE (1 << 5) 584169689Skan#define IWN_RXON_NODIVERSITY (1 << 7) 585169689Skan#define IWN_RXON_ANTENNA_A (1 << 8) 586169689Skan#define IWN_RXON_ANTENNA_B (1 << 9) 587169689Skan#define IWN_RXON_TSF (1 << 15) 588169689Skan#define IWN_RXON_HT_HT40MINUS (1 << 22) 589169689Skan#define IWN_RXON_HT_PROTMODE(x) (x << 23) 590169689Skan#define IWN_RXON_HT_MODEPURE40 (1 << 25) 591169689Skan#define IWN_RXON_HT_MODEMIXED (2 << 25) 592169689Skan#define IWN_RXON_CTS_TO_SELF (1 << 30) 593169689Skan 594169689Skan uint32_t filter; 595169689Skan#define IWN_FILTER_PROMISC (1 << 0) 596169689Skan#define IWN_FILTER_CTL (1 << 1) 597169689Skan#define IWN_FILTER_MULTICAST (1 << 2) 598169689Skan#define IWN_FILTER_NODECRYPT (1 << 3) 599169689Skan#define IWN_FILTER_BSS (1 << 5) 600169689Skan#define IWN_FILTER_BEACON (1 << 6) 601169689Skan 602169689Skan uint8_t chan; 603169689Skan uint8_t reserved4; 604169689Skan uint8_t ht_single_mask; 605169689Skan uint8_t ht_dual_mask; 606169689Skan /* The following fields are for >=5000 Series only. */ 607169689Skan uint8_t ht_triple_mask; 608169689Skan uint8_t reserved5; 609169689Skan uint16_t acquisition; 610169689Skan uint16_t reserved6; 611169689Skan} __packed; 612169689Skan 613169689Skan#define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 614169689Skan#define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 615169689Skan 616169689Skan/* Structure for command IWN_CMD_ASSOCIATE. */ 617169689Skanstruct iwn_assoc { 618169689Skan uint32_t flags; 619169689Skan uint32_t filter; 620169689Skan uint8_t ofdm_mask; 621169689Skan uint8_t cck_mask; 622169689Skan uint16_t reserved; 623169689Skan} __packed; 624169689Skan 625169689Skan/* Structure for command IWN_CMD_EDCA_PARAMS. */ 626169689Skanstruct iwn_edca_params { 627169689Skan uint32_t flags; 628169689Skan#define IWN_EDCA_UPDATE (1 << 0) 629169689Skan#define IWN_EDCA_TXOP (1 << 4) 630169689Skan 631169689Skan struct { 632169689Skan uint16_t cwmin; 633169689Skan uint16_t cwmax; 634169689Skan uint8_t aifsn; 635169689Skan uint8_t reserved; 636169689Skan uint16_t txoplimit; 637169689Skan } __packed ac[WME_NUM_AC]; 638169689Skan} __packed; 639169689Skan 640169689Skan/* Structure for command IWN_CMD_TIMING. */ 641169689Skanstruct iwn_cmd_timing { 642169689Skan uint64_t tstamp; 643169689Skan uint16_t bintval; 644169689Skan uint16_t atim; 645169689Skan uint32_t binitval; 646169689Skan uint16_t lintval; 647169689Skan uint8_t dtim_period; 648169689Skan uint8_t delta_cp_bss_tbtts; 649169689Skan} __packed; 650169689Skan 651169689Skan/* Structure for command IWN_CMD_ADD_NODE. */ 652169689Skanstruct iwn_node_info { 653169689Skan uint8_t control; 654169689Skan#define IWN_NODE_UPDATE (1 << 0) 655169689Skan 656169689Skan uint8_t reserved1[3]; 657169689Skan 658169689Skan uint8_t macaddr[IEEE80211_ADDR_LEN]; 659169689Skan uint16_t reserved2; 660169689Skan uint8_t id; 661169689Skan#define IWN_ID_BSS 0 662169689Skan#define IWN_STA_ID 1 663169689Skan 664169689Skan#define IWN_PAN_ID_BCAST 14 665169689Skan#define IWN5000_ID_BROADCAST 15 666169689Skan#define IWN4965_ID_BROADCAST 31 667169689Skan 668169689Skan uint8_t flags; 669169689Skan#define IWN_FLAG_SET_KEY (1 << 0) 670169689Skan#define IWN_FLAG_SET_DISABLE_TID (1 << 1) 671169689Skan#define IWN_FLAG_SET_TXRATE (1 << 2) 672169689Skan#define IWN_FLAG_SET_ADDBA (1 << 3) 673169689Skan#define IWN_FLAG_SET_DELBA (1 << 4) 674169689Skan 675169689Skan uint16_t reserved3; 676169689Skan uint16_t kflags; 677169689Skan#define IWN_KFLAG_CCMP (1 << 1) 678169689Skan#define IWN_KFLAG_MAP (1 << 3) 679169689Skan#define IWN_KFLAG_KID(kid) ((kid) << 8) 680169689Skan#define IWN_KFLAG_INVALID (1 << 11) 681169689Skan#define IWN_KFLAG_GROUP (1 << 14) 682169689Skan 683169689Skan uint8_t tsc2; /* TKIP TSC2 */ 684169689Skan uint8_t reserved4; 685169689Skan uint16_t ttak[5]; 686169689Skan uint8_t kid; 687169689Skan uint8_t reserved5; 688169689Skan uint8_t key[16]; 689169689Skan /* The following 3 fields are for 5000 Series only. */ 690169689Skan uint64_t tsc; 691169689Skan uint8_t rxmic[8]; 692169689Skan uint8_t txmic[8]; 693169689Skan 694169689Skan uint32_t htflags; 695169689Skan#define IWN_SMPS_MIMO_PROT (1 << 17) 696169689Skan#define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 697169689Skan#define IWN_NODE_HT40 (1 << 21) 698169689Skan#define IWN_SMPS_MIMO_DIS (1 << 22) 699169689Skan#define IWN_AMDPU_DENSITY(x) ((x) << 23) 700169689Skan 701169689Skan uint32_t mask; 702169689Skan uint16_t disable_tid; 703169689Skan uint16_t reserved6; 704169689Skan uint8_t addba_tid; 705169689Skan uint8_t delba_tid; 706169689Skan uint16_t addba_ssn; 707169689Skan uint32_t reserved7; 708169689Skan} __packed; 709169689Skan 710169689Skanstruct iwn4965_node_info { 711169689Skan uint8_t control; 712169689Skan uint8_t reserved1[3]; 713169689Skan uint8_t macaddr[IEEE80211_ADDR_LEN]; 714169689Skan uint16_t reserved2; 715169689Skan uint8_t id; 716169689Skan uint8_t flags; 717169689Skan uint16_t reserved3; 718169689Skan uint16_t kflags; 719169689Skan uint8_t tsc2; /* TKIP TSC2 */ 720169689Skan uint8_t reserved4; 721169689Skan uint16_t ttak[5]; 722169689Skan uint8_t kid; 723169689Skan uint8_t reserved5; 724169689Skan uint8_t key[16]; 725169689Skan uint32_t htflags; 726169689Skan uint32_t mask; 727169689Skan uint16_t disable_tid; 728169689Skan uint16_t reserved6; 729169689Skan uint8_t addba_tid; 730169689Skan uint8_t delba_tid; 731169689Skan uint16_t addba_ssn; 732169689Skan uint32_t reserved7; 733169689Skan} __packed; 734169689Skan 735169689Skan#define IWN_RFLAG_MCS (1 << 8) 736169689Skan#define IWN_RFLAG_CCK (1 << 9) 737169689Skan#define IWN_RFLAG_GREENFIELD (1 << 10) 738169689Skan#define IWN_RFLAG_HT40 (1 << 11) 739169689Skan#define IWN_RFLAG_DUPLICATE (1 << 12) 740169689Skan#define IWN_RFLAG_SGI (1 << 13) 741169689Skan#define IWN_RFLAG_ANT(x) ((x) << 14) 742169689Skan 743169689Skan/* Structure for command IWN_CMD_TX_DATA. */ 744169689Skanstruct iwn_cmd_data { 745169689Skan uint16_t len; 746169689Skan uint16_t lnext; 747169689Skan uint32_t flags; 748169689Skan#define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 74918334Speter#define IWN_TX_NEED_RTS (1 << 1) 750169689Skan#define IWN_TX_NEED_CTS (1 << 2) 751169689Skan#define IWN_TX_NEED_ACK (1 << 3) 752169689Skan#define IWN_TX_LINKQ (1 << 4) 753169689Skan#define IWN_TX_IMM_BA (1 << 6) 754169689Skan#define IWN_TX_FULL_TXOP (1 << 7) 755169689Skan#define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 756169689Skan#define IWN_TX_AUTO_SEQ (1 << 13) 757169689Skan#define IWN_TX_MORE_FRAG (1 << 14) 758169689Skan#define IWN_TX_INSERT_TSTAMP (1 << 16) 759169689Skan#define IWN_TX_NEED_PADDING (1 << 20) 760169689Skan 761169689Skan uint32_t scratch; 762169689Skan uint32_t rate; 763169689Skan 764169689Skan uint8_t id; 765169689Skan uint8_t security; 766169689Skan#define IWN_CIPHER_WEP40 1 767169689Skan#define IWN_CIPHER_CCMP 2 768169689Skan#define IWN_CIPHER_TKIP 3 769169689Skan#define IWN_CIPHER_WEP104 9 770169689Skan 771169689Skan uint8_t linkq; 772169689Skan uint8_t reserved2; 773169689Skan uint8_t key[16]; 774169689Skan uint16_t fnext; 775169689Skan uint16_t reserved3; 776169689Skan uint32_t lifetime; 77718334Speter#define IWN_LIFETIME_INFINITE 0xffffffff 77818334Speter 77918334Speter uint32_t loaddr; 78018334Speter uint8_t hiaddr; 78118334Speter uint8_t rts_ntries; 782169689Skan uint8_t data_ntries; 78318334Speter uint8_t tid; 784169689Skan uint16_t timeout; 785169689Skan uint16_t txop; 786169689Skan} __packed; 787169689Skan 788169689Skan/* Structure for command IWN_CMD_LINK_QUALITY. */ 789169689Skan#define IWN_MAX_TX_RETRIES 16 790169689Skanstruct iwn_cmd_link_quality { 791169689Skan uint8_t id; 792169689Skan uint8_t reserved1; 793169689Skan uint16_t ctl; 794169689Skan uint8_t flags; 795169689Skan uint8_t mimo; 796169689Skan uint8_t antmsk_1stream; 797169689Skan uint8_t antmsk_2stream; 798169689Skan uint8_t ridx[WME_NUM_AC]; 799169689Skan uint16_t ampdu_limit; 800169689Skan uint8_t ampdu_threshold; 80190075Sobrien uint8_t ampdu_max; 80290075Sobrien uint32_t reserved2; 80318334Speter uint32_t retry[IWN_MAX_TX_RETRIES]; 80418334Speter uint32_t reserved3; 80518334Speter} __packed; 80618334Speter 80750397Sobrien/* Structure for command IWN_CMD_SET_LED. */ 80850397Sobrienstruct iwn_cmd_led { 80918334Speter uint32_t unit; /* multiplier (in usecs) */ 81018334Speter uint8_t which; 81190075Sobrien#define IWN_LED_ACTIVITY 1 81290075Sobrien#define IWN_LED_LINK 2 81390075Sobrien 814169689Skan uint8_t off; 815169689Skan uint8_t on; 81690075Sobrien uint8_t reserved; 81790075Sobrien} __packed; 818169689Skan 819169689Skan/* Structure for command IWN5000_CMD_WIMAX_COEX. */ 82090075Sobrienstruct iwn5000_wimax_coex { 821169689Skan uint32_t flags; 822132718Skan#define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 823132718Skan#define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 824132718Skan#define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 82518334Speter#define IWN_WIMAX_COEX_ENABLE (1 << 7) 826132718Skan 827169689Skan struct iwn5000_wimax_event { 828132718Skan uint8_t request; 829169689Skan uint8_t window; 83018334Speter uint8_t reserved; 83118334Speter uint8_t flags; 83218334Speter } __packed events[16]; 83318334Speter} __packed; 83418334Speter 83518334Speter/* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 836132718Skanstruct iwn5000_calib_elem { 837132718Skan uint32_t enable; 83818334Speter uint32_t start; 839169689Skan#define IWN5000_CALIB_DC (1 << 1) 84018334Speter 84152284Sobrien uint32_t send; 84218334Speter uint32_t apply; 84318334Speter uint32_t reserved; 84418334Speter} __packed; 84518334Speter 84650397Sobrienstruct iwn5000_calib_status { 84718334Speter struct iwn5000_calib_elem once; 848169689Skan struct iwn5000_calib_elem perd; 849169689Skan uint32_t flags; 85018334Speter} __packed; 85118334Speter 85218334Speterstruct iwn5000_calib_config { 853169689Skan struct iwn5000_calib_status ucode; 85418334Speter struct iwn5000_calib_status driver; 85518334Speter uint32_t reserved; 85618334Speter} __packed; 85718334Speter 85818334Speter/* Structure for command IWN_CMD_SET_POWER_MODE. */ 85918334Speterstruct iwn_pmgt_cmd { 86018334Speter uint16_t flags; 861260311Spfg#define IWN_PS_ALLOW_SLEEP (1 << 0) 862260311Spfg#define IWN_PS_NOTIFY (1 << 1) 863260311Spfg#define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 864260311Spfg#define IWN_PS_PCI_PMGT (1 << 3) 865260311Spfg#define IWN_PS_FAST_PD (1 << 4) 866260311Spfg#define IWN_PS_BEACON_FILTERING (1 << 5) 867260311Spfg#define IWN_PS_SHADOW_REG (1 << 6) 86818334Speter#define IWN_PS_CT_KILL (1 << 7) 869169689Skan#define IWN_PS_BT_SCD (1 << 8) 870169689Skan#define IWN_PS_ADVANCED_PM (1 << 9) 871169689Skan 872132718Skan uint8_t keepalive; 87318334Speter uint8_t debug; 874169689Skan uint32_t rxtimeout; 87518334Speter uint32_t txtimeout; 87618334Speter uint32_t intval[5]; 87718334Speter uint32_t beacons; 878169689Skan} __packed; 87918334Speter 88018334Speter/* Structures for command IWN_CMD_SCAN. */ 88118334Speterstruct iwn_scan_essid { 88218334Speter uint8_t id; 88318334Speter uint8_t len; 88418334Speter uint8_t data[IEEE80211_NWID_LEN]; 88590075Sobrien} __packed; 88690075Sobrien 88718334Speterstruct iwn_scan_hdr { 88818334Speter uint16_t len; 88918334Speter uint8_t scan_flags; 89018334Speter uint8_t nchan; 891169689Skan uint16_t quiet_time; 89218334Speter uint16_t quiet_threshold; 89318334Speter uint16_t crc_threshold; 89418334Speter uint16_t rxchain; 89590075Sobrien uint32_t max_svc; /* background scans */ 89618334Speter uint32_t pause_svc; /* background scans */ 89718334Speter uint32_t flags; 898169689Skan uint32_t filter; 899169689Skan 90090075Sobrien /* Followed by a struct iwn_cmd_data. */ 901169689Skan /* Followed by an array of 20 structs iwn_scan_essid. */ 90290075Sobrien /* Followed by probe request body. */ 90390075Sobrien /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 904169689Skan} __packed; 90590075Sobrien 90690075Sobrienstruct iwn_scan_chan { 907169689Skan uint32_t flags; 908169689Skan#define IWN_CHAN_PASSIVE (0 << 0) 90990075Sobrien#define IWN_CHAN_ACTIVE (1 << 0) 91090075Sobrien#define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 91190075Sobrien 91290075Sobrien uint16_t chan; 91390075Sobrien uint8_t rf_gain; 91490075Sobrien uint8_t dsp_gain; 915169689Skan uint16_t active; /* msecs */ 916169689Skan uint16_t passive; /* msecs */ 91790075Sobrien} __packed; 91890075Sobrien 919169689Skan#define IWN_SCAN_CRC_TH_DISABLED 0 92018334Speter#define IWN_SCAN_CRC_TH_DEFAULT htole16(1) 92118334Speter#define IWN_SCAN_CRC_TH_NEVER htole16(0xffff) 922169689Skan 92318334Speter/* Maximum size of a scan command. */ 924132718Skan#define IWN_SCAN_MAXSZ (MCLBYTES - 4) 925132718Skan 926169689Skan/* 927169689Skan * For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after 928169689Skan * sending probe req. This should be set long enough to hear probe responses 929169689Skan * from more than one AP. 930169689Skan */ 931169689Skan#define IWN_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */ 932169689Skan#define IWN_ACTIVE_DWELL_TIME_5GHZ (20) 933169689Skan#define IWN_ACTIVE_DWELL_FACTOR_2GHZ (3) 934169689Skan#define IWN_ACTIVE_DWELL_FACTOR_5GHZ (2) 935169689Skan 936169689Skan/* 937169689Skan * For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel. 93818334Speter * Must be set longer than active dwell time. 93950397Sobrien * For the most reliable scan, set > AP beacon interval (typically 100msec). 940132718Skan */ 941169689Skan#define IWN_PASSIVE_DWELL_TIME_2GHZ (20) /* all times in msec */ 942169689Skan#define IWN_PASSIVE_DWELL_TIME_5GHZ (10) 943132718Skan#define IWN_PASSIVE_DWELL_BASE (100) 944132718Skan#define IWN_CHANNEL_TUNE_TIME (5) 94550397Sobrien 94650397Sobrien#define IWN_SCAN_CHAN_TIMEOUT 2 94718334Speter#define IWN_MAX_SCAN_CHANNEL 50 94818334Speter 94918334Speter/* 95018334Speter * If active scanning is requested but a certain channel is 95118334Speter * marked passive, we can do active scanning if we detect 952169689Skan * transmissions. 95318334Speter * 95418334Speter * There is an issue with some firmware versions that triggers 955169689Skan * a sysassert on a "good CRC threshold" of zero (== disabled), 95618334Speter * on a radar channel even though this means that we should NOT 95718334Speter * send probes. 958169689Skan * 95918334Speter * The "good CRC threshold" is the number of frames that we 960260311Spfg * need to receive during our dwell time on a channel before 961260311Spfg * sending out probes -- setting this to a huge value will 962260311Spfg * mean we never reach it, but at the same time work around 963260311Spfg * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER 964260311Spfg * here instead of IWL_GOOD_CRC_TH_DISABLED. 965260311Spfg * 966260311Spfg * This was fixed in later versions along with some other 967260311Spfg * scan changes, and the threshold behaves as a flag in those 968260311Spfg * versions. 969169689Skan */ 970169689Skan#define IWN_GOOD_CRC_TH_DISABLED 0 971169689Skan#define IWN_GOOD_CRC_TH_DEFAULT htole16(1) 972169689Skan#define IWN_GOOD_CRC_TH_NEVER htole16(0xffff) 973169689Skan 974169689Skan/* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 975169689Skan#define IWN_RIDX_MAX 32 976169689Skanstruct iwn4965_cmd_txpower { 977169689Skan uint8_t band; 97818334Speter uint8_t reserved1; 97918334Speter uint8_t chan; 98018334Speter uint8_t reserved2; 98118334Speter struct { 98218334Speter uint8_t rf_gain[2]; 98318334Speter uint8_t dsp_gain[2]; 98418334Speter } __packed power[IWN_RIDX_MAX + 1]; 98518334Speter} __packed; 986169689Skan 987169689Skan/* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 988169689Skanstruct iwn5000_cmd_txpower { 989132718Skan int8_t global_limit; /* in half-dBm */ 990169689Skan#define IWN5000_TXPOWER_AUTO 0x7f 991132718Skan#define IWN5000_TXPOWER_MAX_DBM 16 992132718Skan 993132718Skan uint8_t flags; 994132718Skan#define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 995132718Skan 996169689Skan int8_t srv_limit; /* in half-dBm */ 997169689Skan uint8_t reserved; 998169689Skan} __packed; 999169689Skan 1000169689Skan/* Structures for command IWN_CMD_BLUETOOTH. */ 1001169689Skanstruct iwn_bluetooth { 1002169689Skan uint8_t flags; 1003132718Skan#define IWN_BT_COEX_CHAN_ANN (1 << 0) 1004132718Skan#define IWN_BT_COEX_BT_PRIO (1 << 1) 1005132718Skan#define IWN_BT_COEX_2_WIRE (1 << 2) 1006132718Skan 1007132718Skan uint8_t lead_time; 1008169689Skan#define IWN_BT_LEAD_TIME_DEF 30 1009169689Skan 1010169689Skan uint8_t max_kill; 1011169689Skan#define IWN_BT_MAX_KILL_DEF 5 1012169689Skan 1013169689Skan uint8_t reserved; 1014169689Skan uint32_t kill_ack; 1015132718Skan uint32_t kill_cts; 1016132718Skan} __packed; 1017132718Skan 1018132718Skanstruct iwn6000_btcoex_config { 1019132718Skan uint8_t flags; 1020169689Skan#define IWN_BT_FLAG_COEX6000_CHAN_INHIBITION 1 1021132718Skan#define IWN_BT_FLAG_COEX6000_MODE_MASK ((1 << 3) | (1 << 4) | (1 << 5 )) 1022169689Skan#define IWN_BT_FLAG_COEX6000_MODE_SHIFT 3 1023169689Skan#define IWN_BT_FLAG_COEX6000_MODE_DISABLED 0 1024169689Skan#define IWN_BT_FLAG_COEX6000_MODE_LEGACY_2W 1 1025169689Skan#define IWN_BT_FLAG_COEX6000_MODE_3W 2 1026169689Skan#define IWN_BT_FLAG_COEX6000_MODE_4W 3 1027169689Skan 1028169689Skan#define IWN_BT_FLAG_UCODE_DEFAULT (1 << 6) 1029132718Skan#define IWN_BT_FLAG_SYNC_2_BT_DISABLE (1 << 7) 1030169689Skan uint8_t lead_time; 1031132718Skan uint8_t max_kill; 1032169689Skan uint8_t bt3_t7_timer; 1033169689Skan uint32_t kill_ack; 1034169689Skan uint32_t kill_cts; 1035169689Skan uint8_t sample_time; 1036169689Skan uint8_t bt3_t2_timer; 1037169689Skan uint16_t bt4_reaction; 1038169689Skan uint32_t lookup_table[12]; 1039169689Skan uint16_t bt4_decision; 1040169689Skan uint16_t valid; 1041169689Skan uint8_t prio_boost; 1042169689Skan uint8_t tx_prio_boost; 1043169689Skan uint16_t rx_prio_boost; 1044169689Skan} __packed; 1045169689Skan 1046169689Skan/* Structure for enhanced command IWN_CMD_BLUETOOTH for 2000 Series. */ 1047132718Skanstruct iwn2000_btcoex_config { 1048169689Skan uint8_t flags; /* Cf Flags in iwn6000_btcoex_config */ 1049169689Skan uint8_t lead_time; 1050169689Skan uint8_t max_kill; 1051169689Skan uint8_t bt3_t7_timer; 1052169689Skan uint32_t kill_ack; 1053169689Skan uint32_t kill_cts; 1054169689Skan uint8_t sample_time; 1055169689Skan uint8_t bt3_t2_timer; 1056169689Skan uint16_t bt4_reaction; 1057169689Skan uint32_t lookup_table[12]; 1058169689Skan uint16_t bt4_decision; 1059169689Skan uint16_t valid; 1060169689Skan 1061169689Skan uint32_t prio_boost; /* size change prior to iwn6000_btcoex_config */ 1062169689Skan uint8_t reserved; /* added prior to iwn6000_btcoex_config */ 1063132718Skan 1064132718Skan uint8_t tx_prio_boost; 1065132718Skan uint16_t rx_prio_boost; 1066132718Skan} __packed; 1067132718Skan 1068132718Skanstruct iwn_btcoex_priotable { 1069132718Skan uint8_t calib_init1; 1070169689Skan uint8_t calib_init2; 1071132718Skan uint8_t calib_periodic_low1; 1072132718Skan uint8_t calib_periodic_low2; 1073132718Skan uint8_t calib_periodic_high1; 1074132718Skan uint8_t calib_periodic_high2; 1075132718Skan uint8_t dtim; 1076132718Skan uint8_t scan52; 1077132718Skan uint8_t scan24; 1078169689Skan uint8_t reserved[7]; 1079169689Skan} __packed; 1080169689Skan 1081132718Skanstruct iwn_btcoex_prot { 1082132718Skan uint8_t open; 1083132718Skan uint8_t type; 1084132718Skan uint8_t reserved[2]; 1085132718Skan} __packed; 1086132718Skan 1087132718Skan/* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 1088132718Skanstruct iwn_critical_temp { 1089132718Skan uint32_t reserved; 1090132718Skan uint32_t tempM; 1091132718Skan uint32_t tempR; 1092132718Skan/* degK <-> degC conversion macros. */ 1093132718Skan#define IWN_CTOK(c) ((c) + 273) 1094132718Skan#define IWN_KTOC(k) ((k) - 273) 1095132718Skan#define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 1096132718Skan} __packed; 1097132718Skan 1098132718Skan/* Structures for command IWN_CMD_SET_SENSITIVITY. */ 1099132718Skanstruct iwn_sensitivity_cmd { 1100132718Skan uint16_t which; 1101132718Skan#define IWN_SENSITIVITY_DEFAULTTBL 0 1102132718Skan#define IWN_SENSITIVITY_WORKTBL 1 1103169689Skan 1104132718Skan uint16_t energy_cck; 1105132718Skan uint16_t energy_ofdm; 1106169689Skan uint16_t corr_ofdm_x1; 1107132718Skan uint16_t corr_ofdm_mrc_x1; 1108132718Skan uint16_t corr_cck_mrc_x4; 1109132718Skan uint16_t corr_ofdm_x4; 1110132718Skan uint16_t corr_ofdm_mrc_x4; 1111132718Skan uint16_t corr_barker; 1112132718Skan uint16_t corr_barker_mrc; 1113169689Skan uint16_t corr_cck_x4; 1114169689Skan uint16_t energy_ofdm_th; 1115169689Skan} __packed; 1116169689Skan 1117169689Skanstruct iwn_enhanced_sensitivity_cmd { 1118169689Skan uint16_t which; 1119169689Skan uint16_t energy_cck; 1120169689Skan uint16_t energy_ofdm; 1121169689Skan uint16_t corr_ofdm_x1; 1122169689Skan uint16_t corr_ofdm_mrc_x1; 1123169689Skan uint16_t corr_cck_mrc_x4; 1124169689Skan uint16_t corr_ofdm_x4; 1125169689Skan uint16_t corr_ofdm_mrc_x4; 1126169689Skan uint16_t corr_barker; 1127169689Skan uint16_t corr_barker_mrc; 1128169689Skan uint16_t corr_cck_x4; 1129169689Skan uint16_t energy_ofdm_th; 1130169689Skan /* "Enhanced" part. */ 1131169689Skan uint16_t ina_det_ofdm; 1132169689Skan uint16_t ina_det_cck; 1133169689Skan uint16_t corr_11_9_en; 1134169689Skan uint16_t ofdm_det_slope_mrc; 1135169689Skan uint16_t ofdm_det_icept_mrc; 1136169689Skan uint16_t ofdm_det_slope; 1137169689Skan uint16_t ofdm_det_icept; 1138169689Skan uint16_t cck_det_slope_mrc; 1139169689Skan uint16_t cck_det_icept_mrc; 1140169689Skan uint16_t cck_det_slope; 1141169689Skan uint16_t cck_det_icept; 1142169689Skan uint16_t reserved; 1143169689Skan} __packed; 1144132718Skan 1145169689Skan/* 1146169689Skan * Define maximal number of calib result send to runtime firmware 1147169689Skan * PS: TEMP_OFFSET count for 2 (std and v2) 1148169689Skan */ 1149132718Skan#define IWN5000_PHY_CALIB_MAX_RESULT 8 1150132718Skan 1151132718Skan/* Structures for command IWN_CMD_PHY_CALIB. */ 1152132718Skanstruct iwn_phy_calib { 1153132718Skan uint8_t code; 1154132718Skan#define IWN4965_PHY_CALIB_DIFF_GAIN 7 1155169689Skan#define IWN5000_PHY_CALIB_DC 8 1156169689Skan#define IWN5000_PHY_CALIB_LO 9 1157169689Skan#define IWN5000_PHY_CALIB_TX_IQ 11 1158169689Skan#define IWN5000_PHY_CALIB_CRYSTAL 15 1159132718Skan#define IWN5000_PHY_CALIB_BASE_BAND 16 1160132718Skan#define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 1161132718Skan#define IWN5000_PHY_CALIB_TEMP_OFFSET 18 1162132718Skan 1163132718Skan#define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 1164132718Skan#define IWN5000_PHY_CALIB_NOISE_GAIN 19 1165169689Skan 1166132718Skan uint8_t group; 1167169689Skan uint8_t ngroups; 1168169689Skan uint8_t isvalid; 1169169689Skan} __packed; 1170169689Skan 1171132718Skanstruct iwn5000_phy_calib_crystal { 1172169689Skan uint8_t code; 1173169689Skan uint8_t group; 1174169689Skan uint8_t ngroups; 1175169689Skan uint8_t isvalid; 1176169689Skan 1177169689Skan uint8_t cap_pin[2]; 1178169689Skan uint8_t reserved[2]; 1179169689Skan} __packed; 1180169689Skan 1181169689Skanstruct iwn5000_phy_calib_temp_offset { 1182169689Skan uint8_t code; 1183169689Skan uint8_t group; 1184169689Skan uint8_t ngroups; 1185169689Skan uint8_t isvalid; 1186169689Skan int16_t offset; 1187169689Skan#define IWN_DEFAULT_TEMP_OFFSET 2700 1188169689Skan 1189169689Skan uint16_t reserved; 1190169689Skan} __packed; 1191169689Skan 1192169689Skanstruct iwn5000_phy_calib_temp_offsetv2 { 1193169689Skan uint8_t code; 1194169689Skan uint8_t group; 1195169689Skan uint8_t ngroups; 1196169689Skan uint8_t isvalid; 1197169689Skan int16_t offset_high; 1198169689Skan int16_t offset_low; 1199169689Skan int16_t burnt_voltage_ref; 1200169689Skan int16_t reserved; 1201169689Skan} __packed; 1202169689Skan 1203169689Skanstruct iwn_phy_calib_gain { 1204169689Skan uint8_t code; 1205132718Skan uint8_t group; 1206132718Skan uint8_t ngroups; 1207132718Skan uint8_t isvalid; 1208132718Skan 1209132718Skan int8_t gain[3]; 1210169689Skan uint8_t reserved; 1211132718Skan} __packed; 1212132718Skan 1213132718Skan/* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 1214169689Skanstruct iwn_spectrum_cmd { 1215132718Skan uint16_t len; 1216169689Skan uint8_t token; 1217169689Skan uint8_t id; 1218169689Skan uint8_t origin; 1219169689Skan uint8_t periodic; 1220132718Skan uint16_t timeout; 1221132718Skan uint32_t start; 1222132718Skan uint32_t reserved1; 1223132718Skan uint32_t flags; 1224132718Skan uint32_t filter; 1225132718Skan uint16_t nchan; 1226132718Skan uint16_t reserved2; 1227132718Skan struct { 1228132718Skan uint32_t duration; 1229132718Skan uint8_t chan; 1230132718Skan uint8_t type; 1231169689Skan#define IWN_MEASUREMENT_BASIC (1 << 0) 1232169689Skan#define IWN_MEASUREMENT_CCA (1 << 1) 1233169689Skan#define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 1234169689Skan#define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 1235169689Skan#define IWN_MEASUREMENT_FRAME (1 << 4) 1236132718Skan#define IWN_MEASUREMENT_IDLE (1 << 7) 1237169689Skan 1238169689Skan uint16_t reserved; 1239132718Skan } __packed chan[10]; 1240132718Skan} __packed; 1241132718Skan 1242132718Skan/* Structure for IWN_UC_READY notification. */ 1243169689Skan#define IWN_NATTEN_GROUPS 5 1244132718Skanstruct iwn_ucode_info { 1245132718Skan uint8_t minor; 1246132718Skan uint8_t major; 1247132718Skan uint16_t reserved1; 1248132718Skan uint8_t revision[8]; 1249132718Skan uint8_t type; 1250132718Skan uint8_t subtype; 1251132718Skan#define IWN_UCODE_RUNTIME 0 1252132718Skan#define IWN_UCODE_INIT 9 1253169689Skan 1254132718Skan uint16_t reserved2; 1255132718Skan uint32_t logptr; 1256132718Skan uint32_t errptr; 1257132718Skan uint32_t tstamp; 1258132718Skan uint32_t valid; 1259132718Skan 1260132718Skan /* The following fields are for UCODE_INIT only. */ 1261132718Skan int32_t volt; 1262132718Skan struct { 1263132718Skan int32_t chan20MHz; 1264132718Skan int32_t chan40MHz; 1265169689Skan } __packed temp[4]; 1266169689Skan int32_t atten[IWN_NATTEN_GROUPS][2]; 1267169689Skan} __packed; 1268169689Skan 1269132718Skan/* Structures for IWN_TX_DONE notification. */ 1270132718Skan 1271132718Skan/* 1272169689Skan * TX command response is sent after *agn* transmission attempts. 1273132718Skan * 1274132718Skan * both postpone and abort status are expected behavior from uCode. there is 1275132718Skan * no special operation required from driver; except for RFKILL_FLUSH, 127618334Speter * which required tx flush host command to flush all the tx frames in queues 127718334Speter */ 127818334Speter#define IWN_TX_STATUS_MSK 0x000000ff 1279132718Skan#define IWN_TX_STATUS_DELAY_MSK 0x00000040 128018334Speter#define IWN_TX_STATUS_ABORT_MSK 0x00000080 128118334Speter#define IWN_TX_PACKET_MODE_MSK 0x0000ff00 128218334Speter#define IWN_TX_FIFO_NUMBER_MSK 0x00070000 128318334Speter#define IWN_TX_RESERVED 0x00780000 1284169689Skan#define IWN_TX_POWER_PA_DETECT_MSK 0x7f800000 128518334Speter#define IWN_TX_ABORT_REQUIRED_MSK 0x80000000 128618334Speter 128718334Speter/* Success status */ 128818334Speter#define IWN_TX_STATUS_SUCCESS 0x01 128918334Speter#define IWN_TX_STATUS_DIRECT_DONE 0x02 1290132718Skan 129118334Speter/* postpone TX */ 1292132718Skan#define IWN_TX_STATUS_POSTPONE_DELAY 0x40 1293132718Skan#define IWN_TX_STATUS_POSTPONE_FEW_BYTES 0x41 1294132718Skan#define IWN_TX_STATUS_POSTPONE_BT_PRIO 0x42 1295169689Skan#define IWN_TX_STATUS_POSTPONE_QUIET_PERIOD 0x43 1296169689Skan#define IWN_TX_STATUS_POSTPONE_CALC_TTAK 0x44 1297169689Skan 1298169689Skan/* Failures */ 1299132718Skan#define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */ 1300132718Skan#define IWN_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY 0x81 1301132718Skan#define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */ 1302132718Skan#define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */ 1303132718Skan#define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */ 1304132718Skan#define IWN_TX_STATUS_FAIL_DRAIN_FLOW 0x85 1305169689Skan#define IWN_TX_STATUS_FAIL_RFKILL_FLUSH 0x86 1306132718Skan#define IWN_TX_STATUS_FAIL_LIFE_EXPIRE 0x87 130718334Speter#define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */ 130818334Speter#define IWN_TX_STATUS_FAIL_HOST_ABORTED 0x89 130918334Speter#define IWN_TX_STATUS_FAIL_BT_RETRY 0x8a 131018334Speter#define IWN_TX_FAIL_STA_INVALID 0x8b /* XXX STA invalid (???) */ 131118334Speter#define IWN_TX_STATUS_FAIL_FRAG_DROPPED 0x8c 131218334Speter#define IWN_TX_STATUS_FAIL_TID_DISABLE 0x8d 131318334Speter#define IWN_TX_STATUS_FAIL_FIFO_FLUSHED 0x8e 131418334Speter#define IWN_TX_STATUS_FAIL_INSUFFICIENT_CF_POLL 0x8f 131518334Speter#define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */ 131618334Speter#define IWN_TX_STATUS_FAIL_NO_BEACON_ON_RADAR 0x91 131718334Speter 131818334Speter/* 131918334Speter * TX command response for A-MPDU packet responses. 132018334Speter * 132118334Speter * The status response is different to the non A-MPDU responses. 132218334Speter * In addition, the sequence number is treated as the sequence 1323169689Skan * number of the TX command, NOT the 802.11 sequence number! 132418334Speter */ 132518334Speter#define IWN_AGG_TX_STATE_TRANSMITTED 0x00 132618334Speter#define IWN_AGG_TX_STATE_UNDERRUN_MSK 0x01 132718334Speter#define IWN_AGG_TX_STATE_FEW_BYTES_MSK 0x04 132818334Speter#define IWN_AGG_TX_STATE_ABORT_MSK 0x08 132918334Speter 133018334Speter#define IWN_AGG_TX_STATE_LAST_SENT_TTL_MSK 0x10 133118334Speter#define IWN_AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK 0x20 1332169689Skan 133318334Speter#define IWN_AGG_TX_STATE_SCD_QUERY_MSK 0x80 133418334Speter 133518334Speter#define IWN_AGG_TX_STATE_TEST_BAD_CRC32_MSK 0x100 133618334Speter 133718334Speter#define IWN_AGG_TX_STATE_RESPONSE_MSK 0x1ff 1338169689Skan#define IWN_AGG_TX_STATE_DUMP_TX_MSK 0x200 133918334Speter#define IWN_AGG_TX_STATE_DELAY_TX_MSK 0x400 134018334Speter 134118334Speter#define IWN_AGG_TX_STATUS_MSK 0x00000fff 134218334Speter#define IWN_AGG_TX_TRY_MSK 0x0000f000 134318334Speter 134418334Speter#define IWN_AGG_TX_STATE_LAST_SENT_MSK \ 134518334Speter (IWN_AGG_TX_STATE_LAST_SENT_TTL_MSK | \ 134618334Speter IWN_AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK) 1347169689Skan 134818334Speter/* # tx attempts for first frame in aggregation */ 134918334Speter#define IWN_AGG_TX_STATE_TRY_CNT_POS 12 135018334Speter#define IWN_AGG_TX_STATE_TRY_CNT_MSK 0xf000 135118334Speter 135218334Speter/* Command ID and sequence number of Tx command for this frame */ 135318334Speter#define IWN_AGG_TX_STATE_SEQ_NUM_POS 16 135418334Speter#define IWN_AGG_TX_STATE_SEQ_NUM_MSK 0xffff0000 1355169689Skan 135618334Speterstruct iwn4965_tx_stat { 135718334Speter uint8_t nframes; 135818334Speter uint8_t btkillcnt; 135918334Speter uint8_t rtsfailcnt; 136018334Speter uint8_t ackfailcnt; 136118334Speter uint32_t rate; 1362169689Skan uint16_t duration; 1363169689Skan uint16_t reserved; 1364169689Skan uint32_t power[2]; 1365169689Skan uint32_t status; 1366169689Skan} __packed; 1367169689Skan 136818334Speterstruct iwn5000_tx_stat { 136918334Speter uint8_t nframes; /* 1 no aggregation, >1 aggregation */ 137018334Speter uint8_t btkillcnt; 137118334Speter uint8_t rtsfailcnt; 1372169689Skan uint8_t ackfailcnt; 137318334Speter uint32_t rate; 1374169689Skan uint16_t duration; 137518334Speter uint16_t reserved; 137618334Speter uint32_t power[2]; 1377169689Skan uint32_t info; 137818334Speter uint16_t seq; 1379169689Skan uint16_t len; 138018334Speter uint8_t tlc; 138118334Speter uint8_t ratid; /* tid (0:3), sta_id (4:7) */ 1382132718Skan uint8_t fc[2]; 1383169689Skan uint16_t status; 1384169689Skan uint16_t sequence; 1385132718Skan} __packed; 1386169689Skan 138718334Speter/* Structure for IWN_BEACON_MISSED notification. */ 138818334Speterstruct iwn_beacon_missed { 138918334Speter uint32_t consecutive; 1390169689Skan uint32_t total; 1391169689Skan uint32_t expected; 1392169689Skan uint32_t received; 1393169689Skan} __packed; 1394169689Skan 1395169689Skan/* Structure for IWN_MPDU_RX_DONE notification. */ 139618334Speterstruct iwn_rx_mpdu { 139718334Speter uint16_t len; 1398169689Skan uint16_t reserved; 139918334Speter} __packed; 1400169689Skan 1401169689Skan/* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1402169689Skanstruct iwn4965_rx_phystat { 1403169689Skan uint16_t antenna; 1404169689Skan uint16_t agc; 1405169689Skan uint8_t rssi[6]; 1406169689Skan} __packed; 1407169689Skan 140818334Speterstruct iwn5000_rx_phystat { 140918334Speter uint32_t reserved1; 141018334Speter uint32_t agc; 1411169689Skan uint16_t rssi[3]; 1412169689Skan} __packed; 1413169689Skan 1414169689Skanstruct iwn_rx_stat { 1415169689Skan uint8_t phy_len; 1416169689Skan uint8_t cfg_phy_len; 141718334Speter#define IWN_STAT_MAXLEN 20 141818334Speter 1419169689Skan uint8_t id; 142018334Speter uint8_t reserved1; 1421169689Skan uint64_t tstamp; 1422169689Skan uint32_t beacon; 1423169689Skan uint16_t flags; 1424169689Skan#define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1425169689Skan 1426169689Skan uint16_t chan; 1427169689Skan uint8_t phybuf[32]; 1428169689Skan uint32_t rate; 142918334Speter/* 143018334Speter * rate bit fields 143118334Speter * 143218334Speter * High-throughput (HT) rate format for bits 7:0 (bit 8 must be "1"): 143318334Speter * 2-0: 0) 6 Mbps 143418334Speter * 1) 12 Mbps 143518334Speter * 2) 18 Mbps 143618334Speter * 3) 24 Mbps 143718334Speter * 4) 36 Mbps 143818334Speter * 5) 48 Mbps 143918334Speter * 6) 54 Mbps 144018334Speter * 7) 60 Mbps 144118334Speter * 144218334Speter * 4-3: 0) Single stream (SISO) 144318334Speter * 1) Dual stream (MIMO) 144418334Speter * 2) Triple stream (MIMO) 144518334Speter * 144618334Speter * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 1447169689Skan * 1448132718Skan * Legacy OFDM rate format for bits 7:0 (bit 8 must be "0", bit 9 "0"): 144918334Speter * 3-0: 0xD) 6 Mbps 145018334Speter * 0xF) 9 Mbps 145118334Speter * 0x5) 12 Mbps 145290075Sobrien * 0x7) 18 Mbps 145390075Sobrien * 0x9) 24 Mbps 145490075Sobrien * 0xB) 36 Mbps 145590075Sobrien * 0x1) 48 Mbps 145618334Speter * 0x3) 54 Mbps 145718334Speter * 145890075Sobrien * Legacy CCK rate format for bits 7:0 (bit 8 must be "0", bit 9 "1"): 145918334Speter * 6-0: 10) 1 Mbps 146018334Speter * 20) 2 Mbps 146118334Speter * 55) 5.5 Mbps 146290075Sobrien * 110) 11 Mbps 146390075Sobrien * 146490075Sobrien */ 146518334Speter uint16_t len; 146618334Speter uint16_t reserve3; 146790075Sobrien} __packed; 146818334Speter 146918334Speter#define IWN_RSSI_TO_DBM 44 1470132718Skan 147118334Speter/* Structure for IWN_RX_COMPRESSED_BA notification. */ 147250397Sobrienstruct iwn_compressed_ba { 1473169689Skan uint8_t macaddr[IEEE80211_ADDR_LEN]; 1474169689Skan uint16_t reserved; 147550397Sobrien uint8_t id; 1476169689Skan uint8_t tid; 1477169689Skan uint16_t seq; 147890075Sobrien uint64_t bitmap; 147918334Speter uint16_t qid; 148018334Speter uint16_t ssn; 148118334Speter /* extra fields starting with iwn5000 */ 148218334Speter#if 0 148318334Speter uint8_t txed; /* number of frames sent */ 148418334Speter uint8_t txed_2_done; /* number of frames acked */ 148518334Speter uint16_t reserved1; 148690075Sobrien#endif 148718334Speter} __packed; 148818334Speter 148918334Speter/* Structure for IWN_START_SCAN notification. */ 149018334Speterstruct iwn_start_scan { 149190075Sobrien uint64_t tstamp; 149290075Sobrien uint32_t tbeacon; 149390075Sobrien uint8_t chan; 149490075Sobrien uint8_t band; 149590075Sobrien uint16_t reserved; 149690075Sobrien uint32_t status; 149790075Sobrien} __packed; 149818334Speter 149990075Sobrien/* Structure for IWN_STOP_SCAN notification. */ 1500132718Skanstruct iwn_stop_scan { 150118334Speter uint8_t nchan; 1502169689Skan uint8_t status; 1503169689Skan uint8_t reserved; 150490075Sobrien uint8_t chan; 150590075Sobrien uint64_t tsf; 1506169689Skan} __packed; 1507169689Skan 1508169689Skan/* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1509169689Skanstruct iwn_spectrum_notif { 1510169689Skan uint8_t id; 1511169689Skan uint8_t token; 1512169689Skan uint8_t idx; 1513169689Skan uint8_t state; 151490075Sobrien#define IWN_MEASUREMENT_START 0 151518334Speter#define IWN_MEASUREMENT_STOP 1 1516169689Skan 1517260311Spfg uint32_t start; 1518260311Spfg uint8_t band; 1519169689Skan uint8_t chan; 152090075Sobrien uint8_t type; 1521169689Skan uint8_t reserved1; 152290075Sobrien uint32_t cca_ofdm; 1523169689Skan uint32_t cca_cck; 1524169689Skan uint32_t cca_time; 1525169689Skan uint8_t basic; 152690075Sobrien uint8_t reserved2[3]; 1527169689Skan uint32_t ofdm[8]; 152890075Sobrien uint32_t cck[8]; 1529169689Skan uint32_t stop; 153018334Speter uint32_t status; 1531169689Skan#define IWN_MEASUREMENT_OK 0 1532169689Skan#define IWN_MEASUREMENT_CONCURRENT 1 153350397Sobrien#define IWN_MEASUREMENT_CSA_CONFLICT 2 1534169689Skan#define IWN_MEASUREMENT_TGH_CONFLICT 3 1535169689Skan#define IWN_MEASUREMENT_STOPPED 6 1536169689Skan#define IWN_MEASUREMENT_TIMEOUT 7 1537169689Skan#define IWN_MEASUREMENT_FAILED 8 1538169689Skan} __packed; 1539169689Skan 154018334Speter/* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1541169689Skanstruct iwn_rx_phy_stats { 1542169689Skan uint32_t ina; 1543169689Skan uint32_t fina; 1544169689Skan uint32_t bad_plcp; 1545169689Skan uint32_t bad_crc32; 1546169689Skan uint32_t overrun; 1547169689Skan uint32_t eoverrun; 1548169689Skan uint32_t good_crc32; 1549169689Skan uint32_t fa; 155018334Speter uint32_t bad_fina_sync; 155118334Speter uint32_t sfd_timeout; 1552169689Skan uint32_t fina_timeout; 1553169689Skan uint32_t no_rts_ack; 1554169689Skan uint32_t rxe_limit; 1555169689Skan uint32_t ack; 1556169689Skan uint32_t cts; 155718334Speter uint32_t ba_resp; 1558169689Skan uint32_t dsp_kill; 1559260311Spfg uint32_t bad_mh; 1560260311Spfg uint32_t rssi_sum; 1561169689Skan uint32_t reserved; 1562169689Skan} __packed; 1563169689Skan 156418334Speterstruct iwn_rx_general_stats { 1565169689Skan uint32_t bad_cts; 156618334Speter uint32_t bad_ack; 1567169689Skan uint32_t not_bss; 156818334Speter uint32_t filtered; 1569169689Skan uint32_t bad_chan; 1570169689Skan uint32_t beacons; 157118334Speter uint32_t missed_beacons; 1572169689Skan uint32_t adc_saturated; /* time in 0.8us */ 157318334Speter uint32_t ina_searched; /* time in 0.8us */ 157490075Sobrien uint32_t noise[3]; 1575169689Skan uint32_t flags; 1576169689Skan uint32_t load; 1577169689Skan uint32_t fa; 157890075Sobrien uint32_t rssi[3]; 1579169689Skan uint32_t energy[3]; 1580169689Skan} __packed; 158190075Sobrien 1582169689Skanstruct iwn_rx_ht_phy_stats { 1583169689Skan uint32_t bad_plcp; 158490075Sobrien uint32_t overrun; 158590075Sobrien uint32_t eoverrun; 1586169689Skan uint32_t good_crc32; 1587169689Skan uint32_t bad_crc32; 1588169689Skan uint32_t bad_mh; 1589169689Skan uint32_t good_ampdu_crc32; 1590169689Skan uint32_t ampdu; 1591169689Skan uint32_t fragment; 159290075Sobrien uint32_t unsupport_mcs; 1593169689Skan} __packed; 1594169689Skan 1595169689Skanstruct iwn_rx_stats { 1596169689Skan struct iwn_rx_phy_stats ofdm; 1597169689Skan struct iwn_rx_phy_stats cck; 1598169689Skan struct iwn_rx_general_stats general; 1599169689Skan struct iwn_rx_ht_phy_stats ht; 1600169689Skan} __packed; 1601169689Skan 160290075Sobrienstruct iwn_rx_general_stats_bt { 1603169689Skan struct iwn_rx_general_stats common; 1604169689Skan /* additional stats for bt */ 1605169689Skan uint32_t num_bt_kills; 1606169689Skan uint32_t reserved[2]; 1607169689Skan} __packed; 1608169689Skan 1609169689Skanstruct iwn_rx_stats_bt { 1610169689Skan struct iwn_rx_phy_stats ofdm; 1611169689Skan struct iwn_rx_phy_stats cck; 1612169689Skan struct iwn_rx_general_stats_bt general_bt; 1613169689Skan struct iwn_rx_ht_phy_stats ht; 1614169689Skan} __packed; 1615169689Skan 1616169689Skanstruct iwn_tx_stats { 1617169689Skan uint32_t preamble; 1618169689Skan uint32_t rx_detected; 1619169689Skan uint32_t bt_defer; 1620169689Skan uint32_t bt_kill; 1621169689Skan uint32_t short_len; 1622169689Skan uint32_t cts_timeout; 1623169689Skan uint32_t ack_timeout; 1624169689Skan uint32_t exp_ack; 1625169689Skan uint32_t ack; 1626169689Skan uint32_t msdu; 162790075Sobrien uint32_t burst_err1; 162890075Sobrien uint32_t burst_err2; 1629169689Skan uint32_t cts_collision; 1630169689Skan uint32_t ack_collision; 163190075Sobrien uint32_t ba_timeout; 163290075Sobrien uint32_t ba_resched; 1633169689Skan uint32_t query_ampdu; 1634169689Skan uint32_t query; 163590075Sobrien uint32_t query_ampdu_frag; 1636169689Skan uint32_t query_mismatch; 1637169689Skan uint32_t not_ready; 1638169689Skan uint32_t underrun; 1639169689Skan uint32_t bt_ht_kill; 1640169689Skan uint32_t rx_ba_resp; 1641169689Skan /* 1642169689Skan * 6000 series only - LSB=ant A, ant B, ant C, MSB=reserved 1643169689Skan * TX power on chain in 1/2 dBm. 164490075Sobrien */ 164590075Sobrien uint32_t tx_power; 164690075Sobrien uint32_t reserved[1]; 164790075Sobrien} __packed; 1648117395Skan 1649117395Skanstruct iwn_general_stats { 1650117395Skan uint32_t temp; /* radio temperature */ 1651117395Skan uint32_t temp_m; /* radio voltage */ 1652169689Skan uint32_t burst_check; 165390075Sobrien uint32_t burst; 165490075Sobrien uint32_t wait_for_silence_timeout_cnt; 165590075Sobrien uint32_t reserved1[3]; 165690075Sobrien uint32_t sleep; 1657169689Skan uint32_t slot_out; 1658169689Skan uint32_t slot_idle; 165990075Sobrien uint32_t ttl_tstamp; 166090075Sobrien uint32_t tx_ant_a; 166190075Sobrien uint32_t tx_ant_b; 166290075Sobrien uint32_t exec; 166390075Sobrien uint32_t probe; 166490075Sobrien uint32_t reserved2[2]; 1665117395Skan uint32_t rx_enabled; 166690075Sobrien /* 166790075Sobrien * This is the number of times we have to re-tune 166890075Sobrien * in order to get out of bad PHY status. 1669117395Skan */ 1670169689Skan uint32_t num_of_sos_states; 1671117395Skan} __packed; 167290075Sobrien 167390075Sobrienstruct iwn_stats { 167490075Sobrien uint32_t flags; 167590075Sobrien struct iwn_rx_stats rx; 167690075Sobrien struct iwn_tx_stats tx; 1677169689Skan struct iwn_general_stats general; 1678169689Skan uint32_t reserved1[2]; 1679169689Skan} __packed; 1680169689Skan 1681169689Skanstruct iwn_bt_activity_stats { 1682169689Skan /* Tx statistics */ 1683169689Skan uint32_t hi_priority_tx_req_cnt; 1684169689Skan uint32_t hi_priority_tx_denied_cnt; 1685169689Skan uint32_t lo_priority_tx_req_cnt; 1686169689Skan uint32_t lo_priority_tx_denied_cnt; 1687169689Skan /* Rx statistics */ 1688169689Skan uint32_t hi_priority_rx_req_cnt; 1689169689Skan uint32_t hi_priority_rx_denied_cnt; 1690169689Skan uint32_t lo_priority_rx_req_cnt; 1691169689Skan uint32_t lo_priority_rx_denied_cnt; 1692169689Skan} __packed; 1693169689Skan 1694169689Skanstruct iwn_stats_bt { 1695169689Skan uint32_t flags; 1696169689Skan struct iwn_rx_stats_bt rx_bt; 1697169689Skan struct iwn_tx_stats tx; 1698169689Skan struct iwn_general_stats general; 1699169689Skan struct iwn_bt_activity_stats activity; 1700169689Skan uint32_t reserved1[2]; 1701169689Skan}; 1702169689Skan 1703169689Skan/* Firmware error dump. */ 1704169689Skanstruct iwn_fw_dump { 1705169689Skan uint32_t valid; 1706169689Skan uint32_t id; 1707169689Skan uint32_t pc; 1708169689Skan uint32_t branch_link[2]; 1709169689Skan uint32_t interrupt_link[2]; 1710169689Skan uint32_t error_data[2]; 1711169689Skan uint32_t src_line; 1712169689Skan uint32_t tsf; 1713169689Skan uint32_t time[2]; 1714169689Skan} __packed; 1715169689Skan 1716169689Skan/* TLV firmware header. */ 1717169689Skanstruct iwn_fw_tlv_hdr { 1718169689Skan uint32_t zero; /* Always 0, to differentiate from legacy. */ 1719169689Skan uint32_t signature; 172090075Sobrien#define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */ 172190075Sobrien 172290075Sobrien uint8_t descr[64]; 172390075Sobrien uint32_t rev; 172490075Sobrien#define IWN_FW_API(x) (((x) >> 8) & 0xff) 172590075Sobrien 172690075Sobrien uint32_t build; 172718334Speter uint64_t altmask; 172890075Sobrien} __packed; 172918334Speter 173090075Sobrien/* TLV header. */ 173190075Sobrienstruct iwn_fw_tlv { 173290075Sobrien uint16_t type; 173390075Sobrien#define IWN_FW_TLV_MAIN_TEXT 1 173490075Sobrien#define IWN_FW_TLV_MAIN_DATA 2 173590075Sobrien#define IWN_FW_TLV_INIT_TEXT 3 1736132718Skan#define IWN_FW_TLV_INIT_DATA 4 173718334Speter#define IWN_FW_TLV_BOOT_TEXT 5 1738132718Skan#define IWN_FW_TLV_PBREQ_MAXLEN 6 173918334Speter#define IWN_FW_TLV_PAN 7 174090075Sobrien#define IWN_FW_TLV_RUNT_EVTLOG_PTR 8 174118334Speter#define IWN_FW_TLV_RUNT_EVTLOG_SIZE 9 174218334Speter#define IWN_FW_TLV_RUNT_ERRLOG_PTR 10 174318334Speter#define IWN_FW_TLV_INIT_EVTLOG_PTR 11 174418334Speter#define IWN_FW_TLV_INIT_EVTLOG_SIZE 12 174518334Speter#define IWN_FW_TLV_INIT_ERRLOG_PTR 13 174618334Speter#define IWN_FW_TLV_ENH_SENS 14 174718334Speter#define IWN_FW_TLV_PHY_CALIB 15 1748169689Skan#define IWN_FW_TLV_WOWLAN_INST 16 174918334Speter#define IWN_FW_TLV_WOWLAN_DATA 17 175018334Speter#define IWN_FW_TLV_FLAGS 18 1751132718Skan 175218334Speter uint16_t alt; 175318334Speter uint32_t len; 175418334Speter} __packed; 1755132718Skan 175618334Speter#define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 175718334Speter#define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 175818334Speter#define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 175918334Speter#define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 176018334Speter#define IWN_FW_BOOT_TEXT_MAXSZ 1024 176118334Speter#define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 176218334Speter#define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 176318334Speter 176418334Speter/* 176518334Speter * Microcode flags TLV (18.) 176618334Speter */ 176750397Sobrien 176850397Sobrien/** 176990075Sobrien * enum iwn_ucode_tlv_flag - ucode API flags 177090075Sobrien * @IWN_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 177150397Sobrien * was a separate TLV but moved here to save space. 177290075Sobrien * @IWN_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 177390075Sobrien * treats good CRC threshold as a boolean 1774132718Skan * @IWN_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 177518334Speter * @IWN_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 177618334Speter * @IWN_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 177718334Speter * @IWN_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 177818334Speter * @IWN_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 177918334Speter * offload profile config command. 178018334Speter * @IWN_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api 178118334Speter * @IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API. 178218334Speter * @IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 178318334Speter * (rather than two) IPv6 addresses 178418334Speter * @IWN_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API 178518334Speter * @IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 178618334Speter * from the probe request template. 178718334Speter * @IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping 178818334Speter * connection when going back to D0 178918334Speter * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 179018334Speter * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 179118334Speter * @IWN_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan. 179218334Speter * @IWN_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API 179318334Speter * @IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command 179418334Speter * containing CAM (Continuous Active Mode) indication. 179518334Speter */ 179690075Sobrienenum iwn_ucode_tlv_flag { 179718334Speter IWN_UCODE_TLV_FLAGS_PAN = (1 << 0), 179818334Speter IWN_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 179918334Speter IWN_UCODE_TLV_FLAGS_MFP = (1 << 2), 180018334Speter IWN_UCODE_TLV_FLAGS_P2P = (1 << 3), 180118334Speter IWN_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), 180290075Sobrien IWN_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5), 180390075Sobrien IWN_UCODE_TLV_FLAGS_UAPSD = (1 << 6), 180490075Sobrien IWN_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 180518334Speter IWN_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8), 180690075Sobrien IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9), 180750397Sobrien IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 180890075Sobrien IWN_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11), 180990075Sobrien IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 181018334Speter IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14), 181118334Speter IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 181218334Speter IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 181318334Speter IWN_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17), 181418334Speter IWN_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19), 181590075Sobrien IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20), 181690075Sobrien}; 181790075Sobrien 181818334Speter/* 181918334Speter * Offsets into EEPROM. 182090075Sobrien */ 182118334Speter#define IWN_EEPROM_MAC 0x015 182218334Speter#define IWN_EEPROM_SKU_CAP 0x045 182318334Speter#define IWN_EEPROM_RFCFG 0x048 182418334Speter#define IWN4965_EEPROM_DOMAIN 0x060 182518334Speter#define IWN4965_EEPROM_BAND1 0x063 182618334Speter#define IWN5000_EEPROM_REG 0x066 1827132718Skan#define IWN5000_EEPROM_CAL 0x067 182818334Speter#define IWN4965_EEPROM_BAND2 0x072 182990075Sobrien#define IWN4965_EEPROM_BAND3 0x080 183090075Sobrien#define IWN4965_EEPROM_BAND4 0x08d 183190075Sobrien#define IWN4965_EEPROM_BAND5 0x099 183290075Sobrien#define IWN4965_EEPROM_BAND6 0x0a0 183318334Speter#define IWN4965_EEPROM_BAND7 0x0a8 1834169689Skan#define IWN4965_EEPROM_MAXPOW 0x0e8 1835169689Skan#define IWN4965_EEPROM_VOLTAGE 0x0e9 1836169689Skan#define IWN4965_EEPROM_BANDS 0x0ea 1837260311Spfg/* Indirect offsets. */ 1838260311Spfg#define IWN5000_EEPROM_NO_HT40 0x000 1839260311Spfg#define IWN5000_EEPROM_DOMAIN 0x001 1840260311Spfg#define IWN5000_EEPROM_BAND1 0x004 1841260311Spfg#define IWN5000_EEPROM_BAND2 0x013 1842260311Spfg#define IWN5000_EEPROM_BAND3 0x021 184318334Speter#define IWN5000_EEPROM_BAND4 0x02e 184418334Speter#define IWN5000_EEPROM_BAND5 0x03a 184518334Speter#define IWN5000_EEPROM_BAND6 0x041 184618334Speter#define IWN6000_EEPROM_BAND6 0x040 184790075Sobrien#define IWN5000_EEPROM_BAND7 0x049 184818334Speter#define IWN6000_EEPROM_ENHINFO 0x054 1849117395Skan#define IWN5000_EEPROM_CRYSTAL 0x128 185018334Speter#define IWN5000_EEPROM_TEMP 0x12a 185118334Speter#define IWN5000_EEPROM_VOLT 0x12b 185218334Speter 185390075Sobrien/* Possible flags for IWN_EEPROM_SKU_CAP. */ 185418334Speter#define IWN_EEPROM_SKU_CAP_11N (1 << 6) 185518334Speter#define IWN_EEPROM_SKU_CAP_AMT (1 << 7) 185618334Speter#define IWN_EEPROM_SKU_CAP_IPAN (1 << 8) 1857169689Skan 185818334Speter/* Possible flags for IWN_EEPROM_RFCFG. */ 185918334Speter#define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 186018334Speter#define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 186190075Sobrien#define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 186290075Sobrien#define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 186390075Sobrien#define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 186490075Sobrien 186590075Sobrienstruct iwn_eeprom_chan { 1866117395Skan uint8_t flags; 186718334Speter#define IWN_EEPROM_CHAN_VALID (1 << 0) 186890075Sobrien#define IWN_EEPROM_CHAN_IBSS (1 << 1) 1869169689Skan#define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1870169689Skan#define IWN_EEPROM_CHAN_RADAR (1 << 4) 187190075Sobrien 187290075Sobrien int8_t maxpwr; 187390075Sobrien} __packed; 187490075Sobrien 1875169689Skanstruct iwn_eeprom_enhinfo { 1876169689Skan uint8_t flags; 1877169689Skan#define IWN_ENHINFO_VALID 0x01 1878169689Skan#define IWN_ENHINFO_5GHZ 0x02 1879169689Skan#define IWN_ENHINFO_OFDM 0x04 1880169689Skan#define IWN_ENHINFO_HT40 0x08 1881260311Spfg#define IWN_ENHINFO_HTAP 0x10 1882260311Spfg#define IWN_ENHINFO_RES1 0x20 188390075Sobrien#define IWN_ENHINFO_RES2 0x40 188418334Speter#define IWN_ENHINFO_COMMON 0x80 188590075Sobrien 188618334Speter uint8_t chan; 188790075Sobrien int8_t chain[3]; /* max power in half-dBm */ 188890075Sobrien uint8_t reserved; 188990075Sobrien int8_t mimo2; /* max power in half-dBm */ 189090075Sobrien int8_t mimo3; /* max power in half-dBm */ 1891260014Spfg} __packed; 1892260014Spfg 1893260014Spfgstruct iwn5000_eeprom_calib_hdr { 1894260014Spfg uint8_t version; 1895260014Spfg uint8_t pa_type; 189618334Speter uint16_t volt; 1897117395Skan} __packed; 1898117395Skan 189918334Speter#define IWN_NSAMPLES 3 1900117395Skanstruct iwn4965_eeprom_chan_samples { 190118334Speter uint8_t num; 190218334Speter struct { 190318334Speter uint8_t temp; 190418334Speter uint8_t gain; 1905169689Skan uint8_t power; 1906169689Skan int8_t pa_det; 190718334Speter } samples[2][IWN_NSAMPLES]; 190818334Speter} __packed; 190918334Speter 191018334Speter#define IWN_NBANDS 8 191118334Speterstruct iwn4965_eeprom_band { 191218334Speter uint8_t lo; /* low channel number */ 191318334Speter uint8_t hi; /* high channel number */ 191418334Speter struct iwn4965_eeprom_chan_samples chans[2]; 191518334Speter} __packed; 1916132718Skan 191718334Speter/* 191890075Sobrien * Offsets of channels descriptions in EEPROM. 191990075Sobrien */ 192018334Speterstatic const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 192118334Speter IWN4965_EEPROM_BAND1, 192218334Speter IWN4965_EEPROM_BAND2, 1923258501Spfg IWN4965_EEPROM_BAND3, 1924258501Spfg IWN4965_EEPROM_BAND4, 1925258501Spfg IWN4965_EEPROM_BAND5, 1926258501Spfg IWN4965_EEPROM_BAND6, 1927258501Spfg IWN4965_EEPROM_BAND7 1928258501Spfg}; 1929258501Spfg 1930258501Spfgstatic const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1931258501Spfg IWN5000_EEPROM_BAND1, 1932258501Spfg IWN5000_EEPROM_BAND2, 1933258501Spfg IWN5000_EEPROM_BAND3, 1934258501Spfg IWN5000_EEPROM_BAND4, 1935258501Spfg IWN5000_EEPROM_BAND5, 193618334Speter IWN5000_EEPROM_BAND6, 193718334Speter IWN5000_EEPROM_BAND7 193818334Speter}; 193918334Speter 194018334Speterstatic const uint32_t iwn6000_regulatory_bands[IWN_NBANDS] = { 194118334Speter IWN5000_EEPROM_BAND1, 194218334Speter IWN5000_EEPROM_BAND2, 1943169689Skan IWN5000_EEPROM_BAND3, 194418334Speter IWN5000_EEPROM_BAND4, 1945169689Skan IWN5000_EEPROM_BAND5, 1946169689Skan IWN6000_EEPROM_BAND6, 194790075Sobrien IWN5000_EEPROM_BAND7 194818334Speter}; 194918334Speter 195018334Speterstatic const uint32_t iwn1000_regulatory_bands[IWN_NBANDS] = { 195118334Speter IWN5000_EEPROM_BAND1, 195290075Sobrien IWN5000_EEPROM_BAND2, 1953169689Skan IWN5000_EEPROM_BAND3, 195418334Speter IWN5000_EEPROM_BAND4, 195518334Speter IWN5000_EEPROM_BAND5, 195618334Speter IWN5000_EEPROM_BAND6, 195718334Speter IWN5000_EEPROM_NO_HT40, 195818334Speter}; 195918334Speter 196018334Speterstatic const uint32_t iwn2030_regulatory_bands[IWN_NBANDS] = { 196118334Speter IWN5000_EEPROM_BAND1, 196218334Speter IWN5000_EEPROM_BAND2, 196318334Speter IWN5000_EEPROM_BAND3, 1964132718Skan IWN5000_EEPROM_BAND4, 196518334Speter IWN5000_EEPROM_BAND5, 196618334Speter IWN6000_EEPROM_BAND6, 196718334Speter IWN5000_EEPROM_BAND7 196818334Speter}; 196918334Speter 1970259022Spfg#define IWN_CHAN_BANDS_COUNT 7 197118334Speter#define IWN_MAX_CHAN_PER_BAND 14 197218334Speterstatic const struct iwn_chan_band { 197318334Speter uint8_t nchan; 197418334Speter uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 197518334Speter} iwn_bands[] = { 197618334Speter /* 20MHz channels, 2GHz band. */ 197718334Speter { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 197818334Speter /* 20MHz channels, 5GHz band. */ 197918334Speter { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 198018334Speter { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 198118334Speter { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 198218334Speter { 6, { 145, 149, 153, 157, 161, 165 } }, 198318334Speter /* 40MHz channels (primary channels), 2GHz band. */ 1984132718Skan { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 198518334Speter /* 40MHz channels (primary channels), 5GHz band. */ 1986169689Skan { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 198718334Speter}; 198818334Speter 198918334Speterstatic const uint8_t iwn_bss_ac_to_queue[] = { 199018334Speter 2, 3, 1, 0, 1991169689Skan}; 1992169689Skan 199318334Speterstatic const uint8_t iwn_pan_ac_to_queue[] = { 1994169689Skan 5, 4, 6, 7, 1995169689Skan}; 1996169689Skan#define IWN1000_OTP_NBLOCKS 3 199718334Speter#define IWN6000_OTP_NBLOCKS 4 1998169689Skan#define IWN6050_OTP_NBLOCKS 7 199918334Speter 200018334Speter/* HW rate indices. */ 2001169689Skan#define IWN_RIDX_CCK1 0 2002169689Skan#define IWN_RIDX_OFDM6 4 2003169689Skan 2004169689Skan#define IWN4965_MAX_PWR_INDEX 107 2005169689Skan#define IWN_POWERSAVE_LVL_NONE 0 200618334Speter#define IWN_POWERSAVE_LVL_VOIP_COMPATIBLE 1 2007169689Skan#define IWN_POWERSAVE_LVL_MAX 5 2008169689Skan 2009169689Skan#define IWN_POWERSAVE_LVL_DEFAULT IWN_POWERSAVE_LVL_NONE 2010169689Skan 2011169689Skan/* DTIM value to pass in for IWN_POWERSAVE_LVL_VOIP_COMPATIBLE */ 2012169689Skan#define IWN_POWERSAVE_DTIM_VOIP_COMPATIBLE 2 2013169689Skan 2014169689Skan/* 2015169689Skan * RF Tx gain values from highest to lowest power (values obtained from 2016169689Skan * the reference driver.) 2017169689Skan */ 2018169689Skanstatic const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 2019169689Skan 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 2020169689Skan 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 2021169689Skan 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 2022169689Skan 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 2023169689Skan 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 2024169689Skan 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 2025169689Skan 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 2026169689Skan 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 2027169689Skan 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 2028169689Skan 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 2029169689Skan}; 2030169689Skan 2031169689Skanstatic const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 2032169689Skan 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 203318334Speter 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 203418334Speter 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 203518334Speter 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 203618334Speter 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 203718334Speter 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 203890075Sobrien 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 203918334Speter 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 204018334Speter 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 2041117395Skan 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 204218334Speter}; 204318334Speter 204418334Speter/* 204518334Speter * DSP pre-DAC gain values from highest to lowest power (values obtained 204618334Speter * from the reference driver.) 204718334Speter */ 204818334Speterstatic const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 2049169689Skan 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 2050169689Skan 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 205118334Speter 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 2052117395Skan 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 205318334Speter 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 205418334Speter 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 205518334Speter 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 205618334Speter 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 205718334Speter 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 205818334Speter 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 205918334Speter}; 206018334Speter 2061169689Skanstatic const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 2062169689Skan 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 2063169689Skan 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 2064117395Skan 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 206518334Speter 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 206618334Speter 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 2067169689Skan 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 2068169689Skan 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 2069169689Skan 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 2070169689Skan 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 207118334Speter 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 2072169689Skan}; 207318334Speter 207418334Speter/* 207518334Speter * Power saving settings (values obtained from the reference driver.) 207618334Speter */ 207718334Speter#define IWN_NDTIMRANGES 3 207818334Speter#define IWN_NPOWERLEVELS 6 207918334Speterstatic const struct iwn_pmgt { 208018334Speter uint32_t rxtimeout; 208118334Speter uint32_t txtimeout; 2082132718Skan uint32_t intval[5]; 208318334Speter int skip_dtim; 208418334Speter} iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 208518334Speter /* DTIM <= 2 */ 208618334Speter { 208718334Speter { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 2088169689Skan { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 2089169689Skan { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 2090169689Skan { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 209118334Speter { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 2092169689Skan { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 2093169689Skan }, 209418334Speter /* 3 <= DTIM <= 10 */ 2095169689Skan { 2096169689Skan { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 209750397Sobrien { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 2098169689Skan { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 2099169689Skan { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 2100169689Skan { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 210118334Speter { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 210218334Speter }, 210390075Sobrien /* DTIM >= 11 */ 2104169689Skan { 2105169689Skan { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 210690075Sobrien { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 2107169689Skan { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 210890075Sobrien { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 210990075Sobrien { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 211090075Sobrien { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 211190075Sobrien } 2112169689Skan}; 2113169689Skan 2114169689Skanstruct iwn_sensitivity_limits { 2115260311Spfg uint32_t min_ofdm_x1; 2116132718Skan uint32_t max_ofdm_x1; 2117260311Spfg uint32_t min_ofdm_mrc_x1; 2118260311Spfg uint32_t max_ofdm_mrc_x1; 2119260311Spfg uint32_t min_ofdm_x4; 2120260311Spfg uint32_t max_ofdm_x4; 2121260311Spfg uint32_t min_ofdm_mrc_x4; 2122260311Spfg uint32_t max_ofdm_mrc_x4; 2123260311Spfg uint32_t min_cck_x4; 2124260311Spfg uint32_t max_cck_x4; 2125260311Spfg uint32_t min_cck_mrc_x4; 2126260311Spfg uint32_t max_cck_mrc_x4; 2127260311Spfg uint32_t min_energy_cck; 2128260311Spfg uint32_t energy_cck; 2129260311Spfg uint32_t energy_ofdm; 2130260311Spfg uint32_t barker_mrc; 2131260311Spfg}; 2132260311Spfg 2133260311Spfg/* 2134260311Spfg * RX sensitivity limits (values obtained from the reference driver.) 2135260311Spfg */ 2136260311Spfgstatic const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 2137260311Spfg 105, 140, 2138260311Spfg 220, 270, 2139260311Spfg 85, 120, 2140260311Spfg 170, 210, 2141260311Spfg 125, 200, 2142260311Spfg 200, 400, 2143260311Spfg 97, 2144260311Spfg 100, 2145260311Spfg 100, 2146260311Spfg 390 2147260311Spfg}; 2148260311Spfg 2149260311Spfgstatic const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 2150260311Spfg 120, 120, /* min = max for performance bug in DSP. */ 2151260311Spfg 240, 240, /* min = max for performance bug in DSP. */ 2152260311Spfg 90, 120, 2153260311Spfg 170, 210, 2154260311Spfg 125, 200, 2155260311Spfg 170, 400, 2156260311Spfg 95, 2157260311Spfg 95, 2158260311Spfg 95, 2159260311Spfg 390 2160260311Spfg}; 2161260311Spfg 2162260311Spfgstatic const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 2163260311Spfg 105, 105, /* min = max for performance bug in DSP. */ 2164260311Spfg 220, 220, /* min = max for performance bug in DSP. */ 2165260311Spfg 90, 120, 2166260311Spfg 170, 210, 2167260311Spfg 125, 200, 2168260311Spfg 170, 400, 2169260311Spfg 95, 2170260311Spfg 95, 2171132718Skan 95, 2172132718Skan 390, 2173132718Skan}; 2174132718Skan 2175132718Skanstatic const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 2176132718Skan 120, 155, 2177132718Skan 240, 290, 2178132718Skan 90, 120, 2179132718Skan 170, 210, 2180169689Skan 125, 200, 2181132718Skan 170, 400, 2182132718Skan 95, 218390075Sobrien 95, 218490075Sobrien 95, 218590075Sobrien 390, 218690075Sobrien}; 2187132718Skan 2188132718Skanstatic const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 2189132718Skan 105, 110, 2190260014Spfg 192, 232, 2191260014Spfg 80, 145, 2192260014Spfg 128, 232, 2193260014Spfg 125, 175, 2194260014Spfg 160, 310, 2195103445Skan 97, 2196103445Skan 97, 219790075Sobrien 100, 219890075Sobrien 390 2199169689Skan}; 2200169689Skan 2201169689Skanstatic const struct iwn_sensitivity_limits iwn6235_sensitivity_limits = { 2202169689Skan 105, 110, 2203169689Skan 192, 232, 2204169689Skan 80, 145, 2205169689Skan 128, 232, 2206169689Skan 125, 175, 2207169689Skan 160, 310, 2208169689Skan 100, 220990075Sobrien 110, 221090075Sobrien 110, 2211169689Skan 336 221290075Sobrien}; 221390075Sobrien 2214169689Skan 221590075Sobrien/* Get value from linux kernel 3.2.+ in Drivers/net/wireless/iwlwifi/iwl-2000.c*/ 2216117395Skanstatic const struct iwn_sensitivity_limits iwn2030_sensitivity_limits = { 2217132718Skan 105,110, 2218117395Skan 128,232, 2219117395Skan 80,145, 2220117395Skan 128,232, 2221117395Skan 125,175, 2222117395Skan 160,310, 2223132718Skan 97, 2224117395Skan 97, 2225117395Skan 110 2226117395Skan}; 2227189824Sdas 2228189824Sdas/* Map TID to TX scheduler's FIFO. */ 2229189824Sdasstatic const uint8_t iwn_tid2fifo[] = { 2230189824Sdas 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 2231189824Sdas}; 2232189824Sdas 2233189824Sdas/* WiFi/WiMAX coexist event priority table for 6050. */ 2234189824Sdasstatic const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 2235189824Sdas { 0x04, 0x03, 0x00, 0x00 }, 2236189824Sdas { 0x04, 0x03, 0x00, 0x03 }, 2237189824Sdas { 0x04, 0x03, 0x00, 0x03 }, 2238189824Sdas { 0x04, 0x03, 0x00, 0x03 }, 2239189824Sdas { 0x04, 0x03, 0x00, 0x00 }, 224090075Sobrien { 0x04, 0x03, 0x00, 0x07 }, 224190075Sobrien { 0x04, 0x03, 0x00, 0x00 }, 224290075Sobrien { 0x04, 0x03, 0x00, 0x03 }, 224390075Sobrien { 0x04, 0x03, 0x00, 0x03 }, 2244169689Skan { 0x04, 0x03, 0x00, 0x00 }, 2245169689Skan { 0x06, 0x03, 0x00, 0x07 }, 2246169689Skan { 0x04, 0x03, 0x00, 0x00 }, 2247169689Skan { 0x06, 0x06, 0x00, 0x03 }, 2248169689Skan { 0x04, 0x03, 0x00, 0x07 }, 2249169689Skan { 0x04, 0x03, 0x00, 0x00 }, 2250169689Skan { 0x04, 0x03, 0x00, 0x00 } 2251169689Skan}; 2252169689Skan 2253169689Skan/* Firmware errors. */ 2254169689Skanstatic const char * const iwn_fw_errmsg[] = { 2255169689Skan "OK", 2256169689Skan "FAIL", 2257169689Skan "BAD_PARAM", 2258169689Skan "BAD_CHECKSUM", 2259169689Skan "NMI_INTERRUPT_WDG", 2260169689Skan "SYSASSERT", 2261169689Skan "FATAL_ERROR", 2262169689Skan "BAD_COMMAND", 2263169689Skan "HW_ERROR_TUNE_LOCK", 2264169689Skan "HW_ERROR_TEMPERATURE", 2265169689Skan "ILLEGAL_CHAN_FREQ", 2266169689Skan "VCC_NOT_STABLE", 2267169689Skan "FH_ERROR", 2268169689Skan "NMI_INTERRUPT_HOST", 2269169689Skan "NMI_INTERRUPT_ACTION_PT", 2270169689Skan "NMI_INTERRUPT_UNKNOWN", 2271169689Skan "UCODE_VERSION_MISMATCH", 2272169689Skan "HW_ERROR_ABS_LOCK", 2273169689Skan "HW_ERROR_CAL_LOCK_FAIL", 2274169689Skan "NMI_INTERRUPT_INST_ACTION_PT", 2275169689Skan "NMI_INTERRUPT_DATA_ACTION_PT", 2276169689Skan "NMI_TRM_HW_ER", 2277169689Skan "NMI_INTERRUPT_TRM", 2278169689Skan "NMI_INTERRUPT_BREAKPOINT", 2279169689Skan "DEBUG_0", 2280169689Skan "DEBUG_1", 2281169689Skan "DEBUG_2", 2282169689Skan "DEBUG_3", 2283169689Skan "ADVANCED_SYSASSERT" 2284169689Skan}; 2285169689Skan 2286169689Skan/* Find least significant bit that is set. */ 2287169689Skan#define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 2288169689Skan 2289169689Skan#define IWN_READ(sc, reg) \ 2290169689Skan bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 2291169689Skan 2292169689Skan#define IWN_WRITE(sc, reg, val) \ 2293169689Skan bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 2294169689Skan 2295169689Skan#define IWN_WRITE_1(sc, reg, val) \ 2296169689Skan bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 2297169689Skan 2298169689Skan#define IWN_SETBITS(sc, reg, mask) \ 2299169689Skan IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 2300169689Skan 2301169689Skan#define IWN_CLRBITS(sc, reg, mask) \ 2302169689Skan IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 2303169689Skan 2304169689Skan#define IWN_BARRIER_WRITE(sc) \ 2305169689Skan bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2306169689Skan BUS_SPACE_BARRIER_WRITE) 2307169689Skan 2308169689Skan#define IWN_BARRIER_READ_WRITE(sc) \ 2309169689Skan bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2310169689Skan BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 2311169689Skan 2312169689Skan#endif /* __IF_IWNREG_H__ */ 2313169689Skan