if_iwnreg.h revision 257880
1/* $FreeBSD: head/sys/dev/iwn/if_iwnreg.h 257880 2013-11-09 06:30:09Z adrian $ */ 2/* $OpenBSD: if_iwnreg.h,v 1.40 2010/05/05 19:41:57 damien Exp $ */ 3 4/*- 5 * Copyright (c) 2007, 2008 6 * Damien Bergamini <damien.bergamini@free.fr> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20#ifndef __IF_IWNREG_H__ 21#define __IF_IWNREG_H__ 22 23#define IWN_CT_KILL_THRESHOLD 114 /* in Celsius */ 24#define IWN_CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */ 25 26#define IWN_TX_RING_COUNT 256 27#define IWN_TX_RING_LOMARK 192 28#define IWN_TX_RING_HIMARK 224 29#define IWN_RX_RING_COUNT_LOG 6 30#define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 31 32#define IWN4965_NTXQUEUES 16 33#define IWN5000_NTXQUEUES 20 34 35#define IWN4965_FIRSTAGGQUEUE 7 36#define IWN5000_FIRSTAGGQUEUE 10 37 38#define IWN4965_NDMACHNLS 7 39#define IWN5000_NDMACHNLS 8 40 41#define IWN_SRVC_DMACHNL 9 42 43#define IWN_ICT_SIZE 4096 44#define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 45 46/* For cards with PAN command, default is IWN_CMD_QUEUE_NUM */ 47#define IWN_CMD_QUEUE_NUM 4 48#define IWN_PAN_CMD_QUEUE 9 49 50/* Maximum number of DMA segments for TX. */ 51#define IWN_MAX_SCATTER 20 52 53/* RX buffers must be large enough to hold a full 4K A-MPDU. */ 54#define IWN_RBUF_SIZE (4 * 1024) 55 56#if defined(__LP64__) 57/* HW supports 36-bit DMA addresses. */ 58#define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 59#define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 60#else 61#define IWN_LOADDR(paddr) (paddr) 62#define IWN_HIADDR(paddr) (0) 63#endif 64 65/* 66 * Control and status registers. 67 */ 68#define IWN_HW_IF_CONFIG 0x000 69#define IWN_INT_COALESCING 0x004 70#define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 71#define IWN_INT 0x008 72#define IWN_INT_MASK 0x00c 73#define IWN_FH_INT 0x010 74#define IWN_GPIO_IN 0x018 /* read external chip pins */ 75#define IWN_RESET 0x020 76#define IWN_GP_CNTRL 0x024 77#define IWN_HW_REV 0x028 78#define IWN_EEPROM 0x02c 79#define IWN_EEPROM_GP 0x030 80#define IWN_OTP_GP 0x034 81#define IWN_GIO 0x03c 82#define IWN_GP_UCODE 0x048 83#define IWN_GP_DRIVER 0x050 84#define IWN_UCODE_GP1 0x054 85#define IWN_UCODE_GP1_SET 0x058 86#define IWN_UCODE_GP1_CLR 0x05c 87#define IWN_UCODE_GP2 0x060 88#define IWN_LED 0x094 89#define IWN_DRAM_INT_TBL 0x0a0 90#define IWN_SHADOW_REG_CTRL 0x0a8 91#define IWN_GIO_CHICKEN 0x100 92#define IWN_ANA_PLL 0x20c 93#define IWN_HW_REV_WA 0x22c 94#define IWN_DBG_HPET_MEM 0x240 95#define IWN_DBG_LINK_PWR_MGMT 0x250 96/* Need nic_lock for use above */ 97#define IWN_MEM_RADDR 0x40c 98#define IWN_MEM_WADDR 0x410 99#define IWN_MEM_WDATA 0x418 100#define IWN_MEM_RDATA 0x41c 101#define IWN_TARG_MBX_C 0x430 102#define IWN_PRPH_WADDR 0x444 103#define IWN_PRPH_RADDR 0x448 104#define IWN_PRPH_WDATA 0x44c 105#define IWN_PRPH_RDATA 0x450 106#define IWN_HBUS_TARG_WRPTR 0x460 107 108/* 109 * Flow-Handler registers. 110 */ 111#define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 112#define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 113#define IWN_FH_KW_ADDR 0x197c 114#define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 115#define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 116#define IWN_FH_STATUS_WPTR 0x1bc0 117#define IWN_FH_RX_BASE 0x1bc4 118#define IWN_FH_RX_WPTR 0x1bc8 119#define IWN_FH_RX_CONFIG 0x1c00 120#define IWN_FH_RX_STATUS 0x1c44 121#define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 122#define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 123#define IWN_FH_TX_CHICKEN 0x1e98 124#define IWN_FH_TX_STATUS 0x1eb0 125 126/* 127 * TX scheduler registers. 128 */ 129#define IWN_SCHED_BASE 0xa02c00 130#define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 131#define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 132#define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 133#define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 134#define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 135#define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 136#define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 137#define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 138#define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 139#define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 140#define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 141#define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 142#define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 143#define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 144 145/* 146 * Offsets in TX scheduler's SRAM. 147 */ 148#define IWN4965_SCHED_CTX_OFF 0x380 149#define IWN4965_SCHED_CTX_LEN 416 150#define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 151#define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 152#define IWN5000_SCHED_CTX_OFF 0x600 153#define IWN5000_SCHED_CTX_LEN 520 154#define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 155#define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 156 157/* 158 * NIC internal memory offsets. 159 */ 160#define IWN_APMG_CLK_CTRL 0x3000 161#define IWN_APMG_CLK_EN 0x3004 162#define IWN_APMG_CLK_DIS 0x3008 163#define IWN_APMG_PS 0x300c 164#define IWN_APMG_DIGITAL_SVR 0x3058 165#define IWN_APMG_ANALOG_SVR 0x306c 166#define IWN_APMG_PCI_STT 0x3010 167#define IWN_BSM_WR_CTRL 0x3400 168#define IWN_BSM_WR_MEM_SRC 0x3404 169#define IWN_BSM_WR_MEM_DST 0x3408 170#define IWN_BSM_WR_DWCOUNT 0x340c 171#define IWN_BSM_DRAM_TEXT_ADDR 0x3490 172#define IWN_BSM_DRAM_TEXT_SIZE 0x3494 173#define IWN_BSM_DRAM_DATA_ADDR 0x3498 174#define IWN_BSM_DRAM_DATA_SIZE 0x349c 175#define IWN_BSM_SRAM_BASE 0x3800 176 177/* Possible flags for register IWN_HW_IF_CONFIG. */ 178#define IWN_HW_IF_CONFIG_4965_R (1 << 4) 179#define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 180#define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 181#define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 182#define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 183#define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 184#define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 185#define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 186 187/* Possible values for register IWN_INT_PERIODIC. */ 188#define IWN_INT_PERIODIC_DIS 0x00 189#define IWN_INT_PERIODIC_ENA 0xff 190 191/* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 192#define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 193 194/* Possible values for IWN_BSM_WR_MEM_DST. */ 195#define IWN_FW_TEXT_BASE 0x00000000 196#define IWN_FW_DATA_BASE 0x00800000 197 198/* Possible flags for register IWN_RESET. */ 199#define IWN_RESET_NEVO (1 << 0) 200#define IWN_RESET_SW (1 << 7) 201#define IWN_RESET_MASTER_DISABLED (1 << 8) 202#define IWN_RESET_STOP_MASTER (1 << 9) 203#define IWN_RESET_LINK_PWR_MGMT_DIS (1 << 31) 204 205/* Possible flags for register IWN_GP_CNTRL. */ 206#define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 207#define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 208#define IWN_GP_CNTRL_INIT_DONE (1 << 2) 209#define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 210#define IWN_GP_CNTRL_SLEEP (1 << 4) 211#define IWN_GP_CNTRL_RFKILL (1 << 27) 212 213/* Possible flags for register IWN_GIO_CHICKEN. */ 214#define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 215#define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 216 217/* Possible flags for register IWN_GIO. */ 218#define IWN_GIO_L0S_ENA (1 << 1) 219 220/* Possible flags for register IWN_GP_DRIVER. */ 221#define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 222#define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 223#define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 224#define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 225#define IWN_GP_DRIVER_6050_1X2 (1 << 3) 226#define IWN_GP_DRIVER_REG_BIT_RADIO_IQ_INVERT (1 << 7) 227#define IWN_GP_DRIVER_NONE 0 228 229/* Possible flags for register IWN_UCODE_GP1_CLR. */ 230#define IWN_UCODE_GP1_RFKILL (1 << 1) 231#define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 232#define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 233#define IWN_UCODE_GP1_CFG_COMPLETE (1 << 5) 234 235/* Possible flags/values for register IWN_LED. */ 236#define IWN_LED_BSM_CTRL (1 << 5) 237#define IWN_LED_OFF 0x00000038 238#define IWN_LED_ON 0x00000078 239 240#define IWN_MAX_BLINK_TBL 10 241#define IWN_LED_STATIC_ON 0 242#define IWN_LED_STATIC_OFF 1 243#define IWN_LED_SLOW_BLINK 2 244#define IWN_LED_INT_BLINK 3 245#define IWN_LED_UNIT 0x1388 /* 5 ms */ 246 247static const struct { 248 uint16_t tpt; /* Mb/s */ 249 uint8_t on_time; 250 uint8_t off_time; 251} blink_tbl[] = 252{ 253 {300, 5, 5}, 254 {200, 8, 8}, 255 {100, 11, 11}, 256 {70, 13, 13}, 257 {50, 15, 15}, 258 {20, 17, 17}, 259 {10, 19, 19}, 260 {5, 22, 22}, 261 {1, 26, 26}, 262 {0, 33, 33}, 263 /* SOLID_ON */ 264}; 265 266/* Possible flags for register IWN_DRAM_INT_TBL. */ 267#define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) 268#define IWN_DRAM_INT_TBL_ENABLE (1 << 31) 269 270/* Possible values for register IWN_ANA_PLL. */ 271#define IWN_ANA_PLL_INIT 0x00880300 272 273/* Possible flags for register IWN_FH_RX_STATUS. */ 274#define IWN_FH_RX_STATUS_IDLE (1 << 24) 275 276/* Possible flags for register IWN_BSM_WR_CTRL. */ 277#define IWN_BSM_WR_CTRL_START_EN (1 << 30) 278#define IWN_BSM_WR_CTRL_START (1 << 31) 279 280/* Possible flags for register IWN_INT. */ 281#define IWN_INT_ALIVE (1 << 0) 282#define IWN_INT_WAKEUP (1 << 1) 283#define IWN_INT_SW_RX (1 << 3) 284#define IWN_INT_CT_REACHED (1 << 6) 285#define IWN_INT_RF_TOGGLED (1 << 7) 286#define IWN_INT_SW_ERR (1 << 25) 287#define IWN_INT_SCHED (1 << 26) 288#define IWN_INT_FH_TX (1 << 27) 289#define IWN_INT_RX_PERIODIC (1 << 28) 290#define IWN_INT_HW_ERR (1 << 29) 291#define IWN_INT_FH_RX (1 << 31) 292 293/* Shortcut. */ 294#define IWN_INT_MASK_DEF \ 295 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 296 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 297 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 298 299/* Possible flags for register IWN_FH_INT. */ 300#define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 301#define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 302#define IWN_FH_INT_HI_PRIOR (1 << 30) 303/* Shortcuts for the above. */ 304#define IWN_FH_INT_TX \ 305 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 306#define IWN_FH_INT_RX \ 307 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 308 309/* Possible flags/values for register IWN_FH_TX_CONFIG. */ 310#define IWN_FH_TX_CONFIG_DMA_PAUSE 0 311#define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 312#define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20) 313 314/* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 315#define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 316#define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 317#define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 318 319/* Possible flags for register IWN_FH_TX_CHICKEN. */ 320#define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 321 322/* Possible flags for register IWN_FH_TX_STATUS. */ 323#define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16)) 324 325/* Possible flags for register IWN_FH_RX_CONFIG. */ 326#define IWN_FH_RX_CONFIG_ENA (1 << 31) 327#define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 328#define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16) 329#define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15) 330#define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 331#define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 332#define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2) 333 334/* Possible flags for register IWN_FH_TX_CONFIG. */ 335#define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 336#define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3) 337 338/* Possible flags for register IWN_EEPROM. */ 339#define IWN_EEPROM_READ_VALID (1 << 0) 340#define IWN_EEPROM_CMD (1 << 1) 341 342/* Possible flags for register IWN_EEPROM_GP. */ 343#define IWN_EEPROM_GP_IF_OWNER 0x00000180 344 345/* Possible flags for register IWN_OTP_GP. */ 346#define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 347#define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 348#define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 349#define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 350 351/* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 352#define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 353#define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 354#define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 355#define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 356#define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 357#define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 358#define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 359 360/* Possible flags for registers IWN_APMG_CLK_*. */ 361#define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 362#define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 363 364/* Possible flags for register IWN_APMG_PS. */ 365#define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 366#define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 367#define IWN_APMG_PS_PWR_SRC_VMAIN 0 368#define IWN_APMG_PS_PWR_SRC_VAUX 2 369#define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 370#define IWN_APMG_PS_RESET_REQ (1 << 26) 371 372/* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 373#define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 374#define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 375 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 376#define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 377 IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 378 379/* Possible flags for IWN_APMG_PCI_STT. */ 380#define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 381 382/* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 383#define IWN_FW_UPDATED (1 << 31) 384 385#define IWN_SCHED_WINSZ 64 386#define IWN_SCHED_LIMIT 64 387#define IWN4965_SCHED_COUNT 512 388#define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 389#define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 390#define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 391 392struct iwn_tx_desc { 393 uint8_t reserved1[3]; 394 uint8_t nsegs; 395 struct { 396 uint32_t addr; 397 uint16_t len; 398 } __packed segs[IWN_MAX_SCATTER]; 399 /* Pad to 128 bytes. */ 400 uint32_t reserved2; 401} __packed; 402 403struct iwn_rx_status { 404 uint16_t closed_count; 405 uint16_t closed_rx_count; 406 uint16_t finished_count; 407 uint16_t finished_rx_count; 408 uint32_t reserved[2]; 409} __packed; 410 411struct iwn_rx_desc { 412 /* 413 * The first 4 bytes of the RX frame header contain both the RX frame 414 * size and some flags. 415 * Bit fields: 416 * 31: flag flush RB request 417 * 30: flag ignore TC (terminal counter) request 418 * 29: flag fast IRQ request 419 * 28-14: Reserved 420 * 13-00: RX frame size 421 */ 422 uint32_t len; 423 uint8_t type; 424#define IWN_UC_READY 1 425#define IWN_ADD_NODE_DONE 24 426#define IWN_TX_DONE 28 427#define IWN_REPLY_LED_CMD 72 428#define IWN5000_CALIBRATION_RESULT 102 429#define IWN5000_CALIBRATION_DONE 103 430#define IWN_START_SCAN 130 431#define IWN_NOTIF_SCAN_RESULT 131 432#define IWN_STOP_SCAN 132 433#define IWN_RX_STATISTICS 156 434#define IWN_BEACON_STATISTICS 157 435#define IWN_STATE_CHANGED 161 436#define IWN_BEACON_MISSED 162 437#define IWN_RX_PHY 192 438#define IWN_MPDU_RX_DONE 193 439#define IWN_RX_DONE 195 440#define IWN_RX_COMPRESSED_BA 197 441 442 uint8_t flags; /* 0:5 reserved, 6 abort, 7 internal */ 443 uint8_t idx; /* position within TX queue */ 444 uint8_t qid; 445 /* 0:4 TX queue id - 5:6 reserved - 7 unsolicited RX 446 * or uCode-originated notification 447 */ 448} __packed; 449 450#define IWN_RX_DESC_QID_MSK 0x1F 451#define IWN_UNSOLICITED_RX_NOTIF 0x80 452 453/* CARD_STATE_NOTIFICATION */ 454#define IWN_STATE_CHANGE_HW_CARD_DISABLED 0x01 455#define IWN_STATE_CHANGE_SW_CARD_DISABLED 0x02 456#define IWN_STATE_CHANGE_CT_CARD_DISABLED 0x04 457#define IWN_STATE_CHANGE_RXON_CARD_DISABLED 0x10 458 459/* Possible RX status flags. */ 460#define IWN_RX_NO_CRC_ERR (1 << 0) 461#define IWN_RX_NO_OVFL_ERR (1 << 1) 462/* Shortcut for the above. */ 463#define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 464#define IWN_RX_MPDU_MIC_OK (1 << 6) 465#define IWN_RX_CIPHER_MASK (7 << 8) 466#define IWN_RX_CIPHER_CCMP (2 << 8) 467#define IWN_RX_MPDU_DEC (1 << 11) 468#define IWN_RX_DECRYPT_MASK (3 << 11) 469#define IWN_RX_DECRYPT_OK (3 << 11) 470 471struct iwn_tx_cmd { 472 uint8_t code; 473#define IWN_CMD_RXON 16 474#define IWN_CMD_RXON_ASSOC 17 475#define IWN_CMD_EDCA_PARAMS 19 476#define IWN_CMD_TIMING 20 477#define IWN_CMD_ADD_NODE 24 478#define IWN_CMD_TX_DATA 28 479#define IWN_CMD_LINK_QUALITY 78 480#define IWN_CMD_SET_LED 72 481#define IWN5000_CMD_WIMAX_COEX 90 482#define IWN_TEMP_NOTIFICATION 98 483#define IWN5000_CMD_CALIB_CONFIG 101 484#define IWN5000_CMD_CALIB_RESULT 102 485#define IWN5000_CMD_CALIB_COMPLETE 103 486#define IWN_CMD_SET_POWER_MODE 119 487#define IWN_CMD_SCAN 128 488#define IWN_CMD_SCAN_RESULTS 131 489#define IWN_CMD_TXPOWER_DBM 149 490#define IWN_CMD_TXPOWER 151 491#define IWN5000_CMD_TX_ANT_CONFIG 152 492#define IWN_CMD_BT_COEX 155 493#define IWN_CMD_GET_STATISTICS 156 494#define IWN_CMD_SET_CRITICAL_TEMP 164 495#define IWN_CMD_SET_SENSITIVITY 168 496#define IWN_CMD_PHY_CALIB 176 497#define IWN_CMD_BT_COEX_PRIOTABLE 204 498#define IWN_CMD_BT_COEX_PROT 205 499#define IWN_CMD_BT_COEX_NOTIF 206 500/* PAN commands */ 501#define IWN_CMD_WIPAN_PARAMS 0xb2 502#define IWN_CMD_WIPAN_RXON 0xb3 503#define IWN_CMD_WIPAN_RXON_TIMING 0xb4 504#define IWN_CMD_WIPAN_RXON_ASSOC 0xb6 505#define IWN_CMD_WIPAN_QOS_PARAM 0xb7 506#define IWN_CMD_WIPAN_WEPKEY 0xb8 507#define IWN_CMD_WIPAN_P2P_CHANNEL_SWITCH 0xb9 508#define IWN_CMD_WIPAN_NOA_NOTIFICATION 0xbc 509#define IWN_CMD_WIPAN_DEACTIVATION_COMPLETE 0xbd 510 511 uint8_t flags; 512 uint8_t idx; 513 uint8_t qid; 514 uint8_t data[136]; 515} __packed; 516 517/* 518 * Structure for IWN_CMD_GET_STATISTICS = (0x9c) 156 519 * all devices identical. 520 * 521 * This command triggers an immediate response containing uCode statistics. 522 * The response is in the same format as IWN_BEACON_STATISTICS (0x9d) 157. 523 * 524 * If the CLEAR_STATS configuration flag is set, uCode will clear its 525 * internal copy of the statistics (counters) after issuing the response. 526 * This flag does not affect IWN_BEACON_STATISTICS after beacons (see below). 527 * 528 * If the DISABLE_NOTIF configuration flag is set, uCode will not issue 529 * IWN_BEACON_STATISTICS after received beacons. This flag 530 * does not affect the response to the IWN_CMD_GET_STATISTICS 0x9c itself. 531 */ 532struct iwn_statistics_cmd { 533 uint32_t configuration_flags; 534#define IWN_STATS_CONF_CLEAR_STATS htole32(0x1) 535#define IWN_STATS_CONF_DISABLE_NOTIF htole32(0x2) 536} __packed; 537 538/* Antenna flags, used in various commands. */ 539#define IWN_ANT_A (1 << 0) 540#define IWN_ANT_B (1 << 1) 541#define IWN_ANT_C (1 << 2) 542/* Shortcuts. */ 543#define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 544#define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 545#define IWN_ANT_AC (IWN_ANT_A | IWN_ANT_C) 546#define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 547 548/* Structure for command IWN_CMD_RXON. */ 549struct iwn_rxon { 550 uint8_t myaddr[IEEE80211_ADDR_LEN]; 551 uint16_t reserved1; 552 uint8_t bssid[IEEE80211_ADDR_LEN]; 553 uint16_t reserved2; 554 uint8_t wlap[IEEE80211_ADDR_LEN]; 555 uint16_t reserved3; 556 uint8_t mode; 557#define IWN_MODE_HOSTAP 1 558#define IWN_MODE_STA 3 559#define IWN_MODE_IBSS 4 560#define IWN_MODE_MONITOR 6 561#define IWN_MODE_2STA 8 562#define IWN_MODE_P2P 9 563 564 uint8_t air; 565 uint16_t rxchain; 566#define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 567#define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 568#define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 569#define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 570#define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 571#define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 572#define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 573 574 uint8_t ofdm_mask; 575 uint8_t cck_mask; 576 uint16_t associd; 577 uint32_t flags; 578#define IWN_RXON_24GHZ (1 << 0) 579#define IWN_RXON_CCK (1 << 1) 580#define IWN_RXON_AUTO (1 << 2) 581#define IWN_RXON_SHSLOT (1 << 4) 582#define IWN_RXON_SHPREAMBLE (1 << 5) 583#define IWN_RXON_NODIVERSITY (1 << 7) 584#define IWN_RXON_ANTENNA_A (1 << 8) 585#define IWN_RXON_ANTENNA_B (1 << 9) 586#define IWN_RXON_TSF (1 << 15) 587#define IWN_RXON_HT_HT40MINUS (1 << 22) 588#define IWN_RXON_HT_PROTMODE(x) (x << 23) 589#define IWN_RXON_HT_MODEPURE40 (1 << 25) 590#define IWN_RXON_HT_MODEMIXED (2 << 25) 591#define IWN_RXON_CTS_TO_SELF (1 << 30) 592 593 uint32_t filter; 594#define IWN_FILTER_PROMISC (1 << 0) 595#define IWN_FILTER_CTL (1 << 1) 596#define IWN_FILTER_MULTICAST (1 << 2) 597#define IWN_FILTER_NODECRYPT (1 << 3) 598#define IWN_FILTER_BSS (1 << 5) 599#define IWN_FILTER_BEACON (1 << 6) 600 601 uint8_t chan; 602 uint8_t reserved4; 603 uint8_t ht_single_mask; 604 uint8_t ht_dual_mask; 605 /* The following fields are for >=5000 Series only. */ 606 uint8_t ht_triple_mask; 607 uint8_t reserved5; 608 uint16_t acquisition; 609 uint16_t reserved6; 610} __packed; 611 612#define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 613#define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 614 615/* Structure for command IWN_CMD_ASSOCIATE. */ 616struct iwn_assoc { 617 uint32_t flags; 618 uint32_t filter; 619 uint8_t ofdm_mask; 620 uint8_t cck_mask; 621 uint16_t reserved; 622} __packed; 623 624/* Structure for command IWN_CMD_EDCA_PARAMS. */ 625struct iwn_edca_params { 626 uint32_t flags; 627#define IWN_EDCA_UPDATE (1 << 0) 628#define IWN_EDCA_TXOP (1 << 4) 629 630 struct { 631 uint16_t cwmin; 632 uint16_t cwmax; 633 uint8_t aifsn; 634 uint8_t reserved; 635 uint16_t txoplimit; 636 } __packed ac[WME_NUM_AC]; 637} __packed; 638 639/* Structure for command IWN_CMD_TIMING. */ 640struct iwn_cmd_timing { 641 uint64_t tstamp; 642 uint16_t bintval; 643 uint16_t atim; 644 uint32_t binitval; 645 uint16_t lintval; 646 uint8_t dtim_period; 647 uint8_t delta_cp_bss_tbtts; 648} __packed; 649 650/* Structure for command IWN_CMD_ADD_NODE. */ 651struct iwn_node_info { 652 uint8_t control; 653#define IWN_NODE_UPDATE (1 << 0) 654 655 uint8_t reserved1[3]; 656 657 uint8_t macaddr[IEEE80211_ADDR_LEN]; 658 uint16_t reserved2; 659 uint8_t id; 660#define IWN_ID_BSS 0 661#define IWN_STA_ID 1 662 663#define IWN_PAN_ID_BCAST 14 664#define IWN5000_ID_BROADCAST 15 665#define IWN4965_ID_BROADCAST 31 666 667 uint8_t flags; 668#define IWN_FLAG_SET_KEY (1 << 0) 669#define IWN_FLAG_SET_DISABLE_TID (1 << 1) 670#define IWN_FLAG_SET_TXRATE (1 << 2) 671#define IWN_FLAG_SET_ADDBA (1 << 3) 672#define IWN_FLAG_SET_DELBA (1 << 4) 673 674 uint16_t reserved3; 675 uint16_t kflags; 676#define IWN_KFLAG_CCMP (1 << 1) 677#define IWN_KFLAG_MAP (1 << 3) 678#define IWN_KFLAG_KID(kid) ((kid) << 8) 679#define IWN_KFLAG_INVALID (1 << 11) 680#define IWN_KFLAG_GROUP (1 << 14) 681 682 uint8_t tsc2; /* TKIP TSC2 */ 683 uint8_t reserved4; 684 uint16_t ttak[5]; 685 uint8_t kid; 686 uint8_t reserved5; 687 uint8_t key[16]; 688 /* The following 3 fields are for 5000 Series only. */ 689 uint64_t tsc; 690 uint8_t rxmic[8]; 691 uint8_t txmic[8]; 692 693 uint32_t htflags; 694#define IWN_SMPS_MIMO_PROT (1 << 17) 695#define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 696#define IWN_NODE_HT40 (1 << 21) 697#define IWN_SMPS_MIMO_DIS (1 << 22) 698#define IWN_AMDPU_DENSITY(x) ((x) << 23) 699 700 uint32_t mask; 701 uint16_t disable_tid; 702 uint16_t reserved6; 703 uint8_t addba_tid; 704 uint8_t delba_tid; 705 uint16_t addba_ssn; 706 uint32_t reserved7; 707} __packed; 708 709struct iwn4965_node_info { 710 uint8_t control; 711 uint8_t reserved1[3]; 712 uint8_t macaddr[IEEE80211_ADDR_LEN]; 713 uint16_t reserved2; 714 uint8_t id; 715 uint8_t flags; 716 uint16_t reserved3; 717 uint16_t kflags; 718 uint8_t tsc2; /* TKIP TSC2 */ 719 uint8_t reserved4; 720 uint16_t ttak[5]; 721 uint8_t kid; 722 uint8_t reserved5; 723 uint8_t key[16]; 724 uint32_t htflags; 725 uint32_t mask; 726 uint16_t disable_tid; 727 uint16_t reserved6; 728 uint8_t addba_tid; 729 uint8_t delba_tid; 730 uint16_t addba_ssn; 731 uint32_t reserved7; 732} __packed; 733 734#define IWN_RFLAG_MCS (1 << 8) 735#define IWN_RFLAG_CCK (1 << 9) 736#define IWN_RFLAG_GREENFIELD (1 << 10) 737#define IWN_RFLAG_HT40 (1 << 11) 738#define IWN_RFLAG_DUPLICATE (1 << 12) 739#define IWN_RFLAG_SGI (1 << 13) 740#define IWN_RFLAG_ANT(x) ((x) << 14) 741 742/* Structure for command IWN_CMD_TX_DATA. */ 743struct iwn_cmd_data { 744 uint16_t len; 745 uint16_t lnext; 746 uint32_t flags; 747#define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 748#define IWN_TX_NEED_RTS (1 << 1) 749#define IWN_TX_NEED_CTS (1 << 2) 750#define IWN_TX_NEED_ACK (1 << 3) 751#define IWN_TX_LINKQ (1 << 4) 752#define IWN_TX_IMM_BA (1 << 6) 753#define IWN_TX_FULL_TXOP (1 << 7) 754#define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 755#define IWN_TX_AUTO_SEQ (1 << 13) 756#define IWN_TX_MORE_FRAG (1 << 14) 757#define IWN_TX_INSERT_TSTAMP (1 << 16) 758#define IWN_TX_NEED_PADDING (1 << 20) 759 760 uint32_t scratch; 761 uint32_t rate; 762 763 uint8_t id; 764 uint8_t security; 765#define IWN_CIPHER_WEP40 1 766#define IWN_CIPHER_CCMP 2 767#define IWN_CIPHER_TKIP 3 768#define IWN_CIPHER_WEP104 9 769 770 uint8_t linkq; 771 uint8_t reserved2; 772 uint8_t key[16]; 773 uint16_t fnext; 774 uint16_t reserved3; 775 uint32_t lifetime; 776#define IWN_LIFETIME_INFINITE 0xffffffff 777 778 uint32_t loaddr; 779 uint8_t hiaddr; 780 uint8_t rts_ntries; 781 uint8_t data_ntries; 782 uint8_t tid; 783 uint16_t timeout; 784 uint16_t txop; 785} __packed; 786 787/* Structure for command IWN_CMD_LINK_QUALITY. */ 788#define IWN_MAX_TX_RETRIES 16 789struct iwn_cmd_link_quality { 790 uint8_t id; 791 uint8_t reserved1; 792 uint16_t ctl; 793 uint8_t flags; 794 uint8_t mimo; 795 uint8_t antmsk_1stream; 796 uint8_t antmsk_2stream; 797 uint8_t ridx[WME_NUM_AC]; 798 uint16_t ampdu_limit; 799 uint8_t ampdu_threshold; 800 uint8_t ampdu_max; 801 uint32_t reserved2; 802 uint32_t retry[IWN_MAX_TX_RETRIES]; 803 uint32_t reserved3; 804} __packed; 805 806/* Structure for command IWN_CMD_SET_LED. */ 807struct iwn_cmd_led { 808 uint32_t unit; /* multiplier (in usecs) */ 809 uint8_t which; 810#define IWN_LED_ACTIVITY 1 811#define IWN_LED_LINK 2 812 813 uint8_t off; 814 uint8_t on; 815 uint8_t reserved; 816} __packed; 817 818/* Structure for command IWN5000_CMD_WIMAX_COEX. */ 819struct iwn5000_wimax_coex { 820 uint32_t flags; 821#define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 822#define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 823#define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 824#define IWN_WIMAX_COEX_ENABLE (1 << 7) 825 826 struct iwn5000_wimax_event { 827 uint8_t request; 828 uint8_t window; 829 uint8_t reserved; 830 uint8_t flags; 831 } __packed events[16]; 832} __packed; 833 834/* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 835struct iwn5000_calib_elem { 836 uint32_t enable; 837 uint32_t start; 838#define IWN5000_CALIB_DC (1 << 1) 839 840 uint32_t send; 841 uint32_t apply; 842 uint32_t reserved; 843} __packed; 844 845struct iwn5000_calib_status { 846 struct iwn5000_calib_elem once; 847 struct iwn5000_calib_elem perd; 848 uint32_t flags; 849} __packed; 850 851struct iwn5000_calib_config { 852 struct iwn5000_calib_status ucode; 853 struct iwn5000_calib_status driver; 854 uint32_t reserved; 855} __packed; 856 857/* Structure for command IWN_CMD_SET_POWER_MODE. */ 858struct iwn_pmgt_cmd { 859 uint16_t flags; 860#define IWN_PS_ALLOW_SLEEP (1 << 0) 861#define IWN_PS_NOTIFY (1 << 1) 862#define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 863#define IWN_PS_PCI_PMGT (1 << 3) 864#define IWN_PS_FAST_PD (1 << 4) 865#define IWN_PS_BEACON_FILTERING (1 << 5) 866#define IWN_PS_SHADOW_REG (1 << 6) 867#define IWN_PS_CT_KILL (1 << 7) 868#define IWN_PS_BT_SCD (1 << 8) 869#define IWN_PS_ADVANCED_PM (1 << 9) 870 871 uint8_t keepalive; 872 uint8_t debug; 873 uint32_t rxtimeout; 874 uint32_t txtimeout; 875 uint32_t intval[5]; 876 uint32_t beacons; 877} __packed; 878 879/* Structures for command IWN_CMD_SCAN. */ 880struct iwn_scan_essid { 881 uint8_t id; 882 uint8_t len; 883 uint8_t data[IEEE80211_NWID_LEN]; 884} __packed; 885 886struct iwn_scan_hdr { 887 uint16_t len; 888 uint8_t reserved1; 889 uint8_t nchan; 890 uint16_t quiet_time; 891 uint16_t quiet_threshold; 892 uint16_t crc_threshold; 893 uint16_t rxchain; 894 uint32_t max_svc; /* background scans */ 895 uint32_t pause_svc; /* background scans */ 896 uint32_t flags; 897 uint32_t filter; 898 899 /* Followed by a struct iwn_cmd_data. */ 900 /* Followed by an array of 20 structs iwn_scan_essid. */ 901 /* Followed by probe request body. */ 902 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 903} __packed; 904 905struct iwn_scan_chan { 906 uint32_t flags; 907#define IWN_CHAN_PASSIVE (0 << 0) 908#define IWN_CHAN_ACTIVE (1 << 0) 909#define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 910 911 uint16_t chan; 912 uint8_t rf_gain; 913 uint8_t dsp_gain; 914 uint16_t active; /* msecs */ 915 uint16_t passive; /* msecs */ 916} __packed; 917 918#define IWN_SCAN_CRC_TH_DISABLED 0 919#define IWN_SCAN_CRC_TH_DEFAULT htole16(1) 920#define IWN_SCAN_CRC_TH_NEVER htole16(0xffff) 921 922/* Maximum size of a scan command. */ 923#define IWN_SCAN_MAXSZ (MCLBYTES - 4) 924 925#define IWN_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */ 926#define IWN_ACTIVE_DWELL_TIME_52 (20) 927#define IWN_ACTIVE_DWELL_FACTOR_24 (3) 928#define IWN_ACTIVE_DWELL_FACTOR_52 (2) 929 930#define IWN_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */ 931#define IWN_PASSIVE_DWELL_TIME_52 (10) 932#define IWN_PASSIVE_DWELL_BASE (100) 933#define IWN_CHANNEL_TUNE_TIME (5) 934 935#define IWN_SCAN_CHAN_TIMEOUT 2 936 937/* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 938#define IWN_RIDX_MAX 32 939struct iwn4965_cmd_txpower { 940 uint8_t band; 941 uint8_t reserved1; 942 uint8_t chan; 943 uint8_t reserved2; 944 struct { 945 uint8_t rf_gain[2]; 946 uint8_t dsp_gain[2]; 947 } __packed power[IWN_RIDX_MAX + 1]; 948} __packed; 949 950/* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 951struct iwn5000_cmd_txpower { 952 int8_t global_limit; /* in half-dBm */ 953#define IWN5000_TXPOWER_AUTO 0x7f 954#define IWN5000_TXPOWER_MAX_DBM 16 955 956 uint8_t flags; 957#define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 958 959 int8_t srv_limit; /* in half-dBm */ 960 uint8_t reserved; 961} __packed; 962 963/* Structures for command IWN_CMD_BLUETOOTH. */ 964struct iwn_bluetooth { 965 uint8_t flags; 966#define IWN_BT_COEX_CHAN_ANN (1 << 0) 967#define IWN_BT_COEX_BT_PRIO (1 << 1) 968#define IWN_BT_COEX_2_WIRE (1 << 2) 969 970 uint8_t lead_time; 971#define IWN_BT_LEAD_TIME_DEF 30 972 973 uint8_t max_kill; 974#define IWN_BT_MAX_KILL_DEF 5 975 976 uint8_t reserved; 977 uint32_t kill_ack; 978 uint32_t kill_cts; 979} __packed; 980 981struct iwn6000_btcoex_config { 982 uint8_t flags; 983#define IWN_BT_FLAG_COEX6000_CHAN_INHIBITION 1 984#define IWN_BT_FLAG_COEX6000_MODE_MASK ((1 << 3) | (1 << 4) | (1 << 5 )) 985#define IWN_BT_FLAG_COEX6000_MODE_SHIFT 3 986#define IWN_BT_FLAG_COEX6000_MODE_DISABLED 0 987#define IWN_BT_FLAG_COEX6000_MODE_LEGACY_2W 1 988#define IWN_BT_FLAG_COEX6000_MODE_3W 2 989#define IWN_BT_FLAG_COEX6000_MODE_4W 3 990 991#define IWN_BT_FLAG_UCODE_DEFAULT (1 << 6) 992#define IWN_BT_FLAG_SYNC_2_BT_DISABLE (1 << 7) 993 uint8_t lead_time; 994 uint8_t max_kill; 995 uint8_t bt3_t7_timer; 996 uint32_t kill_ack; 997 uint32_t kill_cts; 998 uint8_t sample_time; 999 uint8_t bt3_t2_timer; 1000 uint16_t bt4_reaction; 1001 uint32_t lookup_table[12]; 1002 uint16_t bt4_decision; 1003 uint16_t valid; 1004 uint8_t prio_boost; 1005 uint8_t tx_prio_boost; 1006 uint16_t rx_prio_boost; 1007} __packed; 1008 1009/* Structure for enhanced command IWN_CMD_BLUETOOTH for 2000 Series. */ 1010struct iwn2000_btcoex_config { 1011 uint8_t flags; /* Cf Flags in iwn6000_btcoex_config */ 1012 uint8_t lead_time; 1013 uint8_t max_kill; 1014 uint8_t bt3_t7_timer; 1015 uint32_t kill_ack; 1016 uint32_t kill_cts; 1017 uint8_t sample_time; 1018 uint8_t bt3_t2_timer; 1019 uint16_t bt4_reaction; 1020 uint32_t lookup_table[12]; 1021 uint16_t bt4_decision; 1022 uint16_t valid; 1023 1024 uint32_t prio_boost; /* size change prior to iwn6000_btcoex_config */ 1025 uint8_t reserved; /* added prior to iwn6000_btcoex_config */ 1026 1027 uint8_t tx_prio_boost; 1028 uint16_t rx_prio_boost; 1029} __packed; 1030 1031struct iwn_btcoex_priotable { 1032 uint8_t calib_init1; 1033 uint8_t calib_init2; 1034 uint8_t calib_periodic_low1; 1035 uint8_t calib_periodic_low2; 1036 uint8_t calib_periodic_high1; 1037 uint8_t calib_periodic_high2; 1038 uint8_t dtim; 1039 uint8_t scan52; 1040 uint8_t scan24; 1041 uint8_t reserved[7]; 1042} __packed; 1043 1044struct iwn_btcoex_prot { 1045 uint8_t open; 1046 uint8_t type; 1047 uint8_t reserved[2]; 1048} __packed; 1049 1050/* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 1051struct iwn_critical_temp { 1052 uint32_t reserved; 1053 uint32_t tempM; 1054 uint32_t tempR; 1055/* degK <-> degC conversion macros. */ 1056#define IWN_CTOK(c) ((c) + 273) 1057#define IWN_KTOC(k) ((k) - 273) 1058#define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 1059} __packed; 1060 1061/* Structures for command IWN_CMD_SET_SENSITIVITY. */ 1062struct iwn_sensitivity_cmd { 1063 uint16_t which; 1064#define IWN_SENSITIVITY_DEFAULTTBL 0 1065#define IWN_SENSITIVITY_WORKTBL 1 1066 1067 uint16_t energy_cck; 1068 uint16_t energy_ofdm; 1069 uint16_t corr_ofdm_x1; 1070 uint16_t corr_ofdm_mrc_x1; 1071 uint16_t corr_cck_mrc_x4; 1072 uint16_t corr_ofdm_x4; 1073 uint16_t corr_ofdm_mrc_x4; 1074 uint16_t corr_barker; 1075 uint16_t corr_barker_mrc; 1076 uint16_t corr_cck_x4; 1077 uint16_t energy_ofdm_th; 1078} __packed; 1079 1080struct iwn_enhanced_sensitivity_cmd { 1081 uint16_t which; 1082 uint16_t energy_cck; 1083 uint16_t energy_ofdm; 1084 uint16_t corr_ofdm_x1; 1085 uint16_t corr_ofdm_mrc_x1; 1086 uint16_t corr_cck_mrc_x4; 1087 uint16_t corr_ofdm_x4; 1088 uint16_t corr_ofdm_mrc_x4; 1089 uint16_t corr_barker; 1090 uint16_t corr_barker_mrc; 1091 uint16_t corr_cck_x4; 1092 uint16_t energy_ofdm_th; 1093 /* "Enhanced" part. */ 1094 uint16_t ina_det_ofdm; 1095 uint16_t ina_det_cck; 1096 uint16_t corr_11_9_en; 1097 uint16_t ofdm_det_slope_mrc; 1098 uint16_t ofdm_det_icept_mrc; 1099 uint16_t ofdm_det_slope; 1100 uint16_t ofdm_det_icept; 1101 uint16_t cck_det_slope_mrc; 1102 uint16_t cck_det_icept_mrc; 1103 uint16_t cck_det_slope; 1104 uint16_t cck_det_icept; 1105 uint16_t reserved; 1106} __packed; 1107 1108/* 1109 * Define maximal number of calib result send to runtime firmware 1110 * PS: TEMP_OFFSET count for 2 (std and v2) 1111 */ 1112#define IWN5000_PHY_CALIB_MAX_RESULT 8 1113 1114/* Structures for command IWN_CMD_PHY_CALIB. */ 1115struct iwn_phy_calib { 1116 uint8_t code; 1117#define IWN4965_PHY_CALIB_DIFF_GAIN 7 1118#define IWN5000_PHY_CALIB_DC 8 1119#define IWN5000_PHY_CALIB_LO 9 1120#define IWN5000_PHY_CALIB_TX_IQ 11 1121#define IWN5000_PHY_CALIB_CRYSTAL 15 1122#define IWN5000_PHY_CALIB_BASE_BAND 16 1123#define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 1124#define IWN5000_PHY_CALIB_TEMP_OFFSET 18 1125 1126#define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 1127#define IWN5000_PHY_CALIB_NOISE_GAIN 19 1128 1129 uint8_t group; 1130 uint8_t ngroups; 1131 uint8_t isvalid; 1132} __packed; 1133 1134struct iwn5000_phy_calib_crystal { 1135 uint8_t code; 1136 uint8_t group; 1137 uint8_t ngroups; 1138 uint8_t isvalid; 1139 1140 uint8_t cap_pin[2]; 1141 uint8_t reserved[2]; 1142} __packed; 1143 1144struct iwn5000_phy_calib_temp_offset { 1145 uint8_t code; 1146 uint8_t group; 1147 uint8_t ngroups; 1148 uint8_t isvalid; 1149 int16_t offset; 1150#define IWN_DEFAULT_TEMP_OFFSET 2700 1151 1152 uint16_t reserved; 1153} __packed; 1154 1155struct iwn5000_phy_calib_temp_offsetv2 { 1156 uint8_t code; 1157 uint8_t group; 1158 uint8_t ngroups; 1159 uint8_t isvalid; 1160 int16_t offset_high; 1161 int16_t offset_low; 1162 int16_t burnt_voltage_ref; 1163 int16_t reserved; 1164} __packed; 1165 1166struct iwn_phy_calib_gain { 1167 uint8_t code; 1168 uint8_t group; 1169 uint8_t ngroups; 1170 uint8_t isvalid; 1171 1172 int8_t gain[3]; 1173 uint8_t reserved; 1174} __packed; 1175 1176/* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 1177struct iwn_spectrum_cmd { 1178 uint16_t len; 1179 uint8_t token; 1180 uint8_t id; 1181 uint8_t origin; 1182 uint8_t periodic; 1183 uint16_t timeout; 1184 uint32_t start; 1185 uint32_t reserved1; 1186 uint32_t flags; 1187 uint32_t filter; 1188 uint16_t nchan; 1189 uint16_t reserved2; 1190 struct { 1191 uint32_t duration; 1192 uint8_t chan; 1193 uint8_t type; 1194#define IWN_MEASUREMENT_BASIC (1 << 0) 1195#define IWN_MEASUREMENT_CCA (1 << 1) 1196#define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 1197#define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 1198#define IWN_MEASUREMENT_FRAME (1 << 4) 1199#define IWN_MEASUREMENT_IDLE (1 << 7) 1200 1201 uint16_t reserved; 1202 } __packed chan[10]; 1203} __packed; 1204 1205/* Structure for IWN_UC_READY notification. */ 1206#define IWN_NATTEN_GROUPS 5 1207struct iwn_ucode_info { 1208 uint8_t minor; 1209 uint8_t major; 1210 uint16_t reserved1; 1211 uint8_t revision[8]; 1212 uint8_t type; 1213 uint8_t subtype; 1214#define IWN_UCODE_RUNTIME 0 1215#define IWN_UCODE_INIT 9 1216 1217 uint16_t reserved2; 1218 uint32_t logptr; 1219 uint32_t errptr; 1220 uint32_t tstamp; 1221 uint32_t valid; 1222 1223 /* The following fields are for UCODE_INIT only. */ 1224 int32_t volt; 1225 struct { 1226 int32_t chan20MHz; 1227 int32_t chan40MHz; 1228 } __packed temp[4]; 1229 int32_t atten[IWN_NATTEN_GROUPS][2]; 1230} __packed; 1231 1232/* Structures for IWN_TX_DONE notification. */ 1233#define IWN_TX_STATUS_MSK 0xff 1234#define TX_STATUS_SUCCESS 0x01 1235#define TX_STATUS_DIRECT_DONE 0x02 1236 1237#define IWN_TX_SUCCESS 0x00 1238#define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */ 1239#define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */ 1240#define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */ 1241#define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */ 1242#define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */ 1243#define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */ 1244#define IWN_TX_FAIL_STA_INVALID 0x8b /* XXX STA invalid (???) */ 1245 1246struct iwn4965_tx_stat { 1247 uint8_t nframes; 1248 uint8_t btkillcnt; 1249 uint8_t rtsfailcnt; 1250 uint8_t ackfailcnt; 1251 uint32_t rate; 1252 uint16_t duration; 1253 uint16_t reserved; 1254 uint32_t power[2]; 1255 uint32_t status; 1256} __packed; 1257 1258struct iwn5000_tx_stat { 1259 uint8_t nframes; /* 1 no aggregation, >1 aggregation */ 1260 uint8_t btkillcnt; 1261 uint8_t rtsfailcnt; 1262 uint8_t ackfailcnt; 1263 uint32_t rate; 1264 uint16_t duration; 1265 uint16_t reserved; 1266 uint32_t power[2]; 1267 uint32_t info; 1268 uint16_t seq; 1269 uint16_t len; 1270 uint8_t tlc; 1271 uint8_t ratid; /* tid (0:3), sta_id (4:7) */ 1272 uint8_t fc[2]; 1273 uint16_t status; 1274 uint16_t sequence; 1275} __packed; 1276 1277/* Structure for IWN_BEACON_MISSED notification. */ 1278struct iwn_beacon_missed { 1279 uint32_t consecutive; 1280 uint32_t total; 1281 uint32_t expected; 1282 uint32_t received; 1283} __packed; 1284 1285/* Structure for IWN_MPDU_RX_DONE notification. */ 1286struct iwn_rx_mpdu { 1287 uint16_t len; 1288 uint16_t reserved; 1289} __packed; 1290 1291/* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1292struct iwn4965_rx_phystat { 1293 uint16_t antenna; 1294 uint16_t agc; 1295 uint8_t rssi[6]; 1296} __packed; 1297 1298struct iwn5000_rx_phystat { 1299 uint32_t reserved1; 1300 uint32_t agc; 1301 uint16_t rssi[3]; 1302} __packed; 1303 1304struct iwn_rx_stat { 1305 uint8_t phy_len; 1306 uint8_t cfg_phy_len; 1307#define IWN_STAT_MAXLEN 20 1308 1309 uint8_t id; 1310 uint8_t reserved1; 1311 uint64_t tstamp; 1312 uint32_t beacon; 1313 uint16_t flags; 1314#define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1315 1316 uint16_t chan; 1317 uint8_t phybuf[32]; 1318 uint32_t rate; 1319/* 1320 * rate bit fields 1321 * 1322 * High-throughput (HT) rate format for bits 7:0 (bit 8 must be "1"): 1323 * 2-0: 0) 6 Mbps 1324 * 1) 12 Mbps 1325 * 2) 18 Mbps 1326 * 3) 24 Mbps 1327 * 4) 36 Mbps 1328 * 5) 48 Mbps 1329 * 6) 54 Mbps 1330 * 7) 60 Mbps 1331 * 1332 * 4-3: 0) Single stream (SISO) 1333 * 1) Dual stream (MIMO) 1334 * 2) Triple stream (MIMO) 1335 * 1336 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 1337 * 1338 * Legacy OFDM rate format for bits 7:0 (bit 8 must be "0", bit 9 "0"): 1339 * 3-0: 0xD) 6 Mbps 1340 * 0xF) 9 Mbps 1341 * 0x5) 12 Mbps 1342 * 0x7) 18 Mbps 1343 * 0x9) 24 Mbps 1344 * 0xB) 36 Mbps 1345 * 0x1) 48 Mbps 1346 * 0x3) 54 Mbps 1347 * 1348 * Legacy CCK rate format for bits 7:0 (bit 8 must be "0", bit 9 "1"): 1349 * 6-0: 10) 1 Mbps 1350 * 20) 2 Mbps 1351 * 55) 5.5 Mbps 1352 * 110) 11 Mbps 1353 * 1354 */ 1355 uint16_t len; 1356 uint16_t reserve3; 1357} __packed; 1358 1359#define IWN_RSSI_TO_DBM 44 1360 1361/* Structure for IWN_RX_COMPRESSED_BA notification. */ 1362struct iwn_compressed_ba { 1363 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1364 uint16_t reserved; 1365 uint8_t id; 1366 uint8_t tid; 1367 uint16_t seq; 1368 uint64_t bitmap; 1369 uint16_t qid; 1370 uint16_t ssn; 1371} __packed; 1372 1373/* Structure for IWN_START_SCAN notification. */ 1374struct iwn_start_scan { 1375 uint64_t tstamp; 1376 uint32_t tbeacon; 1377 uint8_t chan; 1378 uint8_t band; 1379 uint16_t reserved; 1380 uint32_t status; 1381} __packed; 1382 1383/* Structure for IWN_STOP_SCAN notification. */ 1384struct iwn_stop_scan { 1385 uint8_t nchan; 1386 uint8_t status; 1387 uint8_t reserved; 1388 uint8_t chan; 1389 uint64_t tsf; 1390} __packed; 1391 1392/* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1393struct iwn_spectrum_notif { 1394 uint8_t id; 1395 uint8_t token; 1396 uint8_t idx; 1397 uint8_t state; 1398#define IWN_MEASUREMENT_START 0 1399#define IWN_MEASUREMENT_STOP 1 1400 1401 uint32_t start; 1402 uint8_t band; 1403 uint8_t chan; 1404 uint8_t type; 1405 uint8_t reserved1; 1406 uint32_t cca_ofdm; 1407 uint32_t cca_cck; 1408 uint32_t cca_time; 1409 uint8_t basic; 1410 uint8_t reserved2[3]; 1411 uint32_t ofdm[8]; 1412 uint32_t cck[8]; 1413 uint32_t stop; 1414 uint32_t status; 1415#define IWN_MEASUREMENT_OK 0 1416#define IWN_MEASUREMENT_CONCURRENT 1 1417#define IWN_MEASUREMENT_CSA_CONFLICT 2 1418#define IWN_MEASUREMENT_TGH_CONFLICT 3 1419#define IWN_MEASUREMENT_STOPPED 6 1420#define IWN_MEASUREMENT_TIMEOUT 7 1421#define IWN_MEASUREMENT_FAILED 8 1422} __packed; 1423 1424/* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1425struct iwn_rx_phy_stats { 1426 uint32_t ina; 1427 uint32_t fina; 1428 uint32_t bad_plcp; 1429 uint32_t bad_crc32; 1430 uint32_t overrun; 1431 uint32_t eoverrun; 1432 uint32_t good_crc32; 1433 uint32_t fa; 1434 uint32_t bad_fina_sync; 1435 uint32_t sfd_timeout; 1436 uint32_t fina_timeout; 1437 uint32_t no_rts_ack; 1438 uint32_t rxe_limit; 1439 uint32_t ack; 1440 uint32_t cts; 1441 uint32_t ba_resp; 1442 uint32_t dsp_kill; 1443 uint32_t bad_mh; 1444 uint32_t rssi_sum; 1445 uint32_t reserved; 1446} __packed; 1447 1448struct iwn_rx_general_stats { 1449 uint32_t bad_cts; 1450 uint32_t bad_ack; 1451 uint32_t not_bss; 1452 uint32_t filtered; 1453 uint32_t bad_chan; 1454 uint32_t beacons; 1455 uint32_t missed_beacons; 1456 uint32_t adc_saturated; /* time in 0.8us */ 1457 uint32_t ina_searched; /* time in 0.8us */ 1458 uint32_t noise[3]; 1459 uint32_t flags; 1460 uint32_t load; 1461 uint32_t fa; 1462 uint32_t rssi[3]; 1463 uint32_t energy[3]; 1464} __packed; 1465 1466struct iwn_rx_ht_phy_stats { 1467 uint32_t bad_plcp; 1468 uint32_t overrun; 1469 uint32_t eoverrun; 1470 uint32_t good_crc32; 1471 uint32_t bad_crc32; 1472 uint32_t bad_mh; 1473 uint32_t good_ampdu_crc32; 1474 uint32_t ampdu; 1475 uint32_t fragment; 1476 uint32_t reserved; 1477} __packed; 1478 1479struct iwn_rx_stats { 1480 struct iwn_rx_phy_stats ofdm; 1481 struct iwn_rx_phy_stats cck; 1482 struct iwn_rx_general_stats general; 1483 struct iwn_rx_ht_phy_stats ht; 1484} __packed; 1485 1486struct iwn_tx_stats { 1487 uint32_t preamble; 1488 uint32_t rx_detected; 1489 uint32_t bt_defer; 1490 uint32_t bt_kill; 1491 uint32_t short_len; 1492 uint32_t cts_timeout; 1493 uint32_t ack_timeout; 1494 uint32_t exp_ack; 1495 uint32_t ack; 1496 uint32_t msdu; 1497 uint32_t busrt_err1; 1498 uint32_t burst_err2; 1499 uint32_t cts_collision; 1500 uint32_t ack_collision; 1501 uint32_t ba_timeout; 1502 uint32_t ba_resched; 1503 uint32_t query_ampdu; 1504 uint32_t query; 1505 uint32_t query_ampdu_frag; 1506 uint32_t query_mismatch; 1507 uint32_t not_ready; 1508 uint32_t underrun; 1509 uint32_t bt_ht_kill; 1510 uint32_t rx_ba_resp; 1511 uint32_t reserved[2]; 1512} __packed; 1513 1514struct iwn_general_stats { 1515 uint32_t temp; 1516 uint32_t temp_m; 1517 uint32_t burst_check; 1518 uint32_t burst; 1519 uint32_t reserved1[4]; 1520 uint32_t sleep; 1521 uint32_t slot_out; 1522 uint32_t slot_idle; 1523 uint32_t ttl_tstamp; 1524 uint32_t tx_ant_a; 1525 uint32_t tx_ant_b; 1526 uint32_t exec; 1527 uint32_t probe; 1528 uint32_t reserved2[2]; 1529 uint32_t rx_enabled; 1530 uint32_t reserved3[3]; 1531} __packed; 1532 1533struct iwn_stats { 1534 uint32_t flags; 1535 struct iwn_rx_stats rx; 1536 struct iwn_tx_stats tx; 1537 struct iwn_general_stats general; 1538} __packed; 1539 1540 1541/* Firmware error dump. */ 1542struct iwn_fw_dump { 1543 uint32_t valid; 1544 uint32_t id; 1545 uint32_t pc; 1546 uint32_t branch_link[2]; 1547 uint32_t interrupt_link[2]; 1548 uint32_t error_data[2]; 1549 uint32_t src_line; 1550 uint32_t tsf; 1551 uint32_t time[2]; 1552} __packed; 1553 1554/* TLV firmware header. */ 1555struct iwn_fw_tlv_hdr { 1556 uint32_t zero; /* Always 0, to differentiate from legacy. */ 1557 uint32_t signature; 1558#define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */ 1559 1560 uint8_t descr[64]; 1561 uint32_t rev; 1562#define IWN_FW_API(x) (((x) >> 8) & 0xff) 1563 1564 uint32_t build; 1565 uint64_t altmask; 1566} __packed; 1567 1568/* TLV header. */ 1569struct iwn_fw_tlv { 1570 uint16_t type; 1571#define IWN_FW_TLV_MAIN_TEXT 1 1572#define IWN_FW_TLV_MAIN_DATA 2 1573#define IWN_FW_TLV_INIT_TEXT 3 1574#define IWN_FW_TLV_INIT_DATA 4 1575#define IWN_FW_TLV_BOOT_TEXT 5 1576#define IWN_FW_TLV_PBREQ_MAXLEN 6 1577#define IWN_FW_TLV_PAN 7 1578#define IWN_FW_TLV_RUNT_EVTLOG_PTR 8 1579#define IWN_FW_TLV_RUNT_EVTLOG_SIZE 9 1580#define IWN_FW_TLV_RUNT_ERRLOG_PTR 10 1581#define IWN_FW_TLV_INIT_EVTLOG_PTR 11 1582#define IWN_FW_TLV_INIT_EVTLOG_SIZE 12 1583#define IWN_FW_TLV_INIT_ERRLOG_PTR 13 1584#define IWN_FW_TLV_ENH_SENS 14 1585#define IWN_FW_TLV_PHY_CALIB 15 1586#define IWN_FW_TLV_WOWLAN_INST 16 1587#define IWN_FW_TLV_WOWLAN_DATA 17 1588#define IWN_FW_TLV_FLAGS 18 1589 1590 uint16_t alt; 1591 uint32_t len; 1592} __packed; 1593 1594#define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1595#define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1596#define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1597#define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1598#define IWN_FW_BOOT_TEXT_MAXSZ 1024 1599#define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1600#define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1601 1602/* 1603 * Offsets into EEPROM. 1604 */ 1605#define IWN_EEPROM_MAC 0x015 1606#define IWN_EEPROM_SKU_CAP 0x045 1607#define IWN_EEPROM_RFCFG 0x048 1608#define IWN4965_EEPROM_DOMAIN 0x060 1609#define IWN4965_EEPROM_BAND1 0x063 1610#define IWN5000_EEPROM_REG 0x066 1611#define IWN5000_EEPROM_CAL 0x067 1612#define IWN4965_EEPROM_BAND2 0x072 1613#define IWN4965_EEPROM_BAND3 0x080 1614#define IWN4965_EEPROM_BAND4 0x08d 1615#define IWN4965_EEPROM_BAND5 0x099 1616#define IWN4965_EEPROM_BAND6 0x0a0 1617#define IWN4965_EEPROM_BAND7 0x0a8 1618#define IWN4965_EEPROM_MAXPOW 0x0e8 1619#define IWN4965_EEPROM_VOLTAGE 0x0e9 1620#define IWN4965_EEPROM_BANDS 0x0ea 1621/* Indirect offsets. */ 1622#define IWN5000_EEPROM_NO_HT40 0x000 1623#define IWN5000_EEPROM_DOMAIN 0x001 1624#define IWN5000_EEPROM_BAND1 0x004 1625#define IWN5000_EEPROM_BAND2 0x013 1626#define IWN5000_EEPROM_BAND3 0x021 1627#define IWN5000_EEPROM_BAND4 0x02e 1628#define IWN5000_EEPROM_BAND5 0x03a 1629#define IWN5000_EEPROM_BAND6 0x041 1630#define IWN6000_EEPROM_BAND6 0x040 1631#define IWN5000_EEPROM_BAND7 0x049 1632#define IWN6000_EEPROM_ENHINFO 0x054 1633#define IWN5000_EEPROM_CRYSTAL 0x128 1634#define IWN5000_EEPROM_TEMP 0x12a 1635#define IWN5000_EEPROM_VOLT 0x12b 1636 1637/* Possible flags for IWN_EEPROM_SKU_CAP. */ 1638#define IWN_EEPROM_SKU_CAP_11N (1 << 6) 1639#define IWN_EEPROM_SKU_CAP_AMT (1 << 7) 1640#define IWN_EEPROM_SKU_CAP_IPAN (1 << 8) 1641 1642/* Possible flags for IWN_EEPROM_RFCFG. */ 1643#define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1644#define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1645#define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1646#define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1647#define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1648 1649struct iwn_eeprom_chan { 1650 uint8_t flags; 1651#define IWN_EEPROM_CHAN_VALID (1 << 0) 1652#define IWN_EEPROM_CHAN_IBSS (1 << 1) 1653#define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1654#define IWN_EEPROM_CHAN_RADAR (1 << 4) 1655 1656 int8_t maxpwr; 1657} __packed; 1658 1659struct iwn_eeprom_enhinfo { 1660 uint8_t flags; 1661#define IWN_ENHINFO_VALID 0x01 1662#define IWN_ENHINFO_5GHZ 0x02 1663#define IWN_ENHINFO_OFDM 0x04 1664#define IWN_ENHINFO_HT40 0x08 1665#define IWN_ENHINFO_HTAP 0x10 1666#define IWN_ENHINFO_RES1 0x20 1667#define IWN_ENHINFO_RES2 0x40 1668#define IWN_ENHINFO_COMMON 0x80 1669 1670 uint8_t chan; 1671 int8_t chain[3]; /* max power in half-dBm */ 1672 uint8_t reserved; 1673 int8_t mimo2; /* max power in half-dBm */ 1674 int8_t mimo3; /* max power in half-dBm */ 1675} __packed; 1676 1677struct iwn5000_eeprom_calib_hdr { 1678 uint8_t version; 1679 uint8_t pa_type; 1680 uint16_t volt; 1681} __packed; 1682 1683#define IWN_NSAMPLES 3 1684struct iwn4965_eeprom_chan_samples { 1685 uint8_t num; 1686 struct { 1687 uint8_t temp; 1688 uint8_t gain; 1689 uint8_t power; 1690 int8_t pa_det; 1691 } samples[2][IWN_NSAMPLES]; 1692} __packed; 1693 1694#define IWN_NBANDS 8 1695struct iwn4965_eeprom_band { 1696 uint8_t lo; /* low channel number */ 1697 uint8_t hi; /* high channel number */ 1698 struct iwn4965_eeprom_chan_samples chans[2]; 1699} __packed; 1700 1701/* 1702 * Offsets of channels descriptions in EEPROM. 1703 */ 1704static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1705 IWN4965_EEPROM_BAND1, 1706 IWN4965_EEPROM_BAND2, 1707 IWN4965_EEPROM_BAND3, 1708 IWN4965_EEPROM_BAND4, 1709 IWN4965_EEPROM_BAND5, 1710 IWN4965_EEPROM_BAND6, 1711 IWN4965_EEPROM_BAND7 1712}; 1713 1714static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1715 IWN5000_EEPROM_BAND1, 1716 IWN5000_EEPROM_BAND2, 1717 IWN5000_EEPROM_BAND3, 1718 IWN5000_EEPROM_BAND4, 1719 IWN5000_EEPROM_BAND5, 1720 IWN5000_EEPROM_BAND6, 1721 IWN5000_EEPROM_BAND7 1722}; 1723 1724static const uint32_t iwn6000_regulatory_bands[IWN_NBANDS] = { 1725 IWN5000_EEPROM_BAND1, 1726 IWN5000_EEPROM_BAND2, 1727 IWN5000_EEPROM_BAND3, 1728 IWN5000_EEPROM_BAND4, 1729 IWN5000_EEPROM_BAND5, 1730 IWN6000_EEPROM_BAND6, 1731 IWN5000_EEPROM_BAND7 1732}; 1733 1734static const uint32_t iwn1000_regulatory_bands[IWN_NBANDS] = { 1735 IWN5000_EEPROM_BAND1, 1736 IWN5000_EEPROM_BAND2, 1737 IWN5000_EEPROM_BAND3, 1738 IWN5000_EEPROM_BAND4, 1739 IWN5000_EEPROM_BAND5, 1740 IWN5000_EEPROM_BAND6, 1741 IWN5000_EEPROM_NO_HT40, 1742}; 1743 1744static const uint32_t iwn2030_regulatory_bands[IWN_NBANDS] = { 1745 IWN5000_EEPROM_BAND1, 1746 IWN5000_EEPROM_BAND2, 1747 IWN5000_EEPROM_BAND3, 1748 IWN5000_EEPROM_BAND4, 1749 IWN5000_EEPROM_BAND5, 1750 IWN6000_EEPROM_BAND6, 1751 IWN5000_EEPROM_BAND7 1752}; 1753 1754#define IWN_CHAN_BANDS_COUNT 7 1755#define IWN_MAX_CHAN_PER_BAND 14 1756static const struct iwn_chan_band { 1757 uint8_t nchan; 1758 uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1759} iwn_bands[] = { 1760 /* 20MHz channels, 2GHz band. */ 1761 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1762 /* 20MHz channels, 5GHz band. */ 1763 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1764 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1765 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1766 { 6, { 145, 149, 153, 157, 161, 165 } }, 1767 /* 40MHz channels (primary channels), 2GHz band. */ 1768 { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1769 /* 40MHz channels (primary channels), 5GHz band. */ 1770 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1771}; 1772 1773static const uint8_t iwn_bss_ac_to_queue[] = { 1774 2, 3, 1, 0, 1775}; 1776 1777static const uint8_t iwn_pan_ac_to_queue[] = { 1778 5, 4, 6, 7, 1779}; 1780#define IWN1000_OTP_NBLOCKS 3 1781#define IWN6000_OTP_NBLOCKS 4 1782#define IWN6050_OTP_NBLOCKS 7 1783 1784/* HW rate indices. */ 1785#define IWN_RIDX_CCK1 0 1786#define IWN_RIDX_OFDM6 4 1787 1788#define IWN4965_MAX_PWR_INDEX 107 1789#define IWN_POWERSAVE_LVL_NONE 0 1790#define IWN_POWERSAVE_LVL_VOIP_COMPATIBLE 1 1791#define IWN_POWERSAVE_LVL_MAX 5 1792 1793#define IWN_POWERSAVE_LVL_DEFAULT IWN_POWERSAVE_LVL_NONE 1794 1795/* DTIM value to pass in for IWN_POWERSAVE_LVL_VOIP_COMPATIBLE */ 1796#define IWN_POWERSAVE_DTIM_VOIP_COMPATIBLE 2 1797 1798/* 1799 * RF Tx gain values from highest to lowest power (values obtained from 1800 * the reference driver.) 1801 */ 1802static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1803 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 1804 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 1805 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 1806 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 1807 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 1808 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 1809 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1810 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1811 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1812 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1813}; 1814 1815static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1816 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 1817 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 1818 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 1819 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 1820 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 1821 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 1822 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 1823 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 1824 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 1825 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1826}; 1827 1828/* 1829 * DSP pre-DAC gain values from highest to lowest power (values obtained 1830 * from the reference driver.) 1831 */ 1832static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1833 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1834 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1835 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1836 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1837 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1838 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1839 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 1840 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 1841 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 1842 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 1843}; 1844 1845static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1846 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1847 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1848 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1849 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1850 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1851 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1852 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1853 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1854 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1855 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 1856}; 1857 1858/* 1859 * Power saving settings (values obtained from the reference driver.) 1860 */ 1861#define IWN_NDTIMRANGES 3 1862#define IWN_NPOWERLEVELS 6 1863static const struct iwn_pmgt { 1864 uint32_t rxtimeout; 1865 uint32_t txtimeout; 1866 uint32_t intval[5]; 1867 int skip_dtim; 1868} iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 1869 /* DTIM <= 2 */ 1870 { 1871 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1872 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 1873 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 1874 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 1875 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 1876 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 1877 }, 1878 /* 3 <= DTIM <= 10 */ 1879 { 1880 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1881 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 1882 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 1883 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 1884 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 1885 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 1886 }, 1887 /* DTIM >= 11 */ 1888 { 1889 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1890 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 1891 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 1892 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 1893 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 1894 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1895 } 1896}; 1897 1898struct iwn_sensitivity_limits { 1899 uint32_t min_ofdm_x1; 1900 uint32_t max_ofdm_x1; 1901 uint32_t min_ofdm_mrc_x1; 1902 uint32_t max_ofdm_mrc_x1; 1903 uint32_t min_ofdm_x4; 1904 uint32_t max_ofdm_x4; 1905 uint32_t min_ofdm_mrc_x4; 1906 uint32_t max_ofdm_mrc_x4; 1907 uint32_t min_cck_x4; 1908 uint32_t max_cck_x4; 1909 uint32_t min_cck_mrc_x4; 1910 uint32_t max_cck_mrc_x4; 1911 uint32_t min_energy_cck; 1912 uint32_t energy_cck; 1913 uint32_t energy_ofdm; 1914}; 1915 1916/* 1917 * RX sensitivity limits (values obtained from the reference driver.) 1918 */ 1919static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 1920 105, 140, 1921 220, 270, 1922 85, 120, 1923 170, 210, 1924 125, 200, 1925 200, 400, 1926 97, 1927 100, 1928 100 1929}; 1930 1931static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 1932 120, 120, /* min = max for performance bug in DSP. */ 1933 240, 240, /* min = max for performance bug in DSP. */ 1934 90, 120, 1935 170, 210, 1936 125, 200, 1937 170, 400, 1938 95, 1939 95, 1940 95 1941}; 1942 1943static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 1944 105, 105, /* min = max for performance bug in DSP. */ 1945 220, 220, /* min = max for performance bug in DSP. */ 1946 90, 120, 1947 170, 210, 1948 125, 200, 1949 170, 400, 1950 95, 1951 95, 1952 95 1953}; 1954 1955static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 1956 120, 155, 1957 240, 290, 1958 90, 120, 1959 170, 210, 1960 125, 200, 1961 170, 400, 1962 95, 1963 95, 1964 95 1965}; 1966 1967static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 1968 105, 110, 1969 192, 232, 1970 80, 145, 1971 128, 232, 1972 125, 175, 1973 160, 310, 1974 97, 1975 97, 1976 100 1977}; 1978 1979/* Get value from linux kernel 3.2.+ in Drivers/net/wireless/iwlwifi/iwl-2000.c*/ 1980static const struct iwn_sensitivity_limits iwn2030_sensitivity_limits = { 1981 105,110, 1982 128,232, 1983 80,145, 1984 128,232, 1985 125,175, 1986 160,310, 1987 97, 1988 97, 1989 110 1990}; 1991 1992/* Map TID to TX scheduler's FIFO. */ 1993static const uint8_t iwn_tid2fifo[] = { 1994 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 1995}; 1996 1997/* WiFi/WiMAX coexist event priority table for 6050. */ 1998static const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 1999 { 0x04, 0x03, 0x00, 0x00 }, 2000 { 0x04, 0x03, 0x00, 0x03 }, 2001 { 0x04, 0x03, 0x00, 0x03 }, 2002 { 0x04, 0x03, 0x00, 0x03 }, 2003 { 0x04, 0x03, 0x00, 0x00 }, 2004 { 0x04, 0x03, 0x00, 0x07 }, 2005 { 0x04, 0x03, 0x00, 0x00 }, 2006 { 0x04, 0x03, 0x00, 0x03 }, 2007 { 0x04, 0x03, 0x00, 0x03 }, 2008 { 0x04, 0x03, 0x00, 0x00 }, 2009 { 0x06, 0x03, 0x00, 0x07 }, 2010 { 0x04, 0x03, 0x00, 0x00 }, 2011 { 0x06, 0x06, 0x00, 0x03 }, 2012 { 0x04, 0x03, 0x00, 0x07 }, 2013 { 0x04, 0x03, 0x00, 0x00 }, 2014 { 0x04, 0x03, 0x00, 0x00 } 2015}; 2016 2017/* Firmware errors. */ 2018static const char * const iwn_fw_errmsg[] = { 2019 "OK", 2020 "FAIL", 2021 "BAD_PARAM", 2022 "BAD_CHECKSUM", 2023 "NMI_INTERRUPT_WDG", 2024 "SYSASSERT", 2025 "FATAL_ERROR", 2026 "BAD_COMMAND", 2027 "HW_ERROR_TUNE_LOCK", 2028 "HW_ERROR_TEMPERATURE", 2029 "ILLEGAL_CHAN_FREQ", 2030 "VCC_NOT_STABLE", 2031 "FH_ERROR", 2032 "NMI_INTERRUPT_HOST", 2033 "NMI_INTERRUPT_ACTION_PT", 2034 "NMI_INTERRUPT_UNKNOWN", 2035 "UCODE_VERSION_MISMATCH", 2036 "HW_ERROR_ABS_LOCK", 2037 "HW_ERROR_CAL_LOCK_FAIL", 2038 "NMI_INTERRUPT_INST_ACTION_PT", 2039 "NMI_INTERRUPT_DATA_ACTION_PT", 2040 "NMI_TRM_HW_ER", 2041 "NMI_INTERRUPT_TRM", 2042 "NMI_INTERRUPT_BREAKPOINT" 2043 "DEBUG_0", 2044 "DEBUG_1", 2045 "DEBUG_2", 2046 "DEBUG_3", 2047 "ADVANCED_SYSASSERT" 2048}; 2049 2050/* Find least significant bit that is set. */ 2051#define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 2052 2053#define IWN_READ(sc, reg) \ 2054 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 2055 2056#define IWN_WRITE(sc, reg, val) \ 2057 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 2058 2059#define IWN_WRITE_1(sc, reg, val) \ 2060 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 2061 2062#define IWN_SETBITS(sc, reg, mask) \ 2063 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 2064 2065#define IWN_CLRBITS(sc, reg, mask) \ 2066 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 2067 2068#define IWN_BARRIER_WRITE(sc) \ 2069 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2070 BUS_SPACE_BARRIER_WRITE) 2071 2072#define IWN_BARRIER_READ_WRITE(sc) \ 2073 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2074 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 2075 2076#endif /* __IF_IWNREG_H__ */ 2077