if_iwnreg.h revision 221635
1/* $FreeBSD: head/sys/dev/iwn/if_iwnreg.h 221635 2011-05-08 10:21:42Z bschmidt $ */ 2/* $OpenBSD: if_iwnreg.h,v 1.40 2010/05/05 19:41:57 damien Exp $ */ 3 4/*- 5 * Copyright (c) 2007, 2008 6 * Damien Bergamini <damien.bergamini@free.fr> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21#define IWN_TX_RING_COUNT 256 22#define IWN_TX_RING_LOMARK 192 23#define IWN_TX_RING_HIMARK 224 24#define IWN_RX_RING_COUNT_LOG 6 25#define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 26 27#define IWN4965_NTXQUEUES 16 28#define IWN5000_NTXQUEUES 20 29 30#define IWN4965_NDMACHNLS 7 31#define IWN5000_NDMACHNLS 8 32 33#define IWN_SRVC_DMACHNL 9 34 35#define IWN_ICT_SIZE 4096 36#define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 37 38/* Maximum number of DMA segments for TX. */ 39#define IWN_MAX_SCATTER 20 40 41/* RX buffers must be large enough to hold a full 4K A-MPDU. */ 42#define IWN_RBUF_SIZE (4 * 1024) 43 44#if defined(__LP64__) 45/* HW supports 36-bit DMA addresses. */ 46#define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 47#define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 48#else 49#define IWN_LOADDR(paddr) (paddr) 50#define IWN_HIADDR(paddr) (0) 51#endif 52 53/* 54 * Control and status registers. 55 */ 56#define IWN_HW_IF_CONFIG 0x000 57#define IWN_INT_COALESCING 0x004 58#define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 59#define IWN_INT 0x008 60#define IWN_INT_MASK 0x00c 61#define IWN_FH_INT 0x010 62#define IWN_RESET 0x020 63#define IWN_GP_CNTRL 0x024 64#define IWN_HW_REV 0x028 65#define IWN_EEPROM 0x02c 66#define IWN_EEPROM_GP 0x030 67#define IWN_OTP_GP 0x034 68#define IWN_GIO 0x03c 69#define IWN_GP_DRIVER 0x050 70#define IWN_UCODE_GP1_CLR 0x05c 71#define IWN_LED 0x094 72#define IWN_DRAM_INT_TBL 0x0a0 73#define IWN_SHADOW_REG_CTRL 0x0a8 74#define IWN_GIO_CHICKEN 0x100 75#define IWN_ANA_PLL 0x20c 76#define IWN_HW_REV_WA 0x22c 77#define IWN_DBG_HPET_MEM 0x240 78#define IWN_DBG_LINK_PWR_MGMT 0x250 79#define IWN_MEM_RADDR 0x40c 80#define IWN_MEM_WADDR 0x410 81#define IWN_MEM_WDATA 0x418 82#define IWN_MEM_RDATA 0x41c 83#define IWN_PRPH_WADDR 0x444 84#define IWN_PRPH_RADDR 0x448 85#define IWN_PRPH_WDATA 0x44c 86#define IWN_PRPH_RDATA 0x450 87#define IWN_HBUS_TARG_WRPTR 0x460 88 89/* 90 * Flow-Handler registers. 91 */ 92#define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 93#define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 94#define IWN_FH_KW_ADDR 0x197c 95#define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 96#define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 97#define IWN_FH_STATUS_WPTR 0x1bc0 98#define IWN_FH_RX_BASE 0x1bc4 99#define IWN_FH_RX_WPTR 0x1bc8 100#define IWN_FH_RX_CONFIG 0x1c00 101#define IWN_FH_RX_STATUS 0x1c44 102#define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 103#define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 104#define IWN_FH_TX_CHICKEN 0x1e98 105#define IWN_FH_TX_STATUS 0x1eb0 106 107/* 108 * TX scheduler registers. 109 */ 110#define IWN_SCHED_BASE 0xa02c00 111#define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 112#define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 113#define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 114#define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 115#define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 116#define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 117#define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 118#define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 119#define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 120#define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 121#define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 122#define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 123#define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 124#define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 125 126/* 127 * Offsets in TX scheduler's SRAM. 128 */ 129#define IWN4965_SCHED_CTX_OFF 0x380 130#define IWN4965_SCHED_CTX_LEN 416 131#define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 132#define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 133#define IWN5000_SCHED_CTX_OFF 0x600 134#define IWN5000_SCHED_CTX_LEN 520 135#define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 136#define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 137 138/* 139 * NIC internal memory offsets. 140 */ 141#define IWN_APMG_CLK_CTRL 0x3000 142#define IWN_APMG_CLK_EN 0x3004 143#define IWN_APMG_CLK_DIS 0x3008 144#define IWN_APMG_PS 0x300c 145#define IWN_APMG_DIGITAL_SVR 0x3058 146#define IWN_APMG_ANALOG_SVR 0x306c 147#define IWN_APMG_PCI_STT 0x3010 148#define IWN_BSM_WR_CTRL 0x3400 149#define IWN_BSM_WR_MEM_SRC 0x3404 150#define IWN_BSM_WR_MEM_DST 0x3408 151#define IWN_BSM_WR_DWCOUNT 0x340c 152#define IWN_BSM_DRAM_TEXT_ADDR 0x3490 153#define IWN_BSM_DRAM_TEXT_SIZE 0x3494 154#define IWN_BSM_DRAM_DATA_ADDR 0x3498 155#define IWN_BSM_DRAM_DATA_SIZE 0x349c 156#define IWN_BSM_SRAM_BASE 0x3800 157 158/* Possible flags for register IWN_HW_IF_CONFIG. */ 159#define IWN_HW_IF_CONFIG_4965_R (1 << 4) 160#define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 161#define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 162#define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 163#define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 164#define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 165#define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 166#define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 167 168/* Possible values for register IWN_INT_PERIODIC. */ 169#define IWN_INT_PERIODIC_DIS 0x00 170#define IWN_INT_PERIODIC_ENA 0xff 171 172/* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 173#define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 174 175/* Possible values for IWN_BSM_WR_MEM_DST. */ 176#define IWN_FW_TEXT_BASE 0x00000000 177#define IWN_FW_DATA_BASE 0x00800000 178 179/* Possible flags for register IWN_RESET. */ 180#define IWN_RESET_NEVO (1 << 0) 181#define IWN_RESET_SW (1 << 7) 182#define IWN_RESET_MASTER_DISABLED (1 << 8) 183#define IWN_RESET_STOP_MASTER (1 << 9) 184#define IWN_RESET_LINK_PWR_MGMT_DIS (1 << 31) 185 186/* Possible flags for register IWN_GP_CNTRL. */ 187#define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 188#define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 189#define IWN_GP_CNTRL_INIT_DONE (1 << 2) 190#define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 191#define IWN_GP_CNTRL_SLEEP (1 << 4) 192#define IWN_GP_CNTRL_RFKILL (1 << 27) 193 194/* Possible flags for register IWN_HW_REV. */ 195#define IWN_HW_REV_TYPE_SHIFT 4 196#define IWN_HW_REV_TYPE_MASK 0x000000f0 197#define IWN_HW_REV_TYPE_4965 0 198#define IWN_HW_REV_TYPE_5300 2 199#define IWN_HW_REV_TYPE_5350 3 200#define IWN_HW_REV_TYPE_5150 4 201#define IWN_HW_REV_TYPE_5100 5 202#define IWN_HW_REV_TYPE_1000 6 203#define IWN_HW_REV_TYPE_6000 7 204#define IWN_HW_REV_TYPE_6050 8 205#define IWN_HW_REV_TYPE_6005 11 206 207/* Possible flags for register IWN_GIO_CHICKEN. */ 208#define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 209#define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 210 211/* Possible flags for register IWN_GIO. */ 212#define IWN_GIO_L0S_ENA (1 << 1) 213 214/* Possible flags for register IWN_GP_DRIVER. */ 215#define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 216#define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 217#define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 218#define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 219#define IWN_GP_DRIVER_6050_1X2 (1 << 3) 220 221/* Possible flags for register IWN_UCODE_GP1_CLR. */ 222#define IWN_UCODE_GP1_RFKILL (1 << 1) 223#define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 224#define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 225 226/* Possible flags/values for register IWN_LED. */ 227#define IWN_LED_BSM_CTRL (1 << 5) 228#define IWN_LED_OFF 0x00000038 229#define IWN_LED_ON 0x00000078 230 231/* Possible flags for register IWN_DRAM_INT_TBL. */ 232#define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) 233#define IWN_DRAM_INT_TBL_ENABLE (1 << 31) 234 235/* Possible values for register IWN_ANA_PLL. */ 236#define IWN_ANA_PLL_INIT 0x00880300 237 238/* Possible flags for register IWN_FH_RX_STATUS. */ 239#define IWN_FH_RX_STATUS_IDLE (1 << 24) 240 241/* Possible flags for register IWN_BSM_WR_CTRL. */ 242#define IWN_BSM_WR_CTRL_START_EN (1 << 30) 243#define IWN_BSM_WR_CTRL_START (1 << 31) 244 245/* Possible flags for register IWN_INT. */ 246#define IWN_INT_ALIVE (1 << 0) 247#define IWN_INT_WAKEUP (1 << 1) 248#define IWN_INT_SW_RX (1 << 3) 249#define IWN_INT_CT_REACHED (1 << 6) 250#define IWN_INT_RF_TOGGLED (1 << 7) 251#define IWN_INT_SW_ERR (1 << 25) 252#define IWN_INT_SCHED (1 << 26) 253#define IWN_INT_FH_TX (1 << 27) 254#define IWN_INT_RX_PERIODIC (1 << 28) 255#define IWN_INT_HW_ERR (1 << 29) 256#define IWN_INT_FH_RX (1 << 31) 257 258/* Shortcut. */ 259#define IWN_INT_MASK_DEF \ 260 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 261 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 262 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 263 264/* Possible flags for register IWN_FH_INT. */ 265#define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 266#define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 267#define IWN_FH_INT_HI_PRIOR (1 << 30) 268/* Shortcuts for the above. */ 269#define IWN_FH_INT_TX \ 270 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 271#define IWN_FH_INT_RX \ 272 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 273 274/* Possible flags/values for register IWN_FH_TX_CONFIG. */ 275#define IWN_FH_TX_CONFIG_DMA_PAUSE 0 276#define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 277#define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20) 278 279/* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 280#define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 281#define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 282#define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 283 284/* Possible flags for register IWN_FH_TX_CHICKEN. */ 285#define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 286 287/* Possible flags for register IWN_FH_TX_STATUS. */ 288#define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16)) 289 290/* Possible flags for register IWN_FH_RX_CONFIG. */ 291#define IWN_FH_RX_CONFIG_ENA (1 << 31) 292#define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 293#define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16) 294#define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15) 295#define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 296#define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 297#define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2) 298 299/* Possible flags for register IWN_FH_TX_CONFIG. */ 300#define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 301#define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3) 302 303/* Possible flags for register IWN_EEPROM. */ 304#define IWN_EEPROM_READ_VALID (1 << 0) 305#define IWN_EEPROM_CMD (1 << 1) 306 307/* Possible flags for register IWN_EEPROM_GP. */ 308#define IWN_EEPROM_GP_IF_OWNER 0x00000180 309 310/* Possible flags for register IWN_OTP_GP. */ 311#define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 312#define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 313#define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 314#define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 315 316/* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 317#define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 318#define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 319#define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 320#define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 321#define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 322#define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 323#define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 324 325/* Possible flags for registers IWN_APMG_CLK_*. */ 326#define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 327#define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 328 329/* Possible flags for register IWN_APMG_PS. */ 330#define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 331#define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 332#define IWN_APMG_PS_PWR_SRC_VMAIN 0 333#define IWN_APMG_PS_PWR_SRC_VAUX 2 334#define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 335#define IWN_APMG_PS_RESET_REQ (1 << 26) 336 337/* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 338#define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 339#define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 340 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 341#define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 342 IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 343 344/* Possible flags for IWN_APMG_PCI_STT. */ 345#define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 346 347/* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 348#define IWN_FW_UPDATED (1 << 31) 349 350#define IWN_SCHED_WINSZ 64 351#define IWN_SCHED_LIMIT 64 352#define IWN4965_SCHED_COUNT 512 353#define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 354#define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 355#define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 356 357struct iwn_tx_desc { 358 uint8_t reserved1[3]; 359 uint8_t nsegs; 360 struct { 361 uint32_t addr; 362 uint16_t len; 363 } __packed segs[IWN_MAX_SCATTER]; 364 /* Pad to 128 bytes. */ 365 uint32_t reserved2; 366} __packed; 367 368struct iwn_rx_status { 369 uint16_t closed_count; 370 uint16_t closed_rx_count; 371 uint16_t finished_count; 372 uint16_t finished_rx_count; 373 uint32_t reserved[2]; 374} __packed; 375 376struct iwn_rx_desc { 377 uint32_t len; 378 uint8_t type; 379#define IWN_UC_READY 1 380#define IWN_ADD_NODE_DONE 24 381#define IWN_TX_DONE 28 382#define IWN5000_CALIBRATION_RESULT 102 383#define IWN5000_CALIBRATION_DONE 103 384#define IWN_START_SCAN 130 385#define IWN_STOP_SCAN 132 386#define IWN_RX_STATISTICS 156 387#define IWN_BEACON_STATISTICS 157 388#define IWN_STATE_CHANGED 161 389#define IWN_BEACON_MISSED 162 390#define IWN_RX_PHY 192 391#define IWN_MPDU_RX_DONE 193 392#define IWN_RX_DONE 195 393#define IWN_RX_COMPRESSED_BA 197 394 395 uint8_t flags; 396 uint8_t idx; 397 uint8_t qid; 398} __packed; 399 400/* Possible RX status flags. */ 401#define IWN_RX_NO_CRC_ERR (1 << 0) 402#define IWN_RX_NO_OVFL_ERR (1 << 1) 403/* Shortcut for the above. */ 404#define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 405#define IWN_RX_MPDU_MIC_OK (1 << 6) 406#define IWN_RX_CIPHER_MASK (7 << 8) 407#define IWN_RX_CIPHER_CCMP (2 << 8) 408#define IWN_RX_MPDU_DEC (1 << 11) 409#define IWN_RX_DECRYPT_MASK (3 << 11) 410#define IWN_RX_DECRYPT_OK (3 << 11) 411 412struct iwn_tx_cmd { 413 uint8_t code; 414#define IWN_CMD_RXON 16 415#define IWN_CMD_RXON_ASSOC 17 416#define IWN_CMD_EDCA_PARAMS 19 417#define IWN_CMD_TIMING 20 418#define IWN_CMD_ADD_NODE 24 419#define IWN_CMD_TX_DATA 28 420#define IWN_CMD_LINK_QUALITY 78 421#define IWN_CMD_SET_LED 72 422#define IWN5000_CMD_WIMAX_COEX 90 423#define IWN5000_CMD_CALIB_CONFIG 101 424#define IWN5000_CMD_CALIB_RESULT 102 425#define IWN5000_CMD_CALIB_COMPLETE 103 426#define IWN_CMD_SET_POWER_MODE 119 427#define IWN_CMD_SCAN 128 428#define IWN_CMD_SCAN_RESULTS 131 429#define IWN_CMD_TXPOWER_DBM 149 430#define IWN_CMD_TXPOWER 151 431#define IWN5000_CMD_TX_ANT_CONFIG 152 432#define IWN_CMD_BT_COEX 155 433#define IWN_CMD_GET_STATISTICS 156 434#define IWN_CMD_SET_CRITICAL_TEMP 164 435#define IWN_CMD_SET_SENSITIVITY 168 436#define IWN_CMD_PHY_CALIB 176 437#define IWN_CMD_BT_COEX_PRIOTABLE 204 438#define IWN_CMD_BT_COEX_PROT 205 439 440 uint8_t flags; 441 uint8_t idx; 442 uint8_t qid; 443 uint8_t data[136]; 444} __packed; 445 446/* Antenna flags, used in various commands. */ 447#define IWN_ANT_A (1 << 0) 448#define IWN_ANT_B (1 << 1) 449#define IWN_ANT_C (1 << 2) 450/* Shortcuts. */ 451#define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 452#define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 453#define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 454 455/* Structure for command IWN_CMD_RXON. */ 456struct iwn_rxon { 457 uint8_t myaddr[IEEE80211_ADDR_LEN]; 458 uint16_t reserved1; 459 uint8_t bssid[IEEE80211_ADDR_LEN]; 460 uint16_t reserved2; 461 uint8_t wlap[IEEE80211_ADDR_LEN]; 462 uint16_t reserved3; 463 uint8_t mode; 464#define IWN_MODE_HOSTAP 1 465#define IWN_MODE_STA 3 466#define IWN_MODE_IBSS 4 467#define IWN_MODE_MONITOR 6 468 469 uint8_t air; 470 uint16_t rxchain; 471#define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 472#define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 473#define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 474#define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 475#define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 476#define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 477#define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 478 479 uint8_t ofdm_mask; 480 uint8_t cck_mask; 481 uint16_t associd; 482 uint32_t flags; 483#define IWN_RXON_24GHZ (1 << 0) 484#define IWN_RXON_CCK (1 << 1) 485#define IWN_RXON_AUTO (1 << 2) 486#define IWN_RXON_SHSLOT (1 << 4) 487#define IWN_RXON_SHPREAMBLE (1 << 5) 488#define IWN_RXON_NODIVERSITY (1 << 7) 489#define IWN_RXON_ANTENNA_A (1 << 8) 490#define IWN_RXON_ANTENNA_B (1 << 9) 491#define IWN_RXON_TSF (1 << 15) 492#define IWN_RXON_CTS_TO_SELF (1 << 30) 493 494 uint32_t filter; 495#define IWN_FILTER_PROMISC (1 << 0) 496#define IWN_FILTER_CTL (1 << 1) 497#define IWN_FILTER_MULTICAST (1 << 2) 498#define IWN_FILTER_NODECRYPT (1 << 3) 499#define IWN_FILTER_BSS (1 << 5) 500#define IWN_FILTER_BEACON (1 << 6) 501 502 uint8_t chan; 503 uint8_t reserved4; 504 uint8_t ht_single_mask; 505 uint8_t ht_dual_mask; 506 /* The following fields are for >=5000 Series only. */ 507 uint8_t ht_triple_mask; 508 uint8_t reserved5; 509 uint16_t acquisition; 510 uint16_t reserved6; 511} __packed; 512 513#define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 514#define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 515 516/* Structure for command IWN_CMD_ASSOCIATE. */ 517struct iwn_assoc { 518 uint32_t flags; 519 uint32_t filter; 520 uint8_t ofdm_mask; 521 uint8_t cck_mask; 522 uint16_t reserved; 523} __packed; 524 525/* Structure for command IWN_CMD_EDCA_PARAMS. */ 526struct iwn_edca_params { 527 uint32_t flags; 528#define IWN_EDCA_UPDATE (1 << 0) 529#define IWN_EDCA_TXOP (1 << 4) 530 531 struct { 532 uint16_t cwmin; 533 uint16_t cwmax; 534 uint8_t aifsn; 535 uint8_t reserved; 536 uint16_t txoplimit; 537 } __packed ac[WME_NUM_AC]; 538} __packed; 539 540/* Structure for command IWN_CMD_TIMING. */ 541struct iwn_cmd_timing { 542 uint64_t tstamp; 543 uint16_t bintval; 544 uint16_t atim; 545 uint32_t binitval; 546 uint16_t lintval; 547 uint16_t reserved; 548} __packed; 549 550/* Structure for command IWN_CMD_ADD_NODE. */ 551struct iwn_node_info { 552 uint8_t control; 553#define IWN_NODE_UPDATE (1 << 0) 554 555 uint8_t reserved1[3]; 556 557 uint8_t macaddr[IEEE80211_ADDR_LEN]; 558 uint16_t reserved2; 559 uint8_t id; 560#define IWN_ID_BSS 0 561#define IWN5000_ID_BROADCAST 15 562#define IWN4965_ID_BROADCAST 31 563 564 uint8_t flags; 565#define IWN_FLAG_SET_KEY (1 << 0) 566#define IWN_FLAG_SET_DISABLE_TID (1 << 1) 567#define IWN_FLAG_SET_TXRATE (1 << 2) 568#define IWN_FLAG_SET_ADDBA (1 << 3) 569#define IWN_FLAG_SET_DELBA (1 << 4) 570 571 uint16_t reserved3; 572 uint16_t kflags; 573#define IWN_KFLAG_CCMP (1 << 1) 574#define IWN_KFLAG_MAP (1 << 3) 575#define IWN_KFLAG_KID(kid) ((kid) << 8) 576#define IWN_KFLAG_INVALID (1 << 11) 577#define IWN_KFLAG_GROUP (1 << 14) 578 579 uint8_t tsc2; /* TKIP TSC2 */ 580 uint8_t reserved4; 581 uint16_t ttak[5]; 582 uint8_t kid; 583 uint8_t reserved5; 584 uint8_t key[16]; 585 /* The following 3 fields are for 5000 Series only. */ 586 uint64_t tsc; 587 uint8_t rxmic[8]; 588 uint8_t txmic[8]; 589 590 uint32_t htflags; 591#define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 592#define IWN_AMDPU_DENSITY(x) ((x) << 23) 593 594 uint32_t mask; 595 uint16_t disable_tid; 596 uint16_t reserved6; 597 uint8_t addba_tid; 598 uint8_t delba_tid; 599 uint16_t addba_ssn; 600 uint32_t reserved7; 601} __packed; 602 603struct iwn4965_node_info { 604 uint8_t control; 605 uint8_t reserved1[3]; 606 uint8_t macaddr[IEEE80211_ADDR_LEN]; 607 uint16_t reserved2; 608 uint8_t id; 609 uint8_t flags; 610 uint16_t reserved3; 611 uint16_t kflags; 612 uint8_t tsc2; /* TKIP TSC2 */ 613 uint8_t reserved4; 614 uint16_t ttak[5]; 615 uint8_t kid; 616 uint8_t reserved5; 617 uint8_t key[16]; 618 uint32_t htflags; 619 uint32_t mask; 620 uint16_t disable_tid; 621 uint16_t reserved6; 622 uint8_t addba_tid; 623 uint8_t delba_tid; 624 uint16_t addba_ssn; 625 uint32_t reserved7; 626} __packed; 627 628#define IWN_RFLAG_CCK (1 << 1) 629#define IWN_RFLAG_ANT(x) ((x) << 6) 630 631/* Structure for command IWN_CMD_TX_DATA. */ 632struct iwn_cmd_data { 633 uint16_t len; 634 uint16_t lnext; 635 uint32_t flags; 636#define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 637#define IWN_TX_NEED_RTS (1 << 1) 638#define IWN_TX_NEED_CTS (1 << 2) 639#define IWN_TX_NEED_ACK (1 << 3) 640#define IWN_TX_LINKQ (1 << 4) 641#define IWN_TX_IMM_BA (1 << 6) 642#define IWN_TX_FULL_TXOP (1 << 7) 643#define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 644#define IWN_TX_AUTO_SEQ (1 << 13) 645#define IWN_TX_MORE_FRAG (1 << 14) 646#define IWN_TX_INSERT_TSTAMP (1 << 16) 647#define IWN_TX_NEED_PADDING (1 << 20) 648 649 uint32_t scratch; 650 uint8_t plcp; 651 uint8_t rflags; 652 uint16_t xrflags; 653 654 uint8_t id; 655 uint8_t security; 656#define IWN_CIPHER_WEP40 1 657#define IWN_CIPHER_CCMP 2 658#define IWN_CIPHER_TKIP 3 659#define IWN_CIPHER_WEP104 9 660 661 uint8_t linkq; 662 uint8_t reserved2; 663 uint8_t key[16]; 664 uint16_t fnext; 665 uint16_t reserved3; 666 uint32_t lifetime; 667#define IWN_LIFETIME_INFINITE 0xffffffff 668 669 uint32_t loaddr; 670 uint8_t hiaddr; 671 uint8_t rts_ntries; 672 uint8_t data_ntries; 673 uint8_t tid; 674 uint16_t timeout; 675 uint16_t txop; 676} __packed; 677 678/* Structure for command IWN_CMD_LINK_QUALITY. */ 679#define IWN_MAX_TX_RETRIES 16 680struct iwn_cmd_link_quality { 681 uint8_t id; 682 uint8_t reserved1; 683 uint16_t ctl; 684 uint8_t flags; 685 uint8_t mimo; 686 uint8_t antmsk_1stream; 687 uint8_t antmsk_2stream; 688 uint8_t ridx[WME_NUM_AC]; 689 uint16_t ampdu_limit; 690 uint8_t ampdu_threshold; 691 uint8_t ampdu_max; 692 uint32_t reserved2; 693 struct { 694 uint8_t plcp; 695 uint8_t rflags; 696 uint16_t xrflags; 697 } __packed retry[IWN_MAX_TX_RETRIES]; 698 uint32_t reserved3; 699} __packed; 700 701/* Structure for command IWN_CMD_SET_LED. */ 702struct iwn_cmd_led { 703 uint32_t unit; /* multiplier (in usecs) */ 704 uint8_t which; 705#define IWN_LED_ACTIVITY 1 706#define IWN_LED_LINK 2 707 708 uint8_t off; 709 uint8_t on; 710 uint8_t reserved; 711} __packed; 712 713/* Structure for command IWN5000_CMD_WIMAX_COEX. */ 714struct iwn5000_wimax_coex { 715 uint32_t flags; 716#define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 717#define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 718#define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 719#define IWN_WIMAX_COEX_ENABLE (1 << 7) 720 721 struct iwn5000_wimax_event { 722 uint8_t request; 723 uint8_t window; 724 uint8_t reserved; 725 uint8_t flags; 726 } __packed events[16]; 727} __packed; 728 729/* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 730struct iwn5000_calib_elem { 731 uint32_t enable; 732 uint32_t start; 733 uint32_t send; 734 uint32_t apply; 735 uint32_t reserved; 736} __packed; 737 738struct iwn5000_calib_status { 739 struct iwn5000_calib_elem once; 740 struct iwn5000_calib_elem perd; 741 uint32_t flags; 742} __packed; 743 744struct iwn5000_calib_config { 745 struct iwn5000_calib_status ucode; 746 struct iwn5000_calib_status driver; 747 uint32_t reserved; 748} __packed; 749 750/* Structure for command IWN_CMD_SET_POWER_MODE. */ 751struct iwn_pmgt_cmd { 752 uint16_t flags; 753#define IWN_PS_ALLOW_SLEEP (1 << 0) 754#define IWN_PS_NOTIFY (1 << 1) 755#define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 756#define IWN_PS_PCI_PMGT (1 << 3) 757#define IWN_PS_FAST_PD (1 << 4) 758 759 uint8_t keepalive; 760 uint8_t debug; 761 uint32_t rxtimeout; 762 uint32_t txtimeout; 763 uint32_t intval[5]; 764 uint32_t beacons; 765} __packed; 766 767/* Structures for command IWN_CMD_SCAN. */ 768struct iwn_scan_essid { 769 uint8_t id; 770 uint8_t len; 771 uint8_t data[IEEE80211_NWID_LEN]; 772} __packed; 773 774struct iwn_scan_hdr { 775 uint16_t len; 776 uint8_t reserved1; 777 uint8_t nchan; 778 uint16_t quiet_time; 779 uint16_t quiet_threshold; 780 uint16_t crc_threshold; 781 uint16_t rxchain; 782 uint32_t max_svc; /* background scans */ 783 uint32_t pause_svc; /* background scans */ 784 uint32_t flags; 785 uint32_t filter; 786 787 /* Followed by a struct iwn_cmd_data. */ 788 /* Followed by an array of 20 structs iwn_scan_essid. */ 789 /* Followed by probe request body. */ 790 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 791} __packed; 792 793struct iwn_scan_chan { 794 uint32_t flags; 795#define IWN_CHAN_ACTIVE (1 << 0) 796#define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 797 798 uint16_t chan; 799 uint8_t rf_gain; 800 uint8_t dsp_gain; 801 uint16_t active; /* msecs */ 802 uint16_t passive; /* msecs */ 803} __packed; 804 805/* Maximum size of a scan command. */ 806#define IWN_SCAN_MAXSZ (MCLBYTES - 4) 807 808/* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 809#define IWN_RIDX_MAX 32 810struct iwn4965_cmd_txpower { 811 uint8_t band; 812 uint8_t reserved1; 813 uint8_t chan; 814 uint8_t reserved2; 815 struct { 816 uint8_t rf_gain[2]; 817 uint8_t dsp_gain[2]; 818 } __packed power[IWN_RIDX_MAX + 1]; 819} __packed; 820 821/* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 822struct iwn5000_cmd_txpower { 823 int8_t global_limit; /* in half-dBm */ 824#define IWN5000_TXPOWER_AUTO 0x7f 825#define IWN5000_TXPOWER_MAX_DBM 16 826 827 uint8_t flags; 828#define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 829 830 int8_t srv_limit; /* in half-dBm */ 831 uint8_t reserved; 832} __packed; 833 834/* Structures for command IWN_CMD_BLUETOOTH. */ 835struct iwn_bluetooth { 836 uint8_t flags; 837#define IWN_BT_COEX_CHAN_ANN (1 << 0) 838#define IWN_BT_COEX_BT_PRIO (1 << 1) 839#define IWN_BT_COEX_2_WIRE (1 << 2) 840 841 uint8_t lead_time; 842#define IWN_BT_LEAD_TIME_DEF 30 843 844 uint8_t max_kill; 845#define IWN_BT_MAX_KILL_DEF 5 846 847 uint8_t reserved; 848 uint32_t kill_ack; 849 uint32_t kill_cts; 850} __packed; 851 852struct iwn6000_btcoex_config { 853 uint8_t flags; 854 uint8_t lead_time; 855 uint8_t max_kill; 856 uint8_t bt3_t7_timer; 857 uint32_t kill_ack; 858 uint32_t kill_cts; 859 uint8_t sample_time; 860 uint8_t bt3_t2_timer; 861 uint16_t bt4_reaction; 862 uint32_t lookup_table[12]; 863 uint16_t bt4_decision; 864 uint16_t valid; 865 uint8_t prio_boost; 866 uint8_t tx_prio_boost; 867 uint16_t rx_prio_boost; 868} __packed; 869 870struct iwn_btcoex_priotable { 871 uint8_t calib_init1; 872 uint8_t calib_init2; 873 uint8_t calib_periodic_low1; 874 uint8_t calib_periodic_low2; 875 uint8_t calib_periodic_high1; 876 uint8_t calib_periodic_high2; 877 uint8_t dtim; 878 uint8_t scan52; 879 uint8_t scan24; 880 uint8_t reserved[7]; 881} __packed; 882 883struct iwn_btcoex_prot { 884 uint8_t open; 885 uint8_t type; 886 uint8_t reserved[2]; 887} __packed; 888 889/* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 890struct iwn_critical_temp { 891 uint32_t reserved; 892 uint32_t tempM; 893 uint32_t tempR; 894/* degK <-> degC conversion macros. */ 895#define IWN_CTOK(c) ((c) + 273) 896#define IWN_KTOC(k) ((k) - 273) 897#define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 898} __packed; 899 900/* Structures for command IWN_CMD_SET_SENSITIVITY. */ 901struct iwn_sensitivity_cmd { 902 uint16_t which; 903#define IWN_SENSITIVITY_DEFAULTTBL 0 904#define IWN_SENSITIVITY_WORKTBL 1 905 906 uint16_t energy_cck; 907 uint16_t energy_ofdm; 908 uint16_t corr_ofdm_x1; 909 uint16_t corr_ofdm_mrc_x1; 910 uint16_t corr_cck_mrc_x4; 911 uint16_t corr_ofdm_x4; 912 uint16_t corr_ofdm_mrc_x4; 913 uint16_t corr_barker; 914 uint16_t corr_barker_mrc; 915 uint16_t corr_cck_x4; 916 uint16_t energy_ofdm_th; 917} __packed; 918 919struct iwn_enhanced_sensitivity_cmd { 920 uint16_t which; 921 uint16_t energy_cck; 922 uint16_t energy_ofdm; 923 uint16_t corr_ofdm_x1; 924 uint16_t corr_ofdm_mrc_x1; 925 uint16_t corr_cck_mrc_x4; 926 uint16_t corr_ofdm_x4; 927 uint16_t corr_ofdm_mrc_x4; 928 uint16_t corr_barker; 929 uint16_t corr_barker_mrc; 930 uint16_t corr_cck_x4; 931 uint16_t energy_ofdm_th; 932 /* "Enhanced" part. */ 933 uint16_t ina_det_ofdm; 934 uint16_t ina_det_cck; 935 uint16_t corr_11_9_en; 936 uint16_t ofdm_det_slope_mrc; 937 uint16_t ofdm_det_icept_mrc; 938 uint16_t ofdm_det_slope; 939 uint16_t ofdm_det_icept; 940 uint16_t cck_det_slope_mrc; 941 uint16_t cck_det_icept_mrc; 942 uint16_t cck_det_slope; 943 uint16_t cck_det_icept; 944 uint16_t reserved; 945} __packed; 946 947/* Structures for command IWN_CMD_PHY_CALIB. */ 948struct iwn_phy_calib { 949 uint8_t code; 950#define IWN4965_PHY_CALIB_DIFF_GAIN 7 951#define IWN5000_PHY_CALIB_DC 8 952#define IWN5000_PHY_CALIB_LO 9 953#define IWN5000_PHY_CALIB_TX_IQ 11 954#define IWN5000_PHY_CALIB_CRYSTAL 15 955#define IWN5000_PHY_CALIB_BASE_BAND 16 956#define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 957#define IWN5000_PHY_CALIB_TEMP_OFFSET 18 958 959#define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 960#define IWN5000_PHY_CALIB_NOISE_GAIN 19 961 962 uint8_t group; 963 uint8_t ngroups; 964 uint8_t isvalid; 965} __packed; 966 967struct iwn5000_phy_calib_crystal { 968 uint8_t code; 969 uint8_t group; 970 uint8_t ngroups; 971 uint8_t isvalid; 972 973 uint8_t cap_pin[2]; 974 uint8_t reserved[2]; 975} __packed; 976 977struct iwn5000_phy_calib_temp_offset { 978 uint8_t code; 979 uint8_t group; 980 uint8_t ngroups; 981 uint8_t isvalid; 982 int16_t offset; 983#define IWN_DEFAULT_TEMP_OFFSET 2700 984 985 uint16_t reserved; 986} __packed; 987 988struct iwn_phy_calib_gain { 989 uint8_t code; 990 uint8_t group; 991 uint8_t ngroups; 992 uint8_t isvalid; 993 994 int8_t gain[3]; 995 uint8_t reserved; 996} __packed; 997 998/* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 999struct iwn_spectrum_cmd { 1000 uint16_t len; 1001 uint8_t token; 1002 uint8_t id; 1003 uint8_t origin; 1004 uint8_t periodic; 1005 uint16_t timeout; 1006 uint32_t start; 1007 uint32_t reserved1; 1008 uint32_t flags; 1009 uint32_t filter; 1010 uint16_t nchan; 1011 uint16_t reserved2; 1012 struct { 1013 uint32_t duration; 1014 uint8_t chan; 1015 uint8_t type; 1016#define IWN_MEASUREMENT_BASIC (1 << 0) 1017#define IWN_MEASUREMENT_CCA (1 << 1) 1018#define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 1019#define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 1020#define IWN_MEASUREMENT_FRAME (1 << 4) 1021#define IWN_MEASUREMENT_IDLE (1 << 7) 1022 1023 uint16_t reserved; 1024 } __packed chan[10]; 1025} __packed; 1026 1027/* Structure for IWN_UC_READY notification. */ 1028#define IWN_NATTEN_GROUPS 5 1029struct iwn_ucode_info { 1030 uint8_t minor; 1031 uint8_t major; 1032 uint16_t reserved1; 1033 uint8_t revision[8]; 1034 uint8_t type; 1035 uint8_t subtype; 1036#define IWN_UCODE_RUNTIME 0 1037#define IWN_UCODE_INIT 9 1038 1039 uint16_t reserved2; 1040 uint32_t logptr; 1041 uint32_t errptr; 1042 uint32_t tstamp; 1043 uint32_t valid; 1044 1045 /* The following fields are for UCODE_INIT only. */ 1046 int32_t volt; 1047 struct { 1048 int32_t chan20MHz; 1049 int32_t chan40MHz; 1050 } __packed temp[4]; 1051 int32_t atten[IWN_NATTEN_GROUPS][2]; 1052} __packed; 1053 1054/* Structures for IWN_TX_DONE notification. */ 1055#define IWN_TX_SUCCESS 0x00 1056#define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */ 1057#define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */ 1058#define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */ 1059#define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */ 1060#define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */ 1061#define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */ 1062 1063struct iwn4965_tx_stat { 1064 uint8_t nframes; 1065 uint8_t btkillcnt; 1066 uint8_t rtsfailcnt; 1067 uint8_t ackfailcnt; 1068 uint8_t rate; 1069 uint8_t rflags; 1070 uint16_t xrflags; 1071 uint16_t duration; 1072 uint16_t reserved; 1073 uint32_t power[2]; 1074 uint32_t status; 1075} __packed; 1076 1077struct iwn5000_tx_stat { 1078 uint8_t nframes; 1079 uint8_t btkillcnt; 1080 uint8_t rtsfailcnt; 1081 uint8_t ackfailcnt; 1082 uint8_t rate; 1083 uint8_t rflags; 1084 uint16_t xrflags; 1085 uint16_t duration; 1086 uint16_t reserved; 1087 uint32_t power[2]; 1088 uint32_t info; 1089 uint16_t seq; 1090 uint16_t len; 1091 uint8_t tlc; 1092 uint8_t ratid; 1093 uint8_t fc[2]; 1094 uint16_t status; 1095 uint16_t sequence; 1096} __packed; 1097 1098/* Structure for IWN_BEACON_MISSED notification. */ 1099struct iwn_beacon_missed { 1100 uint32_t consecutive; 1101 uint32_t total; 1102 uint32_t expected; 1103 uint32_t received; 1104} __packed; 1105 1106/* Structure for IWN_MPDU_RX_DONE notification. */ 1107struct iwn_rx_mpdu { 1108 uint16_t len; 1109 uint16_t reserved; 1110} __packed; 1111 1112/* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1113struct iwn4965_rx_phystat { 1114 uint16_t antenna; 1115 uint16_t agc; 1116 uint8_t rssi[6]; 1117} __packed; 1118 1119struct iwn5000_rx_phystat { 1120 uint32_t reserved1; 1121 uint32_t agc; 1122 uint16_t rssi[3]; 1123} __packed; 1124 1125struct iwn_rx_stat { 1126 uint8_t phy_len; 1127 uint8_t cfg_phy_len; 1128#define IWN_STAT_MAXLEN 20 1129 1130 uint8_t id; 1131 uint8_t reserved1; 1132 uint64_t tstamp; 1133 uint32_t beacon; 1134 uint16_t flags; 1135#define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1136 1137 uint16_t chan; 1138 uint8_t phybuf[32]; 1139 uint8_t rate; 1140 uint8_t rflags; 1141 uint16_t xrflags; 1142 uint16_t len; 1143 uint16_t reserve3; 1144} __packed; 1145 1146#define IWN_RSSI_TO_DBM 44 1147 1148/* Structure for IWN_RX_COMPRESSED_BA notification. */ 1149struct iwn_compressed_ba { 1150 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1151 uint16_t reserved; 1152 uint8_t id; 1153 uint8_t tid; 1154 uint16_t seq; 1155 uint64_t bitmap; 1156 uint16_t qid; 1157 uint16_t ssn; 1158} __packed; 1159 1160/* Structure for IWN_START_SCAN notification. */ 1161struct iwn_start_scan { 1162 uint64_t tstamp; 1163 uint32_t tbeacon; 1164 uint8_t chan; 1165 uint8_t band; 1166 uint16_t reserved; 1167 uint32_t status; 1168} __packed; 1169 1170/* Structure for IWN_STOP_SCAN notification. */ 1171struct iwn_stop_scan { 1172 uint8_t nchan; 1173 uint8_t status; 1174 uint8_t reserved; 1175 uint8_t chan; 1176 uint64_t tsf; 1177} __packed; 1178 1179/* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1180struct iwn_spectrum_notif { 1181 uint8_t id; 1182 uint8_t token; 1183 uint8_t idx; 1184 uint8_t state; 1185#define IWN_MEASUREMENT_START 0 1186#define IWN_MEASUREMENT_STOP 1 1187 1188 uint32_t start; 1189 uint8_t band; 1190 uint8_t chan; 1191 uint8_t type; 1192 uint8_t reserved1; 1193 uint32_t cca_ofdm; 1194 uint32_t cca_cck; 1195 uint32_t cca_time; 1196 uint8_t basic; 1197 uint8_t reserved2[3]; 1198 uint32_t ofdm[8]; 1199 uint32_t cck[8]; 1200 uint32_t stop; 1201 uint32_t status; 1202#define IWN_MEASUREMENT_OK 0 1203#define IWN_MEASUREMENT_CONCURRENT 1 1204#define IWN_MEASUREMENT_CSA_CONFLICT 2 1205#define IWN_MEASUREMENT_TGH_CONFLICT 3 1206#define IWN_MEASUREMENT_STOPPED 6 1207#define IWN_MEASUREMENT_TIMEOUT 7 1208#define IWN_MEASUREMENT_FAILED 8 1209} __packed; 1210 1211/* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1212struct iwn_rx_phy_stats { 1213 uint32_t ina; 1214 uint32_t fina; 1215 uint32_t bad_plcp; 1216 uint32_t bad_crc32; 1217 uint32_t overrun; 1218 uint32_t eoverrun; 1219 uint32_t good_crc32; 1220 uint32_t fa; 1221 uint32_t bad_fina_sync; 1222 uint32_t sfd_timeout; 1223 uint32_t fina_timeout; 1224 uint32_t no_rts_ack; 1225 uint32_t rxe_limit; 1226 uint32_t ack; 1227 uint32_t cts; 1228 uint32_t ba_resp; 1229 uint32_t dsp_kill; 1230 uint32_t bad_mh; 1231 uint32_t rssi_sum; 1232 uint32_t reserved; 1233} __packed; 1234 1235struct iwn_rx_general_stats { 1236 uint32_t bad_cts; 1237 uint32_t bad_ack; 1238 uint32_t not_bss; 1239 uint32_t filtered; 1240 uint32_t bad_chan; 1241 uint32_t beacons; 1242 uint32_t missed_beacons; 1243 uint32_t adc_saturated; /* time in 0.8us */ 1244 uint32_t ina_searched; /* time in 0.8us */ 1245 uint32_t noise[3]; 1246 uint32_t flags; 1247 uint32_t load; 1248 uint32_t fa; 1249 uint32_t rssi[3]; 1250 uint32_t energy[3]; 1251} __packed; 1252 1253struct iwn_rx_ht_phy_stats { 1254 uint32_t bad_plcp; 1255 uint32_t overrun; 1256 uint32_t eoverrun; 1257 uint32_t good_crc32; 1258 uint32_t bad_crc32; 1259 uint32_t bad_mh; 1260 uint32_t good_ampdu_crc32; 1261 uint32_t ampdu; 1262 uint32_t fragment; 1263 uint32_t reserved; 1264} __packed; 1265 1266struct iwn_rx_stats { 1267 struct iwn_rx_phy_stats ofdm; 1268 struct iwn_rx_phy_stats cck; 1269 struct iwn_rx_general_stats general; 1270 struct iwn_rx_ht_phy_stats ht; 1271} __packed; 1272 1273struct iwn_tx_stats { 1274 uint32_t preamble; 1275 uint32_t rx_detected; 1276 uint32_t bt_defer; 1277 uint32_t bt_kill; 1278 uint32_t short_len; 1279 uint32_t cts_timeout; 1280 uint32_t ack_timeout; 1281 uint32_t exp_ack; 1282 uint32_t ack; 1283 uint32_t msdu; 1284 uint32_t busrt_err1; 1285 uint32_t burst_err2; 1286 uint32_t cts_collision; 1287 uint32_t ack_collision; 1288 uint32_t ba_timeout; 1289 uint32_t ba_resched; 1290 uint32_t query_ampdu; 1291 uint32_t query; 1292 uint32_t query_ampdu_frag; 1293 uint32_t query_mismatch; 1294 uint32_t not_ready; 1295 uint32_t underrun; 1296 uint32_t bt_ht_kill; 1297 uint32_t rx_ba_resp; 1298 uint32_t reserved[2]; 1299} __packed; 1300 1301struct iwn_general_stats { 1302 uint32_t temp; 1303 uint32_t temp_m; 1304 uint32_t burst_check; 1305 uint32_t burst; 1306 uint32_t reserved1[4]; 1307 uint32_t sleep; 1308 uint32_t slot_out; 1309 uint32_t slot_idle; 1310 uint32_t ttl_tstamp; 1311 uint32_t tx_ant_a; 1312 uint32_t tx_ant_b; 1313 uint32_t exec; 1314 uint32_t probe; 1315 uint32_t reserved2[2]; 1316 uint32_t rx_enabled; 1317 uint32_t reserved3[3]; 1318} __packed; 1319 1320struct iwn_stats { 1321 uint32_t flags; 1322 struct iwn_rx_stats rx; 1323 struct iwn_tx_stats tx; 1324 struct iwn_general_stats general; 1325} __packed; 1326 1327 1328/* Firmware error dump. */ 1329struct iwn_fw_dump { 1330 uint32_t valid; 1331 uint32_t id; 1332 uint32_t pc; 1333 uint32_t branch_link[2]; 1334 uint32_t interrupt_link[2]; 1335 uint32_t error_data[2]; 1336 uint32_t src_line; 1337 uint32_t tsf; 1338 uint32_t time[2]; 1339} __packed; 1340 1341/* TLV firmware header. */ 1342struct iwn_fw_tlv_hdr { 1343 uint32_t zero; /* Always 0, to differentiate from legacy. */ 1344 uint32_t signature; 1345#define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */ 1346 1347 uint8_t descr[64]; 1348 uint32_t rev; 1349#define IWN_FW_API(x) (((x) >> 8) & 0xff) 1350 1351 uint32_t build; 1352 uint64_t altmask; 1353} __packed; 1354 1355/* TLV header. */ 1356struct iwn_fw_tlv { 1357 uint16_t type; 1358#define IWN_FW_TLV_MAIN_TEXT 1 1359#define IWN_FW_TLV_MAIN_DATA 2 1360#define IWN_FW_TLV_INIT_TEXT 3 1361#define IWN_FW_TLV_INIT_DATA 4 1362#define IWN_FW_TLV_BOOT_TEXT 5 1363#define IWN_FW_TLV_PBREQ_MAXLEN 6 1364#define IWN_FW_TLV_ENH_SENS 14 1365#define IWN_FW_TLV_PHY_CALIB 15 1366 1367 uint16_t alt; 1368 uint32_t len; 1369} __packed; 1370 1371#define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1372#define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1373#define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1374#define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1375#define IWN_FW_BOOT_TEXT_MAXSZ 1024 1376#define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1377#define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1378 1379/* 1380 * Offsets into EEPROM. 1381 */ 1382#define IWN_EEPROM_MAC 0x015 1383#define IWN_EEPROM_SKU_CAP 0x045 1384#define IWN_EEPROM_RFCFG 0x048 1385#define IWN4965_EEPROM_DOMAIN 0x060 1386#define IWN4965_EEPROM_BAND1 0x063 1387#define IWN5000_EEPROM_REG 0x066 1388#define IWN5000_EEPROM_CAL 0x067 1389#define IWN4965_EEPROM_BAND2 0x072 1390#define IWN4965_EEPROM_BAND3 0x080 1391#define IWN4965_EEPROM_BAND4 0x08d 1392#define IWN4965_EEPROM_BAND5 0x099 1393#define IWN4965_EEPROM_BAND6 0x0a0 1394#define IWN4965_EEPROM_BAND7 0x0a8 1395#define IWN4965_EEPROM_MAXPOW 0x0e8 1396#define IWN4965_EEPROM_VOLTAGE 0x0e9 1397#define IWN4965_EEPROM_BANDS 0x0ea 1398/* Indirect offsets. */ 1399#define IWN5000_EEPROM_DOMAIN 0x001 1400#define IWN5000_EEPROM_BAND1 0x004 1401#define IWN5000_EEPROM_BAND2 0x013 1402#define IWN5000_EEPROM_BAND3 0x021 1403#define IWN5000_EEPROM_BAND4 0x02e 1404#define IWN5000_EEPROM_BAND5 0x03a 1405#define IWN5000_EEPROM_BAND6 0x041 1406#define IWN6000_EEPROM_BAND6 0x040 1407#define IWN5000_EEPROM_BAND7 0x049 1408#define IWN6000_EEPROM_ENHINFO 0x054 1409#define IWN5000_EEPROM_CRYSTAL 0x128 1410#define IWN5000_EEPROM_TEMP 0x12a 1411#define IWN5000_EEPROM_VOLT 0x12b 1412 1413/* Possible flags for IWN_EEPROM_SKU_CAP. */ 1414#define IWN_EEPROM_SKU_CAP_11N (1 << 6) 1415#define IWN_EEPROM_SKU_CAP_AMT (1 << 7) 1416#define IWN_EEPROM_SKU_CAP_IPAN (1 << 8) 1417 1418/* Possible flags for IWN_EEPROM_RFCFG. */ 1419#define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1420#define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1421#define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1422#define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1423#define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1424 1425struct iwn_eeprom_chan { 1426 uint8_t flags; 1427#define IWN_EEPROM_CHAN_VALID (1 << 0) 1428#define IWN_EEPROM_CHAN_IBSS (1 << 1) 1429#define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1430#define IWN_EEPROM_CHAN_RADAR (1 << 4) 1431 1432 int8_t maxpwr; 1433} __packed; 1434 1435struct iwn_eeprom_enhinfo { 1436 uint16_t chan; 1437 int8_t chain[3]; /* max power in half-dBm */ 1438 uint8_t reserved; 1439 int8_t mimo2; /* max power in half-dBm */ 1440 int8_t mimo3; /* max power in half-dBm */ 1441} __packed; 1442 1443struct iwn5000_eeprom_calib_hdr { 1444 uint8_t version; 1445 uint8_t pa_type; 1446 uint16_t volt; 1447} __packed; 1448 1449#define IWN_NSAMPLES 3 1450struct iwn4965_eeprom_chan_samples { 1451 uint8_t num; 1452 struct { 1453 uint8_t temp; 1454 uint8_t gain; 1455 uint8_t power; 1456 int8_t pa_det; 1457 } samples[2][IWN_NSAMPLES]; 1458} __packed; 1459 1460#define IWN_NBANDS 8 1461struct iwn4965_eeprom_band { 1462 uint8_t lo; /* low channel number */ 1463 uint8_t hi; /* high channel number */ 1464 struct iwn4965_eeprom_chan_samples chans[2]; 1465} __packed; 1466 1467/* 1468 * Offsets of channels descriptions in EEPROM. 1469 */ 1470static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1471 IWN4965_EEPROM_BAND1, 1472 IWN4965_EEPROM_BAND2, 1473 IWN4965_EEPROM_BAND3, 1474 IWN4965_EEPROM_BAND4, 1475 IWN4965_EEPROM_BAND5, 1476 IWN4965_EEPROM_BAND6, 1477 IWN4965_EEPROM_BAND7 1478}; 1479 1480static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1481 IWN5000_EEPROM_BAND1, 1482 IWN5000_EEPROM_BAND2, 1483 IWN5000_EEPROM_BAND3, 1484 IWN5000_EEPROM_BAND4, 1485 IWN5000_EEPROM_BAND5, 1486 IWN5000_EEPROM_BAND6, 1487 IWN5000_EEPROM_BAND7 1488}; 1489 1490static const uint32_t iwn6000_regulatory_bands[IWN_NBANDS] = { 1491 IWN5000_EEPROM_BAND1, 1492 IWN5000_EEPROM_BAND2, 1493 IWN5000_EEPROM_BAND3, 1494 IWN5000_EEPROM_BAND4, 1495 IWN5000_EEPROM_BAND5, 1496 IWN6000_EEPROM_BAND6, 1497 IWN5000_EEPROM_BAND7 1498}; 1499 1500#define IWN_CHAN_BANDS_COUNT 7 1501#define IWN_MAX_CHAN_PER_BAND 14 1502static const struct iwn_chan_band { 1503 uint8_t nchan; 1504 uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1505} iwn_bands[] = { 1506 /* 20MHz channels, 2GHz band. */ 1507 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1508 /* 20MHz channels, 5GHz band. */ 1509 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1510 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1511 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1512 { 6, { 145, 149, 153, 157, 161, 165 } }, 1513 /* 40MHz channels (primary channels), 2GHz band. */ 1514 { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1515 /* 40MHz channels (primary channels), 5GHz band. */ 1516 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1517}; 1518 1519#define IWN1000_OTP_NBLOCKS 3 1520#define IWN6000_OTP_NBLOCKS 4 1521#define IWN6050_OTP_NBLOCKS 7 1522 1523/* HW rate indices. */ 1524#define IWN_RIDX_CCK1 0 1525#define IWN_RIDX_OFDM6 4 1526 1527static const struct iwn_rate { 1528 uint8_t rate; 1529 uint8_t plcp; 1530 uint8_t flags; 1531} iwn_rates[IWN_RIDX_MAX + 1] = { 1532 { 2, 10, IWN_RFLAG_CCK }, 1533 { 4, 20, IWN_RFLAG_CCK }, 1534 { 11, 55, IWN_RFLAG_CCK }, 1535 { 22, 110, IWN_RFLAG_CCK }, 1536 { 12, 0xd, 0 }, 1537 { 18, 0xf, 0 }, 1538 { 24, 0x5, 0 }, 1539 { 36, 0x7, 0 }, 1540 { 48, 0x9, 0 }, 1541 { 72, 0xb, 0 }, 1542 { 96, 0x1, 0 }, 1543 { 108, 0x3, 0 }, 1544 { 120, 0x3, 0 } 1545}; 1546 1547#define IWN4965_MAX_PWR_INDEX 107 1548 1549/* 1550 * RF Tx gain values from highest to lowest power (values obtained from 1551 * the reference driver.) 1552 */ 1553static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1554 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 1555 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 1556 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 1557 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 1558 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 1559 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 1560 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1561 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1562 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1563 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1564}; 1565 1566static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1567 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 1568 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 1569 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 1570 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 1571 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 1572 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 1573 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 1574 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 1575 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 1576 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1577}; 1578 1579/* 1580 * DSP pre-DAC gain values from highest to lowest power (values obtained 1581 * from the reference driver.) 1582 */ 1583static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1584 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1585 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1586 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1587 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1588 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1589 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1590 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 1591 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 1592 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 1593 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 1594}; 1595 1596static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1597 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1598 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1599 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1600 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1601 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1602 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1603 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1604 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1605 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1606 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 1607}; 1608 1609/* 1610 * Power saving settings (values obtained from the reference driver.) 1611 */ 1612#define IWN_NDTIMRANGES 3 1613#define IWN_NPOWERLEVELS 6 1614static const struct iwn_pmgt { 1615 uint32_t rxtimeout; 1616 uint32_t txtimeout; 1617 uint32_t intval[5]; 1618 int skip_dtim; 1619} iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 1620 /* DTIM <= 2 */ 1621 { 1622 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1623 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 1624 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 1625 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 1626 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 1627 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 1628 }, 1629 /* 3 <= DTIM <= 10 */ 1630 { 1631 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1632 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 1633 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 1634 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 1635 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 1636 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 1637 }, 1638 /* DTIM >= 11 */ 1639 { 1640 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1641 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 1642 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 1643 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 1644 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 1645 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1646 } 1647}; 1648 1649struct iwn_sensitivity_limits { 1650 uint32_t min_ofdm_x1; 1651 uint32_t max_ofdm_x1; 1652 uint32_t min_ofdm_mrc_x1; 1653 uint32_t max_ofdm_mrc_x1; 1654 uint32_t min_ofdm_x4; 1655 uint32_t max_ofdm_x4; 1656 uint32_t min_ofdm_mrc_x4; 1657 uint32_t max_ofdm_mrc_x4; 1658 uint32_t min_cck_x4; 1659 uint32_t max_cck_x4; 1660 uint32_t min_cck_mrc_x4; 1661 uint32_t max_cck_mrc_x4; 1662 uint32_t min_energy_cck; 1663 uint32_t energy_cck; 1664 uint32_t energy_ofdm; 1665}; 1666 1667/* 1668 * RX sensitivity limits (values obtained from the reference driver.) 1669 */ 1670static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 1671 105, 140, 1672 220, 270, 1673 85, 120, 1674 170, 210, 1675 125, 200, 1676 200, 400, 1677 97, 1678 100, 1679 100 1680}; 1681 1682static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 1683 120, 120, /* min = max for performance bug in DSP. */ 1684 240, 240, /* min = max for performance bug in DSP. */ 1685 90, 120, 1686 170, 210, 1687 125, 200, 1688 170, 400, 1689 95, 1690 95, 1691 95 1692}; 1693 1694static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 1695 105, 105, /* min = max for performance bug in DSP. */ 1696 220, 220, /* min = max for performance bug in DSP. */ 1697 90, 120, 1698 170, 210, 1699 125, 200, 1700 170, 400, 1701 95, 1702 95, 1703 95 1704}; 1705 1706static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 1707 120, 155, 1708 240, 290, 1709 90, 120, 1710 170, 210, 1711 125, 200, 1712 170, 400, 1713 95, 1714 95, 1715 95 1716}; 1717 1718static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 1719 105, 110, 1720 192, 232, 1721 80, 145, 1722 128, 232, 1723 125, 175, 1724 160, 310, 1725 97, 1726 97, 1727 100 1728}; 1729 1730/* Map TID to TX scheduler's FIFO. */ 1731static const uint8_t iwn_tid2fifo[] = { 1732 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 1733}; 1734 1735/* WiFi/WiMAX coexist event priority table for 6050. */ 1736static const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 1737 { 0x04, 0x03, 0x00, 0x00 }, 1738 { 0x04, 0x03, 0x00, 0x03 }, 1739 { 0x04, 0x03, 0x00, 0x03 }, 1740 { 0x04, 0x03, 0x00, 0x03 }, 1741 { 0x04, 0x03, 0x00, 0x00 }, 1742 { 0x04, 0x03, 0x00, 0x07 }, 1743 { 0x04, 0x03, 0x00, 0x00 }, 1744 { 0x04, 0x03, 0x00, 0x03 }, 1745 { 0x04, 0x03, 0x00, 0x03 }, 1746 { 0x04, 0x03, 0x00, 0x00 }, 1747 { 0x06, 0x03, 0x00, 0x07 }, 1748 { 0x04, 0x03, 0x00, 0x00 }, 1749 { 0x06, 0x06, 0x00, 0x03 }, 1750 { 0x04, 0x03, 0x00, 0x07 }, 1751 { 0x04, 0x03, 0x00, 0x00 }, 1752 { 0x04, 0x03, 0x00, 0x00 } 1753}; 1754 1755/* Firmware errors. */ 1756static const char * const iwn_fw_errmsg[] = { 1757 "OK", 1758 "FAIL", 1759 "BAD_PARAM", 1760 "BAD_CHECKSUM", 1761 "NMI_INTERRUPT_WDG", 1762 "SYSASSERT", 1763 "FATAL_ERROR", 1764 "BAD_COMMAND", 1765 "HW_ERROR_TUNE_LOCK", 1766 "HW_ERROR_TEMPERATURE", 1767 "ILLEGAL_CHAN_FREQ", 1768 "VCC_NOT_STABLE", 1769 "FH_ERROR", 1770 "NMI_INTERRUPT_HOST", 1771 "NMI_INTERRUPT_ACTION_PT", 1772 "NMI_INTERRUPT_UNKNOWN", 1773 "UCODE_VERSION_MISMATCH", 1774 "HW_ERROR_ABS_LOCK", 1775 "HW_ERROR_CAL_LOCK_FAIL", 1776 "NMI_INTERRUPT_INST_ACTION_PT", 1777 "NMI_INTERRUPT_DATA_ACTION_PT", 1778 "NMI_TRM_HW_ER", 1779 "NMI_INTERRUPT_TRM", 1780 "NMI_INTERRUPT_BREAKPOINT" 1781 "DEBUG_0", 1782 "DEBUG_1", 1783 "DEBUG_2", 1784 "DEBUG_3", 1785 "ADVANCED_SYSASSERT" 1786}; 1787 1788/* Find least significant bit that is set. */ 1789#define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 1790 1791#define IWN_READ(sc, reg) \ 1792 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1793 1794#define IWN_WRITE(sc, reg, val) \ 1795 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1796 1797#define IWN_WRITE_1(sc, reg, val) \ 1798 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1799 1800#define IWN_SETBITS(sc, reg, mask) \ 1801 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 1802 1803#define IWN_CLRBITS(sc, reg, mask) \ 1804 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 1805 1806#define IWN_BARRIER_WRITE(sc) \ 1807 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1808 BUS_SPACE_BARRIER_WRITE) 1809 1810#define IWN_BARRIER_READ_WRITE(sc) \ 1811 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1812 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 1813