if_iwnreg.h revision 210111
1/* $FreeBSD: head/sys/dev/iwn/if_iwnreg.h 210111 2010-07-15 10:37:49Z bschmidt $ */ 2/* $OpenBSD: if_iwnreg.h,v 1.40 2010/05/05 19:41:57 damien Exp $ */ 3 4/*- 5 * Copyright (c) 2007, 2008 6 * Damien Bergamini <damien.bergamini@free.fr> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21#define IWN_TX_RING_COUNT 256 22#define IWN_TX_RING_LOMARK 192 23#define IWN_TX_RING_HIMARK 224 24#define IWN_RX_RING_COUNT_LOG 6 25#define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 26 27#define IWN4965_NTXQUEUES 16 28#define IWN5000_NTXQUEUES 20 29 30#define IWN4965_NDMACHNLS 7 31#define IWN5000_NDMACHNLS 8 32 33#define IWN_SRVC_DMACHNL 9 34 35#define IWN_ICT_SIZE 4096 36#define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 37 38/* Maximum number of DMA segments for TX. */ 39#define IWN_MAX_SCATTER 20 40 41/* RX buffers must be large enough to hold a full 4K A-MPDU. */ 42#define IWN_RBUF_SIZE (4 * 1024) 43 44#if defined(__LP64__) 45/* HW supports 36-bit DMA addresses. */ 46#define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 47#define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 48#else 49#define IWN_LOADDR(paddr) (paddr) 50#define IWN_HIADDR(paddr) (0) 51#endif 52 53/* Base Address Register. */ 54#define IWN_PCI_BAR0 PCI_MAPREG_START 55 56/* 57 * Control and status registers. 58 */ 59#define IWN_HW_IF_CONFIG 0x000 60#define IWN_INT_COALESCING 0x004 61#define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 62#define IWN_INT 0x008 63#define IWN_INT_MASK 0x00c 64#define IWN_FH_INT 0x010 65#define IWN_RESET 0x020 66#define IWN_GP_CNTRL 0x024 67#define IWN_HW_REV 0x028 68#define IWN_EEPROM 0x02c 69#define IWN_EEPROM_GP 0x030 70#define IWN_OTP_GP 0x034 71#define IWN_GIO 0x03c 72#define IWN_GP_DRIVER 0x050 73#define IWN_UCODE_GP1_CLR 0x05c 74#define IWN_LED 0x094 75#define IWN_DRAM_INT_TBL 0x0a0 76#define IWN_GIO_CHICKEN 0x100 77#define IWN_ANA_PLL 0x20c 78#define IWN_HW_REV_WA 0x22c 79#define IWN_DBG_HPET_MEM 0x240 80#define IWN_DBG_LINK_PWR_MGMT 0x250 81#define IWN_MEM_RADDR 0x40c 82#define IWN_MEM_WADDR 0x410 83#define IWN_MEM_WDATA 0x418 84#define IWN_MEM_RDATA 0x41c 85#define IWN_PRPH_WADDR 0x444 86#define IWN_PRPH_RADDR 0x448 87#define IWN_PRPH_WDATA 0x44c 88#define IWN_PRPH_RDATA 0x450 89#define IWN_HBUS_TARG_WRPTR 0x460 90 91/* 92 * Flow-Handler registers. 93 */ 94#define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 95#define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 96#define IWN_FH_KW_ADDR 0x197c 97#define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 98#define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 99#define IWN_FH_STATUS_WPTR 0x1bc0 100#define IWN_FH_RX_BASE 0x1bc4 101#define IWN_FH_RX_WPTR 0x1bc8 102#define IWN_FH_RX_CONFIG 0x1c00 103#define IWN_FH_RX_STATUS 0x1c44 104#define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 105#define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 106#define IWN_FH_TX_CHICKEN 0x1e98 107#define IWN_FH_TX_STATUS 0x1eb0 108 109/* 110 * TX scheduler registers. 111 */ 112#define IWN_SCHED_BASE 0xa02c00 113#define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 114#define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 115#define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 116#define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 117#define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 118#define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 119#define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 120#define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 121#define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 122#define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 123#define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 124#define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 125#define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 126#define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 127 128/* 129 * Offsets in TX scheduler's SRAM. 130 */ 131#define IWN4965_SCHED_CTX_OFF 0x380 132#define IWN4965_SCHED_CTX_LEN 416 133#define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 134#define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 135#define IWN5000_SCHED_CTX_OFF 0x600 136#define IWN5000_SCHED_CTX_LEN 520 137#define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 138#define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 139 140/* 141 * NIC internal memory offsets. 142 */ 143#define IWN_APMG_CLK_CTRL 0x3000 144#define IWN_APMG_CLK_EN 0x3004 145#define IWN_APMG_CLK_DIS 0x3008 146#define IWN_APMG_PS 0x300c 147#define IWN_APMG_DIGITAL_SVR 0x3058 148#define IWN_APMG_ANALOG_SVR 0x306c 149#define IWN_APMG_PCI_STT 0x3010 150#define IWN_BSM_WR_CTRL 0x3400 151#define IWN_BSM_WR_MEM_SRC 0x3404 152#define IWN_BSM_WR_MEM_DST 0x3408 153#define IWN_BSM_WR_DWCOUNT 0x340c 154#define IWN_BSM_DRAM_TEXT_ADDR 0x3490 155#define IWN_BSM_DRAM_TEXT_SIZE 0x3494 156#define IWN_BSM_DRAM_DATA_ADDR 0x3498 157#define IWN_BSM_DRAM_DATA_SIZE 0x349c 158#define IWN_BSM_SRAM_BASE 0x3800 159 160/* Possible flags for register IWN_HW_IF_CONFIG. */ 161#define IWN_HW_IF_CONFIG_4965_R (1 << 4) 162#define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 163#define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 164#define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 165#define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 166#define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 167#define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 168#define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 169 170/* Possible values for register IWN_INT_PERIODIC. */ 171#define IWN_INT_PERIODIC_DIS 0x00 172#define IWN_INT_PERIODIC_ENA 0xff 173 174/* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 175#define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 176 177/* Possible values for IWN_BSM_WR_MEM_DST. */ 178#define IWN_FW_TEXT_BASE 0x00000000 179#define IWN_FW_DATA_BASE 0x00800000 180 181/* Possible flags for register IWN_RESET. */ 182#define IWN_RESET_NEVO (1 << 0) 183#define IWN_RESET_SW (1 << 7) 184#define IWN_RESET_MASTER_DISABLED (1 << 8) 185#define IWN_RESET_STOP_MASTER (1 << 9) 186#define IWN_RESET_LINK_PWR_MGMT_DIS (1 << 31) 187 188/* Possible flags for register IWN_GP_CNTRL. */ 189#define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 190#define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 191#define IWN_GP_CNTRL_INIT_DONE (1 << 2) 192#define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 193#define IWN_GP_CNTRL_SLEEP (1 << 4) 194#define IWN_GP_CNTRL_RFKILL (1 << 27) 195 196/* Possible flags for register IWN_HW_REV. */ 197#define IWN_HW_REV_TYPE_SHIFT 4 198#define IWN_HW_REV_TYPE_MASK 0x000000f0 199#define IWN_HW_REV_TYPE_4965 0 200#define IWN_HW_REV_TYPE_5300 2 201#define IWN_HW_REV_TYPE_5350 3 202#define IWN_HW_REV_TYPE_5150 4 203#define IWN_HW_REV_TYPE_5100 5 204#define IWN_HW_REV_TYPE_1000 6 205#define IWN_HW_REV_TYPE_6000 7 206#define IWN_HW_REV_TYPE_6050 8 207#define IWN_HW_REV_TYPE_6005 11 208 209/* Possible flags for register IWN_GIO_CHICKEN. */ 210#define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 211#define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 212 213/* Possible flags for register IWN_GIO. */ 214#define IWN_GIO_L0S_ENA (1 << 1) 215 216/* Possible flags for register IWN_GP_DRIVER. */ 217#define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 218#define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 219#define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 220#define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 221 222/* Possible flags for register IWN_UCODE_GP1_CLR. */ 223#define IWN_UCODE_GP1_RFKILL (1 << 1) 224#define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 225#define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 226 227/* Possible flags/values for register IWN_LED. */ 228#define IWN_LED_BSM_CTRL (1 << 5) 229#define IWN_LED_OFF 0x00000038 230#define IWN_LED_ON 0x00000078 231 232/* Possible flags for register IWN_DRAM_INT_TBL. */ 233#define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) 234#define IWN_DRAM_INT_TBL_ENABLE (1 << 31) 235 236/* Possible values for register IWN_ANA_PLL. */ 237#define IWN_ANA_PLL_INIT 0x00880300 238 239/* Possible flags for register IWN_FH_RX_STATUS. */ 240#define IWN_FH_RX_STATUS_IDLE (1 << 24) 241 242/* Possible flags for register IWN_BSM_WR_CTRL. */ 243#define IWN_BSM_WR_CTRL_START_EN (1 << 30) 244#define IWN_BSM_WR_CTRL_START (1 << 31) 245 246/* Possible flags for register IWN_INT. */ 247#define IWN_INT_ALIVE (1 << 0) 248#define IWN_INT_WAKEUP (1 << 1) 249#define IWN_INT_SW_RX (1 << 3) 250#define IWN_INT_CT_REACHED (1 << 6) 251#define IWN_INT_RF_TOGGLED (1 << 7) 252#define IWN_INT_SW_ERR (1 << 25) 253#define IWN_INT_SCHED (1 << 26) 254#define IWN_INT_FH_TX (1 << 27) 255#define IWN_INT_RX_PERIODIC (1 << 28) 256#define IWN_INT_HW_ERR (1 << 29) 257#define IWN_INT_FH_RX (1 << 31) 258 259/* Shortcut. */ 260#define IWN_INT_MASK_DEF \ 261 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 262 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 263 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 264 265/* Possible flags for register IWN_FH_INT. */ 266#define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 267#define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 268#define IWN_FH_INT_HI_PRIOR (1 << 30) 269/* Shortcuts for the above. */ 270#define IWN_FH_INT_TX \ 271 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 272#define IWN_FH_INT_RX \ 273 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 274 275/* Possible flags/values for register IWN_FH_TX_CONFIG. */ 276#define IWN_FH_TX_CONFIG_DMA_PAUSE 0 277#define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 278#define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20) 279 280/* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 281#define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 282#define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 283#define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 284 285/* Possible flags for register IWN_FH_TX_CHICKEN. */ 286#define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 287 288/* Possible flags for register IWN_FH_TX_STATUS. */ 289#define IWN_FH_TX_STATUS_IDLE(chnl) \ 290 (1 << ((chnl) + 24) | 1 << ((chnl) + 16)) 291 292/* Possible flags for register IWN_FH_RX_CONFIG. */ 293#define IWN_FH_RX_CONFIG_ENA (1 << 31) 294#define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 295#define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16) 296#define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15) 297#define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 298#define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 299#define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2) 300 301/* Possible flags for register IWN_FH_TX_CONFIG. */ 302#define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 303#define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3) 304 305/* Possible flags for register IWN_EEPROM. */ 306#define IWN_EEPROM_READ_VALID (1 << 0) 307#define IWN_EEPROM_CMD (1 << 1) 308 309/* Possible flags for register IWN_EEPROM_GP. */ 310#define IWN_EEPROM_GP_IF_OWNER 0x00000180 311 312/* Possible flags for register IWN_OTP_GP. */ 313#define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 314#define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 315#define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 316#define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 317 318/* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 319#define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 320#define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 321#define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 322#define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 323#define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 324#define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 325#define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 326 327/* Possible flags for registers IWN_APMG_CLK_*. */ 328#define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 329#define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 330 331/* Possible flags for register IWN_APMG_PS. */ 332#define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 333#define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 334#define IWN_APMG_PS_PWR_SRC_VMAIN 0 335#define IWN_APMG_PS_PWR_SRC_VAUX 2 336#define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 337#define IWN_APMG_PS_RESET_REQ (1 << 26) 338 339/* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 340#define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 341#define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 342 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 343#define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 344 IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 345 346/* Possible flags for IWN_APMG_PCI_STT. */ 347#define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 348 349/* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 350#define IWN_FW_UPDATED (1 << 31) 351 352#define IWN_SCHED_WINSZ 64 353#define IWN_SCHED_LIMIT 64 354#define IWN4965_SCHED_COUNT 512 355#define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 356#define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 357#define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 358 359struct iwn_tx_desc { 360 uint8_t reserved1[3]; 361 uint8_t nsegs; 362 struct { 363 uint32_t addr; 364 uint16_t len; 365 } __packed segs[IWN_MAX_SCATTER]; 366 /* Pad to 128 bytes. */ 367 uint32_t reserved2; 368} __packed; 369 370struct iwn_rx_status { 371 uint16_t closed_count; 372 uint16_t closed_rx_count; 373 uint16_t finished_count; 374 uint16_t finished_rx_count; 375 uint32_t reserved[2]; 376} __packed; 377 378struct iwn_rx_desc { 379 uint32_t len; 380 uint8_t type; 381#define IWN_UC_READY 1 382#define IWN_ADD_NODE_DONE 24 383#define IWN_TX_DONE 28 384#define IWN5000_CALIBRATION_RESULT 102 385#define IWN5000_CALIBRATION_DONE 103 386#define IWN_START_SCAN 130 387#define IWN_STOP_SCAN 132 388#define IWN_RX_STATISTICS 156 389#define IWN_BEACON_STATISTICS 157 390#define IWN_STATE_CHANGED 161 391#define IWN_BEACON_MISSED 162 392#define IWN_RX_PHY 192 393#define IWN_MPDU_RX_DONE 193 394#define IWN_RX_DONE 195 395#define IWN_RX_COMPRESSED_BA 197 396 397 uint8_t flags; 398 uint8_t idx; 399 uint8_t qid; 400} __packed; 401 402/* Possible RX status flags. */ 403#define IWN_RX_NO_CRC_ERR (1 << 0) 404#define IWN_RX_NO_OVFL_ERR (1 << 1) 405/* Shortcut for the above. */ 406#define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 407#define IWN_RX_MPDU_MIC_OK (1 << 6) 408#define IWN_RX_CIPHER_MASK (7 << 8) 409#define IWN_RX_CIPHER_CCMP (2 << 8) 410#define IWN_RX_MPDU_DEC (1 << 11) 411#define IWN_RX_DECRYPT_MASK (3 << 11) 412#define IWN_RX_DECRYPT_OK (3 << 11) 413 414struct iwn_tx_cmd { 415 uint8_t code; 416#define IWN_CMD_RXON 16 417#define IWN_CMD_RXON_ASSOC 17 418#define IWN_CMD_EDCA_PARAMS 19 419#define IWN_CMD_TIMING 20 420#define IWN_CMD_ADD_NODE 24 421#define IWN_CMD_TX_DATA 28 422#define IWN_CMD_LINK_QUALITY 78 423#define IWN_CMD_SET_LED 72 424#define IWN5000_CMD_WIMAX_COEX 90 425#define IWN5000_CMD_CALIB_CONFIG 101 426#define IWN5000_CMD_CALIB_RESULT 102 427#define IWN5000_CMD_CALIB_COMPLETE 103 428#define IWN_CMD_SET_POWER_MODE 119 429#define IWN_CMD_SCAN 128 430#define IWN_CMD_SCAN_RESULTS 131 431#define IWN_CMD_TXPOWER_DBM 149 432#define IWN_CMD_TXPOWER 151 433#define IWN5000_CMD_TX_ANT_CONFIG 152 434#define IWN_CMD_BT_COEX 155 435#define IWN_CMD_GET_STATISTICS 156 436#define IWN_CMD_SET_CRITICAL_TEMP 164 437#define IWN_CMD_SET_SENSITIVITY 168 438#define IWN_CMD_PHY_CALIB 176 439 440 uint8_t flags; 441 uint8_t idx; 442 uint8_t qid; 443 uint8_t data[136]; 444} __packed; 445 446/* Antenna flags, used in various commands. */ 447#define IWN_ANT_A (1 << 0) 448#define IWN_ANT_B (1 << 1) 449#define IWN_ANT_C (1 << 2) 450/* Shortcuts. */ 451#define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 452#define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 453#define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 454 455/* Structure for command IWN_CMD_RXON. */ 456struct iwn_rxon { 457 uint8_t myaddr[IEEE80211_ADDR_LEN]; 458 uint16_t reserved1; 459 uint8_t bssid[IEEE80211_ADDR_LEN]; 460 uint16_t reserved2; 461 uint8_t wlap[IEEE80211_ADDR_LEN]; 462 uint16_t reserved3; 463 uint8_t mode; 464#define IWN_MODE_HOSTAP 1 465#define IWN_MODE_STA 3 466#define IWN_MODE_IBSS 4 467#define IWN_MODE_MONITOR 6 468 469 uint8_t air; 470 uint16_t rxchain; 471#define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 472#define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 473#define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 474#define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 475#define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 476#define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 477#define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 478 479 uint8_t ofdm_mask; 480 uint8_t cck_mask; 481 uint16_t associd; 482 uint32_t flags; 483#define IWN_RXON_24GHZ (1 << 0) 484#define IWN_RXON_CCK (1 << 1) 485#define IWN_RXON_AUTO (1 << 2) 486#define IWN_RXON_SHSLOT (1 << 4) 487#define IWN_RXON_SHPREAMBLE (1 << 5) 488#define IWN_RXON_NODIVERSITY (1 << 7) 489#define IWN_RXON_ANTENNA_A (1 << 8) 490#define IWN_RXON_ANTENNA_B (1 << 9) 491#define IWN_RXON_TSF (1 << 15) 492#define IWN_RXON_CTS_TO_SELF (1 << 30) 493 494 uint32_t filter; 495#define IWN_FILTER_PROMISC (1 << 0) 496#define IWN_FILTER_CTL (1 << 1) 497#define IWN_FILTER_MULTICAST (1 << 2) 498#define IWN_FILTER_NODECRYPT (1 << 3) 499#define IWN_FILTER_BSS (1 << 5) 500#define IWN_FILTER_BEACON (1 << 6) 501 502 uint8_t chan; 503 uint8_t reserved4; 504 uint8_t ht_single_mask; 505 uint8_t ht_dual_mask; 506 /* The following fields are for >=5000 Series only. */ 507 uint8_t ht_triple_mask; 508 uint8_t reserved5; 509 uint16_t acquisition; 510 uint16_t reserved6; 511} __packed; 512 513#define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 514#define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 515 516/* Structure for command IWN_CMD_ASSOCIATE. */ 517struct iwn_assoc { 518 uint32_t flags; 519 uint32_t filter; 520 uint8_t ofdm_mask; 521 uint8_t cck_mask; 522 uint16_t reserved; 523} __packed; 524 525/* Structure for command IWN_CMD_EDCA_PARAMS. */ 526struct iwn_edca_params { 527 uint32_t flags; 528#define IWN_EDCA_UPDATE (1 << 0) 529#define IWN_EDCA_TXOP (1 << 4) 530 531 struct { 532 uint16_t cwmin; 533 uint16_t cwmax; 534 uint8_t aifsn; 535 uint8_t reserved; 536 uint16_t txoplimit; 537 } __packed ac[WME_NUM_AC]; 538} __packed; 539 540/* Structure for command IWN_CMD_TIMING. */ 541struct iwn_cmd_timing { 542 uint64_t tstamp; 543 uint16_t bintval; 544 uint16_t atim; 545 uint32_t binitval; 546 uint16_t lintval; 547 uint16_t reserved; 548} __packed; 549 550/* Structure for command IWN_CMD_ADD_NODE. */ 551struct iwn_node_info { 552 uint8_t control; 553#define IWN_NODE_UPDATE (1 << 0) 554 555 uint8_t reserved1[3]; 556 557 uint8_t macaddr[IEEE80211_ADDR_LEN]; 558 uint16_t reserved2; 559 uint8_t id; 560#define IWN_ID_BSS 0 561#define IWN5000_ID_BROADCAST 15 562#define IWN4965_ID_BROADCAST 31 563 564 uint8_t flags; 565#define IWN_FLAG_SET_KEY (1 << 0) 566#define IWN_FLAG_SET_DISABLE_TID (1 << 1) 567#define IWN_FLAG_SET_TXRATE (1 << 2) 568#define IWN_FLAG_SET_ADDBA (1 << 3) 569#define IWN_FLAG_SET_DELBA (1 << 4) 570 571 uint16_t reserved3; 572 uint16_t kflags; 573#define IWN_KFLAG_CCMP (1 << 1) 574#define IWN_KFLAG_MAP (1 << 3) 575#define IWN_KFLAG_KID(kid) ((kid) << 8) 576#define IWN_KFLAG_INVALID (1 << 11) 577#define IWN_KFLAG_GROUP (1 << 14) 578 579 uint8_t tsc2; /* TKIP TSC2 */ 580 uint8_t reserved4; 581 uint16_t ttak[5]; 582 uint8_t kid; 583 uint8_t reserved5; 584 uint8_t key[16]; 585 /* The following 3 fields are for 5000 Series only. */ 586 uint64_t tsc; 587 uint8_t rxmic[8]; 588 uint8_t txmic[8]; 589 590 uint32_t htflags; 591#define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 592#define IWN_AMDPU_DENSITY(x) ((x) << 23) 593 594 uint32_t mask; 595 uint16_t disable_tid; 596 uint16_t reserved6; 597 uint8_t addba_tid; 598 uint8_t delba_tid; 599 uint16_t addba_ssn; 600 uint32_t reserved7; 601} __packed; 602 603struct iwn4965_node_info { 604 uint8_t control; 605 uint8_t reserved1[3]; 606 uint8_t macaddr[IEEE80211_ADDR_LEN]; 607 uint16_t reserved2; 608 uint8_t id; 609 uint8_t flags; 610 uint16_t reserved3; 611 uint16_t kflags; 612 uint8_t tsc2; /* TKIP TSC2 */ 613 uint8_t reserved4; 614 uint16_t ttak[5]; 615 uint8_t kid; 616 uint8_t reserved5; 617 uint8_t key[16]; 618 uint32_t htflags; 619 uint32_t mask; 620 uint16_t disable_tid; 621 uint16_t reserved6; 622 uint8_t addba_tid; 623 uint8_t delba_tid; 624 uint16_t addba_ssn; 625 uint32_t reserved7; 626} __packed; 627 628#define IWN_RFLAG_CCK (1 << 1) 629#define IWN_RFLAG_ANT(x) ((x) << 6) 630 631/* Structure for command IWN_CMD_TX_DATA. */ 632struct iwn_cmd_data { 633 uint16_t len; 634 uint16_t lnext; 635 uint32_t flags; 636#define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 637#define IWN_TX_NEED_RTS (1 << 1) 638#define IWN_TX_NEED_CTS (1 << 2) 639#define IWN_TX_NEED_ACK (1 << 3) 640#define IWN_TX_LINKQ (1 << 4) 641#define IWN_TX_IMM_BA (1 << 6) 642#define IWN_TX_FULL_TXOP (1 << 7) 643#define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 644#define IWN_TX_AUTO_SEQ (1 << 13) 645#define IWN_TX_MORE_FRAG (1 << 14) 646#define IWN_TX_INSERT_TSTAMP (1 << 16) 647#define IWN_TX_NEED_PADDING (1 << 20) 648 649 uint32_t scratch; 650 uint8_t plcp; 651 uint8_t rflags; 652 uint16_t xrflags; 653 654 uint8_t id; 655 uint8_t security; 656#define IWN_CIPHER_WEP40 1 657#define IWN_CIPHER_CCMP 2 658#define IWN_CIPHER_TKIP 3 659#define IWN_CIPHER_WEP104 9 660 661 uint8_t linkq; 662 uint8_t reserved2; 663 uint8_t key[16]; 664 uint16_t fnext; 665 uint16_t reserved3; 666 uint32_t lifetime; 667#define IWN_LIFETIME_INFINITE 0xffffffff 668 669 uint32_t loaddr; 670 uint8_t hiaddr; 671 uint8_t rts_ntries; 672 uint8_t data_ntries; 673 uint8_t tid; 674 uint16_t timeout; 675 uint16_t txop; 676} __packed; 677 678/* Structure for command IWN_CMD_LINK_QUALITY. */ 679#define IWN_MAX_TX_RETRIES 16 680struct iwn_cmd_link_quality { 681 uint8_t id; 682 uint8_t reserved1; 683 uint16_t ctl; 684 uint8_t flags; 685 uint8_t mimo; 686 uint8_t antmsk_1stream; 687 uint8_t antmsk_2stream; 688 uint8_t ridx[WME_NUM_AC]; 689 uint16_t ampdu_limit; 690 uint8_t ampdu_threshold; 691 uint8_t ampdu_max; 692 uint32_t reserved2; 693 struct { 694 uint8_t plcp; 695 uint8_t rflags; 696 uint16_t xrflags; 697 } __packed retry[IWN_MAX_TX_RETRIES]; 698 uint32_t reserved3; 699} __packed; 700 701/* Structure for command IWN_CMD_SET_LED. */ 702struct iwn_cmd_led { 703 uint32_t unit; /* multiplier (in usecs) */ 704 uint8_t which; 705#define IWN_LED_ACTIVITY 1 706#define IWN_LED_LINK 2 707 708 uint8_t off; 709 uint8_t on; 710 uint8_t reserved; 711} __packed; 712 713/* Structure for command IWN5000_CMD_WIMAX_COEX. */ 714struct iwn5000_wimax_coex { 715 uint32_t flags; 716#define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 717#define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 718#define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 719#define IWN_WIMAX_COEX_ENABLE (1 << 7) 720 721 struct iwn5000_wimax_event { 722 uint8_t request; 723 uint8_t window; 724 uint8_t reserved; 725 uint8_t flags; 726 } __packed events[16]; 727} __packed; 728 729/* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 730struct iwn5000_calib_elem { 731 uint32_t enable; 732 uint32_t start; 733 uint32_t send; 734 uint32_t apply; 735 uint32_t reserved; 736} __packed; 737 738struct iwn5000_calib_status { 739 struct iwn5000_calib_elem once; 740 struct iwn5000_calib_elem perd; 741 uint32_t flags; 742} __packed; 743 744struct iwn5000_calib_config { 745 struct iwn5000_calib_status ucode; 746 struct iwn5000_calib_status driver; 747 uint32_t reserved; 748} __packed; 749 750/* Structure for command IWN_CMD_SET_POWER_MODE. */ 751struct iwn_pmgt_cmd { 752 uint16_t flags; 753#define IWN_PS_ALLOW_SLEEP (1 << 0) 754#define IWN_PS_NOTIFY (1 << 1) 755#define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 756#define IWN_PS_PCI_PMGT (1 << 3) 757#define IWN_PS_FAST_PD (1 << 4) 758 759 uint8_t keepalive; 760 uint8_t debug; 761 uint32_t rxtimeout; 762 uint32_t txtimeout; 763 uint32_t intval[5]; 764 uint32_t beacons; 765} __packed; 766 767/* Structures for command IWN_CMD_SCAN. */ 768struct iwn_scan_essid { 769 uint8_t id; 770 uint8_t len; 771 uint8_t data[IEEE80211_NWID_LEN]; 772} __packed; 773 774struct iwn_scan_hdr { 775 uint16_t len; 776 uint8_t reserved1; 777 uint8_t nchan; 778 uint16_t quiet_time; 779 uint16_t quiet_threshold; 780 uint16_t crc_threshold; 781 uint16_t rxchain; 782 uint32_t max_svc; /* background scans */ 783 uint32_t pause_svc; /* background scans */ 784 uint32_t flags; 785 uint32_t filter; 786 787 /* Followed by a struct iwn_cmd_data. */ 788 /* Followed by an array of 20 structs iwn_scan_essid. */ 789 /* Followed by probe request body. */ 790 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 791} __packed; 792 793struct iwn_scan_chan { 794 uint32_t flags; 795#define IWN_CHAN_ACTIVE (1 << 0) 796#define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 797 798 uint16_t chan; 799 uint8_t rf_gain; 800 uint8_t dsp_gain; 801 uint16_t active; /* msecs */ 802 uint16_t passive; /* msecs */ 803} __packed; 804 805/* Maximum size of a scan command. */ 806#define IWN_SCAN_MAXSZ (MCLBYTES - 4) 807 808/* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 809#define IWN_RIDX_MAX 32 810struct iwn4965_cmd_txpower { 811 uint8_t band; 812 uint8_t reserved1; 813 uint8_t chan; 814 uint8_t reserved2; 815 struct { 816 uint8_t rf_gain[2]; 817 uint8_t dsp_gain[2]; 818 } __packed power[IWN_RIDX_MAX + 1]; 819} __packed; 820 821/* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 822struct iwn5000_cmd_txpower { 823 int8_t global_limit; /* in half-dBm */ 824#define IWN5000_TXPOWER_AUTO 0x7f 825#define IWN5000_TXPOWER_MAX_DBM 16 826 827 uint8_t flags; 828#define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 829 830 int8_t srv_limit; /* in half-dBm */ 831 uint8_t reserved; 832} __packed; 833 834/* Structure for command IWN_CMD_BLUETOOTH. */ 835struct iwn_bluetooth { 836 uint8_t flags; 837#define IWN_BT_COEX_CHAN_ANN (1 << 0) 838#define IWN_BT_COEX_BT_PRIO (1 << 1) 839#define IWN_BT_COEX_2_WIRE (1 << 2) 840 841 uint8_t lead_time; 842#define IWN_BT_LEAD_TIME_DEF 30 843 844 uint8_t max_kill; 845#define IWN_BT_MAX_KILL_DEF 5 846 847 uint8_t reserved; 848 uint32_t kill_ack; 849 uint32_t kill_cts; 850} __packed; 851 852/* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 853struct iwn_critical_temp { 854 uint32_t reserved; 855 uint32_t tempM; 856 uint32_t tempR; 857/* degK <-> degC conversion macros. */ 858#define IWN_CTOK(c) ((c) + 273) 859#define IWN_KTOC(k) ((k) - 273) 860#define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 861} __packed; 862 863/* Structure for command IWN_CMD_SET_SENSITIVITY. */ 864struct iwn_sensitivity_cmd { 865 uint16_t which; 866#define IWN_SENSITIVITY_DEFAULTTBL 0 867#define IWN_SENSITIVITY_WORKTBL 1 868 869 uint16_t energy_cck; 870 uint16_t energy_ofdm; 871 uint16_t corr_ofdm_x1; 872 uint16_t corr_ofdm_mrc_x1; 873 uint16_t corr_cck_mrc_x4; 874 uint16_t corr_ofdm_x4; 875 uint16_t corr_ofdm_mrc_x4; 876 uint16_t corr_barker; 877 uint16_t corr_barker_mrc; 878 uint16_t corr_cck_x4; 879 uint16_t energy_ofdm_th; 880} __packed; 881 882/* Structures for command IWN_CMD_PHY_CALIB. */ 883struct iwn_phy_calib { 884 uint8_t code; 885#define IWN4965_PHY_CALIB_DIFF_GAIN 7 886#define IWN5000_PHY_CALIB_DC 8 887#define IWN5000_PHY_CALIB_LO 9 888#define IWN5000_PHY_CALIB_TX_IQ 11 889#define IWN5000_PHY_CALIB_CRYSTAL 15 890#define IWN5000_PHY_CALIB_BASE_BAND 16 891#define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 892#define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 893#define IWN5000_PHY_CALIB_NOISE_GAIN 19 894 895 uint8_t group; 896 uint8_t ngroups; 897 uint8_t isvalid; 898} __packed; 899 900struct iwn5000_phy_calib_crystal { 901 uint8_t code; 902 uint8_t group; 903 uint8_t ngroups; 904 uint8_t isvalid; 905 906 uint8_t cap_pin[2]; 907 uint8_t reserved[2]; 908} __packed; 909 910struct iwn_phy_calib_gain { 911 uint8_t code; 912 uint8_t group; 913 uint8_t ngroups; 914 uint8_t isvalid; 915 916 int8_t gain[3]; 917 uint8_t reserved; 918} __packed; 919 920/* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 921struct iwn_spectrum_cmd { 922 uint16_t len; 923 uint8_t token; 924 uint8_t id; 925 uint8_t origin; 926 uint8_t periodic; 927 uint16_t timeout; 928 uint32_t start; 929 uint32_t reserved1; 930 uint32_t flags; 931 uint32_t filter; 932 uint16_t nchan; 933 uint16_t reserved2; 934 struct { 935 uint32_t duration; 936 uint8_t chan; 937 uint8_t type; 938#define IWN_MEASUREMENT_BASIC (1 << 0) 939#define IWN_MEASUREMENT_CCA (1 << 1) 940#define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 941#define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 942#define IWN_MEASUREMENT_FRAME (1 << 4) 943#define IWN_MEASUREMENT_IDLE (1 << 7) 944 945 uint16_t reserved; 946 } __packed chan[10]; 947} __packed; 948 949/* Structure for IWN_UC_READY notification. */ 950#define IWN_NATTEN_GROUPS 5 951struct iwn_ucode_info { 952 uint8_t minor; 953 uint8_t major; 954 uint16_t reserved1; 955 uint8_t revision[8]; 956 uint8_t type; 957 uint8_t subtype; 958#define IWN_UCODE_RUNTIME 0 959#define IWN_UCODE_INIT 9 960 961 uint16_t reserved2; 962 uint32_t logptr; 963 uint32_t errptr; 964 uint32_t tstamp; 965 uint32_t valid; 966 967 /* The following fields are for UCODE_INIT only. */ 968 int32_t volt; 969 struct { 970 int32_t chan20MHz; 971 int32_t chan40MHz; 972 } __packed temp[4]; 973 int32_t atten[IWN_NATTEN_GROUPS][2]; 974} __packed; 975 976/* Structures for IWN_TX_DONE notification. */ 977#define IWN_TX_SUCCESS 0x00 978#define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */ 979#define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */ 980#define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */ 981#define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */ 982#define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */ 983#define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */ 984 985struct iwn4965_tx_stat { 986 uint8_t nframes; 987 uint8_t btkillcnt; 988 uint8_t rtsfailcnt; 989 uint8_t ackfailcnt; 990 uint8_t rate; 991 uint8_t rflags; 992 uint16_t xrflags; 993 uint16_t duration; 994 uint16_t reserved; 995 uint32_t power[2]; 996 uint32_t status; 997} __packed; 998 999struct iwn5000_tx_stat { 1000 uint8_t nframes; 1001 uint8_t btkillcnt; 1002 uint8_t rtsfailcnt; 1003 uint8_t ackfailcnt; 1004 uint8_t rate; 1005 uint8_t rflags; 1006 uint16_t xrflags; 1007 uint16_t duration; 1008 uint16_t reserved; 1009 uint32_t power[2]; 1010 uint32_t info; 1011 uint16_t seq; 1012 uint16_t len; 1013 uint8_t tlc; 1014 uint8_t ratid; 1015 uint8_t fc[2]; 1016 uint16_t status; 1017 uint16_t sequence; 1018} __packed; 1019 1020/* Structure for IWN_BEACON_MISSED notification. */ 1021struct iwn_beacon_missed { 1022 uint32_t consecutive; 1023 uint32_t total; 1024 uint32_t expected; 1025 uint32_t received; 1026} __packed; 1027 1028/* Structure for IWN_MPDU_RX_DONE notification. */ 1029struct iwn_rx_mpdu { 1030 uint16_t len; 1031 uint16_t reserved; 1032} __packed; 1033 1034/* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1035struct iwn4965_rx_phystat { 1036 uint16_t antenna; 1037 uint16_t agc; 1038 uint8_t rssi[6]; 1039} __packed; 1040 1041struct iwn5000_rx_phystat { 1042 uint32_t reserved1; 1043 uint32_t agc; 1044 uint16_t rssi[3]; 1045} __packed; 1046 1047struct iwn_rx_stat { 1048 uint8_t phy_len; 1049 uint8_t cfg_phy_len; 1050#define IWN_STAT_MAXLEN 20 1051 1052 uint8_t id; 1053 uint8_t reserved1; 1054 uint64_t tstamp; 1055 uint32_t beacon; 1056 uint16_t flags; 1057#define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1058 1059 uint16_t chan; 1060 uint8_t phybuf[32]; 1061 uint8_t rate; 1062 uint8_t rflags; 1063 uint16_t xrflags; 1064 uint16_t len; 1065 uint16_t reserve3; 1066} __packed; 1067 1068#define IWN_RSSI_TO_DBM 44 1069 1070/* Structure for IWN_RX_COMPRESSED_BA notification. */ 1071struct iwn_compressed_ba { 1072 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1073 uint16_t reserved; 1074 uint8_t id; 1075 uint8_t tid; 1076 uint16_t seq; 1077 uint64_t bitmap; 1078 uint16_t qid; 1079 uint16_t ssn; 1080} __packed; 1081 1082/* Structure for IWN_START_SCAN notification. */ 1083struct iwn_start_scan { 1084 uint64_t tstamp; 1085 uint32_t tbeacon; 1086 uint8_t chan; 1087 uint8_t band; 1088 uint16_t reserved; 1089 uint32_t status; 1090} __packed; 1091 1092/* Structure for IWN_STOP_SCAN notification. */ 1093struct iwn_stop_scan { 1094 uint8_t nchan; 1095 uint8_t status; 1096 uint8_t reserved; 1097 uint8_t chan; 1098 uint64_t tsf; 1099} __packed; 1100 1101/* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1102struct iwn_spectrum_notif { 1103 uint8_t id; 1104 uint8_t token; 1105 uint8_t idx; 1106 uint8_t state; 1107#define IWN_MEASUREMENT_START 0 1108#define IWN_MEASUREMENT_STOP 1 1109 1110 uint32_t start; 1111 uint8_t band; 1112 uint8_t chan; 1113 uint8_t type; 1114 uint8_t reserved1; 1115 uint32_t cca_ofdm; 1116 uint32_t cca_cck; 1117 uint32_t cca_time; 1118 uint8_t basic; 1119 uint8_t reserved2[3]; 1120 uint32_t ofdm[8]; 1121 uint32_t cck[8]; 1122 uint32_t stop; 1123 uint32_t status; 1124#define IWN_MEASUREMENT_OK 0 1125#define IWN_MEASUREMENT_CONCURRENT 1 1126#define IWN_MEASUREMENT_CSA_CONFLICT 2 1127#define IWN_MEASUREMENT_TGH_CONFLICT 3 1128#define IWN_MEASUREMENT_STOPPED 6 1129#define IWN_MEASUREMENT_TIMEOUT 7 1130#define IWN_MEASUREMENT_FAILED 8 1131} __packed; 1132 1133/* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1134struct iwn_rx_phy_stats { 1135 uint32_t ina; 1136 uint32_t fina; 1137 uint32_t bad_plcp; 1138 uint32_t bad_crc32; 1139 uint32_t overrun; 1140 uint32_t eoverrun; 1141 uint32_t good_crc32; 1142 uint32_t fa; 1143 uint32_t bad_fina_sync; 1144 uint32_t sfd_timeout; 1145 uint32_t fina_timeout; 1146 uint32_t no_rts_ack; 1147 uint32_t rxe_limit; 1148 uint32_t ack; 1149 uint32_t cts; 1150 uint32_t ba_resp; 1151 uint32_t dsp_kill; 1152 uint32_t bad_mh; 1153 uint32_t rssi_sum; 1154 uint32_t reserved; 1155} __packed; 1156 1157struct iwn_rx_general_stats { 1158 uint32_t bad_cts; 1159 uint32_t bad_ack; 1160 uint32_t not_bss; 1161 uint32_t filtered; 1162 uint32_t bad_chan; 1163 uint32_t beacons; 1164 uint32_t missed_beacons; 1165 uint32_t adc_saturated; /* time in 0.8us */ 1166 uint32_t ina_searched; /* time in 0.8us */ 1167 uint32_t noise[3]; 1168 uint32_t flags; 1169 uint32_t load; 1170 uint32_t fa; 1171 uint32_t rssi[3]; 1172 uint32_t energy[3]; 1173} __packed; 1174 1175struct iwn_rx_ht_phy_stats { 1176 uint32_t bad_plcp; 1177 uint32_t overrun; 1178 uint32_t eoverrun; 1179 uint32_t good_crc32; 1180 uint32_t bad_crc32; 1181 uint32_t bad_mh; 1182 uint32_t good_ampdu_crc32; 1183 uint32_t ampdu; 1184 uint32_t fragment; 1185 uint32_t reserved; 1186} __packed; 1187 1188struct iwn_rx_stats { 1189 struct iwn_rx_phy_stats ofdm; 1190 struct iwn_rx_phy_stats cck; 1191 struct iwn_rx_general_stats general; 1192 struct iwn_rx_ht_phy_stats ht; 1193} __packed; 1194 1195struct iwn_tx_stats { 1196 uint32_t preamble; 1197 uint32_t rx_detected; 1198 uint32_t bt_defer; 1199 uint32_t bt_kill; 1200 uint32_t short_len; 1201 uint32_t cts_timeout; 1202 uint32_t ack_timeout; 1203 uint32_t exp_ack; 1204 uint32_t ack; 1205 uint32_t msdu; 1206 uint32_t busrt_err1; 1207 uint32_t burst_err2; 1208 uint32_t cts_collision; 1209 uint32_t ack_collision; 1210 uint32_t ba_timeout; 1211 uint32_t ba_resched; 1212 uint32_t query_ampdu; 1213 uint32_t query; 1214 uint32_t query_ampdu_frag; 1215 uint32_t query_mismatch; 1216 uint32_t not_ready; 1217 uint32_t underrun; 1218 uint32_t bt_ht_kill; 1219 uint32_t rx_ba_resp; 1220 uint32_t reserved[2]; 1221} __packed; 1222 1223struct iwn_general_stats { 1224 uint32_t temp; 1225 uint32_t temp_m; 1226 uint32_t burst_check; 1227 uint32_t burst; 1228 uint32_t reserved1[4]; 1229 uint32_t sleep; 1230 uint32_t slot_out; 1231 uint32_t slot_idle; 1232 uint32_t ttl_tstamp; 1233 uint32_t tx_ant_a; 1234 uint32_t tx_ant_b; 1235 uint32_t exec; 1236 uint32_t probe; 1237 uint32_t reserved2[2]; 1238 uint32_t rx_enabled; 1239 uint32_t reserved3[3]; 1240} __packed; 1241 1242struct iwn_stats { 1243 uint32_t flags; 1244 struct iwn_rx_stats rx; 1245 struct iwn_tx_stats tx; 1246 struct iwn_general_stats general; 1247} __packed; 1248 1249 1250/* Firmware error dump. */ 1251struct iwn_fw_dump { 1252 uint32_t valid; 1253 uint32_t id; 1254 uint32_t pc; 1255 uint32_t branch_link[2]; 1256 uint32_t interrupt_link[2]; 1257 uint32_t error_data[2]; 1258 uint32_t src_line; 1259 uint32_t tsf; 1260 uint32_t time[2]; 1261} __packed; 1262 1263/* TLV firmware header. */ 1264struct iwn_fw_tlv_hdr { 1265 uint32_t zero; /* Always 0, to differentiate from legacy. */ 1266 uint32_t signature; 1267#define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */ 1268 1269 uint8_t descr[64]; 1270 uint32_t rev; 1271#define IWN_FW_API(x) (((x) >> 8) & 0xff) 1272 1273 uint32_t build; 1274 uint64_t altmask; 1275} __packed; 1276 1277/* TLV header. */ 1278struct iwn_fw_tlv { 1279 uint16_t type; 1280#define IWN_FW_TLV_MAIN_TEXT 1 1281#define IWN_FW_TLV_MAIN_DATA 2 1282#define IWN_FW_TLV_INIT_TEXT 3 1283#define IWN_FW_TLV_INIT_DATA 4 1284#define IWN_FW_TLV_BOOT_TEXT 5 1285#define IWN_FW_TLV_PBREQ_MAXLEN 6 1286 1287 uint16_t alt; 1288 uint32_t len; 1289} __packed; 1290 1291#define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1292#define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1293#define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1294#define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1295#define IWN_FW_BOOT_TEXT_MAXSZ 1024 1296#define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1297#define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1298 1299/* 1300 * Offsets into EEPROM. 1301 */ 1302#define IWN_EEPROM_MAC 0x015 1303#define IWN_EEPROM_RFCFG 0x048 1304#define IWN4965_EEPROM_DOMAIN 0x060 1305#define IWN4965_EEPROM_BAND1 0x063 1306#define IWN5000_EEPROM_REG 0x066 1307#define IWN5000_EEPROM_CAL 0x067 1308#define IWN4965_EEPROM_BAND2 0x072 1309#define IWN4965_EEPROM_BAND3 0x080 1310#define IWN4965_EEPROM_BAND4 0x08d 1311#define IWN4965_EEPROM_BAND5 0x099 1312#define IWN4965_EEPROM_BAND6 0x0a0 1313#define IWN4965_EEPROM_BAND7 0x0a8 1314#define IWN4965_EEPROM_MAXPOW 0x0e8 1315#define IWN4965_EEPROM_VOLTAGE 0x0e9 1316#define IWN4965_EEPROM_BANDS 0x0ea 1317/* Indirect offsets. */ 1318#define IWN5000_EEPROM_DOMAIN 0x001 1319#define IWN5000_EEPROM_BAND1 0x004 1320#define IWN5000_EEPROM_BAND2 0x013 1321#define IWN5000_EEPROM_BAND3 0x021 1322#define IWN5000_EEPROM_BAND4 0x02e 1323#define IWN5000_EEPROM_BAND5 0x03a 1324#define IWN5000_EEPROM_BAND6 0x041 1325#define IWN5000_EEPROM_BAND7 0x049 1326#define IWN6000_EEPROM_ENHINFO 0x054 1327#define IWN5000_EEPROM_CRYSTAL 0x128 1328#define IWN5000_EEPROM_TEMP 0x12a 1329#define IWN5000_EEPROM_VOLT 0x12b 1330 1331/* Possible flags for IWN_EEPROM_RFCFG. */ 1332#define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1333#define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1334#define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1335#define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1336#define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1337 1338struct iwn_eeprom_chan { 1339 uint8_t flags; 1340#define IWN_EEPROM_CHAN_VALID (1 << 0) 1341#define IWN_EEPROM_CHAN_IBSS (1 << 1) 1342#define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1343#define IWN_EEPROM_CHAN_RADAR (1 << 4) 1344 1345 int8_t maxpwr; 1346} __packed; 1347 1348struct iwn_eeprom_enhinfo { 1349 uint16_t chan; 1350 int8_t chain[3]; /* max power in half-dBm */ 1351 uint8_t reserved; 1352 int8_t mimo2; /* max power in half-dBm */ 1353 int8_t mimo3; /* max power in half-dBm */ 1354} __packed; 1355 1356struct iwn5000_eeprom_calib_hdr { 1357 uint8_t version; 1358 uint8_t pa_type; 1359 uint16_t volt; 1360} __packed; 1361 1362#define IWN_NSAMPLES 3 1363struct iwn4965_eeprom_chan_samples { 1364 uint8_t num; 1365 struct { 1366 uint8_t temp; 1367 uint8_t gain; 1368 uint8_t power; 1369 int8_t pa_det; 1370 } samples[2][IWN_NSAMPLES]; 1371} __packed; 1372 1373#define IWN_NBANDS 8 1374struct iwn4965_eeprom_band { 1375 uint8_t lo; /* low channel number */ 1376 uint8_t hi; /* high channel number */ 1377 struct iwn4965_eeprom_chan_samples chans[2]; 1378} __packed; 1379 1380/* 1381 * Offsets of channels descriptions in EEPROM. 1382 */ 1383static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1384 IWN4965_EEPROM_BAND1, 1385 IWN4965_EEPROM_BAND2, 1386 IWN4965_EEPROM_BAND3, 1387 IWN4965_EEPROM_BAND4, 1388 IWN4965_EEPROM_BAND5, 1389 IWN4965_EEPROM_BAND6, 1390 IWN4965_EEPROM_BAND7 1391}; 1392 1393static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1394 IWN5000_EEPROM_BAND1, 1395 IWN5000_EEPROM_BAND2, 1396 IWN5000_EEPROM_BAND3, 1397 IWN5000_EEPROM_BAND4, 1398 IWN5000_EEPROM_BAND5, 1399 IWN5000_EEPROM_BAND6, 1400 IWN5000_EEPROM_BAND7 1401}; 1402 1403#define IWN_CHAN_BANDS_COUNT 7 1404#define IWN_MAX_CHAN_PER_BAND 14 1405static const struct iwn_chan_band { 1406 uint8_t nchan; 1407 uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1408} iwn_bands[] = { 1409 /* 20MHz channels, 2GHz band. */ 1410 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1411 /* 20MHz channels, 5GHz band. */ 1412 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1413 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1414 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1415 { 6, { 145, 149, 153, 157, 161, 165 } }, 1416 /* 40MHz channels (primary channels), 2GHz band. */ 1417 { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1418 /* 40MHz channels (primary channels), 5GHz band. */ 1419 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1420}; 1421 1422#define IWN1000_OTP_NBLOCKS 3 1423#define IWN6000_OTP_NBLOCKS 4 1424#define IWN6050_OTP_NBLOCKS 7 1425 1426/* HW rate indices. */ 1427#define IWN_RIDX_CCK1 0 1428#define IWN_RIDX_CCK11 3 1429#define IWN_RIDX_OFDM6 4 1430#define IWN_RIDX_OFDM54 11 1431 1432static const struct iwn_rate { 1433 uint8_t rate; 1434 uint8_t plcp; 1435 uint8_t flags; 1436} iwn_rates[IWN_RIDX_MAX + 1] = { 1437 { 2, 10, IWN_RFLAG_CCK }, 1438 { 4, 20, IWN_RFLAG_CCK }, 1439 { 11, 55, IWN_RFLAG_CCK }, 1440 { 22, 110, IWN_RFLAG_CCK }, 1441 { 12, 0xd, 0 }, 1442 { 18, 0xf, 0 }, 1443 { 24, 0x5, 0 }, 1444 { 36, 0x7, 0 }, 1445 { 48, 0x9, 0 }, 1446 { 72, 0xb, 0 }, 1447 { 96, 0x1, 0 }, 1448 { 108, 0x3, 0 }, 1449 { 120, 0x3, 0 } 1450}; 1451 1452#define IWN4965_MAX_PWR_INDEX 107 1453 1454/* 1455 * RF Tx gain values from highest to lowest power (values obtained from 1456 * the reference driver.) 1457 */ 1458static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1459 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 1460 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 1461 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 1462 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 1463 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 1464 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 1465 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1466 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1467 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1468 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1469}; 1470 1471static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1472 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 1473 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 1474 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 1475 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 1476 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 1477 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 1478 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 1479 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 1480 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 1481 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1482}; 1483 1484/* 1485 * DSP pre-DAC gain values from highest to lowest power (values obtained 1486 * from the reference driver.) 1487 */ 1488static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1489 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1490 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1491 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1492 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1493 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1494 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1495 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 1496 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 1497 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 1498 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 1499}; 1500 1501static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1502 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1503 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1504 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1505 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1506 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1507 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1508 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1509 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1510 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1511 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 1512}; 1513 1514/* 1515 * Power saving settings (values obtained from the reference driver.) 1516 */ 1517#define IWN_NDTIMRANGES 3 1518#define IWN_NPOWERLEVELS 6 1519static const struct iwn_pmgt { 1520 uint32_t rxtimeout; 1521 uint32_t txtimeout; 1522 uint32_t intval[5]; 1523 int skip_dtim; 1524} iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 1525 /* DTIM <= 2 */ 1526 { 1527 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1528 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 1529 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 1530 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 1531 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 1532 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 1533 }, 1534 /* 3 <= DTIM <= 10 */ 1535 { 1536 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1537 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 1538 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 1539 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 1540 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 1541 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 1542 }, 1543 /* DTIM >= 11 */ 1544 { 1545 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1546 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 1547 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 1548 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 1549 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 1550 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1551 } 1552}; 1553 1554struct iwn_sensitivity_limits { 1555 uint32_t min_ofdm_x1; 1556 uint32_t max_ofdm_x1; 1557 uint32_t min_ofdm_mrc_x1; 1558 uint32_t max_ofdm_mrc_x1; 1559 uint32_t min_ofdm_x4; 1560 uint32_t max_ofdm_x4; 1561 uint32_t min_ofdm_mrc_x4; 1562 uint32_t max_ofdm_mrc_x4; 1563 uint32_t min_cck_x4; 1564 uint32_t max_cck_x4; 1565 uint32_t min_cck_mrc_x4; 1566 uint32_t max_cck_mrc_x4; 1567 uint32_t min_energy_cck; 1568 uint32_t energy_cck; 1569 uint32_t energy_ofdm; 1570}; 1571 1572/* 1573 * RX sensitivity limits (values obtained from the reference driver.) 1574 */ 1575static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 1576 105, 140, 1577 220, 270, 1578 85, 120, 1579 170, 210, 1580 125, 200, 1581 200, 400, 1582 97, 1583 100, 1584 100 1585}; 1586 1587static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 1588 120, 120, /* min = max for performance bug in DSP. */ 1589 240, 240, /* min = max for performance bug in DSP. */ 1590 90, 120, 1591 170, 210, 1592 125, 200, 1593 170, 400, 1594 95, 1595 95, 1596 95 1597}; 1598 1599static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 1600 105, 105, /* min = max for performance bug in DSP. */ 1601 220, 220, /* min = max for performance bug in DSP. */ 1602 90, 120, 1603 170, 210, 1604 125, 200, 1605 170, 400, 1606 95, 1607 95, 1608 95 1609}; 1610 1611static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 1612 120, 155, 1613 240, 290, 1614 90, 120, 1615 170, 210, 1616 125, 200, 1617 170, 400, 1618 95, 1619 95, 1620 95 1621}; 1622 1623static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 1624 105, 110, 1625 192, 232, 1626 80, 145, 1627 128, 232, 1628 125, 175, 1629 160, 310, 1630 97, 1631 97, 1632 100 1633}; 1634 1635/* Map TID to TX scheduler's FIFO. */ 1636static const uint8_t iwn_tid2fifo[] = { 1637 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 1638}; 1639 1640/* WiFi/WiMAX coexist event priority table for 6050. */ 1641static const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 1642 { 0x04, 0x03, 0x00, 0x00 }, 1643 { 0x04, 0x03, 0x00, 0x03 }, 1644 { 0x04, 0x03, 0x00, 0x03 }, 1645 { 0x04, 0x03, 0x00, 0x03 }, 1646 { 0x04, 0x03, 0x00, 0x00 }, 1647 { 0x04, 0x03, 0x00, 0x07 }, 1648 { 0x04, 0x03, 0x00, 0x00 }, 1649 { 0x04, 0x03, 0x00, 0x03 }, 1650 { 0x04, 0x03, 0x00, 0x03 }, 1651 { 0x04, 0x03, 0x00, 0x00 }, 1652 { 0x06, 0x03, 0x00, 0x07 }, 1653 { 0x04, 0x03, 0x00, 0x00 }, 1654 { 0x06, 0x06, 0x00, 0x03 }, 1655 { 0x04, 0x03, 0x00, 0x07 }, 1656 { 0x04, 0x03, 0x00, 0x00 }, 1657 { 0x04, 0x03, 0x00, 0x00 } 1658}; 1659 1660/* Firmware errors. */ 1661static const char * const iwn_fw_errmsg[] = { 1662 "OK", 1663 "FAIL", 1664 "BAD_PARAM", 1665 "BAD_CHECKSUM", 1666 "NMI_INTERRUPT_WDG", 1667 "SYSASSERT", 1668 "FATAL_ERROR", 1669 "BAD_COMMAND", 1670 "HW_ERROR_TUNE_LOCK", 1671 "HW_ERROR_TEMPERATURE", 1672 "ILLEGAL_CHAN_FREQ", 1673 "VCC_NOT_STABLE", 1674 "FH_ERROR", 1675 "NMI_INTERRUPT_HOST", 1676 "NMI_INTERRUPT_ACTION_PT", 1677 "NMI_INTERRUPT_UNKNOWN", 1678 "UCODE_VERSION_MISMATCH", 1679 "HW_ERROR_ABS_LOCK", 1680 "HW_ERROR_CAL_LOCK_FAIL", 1681 "NMI_INTERRUPT_INST_ACTION_PT", 1682 "NMI_INTERRUPT_DATA_ACTION_PT", 1683 "NMI_TRM_HW_ER", 1684 "NMI_INTERRUPT_TRM", 1685 "NMI_INTERRUPT_BREAKPOINT" 1686 "DEBUG_0", 1687 "DEBUG_1", 1688 "DEBUG_2", 1689 "DEBUG_3", 1690 "ADVANCED_SYSASSERT" 1691}; 1692 1693/* Find least significant bit that is set. */ 1694#define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 1695 1696#define IWN_READ(sc, reg) \ 1697 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1698 1699#define IWN_WRITE(sc, reg, val) \ 1700 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1701 1702#define IWN_WRITE_1(sc, reg, val) \ 1703 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1704 1705#define IWN_SETBITS(sc, reg, mask) \ 1706 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 1707 1708#define IWN_CLRBITS(sc, reg, mask) \ 1709 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 1710 1711#define IWN_BARRIER_WRITE(sc) \ 1712 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1713 BUS_SPACE_BARRIER_WRITE) 1714 1715#define IWN_BARRIER_READ_WRITE(sc) \ 1716 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1717 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 1718