if_iwnreg.h revision 198429
1178676Ssam/* $FreeBSD: head/sys/dev/iwn/if_iwnreg.h 198429 2009-10-23 22:04:18Z rpaulo $ */ 2198429Srpaulo/* $OpenBSD: if_iwnreg.h,v 1.26 2009/05/29 08:25:45 damien Exp $ */ 3178676Ssam 4178676Ssam/*- 5198429Srpaulo * Copyright (c) 2007, 2008 6178676Ssam * Damien Bergamini <damien.bergamini@free.fr> 7178676Ssam * 8178676Ssam * Permission to use, copy, modify, and distribute this software for any 9178676Ssam * purpose with or without fee is hereby granted, provided that the above 10178676Ssam * copyright notice and this permission notice appear in all copies. 11178676Ssam * 12178676Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13178676Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14178676Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15178676Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16178676Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17178676Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18178676Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19178676Ssam */ 20178676Ssam 21198429Srpaulo#define EDCA_NUM_AC 4 22178676Ssam 23178676Ssam#define IWN_TX_RING_COUNT 256 24198429Srpaulo#define IWN_TX_RING_LOMARK 192 25198429Srpaulo#define IWN_TX_RING_HIMARK 224 26198429Srpaulo#define IWN_RX_RING_COUNT_LOG 6 27198429Srpaulo#define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 28178676Ssam 29198429Srpaulo#define IWN4965_NTXQUEUES 16 30198429Srpaulo#define IWN5000_NTXQUEUES 20 31178676Ssam 32198429Srpaulo#define IWN4965_NDMACHNLS 7 33198429Srpaulo#define IWN5000_NDMACHNLS 8 34178676Ssam 35198429Srpaulo#define IWN_SRVC_DMACHNL 9 36198429Srpaulo 37198429Srpaulo/* Maximum number of DMA segments for TX. */ 38178676Ssam#define IWN_MAX_SCATTER 20 39178676Ssam 40198429Srpaulo/* RX buffers must be large enough to hold a full 4K A-MPDU. */ 41178676Ssam#define IWN_RBUF_SIZE (4 * 1024) 42178676Ssam 43198429Srpaulo#if defined(__LP64__) 44198429Srpaulo/* HW supports 36-bit DMA addresses. */ 45198429Srpaulo#define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 46198429Srpaulo#define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 47198429Srpaulo#else 48198429Srpaulo#define IWN_LOADDR(paddr) (paddr) 49198429Srpaulo#define IWN_HIADDR(paddr) (0) 50198429Srpaulo#endif 51198429Srpaulo 52198429Srpaulo/* Base Address Register. */ 53198429Srpaulo#define IWN_PCI_BAR0 PCI_MAPREG_START 54198429Srpaulo 55178676Ssam/* 56178676Ssam * Control and status registers. 57178676Ssam */ 58198429Srpaulo#define IWN_HW_IF_CONFIG 0x000 59198429Srpaulo#define IWN_INT_COALESCING 0x004 60198429Srpaulo#define IWN_INT 0x008 61178676Ssam#define IWN_MASK 0x00c 62198429Srpaulo#define IWN_FH_INT 0x010 63178676Ssam#define IWN_RESET 0x020 64198429Srpaulo#define IWN_GP_CNTRL 0x024 65198429Srpaulo#define IWN_HW_REV 0x028 66198429Srpaulo#define IWN_EEPROM 0x02c 67198429Srpaulo#define IWN_EEPROM_GP 0x030 68198429Srpaulo#define IWN_OTP_GP 0x034 69198429Srpaulo#define IWN_GIO 0x03c 70198429Srpaulo#define IWN_UCODE_GP1_CLR 0x05c 71198429Srpaulo#define IWN_LED 0x094 72198429Srpaulo#define IWN_GIO_CHICKEN 0x100 73198429Srpaulo#define IWN_ANA_PLL 0x20c 74198429Srpaulo#define IWN_DBG_HPET_MEM 0x240 75198429Srpaulo#define IWN_MEM_RADDR 0x40c 76178676Ssam#define IWN_MEM_WADDR 0x410 77178676Ssam#define IWN_MEM_WDATA 0x418 78198429Srpaulo#define IWN_MEM_RDATA 0x41c 79198429Srpaulo#define IWN_PRPH_WADDR 0x444 80198429Srpaulo#define IWN_PRPH_RADDR 0x448 81198429Srpaulo#define IWN_PRPH_WDATA 0x44c 82198429Srpaulo#define IWN_PRPH_RDATA 0x450 83198429Srpaulo#define IWN_HBUS_TARG_WRPTR 0x460 84178676Ssam 85198429Srpaulo/* 86198429Srpaulo * Flow-Handler registers. 87198429Srpaulo */ 88198429Srpaulo#define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 89198429Srpaulo#define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 90198429Srpaulo#define IWN_FH_KW_ADDR 0x197c 91198429Srpaulo#define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 92198429Srpaulo#define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 93198429Srpaulo#define IWN_FH_STATUS_WPTR 0x1bc0 94198429Srpaulo#define IWN_FH_RX_BASE 0x1bc4 95198429Srpaulo#define IWN_FH_RX_WPTR 0x1bc8 96198429Srpaulo#define IWN_FH_RX_CONFIG 0x1c00 97198429Srpaulo#define IWN_FH_RX_STATUS 0x1c44 98198429Srpaulo#define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 99198429Srpaulo#define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 100198429Srpaulo#define IWN_FH_TX_CHICKEN 0x1e98 101198429Srpaulo#define IWN_FH_TX_STATUS 0x1eb0 102178676Ssam 103198429Srpaulo/* 104198429Srpaulo * TX scheduler registers. 105198429Srpaulo */ 106198429Srpaulo#define IWN_SCHED_BASE 0xa02c00 107198429Srpaulo#define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 108198429Srpaulo#define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 109198429Srpaulo#define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 110198429Srpaulo#define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 111198429Srpaulo#define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 112198429Srpaulo#define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 113198429Srpaulo#define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 114198429Srpaulo#define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 115198429Srpaulo#define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 116198429Srpaulo#define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 117198429Srpaulo#define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 118198429Srpaulo#define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 119198429Srpaulo#define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 120198429Srpaulo#define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 121178676Ssam 122178676Ssam/* 123198429Srpaulo * Offsets in TX scheduler's SRAM. 124198429Srpaulo */ 125198429Srpaulo#define IWN4965_SCHED_CTX_OFF 0x380 126198429Srpaulo#define IWN4965_SCHED_CTX_LEN 416 127198429Srpaulo#define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 128198429Srpaulo#define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 129198429Srpaulo#define IWN5000_SCHED_CTX_OFF 0x600 130198429Srpaulo#define IWN5000_SCHED_CTX_LEN 520 131198429Srpaulo#define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 132198429Srpaulo#define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 133198429Srpaulo 134198429Srpaulo/* 135178676Ssam * NIC internal memory offsets. 136178676Ssam */ 137178676Ssam#define IWN_CLOCK_CTL 0x3000 138198429Srpaulo#define IWN_APMG_CLK_CTRL 0x3004 139198429Srpaulo#define IWN_APMG_CLK_DIS 0x3008 140198429Srpaulo#define IWN_APMG_PS 0x300c 141198429Srpaulo#define IWN_APMG_PCI_STT 0x3010 142198429Srpaulo#define IWN_BSM_WR_CTRL 0x3400 143198429Srpaulo#define IWN_BSM_WR_MEM_SRC 0x3404 144198429Srpaulo#define IWN_BSM_WR_MEM_DST 0x3408 145198429Srpaulo#define IWN_BSM_WR_DWCOUNT 0x340c 146198429Srpaulo#define IWN_BSM_DRAM_TEXT_ADDR 0x3490 147198429Srpaulo#define IWN_BSM_DRAM_TEXT_SIZE 0x3494 148198429Srpaulo#define IWN_BSM_DRAM_DATA_ADDR 0x3498 149198429Srpaulo#define IWN_BSM_DRAM_DATA_SIZE 0x349c 150198429Srpaulo#define IWN_BSM_SRAM_BASE 0x3800 151178676Ssam 152198429Srpaulo/* Possible values for IWN_APMG_CLK_DIS. */ 153198429Srpaulo#define IWN_APMG_CLK_DMA_RQT (1 << 9) 154178676Ssam 155198429Srpaulo/* Possible flags for register IWN_HW_IF_CONFIG. */ 156198429Srpaulo#define IWN_HW_IF_CONFIG_4965_R (1 << 4) 157198429Srpaulo#define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 158198429Srpaulo#define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 159198429Srpaulo#define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 160198429Srpaulo#define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 161198429Srpaulo#define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 162198429Srpaulo#define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 163198429Srpaulo#define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 164178676Ssam 165198429Srpaulo/* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 166198429Srpaulo#define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 167178676Ssam 168198429Srpaulo/* Possible values for IWN_BSM_WR_MEM_DST. */ 169198429Srpaulo#define IWN_FW_TEXT_BASE 0x00000000 170198429Srpaulo#define IWN_FW_DATA_BASE 0x00800000 171178676Ssam 172198429Srpaulo/* Possible flags for register IWN_RESET. */ 173198429Srpaulo#define IWN_RESET_NEVO (1 << 0) 174198429Srpaulo#define IWN_RESET_SW (1 << 7) 175198429Srpaulo#define IWN_RESET_MASTER_DISABLED (1 << 8) 176198429Srpaulo#define IWN_RESET_STOP_MASTER (1 << 9) 177178676Ssam 178198429Srpaulo/* Possible flags for register IWN_GP_CNTRL. */ 179198429Srpaulo#define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 180198429Srpaulo#define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 181198429Srpaulo#define IWN_GP_CNTRL_INIT_DONE (1 << 2) 182198429Srpaulo#define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 183198429Srpaulo#define IWN_GP_CNTRL_SLEEP (1 << 4) 184198429Srpaulo#define IWN_GP_CNTRL_RFKILL (1 << 27) 185178676Ssam 186198429Srpaulo/* Possible flags for register IWN_HW_REV. */ 187198429Srpaulo#define IWN_HW_REV_TYPE_SHIFT 4 188198429Srpaulo#define IWN_HW_REV_TYPE_MASK 0x000000f0 189198429Srpaulo#define IWN_HW_REV_TYPE_4965 0 190198429Srpaulo#define IWN_HW_REV_TYPE_5300 2 191198429Srpaulo#define IWN_HW_REV_TYPE_5350 3 192198429Srpaulo#define IWN_HW_REV_TYPE_5150 4 193198429Srpaulo#define IWN_HW_REV_TYPE_5100 5 194198429Srpaulo#define IWN_HW_REV_TYPE_1000 6 195198429Srpaulo#define IWN_HW_REV_TYPE_6000 7 196198429Srpaulo#define IWN_HW_REV_TYPE_6050 8 197178676Ssam 198198429Srpaulo/* Possible flags for register IWN_GIO_CHICKEN. */ 199198429Srpaulo#define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 200198429Srpaulo#define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 201178676Ssam 202198429Srpaulo/* Possible flags for register IWN_GIO. */ 203198429Srpaulo#define IWN_GIO_L0S_ENA (1 << 1) 204178676Ssam 205198429Srpaulo/* Possible flags for register IWN_UCODE_GP1_CLR. */ 206198429Srpaulo#define IWN_UCODE_GP1_RFKILL (1 << 1) 207198429Srpaulo#define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 208198429Srpaulo#define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 209178676Ssam 210198429Srpaulo/* Possible flags/values for register IWN_LED. */ 211198429Srpaulo#define IWN_LED_BSM_CTRL (1 << 5) 212198429Srpaulo#define IWN_LED_OFF 0x00000038 213198429Srpaulo#define IWN_LED_ON 0x00000078 214178676Ssam 215198429Srpaulo/* Possible values for register IWN_ANA_PLL. */ 216198429Srpaulo#define IWN_ANA_PLL_INIT 0x00880300 217178676Ssam 218198429Srpaulo/* Possible flags for register IWN_FH_RX_STATUS. */ 219198429Srpaulo#define IWN_FH_RX_STATUS_IDLE (1 << 24) 220178676Ssam 221198429Srpaulo/* Possible flags for register IWN_BSM_WR_CTRL. */ 222198429Srpaulo#define IWN_BSM_WR_CTRL_START_EN (1 << 30) 223198429Srpaulo#define IWN_BSM_WR_CTRL_START (1 << 31) 224178676Ssam 225198429Srpaulo/* Possible flags for register IWN_INT. */ 226198429Srpaulo#define IWN_INT_ALIVE (1 << 0) 227198429Srpaulo#define IWN_INT_WAKEUP (1 << 1) 228198429Srpaulo#define IWN_INT_SW_RX (1 << 3) 229198429Srpaulo#define IWN_INT_CT_REACHED (1 << 6) 230198429Srpaulo#define IWN_INT_RF_TOGGLED (1 << 7) 231198429Srpaulo#define IWN_INT_SW_ERR (1 << 25) 232198429Srpaulo#define IWN_INT_FH_TX (1 << 27) 233198429Srpaulo#define IWN_INT_HW_ERR (1 << 29) 234198429Srpaulo#define IWN_INT_FH_RX (1 << 31) 235178676Ssam 236198429Srpaulo/* Shortcut. */ 237198429Srpaulo#define IWN_INT_MASK \ 238198429Srpaulo (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 239198429Srpaulo IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 240198429Srpaulo IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 241178676Ssam 242198429Srpaulo/* Possible flags for register IWN_FH_INT. */ 243198429Srpaulo#define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 244198429Srpaulo#define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 245198429Srpaulo#define IWN_FH_INT_HI_PRIOR (1 << 30) 246198429Srpaulo/* Shortcuts for the above. */ 247198429Srpaulo#define IWN_FH_INT_TX \ 248198429Srpaulo (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 249198429Srpaulo#define IWN_FH_INT_RX \ 250198429Srpaulo (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 251178676Ssam 252198429Srpaulo/* Possible flags/values for register IWN_FH_TX_CONFIG. */ 253198429Srpaulo#define IWN_FH_TX_CONFIG_DMA_PAUSE 0 254198429Srpaulo#define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 255198429Srpaulo#define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20) 256178676Ssam 257198429Srpaulo/* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 258198429Srpaulo#define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 259198429Srpaulo#define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 260198429Srpaulo#define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 261198429Srpaulo 262198429Srpaulo/* Possible flags for register IWN_FH_TX_CHICKEN. */ 263198429Srpaulo#define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 264198429Srpaulo 265198429Srpaulo/* Possible flags for register IWN_FH_TX_STATUS. */ 266198429Srpaulo#define IWN_FH_TX_STATUS_IDLE(chnl) \ 267198429Srpaulo (1 << ((chnl) + 24) | 1 << ((chnl) + 16)) 268198429Srpaulo 269198429Srpaulo/* Possible flags for register IWN_FH_RX_CONFIG. */ 270198429Srpaulo#define IWN_FH_RX_CONFIG_ENA (1 << 31) 271198429Srpaulo#define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 272198429Srpaulo#define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16) 273198429Srpaulo#define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15) 274198429Srpaulo#define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 275198429Srpaulo#define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 276198429Srpaulo#define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2) 277198429Srpaulo 278198429Srpaulo/* Possible flags for register IWN_FH_TX_CONFIG. */ 279198429Srpaulo#define IWN_FH_TX_CONFIG_DMA_ENA (1 << 31) 280198429Srpaulo#define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3) 281198429Srpaulo 282198429Srpaulo/* Possible flags for register IWN_EEPROM. */ 283198429Srpaulo#define IWN_EEPROM_READ_VALID (1 << 0) 284198429Srpaulo#define IWN_EEPROM_CMD (1 << 1) 285198429Srpaulo 286198429Srpaulo/* Possible flags for register IWN_EEPROM_GP. */ 287198429Srpaulo#define IWN_EEPROM_GP_IF_OWNER 0x00000180 288198429Srpaulo 289198429Srpaulo/* Possible flags for register IWN_OTP_GP. */ 290198429Srpaulo#define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 291198429Srpaulo#define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 292198429Srpaulo#define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 293198429Srpaulo#define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 294198429Srpaulo 295198429Srpaulo/* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 296198429Srpaulo#define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 297198429Srpaulo#define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 298198429Srpaulo#define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 299198429Srpaulo#define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 300198429Srpaulo#define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 301198429Srpaulo#define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 302198429Srpaulo#define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 303198429Srpaulo 304198429Srpaulo/* Possible flags for register IWN_APMG_CLK_CTRL. */ 305198429Srpaulo#define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 306198429Srpaulo#define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 307198429Srpaulo 308198429Srpaulo/* Possible flags for register IWN_APMG_PS. */ 309198429Srpaulo#define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 310198429Srpaulo#define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 311198429Srpaulo#define IWN_APMG_PS_PWR_SRC_VMAIN 0 312198429Srpaulo#define IWN_APMG_PS_PWR_SRC_VAUX 2 313198429Srpaulo#define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 314198429Srpaulo#define IWN_APMG_PS_RESET_REQ (1 << 26) 315198429Srpaulo 316198429Srpaulo/* Possible flags for IWN_APMG_PCI_STT. */ 317198429Srpaulo#define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 318198429Srpaulo 319198429Srpaulo/* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 320178676Ssam#define IWN_FW_UPDATED (1 << 31) 321178676Ssam 322198429Srpaulo#define IWN_SCHED_WINSZ 64 323198429Srpaulo#define IWN_SCHED_LIMIT 64 324198429Srpaulo#define IWN4965_SCHED_COUNT 512 325198429Srpaulo#define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 326198429Srpaulo#define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 327198429Srpaulo#define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 328178676Ssam 329198429Srpaulostruct iwn_tx_desc { 330198429Srpaulo uint8_t reserved1[3]; 331198429Srpaulo uint8_t nsegs; 332198429Srpaulo struct { 333198429Srpaulo uint32_t addr; 334198429Srpaulo uint16_t len; 335198429Srpaulo } __packed segs[IWN_MAX_SCATTER]; 336198429Srpaulo /* Pad to 128 bytes. */ 337198429Srpaulo uint32_t reserved2; 338198429Srpaulo} __packed; 339178676Ssam 340198429Srpaulostruct iwn_rx_status { 341178676Ssam uint16_t closed_count; 342178676Ssam uint16_t closed_rx_count; 343178676Ssam uint16_t finished_count; 344178676Ssam uint16_t finished_rx_count; 345178676Ssam uint32_t reserved[2]; 346178676Ssam} __packed; 347178676Ssam 348178676Ssamstruct iwn_rx_desc { 349178676Ssam uint32_t len; 350178676Ssam uint8_t type; 351198429Srpaulo#define IWN_UC_READY 1 352198429Srpaulo#define IWN_ADD_NODE_DONE 24 353198429Srpaulo#define IWN_TX_DONE 28 354198429Srpaulo#define IWN5000_CALIBRATION_RESULT 102 355198429Srpaulo#define IWN5000_CALIBRATION_DONE 103 356198429Srpaulo#define IWN_START_SCAN 130 357198429Srpaulo#define IWN_STOP_SCAN 132 358198429Srpaulo#define IWN_RX_STATISTICS 156 359198429Srpaulo#define IWN_BEACON_STATISTICS 157 360198429Srpaulo#define IWN_STATE_CHANGED 161 361198429Srpaulo#define IWN_BEACON_MISSED 162 362198429Srpaulo#define IWN_RX_PHY 192 363198429Srpaulo#define IWN_MPDU_RX_DONE 193 364198429Srpaulo#define IWN_RX_DONE 195 365178676Ssam 366178676Ssam uint8_t flags; 367178676Ssam uint8_t idx; 368178676Ssam uint8_t qid; 369178676Ssam} __packed; 370178676Ssam 371198429Srpaulo/* Possible RX status flags. */ 372198429Srpaulo#define IWN_RX_NO_CRC_ERR (1 << 0) 373198429Srpaulo#define IWN_RX_NO_OVFL_ERR (1 << 1) 374198429Srpaulo/* Shortcut for the above. */ 375178676Ssam#define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 376198429Srpaulo#define IWN_RX_MPDU_MIC_OK (1 << 6) 377198429Srpaulo#define IWN_RX_CIPHER_MASK (7 << 8) 378198429Srpaulo#define IWN_RX_CIPHER_CCMP (2 << 8) 379198429Srpaulo#define IWN_RX_MPDU_DEC (1 << 11) 380198429Srpaulo#define IWN_RX_DECRYPT_MASK (3 << 11) 381198429Srpaulo#define IWN_RX_DECRYPT_OK (3 << 11) 382178676Ssam 383178676Ssamstruct iwn_tx_cmd { 384178676Ssam uint8_t code; 385198429Srpaulo#define IWN_CMD_CONFIGURE 16 386198429Srpaulo#define IWN_CMD_ASSOCIATE 17 387198429Srpaulo#define IWN_CMD_EDCA_PARAMS 19 388198429Srpaulo#define IWN_CMD_TIMING 20 389198429Srpaulo#define IWN_CMD_ADD_NODE 24 390198429Srpaulo#define IWN_CMD_TX_DATA 28 391198429Srpaulo#define IWN_CMD_LINK_QUALITY 78 392198429Srpaulo#define IWN_CMD_SET_LED 72 393198429Srpaulo#define IWN5000_CMD_WIMAX_COEX 90 394198429Srpaulo#define IWN5000_CMD_CALIB_CONFIG 101 395198429Srpaulo#define IWN_CMD_SET_POWER_MODE 119 396198429Srpaulo#define IWN_CMD_SCAN 128 397198429Srpaulo#define IWN_CMD_TXPOWER 151 398198429Srpaulo#define IWN_CMD_TXPOWER_DBM 152 399198429Srpaulo#define IWN_CMD_BT_COEX 155 400198429Srpaulo#define IWN_CMD_GET_STATISTICS 156 401198429Srpaulo#define IWN_CMD_SET_CRITICAL_TEMP 164 402198429Srpaulo#define IWN_CMD_SET_SENSITIVITY 168 403198429Srpaulo#define IWN_CMD_PHY_CALIB 176 404198429Srpaulo 405178676Ssam uint8_t flags; 406178676Ssam uint8_t idx; 407178676Ssam uint8_t qid; 408178676Ssam uint8_t data[136]; 409178676Ssam} __packed; 410178676Ssam 411198429Srpaulo/* Antenna flags, used in various commands. */ 412198429Srpaulo#define IWN_ANT_A (1 << 0) 413198429Srpaulo#define IWN_ANT_B (1 << 1) 414198429Srpaulo#define IWN_ANT_C (1 << 2) 415198429Srpaulo/* Shortcut. */ 416198429Srpaulo#define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 417198429Srpaulo 418198429Srpaulo/* Structure for command IWN_CMD_CONFIGURE. */ 419198429Srpaulostruct iwn_rxon { 420178676Ssam uint8_t myaddr[IEEE80211_ADDR_LEN]; 421178676Ssam uint16_t reserved1; 422178676Ssam uint8_t bssid[IEEE80211_ADDR_LEN]; 423178676Ssam uint16_t reserved2; 424178676Ssam uint8_t wlap[IEEE80211_ADDR_LEN]; 425178676Ssam uint16_t reserved3; 426178676Ssam uint8_t mode; 427178676Ssam#define IWN_MODE_HOSTAP 1 428178676Ssam#define IWN_MODE_STA 3 429178676Ssam#define IWN_MODE_IBSS 4 430178676Ssam#define IWN_MODE_MONITOR 6 431198429Srpaulo 432198429Srpaulo uint8_t air; 433178676Ssam uint16_t rxchain; 434198429Srpaulo#define IWN_RXCHAIN_FORCE (1 << 0) 435198429Srpaulo#define IWN_RXCHAIN_VALID(x) ((x) << 1) 436198429Srpaulo#define IWN_RXCHAIN_SEL(x) ((x) << 4) 437198429Srpaulo#define IWN_RXCHAIN_MIMO(x) ((x) << 7) 438198429Srpaulo#define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 439198429Srpaulo#define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 440198429Srpaulo#define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 441198429Srpaulo 442198429Srpaulo uint8_t ofdm_mask; 443198429Srpaulo uint8_t cck_mask; 444178676Ssam uint16_t associd; 445178676Ssam uint32_t flags; 446198429Srpaulo#define IWN_RXON_24GHZ 0x00000001 /* band */ 447198429Srpaulo#define IWN_RXON_CCK 0x00000002 /* modulation */ 448198429Srpaulo#define IWN_RXON_AUTO 0x00000004 /* 2.4-only auto-detect */ 449198429Srpaulo#define IWN_RXON_HTPROT 0x00000008 /* xmit with HT protection */ 450198429Srpaulo#define IWN_RXON_SHSLOT 0x00000010 /* short slot time */ 451198429Srpaulo#define IWN_RXON_SHPREAMBLE 0x00000020 /* short premable */ 452198429Srpaulo#define IWN_RXON_NODIVERSITY 0x00000080 /* disable antenna diversity */ 453198429Srpaulo#define IWN_RXON_ANTENNA_A 0x00000100 454198429Srpaulo#define IWN_RXON_ANTENNA_B 0x00000200 455198429Srpaulo#define IWN_RXON_RADAR 0x00001000 /* enable radar detect */ 456198429Srpaulo#define IWN_RXON_NARROW 0x00002000 /* MKK narrow band select */ 457198429Srpaulo#define IWN_RXON_TSF 0x00008000 458198429Srpaulo#define IWN_RXON_HT 0x06400000 459198429Srpaulo#define IWN_RXON_HT20 0x02000000 460198429Srpaulo#define IWN_RXON_HT40U 0x04000000 461198429Srpaulo#define IWN_RXON_HT40D 0x04400000 462198429Srpaulo#define IWN_RXON_CTS_TO_SELF 0x40000000 463198429Srpaulo 464178676Ssam uint32_t filter; 465198429Srpaulo#define IWN_FILTER_PROMISC (1 << 0) 466198429Srpaulo#define IWN_FILTER_CTL (1 << 1) 467198429Srpaulo#define IWN_FILTER_MULTICAST (1 << 2) 468198429Srpaulo#define IWN_FILTER_NODECRYPT (1 << 3) 469198429Srpaulo#define IWN_FILTER_BSS (1 << 5) 470198429Srpaulo#define IWN_FILTER_BEACON (1 << 6) 471198429Srpaulo 472198429Srpaulo uint8_t chan; 473198429Srpaulo uint8_t reserved4; 474198429Srpaulo uint8_t ht_single_mask; 475198429Srpaulo uint8_t ht_dual_mask; 476198429Srpaulo /* The following fields are for 5000 Series only. */ 477198429Srpaulo uint8_t ht_triple_mask; 478198429Srpaulo uint8_t reserved5; 479198429Srpaulo uint16_t acquisition; 480198429Srpaulo uint16_t reserved6; 481178676Ssam} __packed; 482178676Ssam 483198429Srpaulo#define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 484198429Srpaulo#define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 485198429Srpaulo 486198429Srpaulo/* Structure for command IWN_CMD_ASSOCIATE. */ 487178676Ssamstruct iwn_assoc { 488178676Ssam uint32_t flags; 489178676Ssam uint32_t filter; 490178676Ssam uint8_t ofdm_mask; 491178676Ssam uint8_t cck_mask; 492178676Ssam uint16_t reserved; 493178676Ssam} __packed; 494178676Ssam 495198429Srpaulo/* Structure for command IWN_CMD_EDCA_PARAMS. */ 496178676Ssamstruct iwn_edca_params { 497178676Ssam uint32_t flags; 498178676Ssam#define IWN_EDCA_UPDATE (1 << 0) 499178676Ssam#define IWN_EDCA_TXOP (1 << 4) 500178676Ssam 501178676Ssam struct { 502178676Ssam uint16_t cwmin; 503178676Ssam uint16_t cwmax; 504178676Ssam uint8_t aifsn; 505178676Ssam uint8_t reserved; 506178676Ssam uint16_t txoplimit; 507178676Ssam } __packed ac[EDCA_NUM_AC]; 508178676Ssam} __packed; 509178676Ssam 510198429Srpaulo/* Structure for command IWN_CMD_TIMING. */ 511198429Srpaulostruct iwn_cmd_timing { 512178676Ssam uint64_t tstamp; 513178676Ssam uint16_t bintval; 514178676Ssam uint16_t atim; 515178676Ssam uint32_t binitval; 516178676Ssam uint16_t lintval; 517178676Ssam uint16_t reserved; 518178676Ssam} __packed; 519178676Ssam 520198429Srpaulo/* Structure for command IWN_CMD_ADD_NODE. */ 521178676Ssamstruct iwn_node_info { 522178676Ssam uint8_t control; 523178676Ssam#define IWN_NODE_UPDATE (1 << 0) 524198429Srpaulo 525178676Ssam uint8_t reserved1[3]; 526198429Srpaulo 527178676Ssam uint8_t macaddr[IEEE80211_ADDR_LEN]; 528178676Ssam uint16_t reserved2; 529178676Ssam uint8_t id; 530178676Ssam#define IWN_ID_BSS 0 531198429Srpaulo#define IWN5000_ID_BROADCAST 15 532198429Srpaulo#define IWN4965_ID_BROADCAST 31 533198429Srpaulo 534178676Ssam uint8_t flags; 535198429Srpaulo#define IWN_FLAG_SET_KEY (1 << 0) 536198429Srpaulo#define IWN_FLAG_SET_DISABLE_TID (1 << 1) 537198429Srpaulo#define IWN_FLAG_SET_TXRATE (1 << 2) 538198429Srpaulo#define IWN_FLAG_SET_ADDBA (1 << 3) 539198429Srpaulo#define IWN_FLAG_SET_DELBA (1 << 4) 540198429Srpaulo 541178676Ssam uint16_t reserved3; 542198429Srpaulo uint16_t kflags; 543198429Srpaulo#define IWN_KFLAG_CCMP (1 << 1) 544198429Srpaulo#define IWN_KFLAG_MAP (1 << 3) 545198429Srpaulo#define IWN_KFLAG_KID(kid) ((kid) << 8) 546198429Srpaulo#define IWN_KFLAG_INVALID (1 << 11) 547198429Srpaulo#define IWN_KFLAG_GROUP (1 << 14) 548198429Srpaulo 549178676Ssam uint8_t tsc2; /* TKIP TSC2 */ 550178676Ssam uint8_t reserved4; 551178676Ssam uint16_t ttak[5]; 552198429Srpaulo uint8_t kid; 553198429Srpaulo uint8_t reserved5; 554198429Srpaulo uint8_t key[16]; 555198429Srpaulo /* The following 3 fields are for 5000 Series only. */ 556198429Srpaulo uint64_t tsc; 557198429Srpaulo uint8_t rxmic[8]; 558198429Srpaulo uint8_t txmic[8]; 559198429Srpaulo 560178676Ssam uint32_t htflags; 561198429Srpaulo#define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 562198429Srpaulo#define IWN_AMDPU_DENSITY(x) ((x) << 23) 563198429Srpaulo 564178676Ssam uint32_t mask; 565198429Srpaulo uint16_t disable_tid; 566198429Srpaulo uint16_t reserved6; 567198429Srpaulo uint8_t addba_tid; 568198429Srpaulo uint8_t delba_tid; 569198429Srpaulo uint16_t addba_ssn; 570198429Srpaulo uint32_t reserved7; 571198429Srpaulo} __packed; 572198429Srpaulo 573198429Srpaulostruct iwn4965_node_info { 574198429Srpaulo uint8_t control; 575198429Srpaulo uint8_t reserved1[3]; 576198429Srpaulo uint8_t macaddr[IEEE80211_ADDR_LEN]; 577198429Srpaulo uint16_t reserved2; 578198429Srpaulo uint8_t id; 579198429Srpaulo uint8_t flags; 580198429Srpaulo uint16_t reserved3; 581198429Srpaulo uint16_t kflags; 582198429Srpaulo uint8_t tsc2; /* TKIP TSC2 */ 583198429Srpaulo uint8_t reserved4; 584198429Srpaulo uint16_t ttak[5]; 585198429Srpaulo uint8_t kid; 586198429Srpaulo uint8_t reserved5; 587198429Srpaulo uint8_t key[16]; 588198429Srpaulo uint32_t htflags; 589198429Srpaulo uint32_t mask; 590198429Srpaulo uint16_t disable_tid; 591198429Srpaulo uint16_t reserved6; 592198429Srpaulo uint8_t addba_tid; 593198429Srpaulo uint8_t delba_tid; 594198429Srpaulo uint16_t addba_ssn; 595198429Srpaulo uint32_t reserved7; 596198429Srpaulo} __packed; 597198429Srpaulo 598198429Srpaulo#define IWN_RFLAG_HT (1 << 0) /* use HT modulation */ 599178676Ssam#define IWN_RFLAG_CCK (1 << 1) /* use CCK modulation */ 600198429Srpaulo#define IWN_RFLAG_HT40 (1 << 3) /* use dual-stream */ 601198429Srpaulo#define IWN_RFLAG_SGI (1 << 5) /* use short GI */ 602178676Ssam#define IWN_RFLAG_ANT_A (1 << 6) /* start on antenna port A */ 603178676Ssam#define IWN_RFLAG_ANT_B (1 << 7) /* start on antenna port B */ 604198429Srpaulo#define IWN_RFLAG_ANT(x) ((x) << 6) 605178676Ssam 606198429Srpaulo/* Structure for command IWN_CMD_TX_DATA. */ 607178676Ssamstruct iwn_cmd_data { 608178676Ssam uint16_t len; 609178676Ssam uint16_t lnext; 610178676Ssam uint32_t flags; 611198429Srpaulo#define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 612178676Ssam#define IWN_TX_NEED_RTS (1 << 1) 613178676Ssam#define IWN_TX_NEED_CTS (1 << 2) 614178676Ssam#define IWN_TX_NEED_ACK (1 << 3) 615198429Srpaulo#define IWN_TX_LINKQ (1 << 4) 616198429Srpaulo#define IWN_TX_IMM_BA (1 << 6) 617178676Ssam#define IWN_TX_FULL_TXOP (1 << 7) 618178676Ssam#define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 619178676Ssam#define IWN_TX_AUTO_SEQ (1 << 13) 620198429Srpaulo#define IWN_TX_MORE_FRAG (1 << 14) 621178676Ssam#define IWN_TX_INSERT_TSTAMP (1 << 16) 622178676Ssam#define IWN_TX_NEED_PADDING (1 << 20) 623178676Ssam 624198429Srpaulo uint32_t scratch; 625198429Srpaulo uint8_t plcp; 626178676Ssam uint8_t rflags; 627178676Ssam uint16_t xrflags; 628198429Srpaulo 629178676Ssam uint8_t id; 630178676Ssam uint8_t security; 631178676Ssam#define IWN_CIPHER_WEP40 1 632178676Ssam#define IWN_CIPHER_CCMP 2 633178676Ssam#define IWN_CIPHER_TKIP 3 634178676Ssam#define IWN_CIPHER_WEP104 9 635178676Ssam 636198429Srpaulo uint8_t linkq; 637178676Ssam uint8_t reserved2; 638198429Srpaulo uint8_t key[16]; 639178676Ssam uint16_t fnext; 640178676Ssam uint16_t reserved3; 641178676Ssam uint32_t lifetime; 642178676Ssam#define IWN_LIFETIME_INFINITE 0xffffffff 643178676Ssam 644178676Ssam uint32_t loaddr; 645178676Ssam uint8_t hiaddr; 646178676Ssam uint8_t rts_ntries; 647178676Ssam uint8_t data_ntries; 648178676Ssam uint8_t tid; 649178676Ssam uint16_t timeout; 650178676Ssam uint16_t txop; 651178676Ssam} __packed; 652178676Ssam 653198429Srpaulo/* Structure for command IWN_CMD_LINK_QUALITY. */ 654178676Ssam#define IWN_MAX_TX_RETRIES 16 655178676Ssamstruct iwn_cmd_link_quality { 656178676Ssam uint8_t id; 657178676Ssam uint8_t reserved1; 658178676Ssam uint16_t ctl; 659178676Ssam uint8_t flags; 660198429Srpaulo uint8_t mimo; 661198429Srpaulo uint8_t antmsk_1stream; 662198429Srpaulo uint8_t antmsk_2stream; 663198429Srpaulo uint8_t ridx[EDCA_NUM_AC]; 664198429Srpaulo uint16_t ampdu_limit; 665198429Srpaulo uint8_t ampdu_threshold; 666198429Srpaulo uint8_t ampdu_max; 667178676Ssam uint32_t reserved2; 668178676Ssam struct { 669198429Srpaulo uint8_t plcp; 670178676Ssam uint8_t rflags; 671178676Ssam uint16_t xrflags; 672198429Srpaulo } __packed retry[IWN_MAX_TX_RETRIES]; 673178676Ssam uint32_t reserved3; 674178676Ssam} __packed; 675178676Ssam 676198429Srpaulo/* Structure for command IWN_CMD_SET_LED. */ 677178676Ssamstruct iwn_cmd_led { 678178676Ssam uint32_t unit; /* multiplier (in usecs) */ 679178676Ssam uint8_t which; 680178676Ssam#define IWN_LED_ACTIVITY 1 681178676Ssam#define IWN_LED_LINK 2 682178676Ssam 683178676Ssam uint8_t off; 684178676Ssam uint8_t on; 685178676Ssam uint8_t reserved; 686178676Ssam} __packed; 687178676Ssam 688198429Srpaulo/* Structure for command IWN5000_CMD_WIMAX_COEX. */ 689198429Srpaulostruct iwn5000_wimax_coex { 690198429Srpaulo uint32_t flags; 691198429Srpaulo struct { 692198429Srpaulo uint8_t request; 693198429Srpaulo uint8_t window; 694198429Srpaulo uint8_t reserved; 695198429Srpaulo uint8_t flags; 696198429Srpaulo } __packed events[16]; 697198429Srpaulo} __packed; 698198429Srpaulo 699198429Srpaulo/* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 700198429Srpaulostruct iwn5000_calib_elem { 701198429Srpaulo uint32_t enable; 702198429Srpaulo uint32_t start; 703198429Srpaulo uint32_t send; 704198429Srpaulo uint32_t apply; 705198429Srpaulo uint32_t reserved; 706198429Srpaulo} __packed; 707198429Srpaulo 708198429Srpaulostruct iwn5000_calib_status { 709198429Srpaulo struct iwn5000_calib_elem once; 710198429Srpaulo struct iwn5000_calib_elem perd; 711198429Srpaulo uint32_t flags; 712198429Srpaulo} __packed; 713198429Srpaulo 714198429Srpaulostruct iwn5000_calib_config { 715198429Srpaulo struct iwn5000_calib_status ucode; 716198429Srpaulo struct iwn5000_calib_status driver; 717198429Srpaulo uint32_t reserved; 718198429Srpaulo} __packed; 719198429Srpaulo 720198429Srpaulo/* Structure for command IWN_CMD_SET_POWER_MODE. */ 721198429Srpaulostruct iwn_pmgt_cmd { 722178676Ssam uint16_t flags; 723198429Srpaulo#define IWN_PS_ALLOW_SLEEP (1 << 0) 724198429Srpaulo#define IWN_PS_NOTIFY (1 << 1) 725198429Srpaulo#define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 726198429Srpaulo#define IWN_PS_PCI_PMGT (1 << 3) 727198429Srpaulo#define IWN_PS_FAST_PD (1 << 4) 728178676Ssam 729198429Srpaulo uint8_t keepalive; 730178676Ssam uint8_t debug; 731198429Srpaulo uint32_t rxtimeout; 732198429Srpaulo uint32_t txtimeout; 733198429Srpaulo uint32_t intval[5]; 734178676Ssam uint32_t beacons; 735178676Ssam} __packed; 736178676Ssam 737198429Srpaulo/* Structures for command IWN_CMD_SCAN. */ 738178676Ssamstruct iwn_scan_essid { 739178676Ssam uint8_t id; 740178676Ssam uint8_t len; 741178676Ssam uint8_t data[IEEE80211_NWID_LEN]; 742178676Ssam} __packed; 743178676Ssam 744178676Ssamstruct iwn_scan_hdr { 745178676Ssam uint16_t len; 746178676Ssam uint8_t reserved1; 747178676Ssam uint8_t nchan; 748198429Srpaulo uint16_t quiet_time; 749198429Srpaulo uint16_t quiet_threshold; 750178676Ssam uint16_t crc_threshold; 751178676Ssam uint16_t rxchain; 752178676Ssam uint32_t max_svc; /* background scans */ 753178676Ssam uint32_t pause_svc; /* background scans */ 754178676Ssam uint32_t flags; 755178676Ssam uint32_t filter; 756178676Ssam 757198429Srpaulo /* Followed by a struct iwn_cmd_data. */ 758198429Srpaulo /* Followed by an array of 20 structs iwn_scan_essid. */ 759198429Srpaulo /* Followed by probe request body. */ 760198429Srpaulo /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 761178676Ssam} __packed; 762178676Ssam 763178676Ssamstruct iwn_scan_chan { 764198429Srpaulo uint32_t flags; 765198429Srpaulo#define IWN_CHAN_ACTIVE (1 << 0) 766198429Srpaulo#define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 767178676Ssam 768198429Srpaulo uint16_t chan; 769178676Ssam uint8_t rf_gain; 770178676Ssam uint8_t dsp_gain; 771178676Ssam uint16_t active; /* msecs */ 772178676Ssam uint16_t passive; /* msecs */ 773178676Ssam} __packed; 774178676Ssam 775198429Srpaulo/* Maximum size of a scan command. */ 776198429Srpaulo#define IWN_SCAN_MAXSZ (MCLBYTES - 4) 777198429Srpaulo 778198429Srpaulo/* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 779178676Ssam#define IWN_RIDX_MAX 32 780198429Srpaulostruct iwn4965_cmd_txpower { 781198429Srpaulo uint8_t band; 782198429Srpaulo uint8_t reserved1; 783198429Srpaulo uint8_t chan; 784198429Srpaulo uint8_t reserved2; 785178676Ssam struct { 786198429Srpaulo uint8_t rf_gain[2]; 787198429Srpaulo uint8_t dsp_gain[2]; 788198429Srpaulo } __packed power[IWN_RIDX_MAX + 1]; 789178676Ssam} __packed; 790178676Ssam 791198429Srpaulo/* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 792198429Srpaulostruct iwn5000_cmd_txpower { 793198429Srpaulo int8_t global_limit; /* in half-dBm */ 794198429Srpaulo#define IWN5000_TXPOWER_AUTO 0x7f 795198429Srpaulo#define IWN5000_TXPOWER_MAX_DBM 16 796198429Srpaulo 797198429Srpaulo uint8_t flags; 798198429Srpaulo#define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 799198429Srpaulo 800198429Srpaulo int8_t srv_limit; /* in half-dBm */ 801198429Srpaulo uint8_t reserved; 802198429Srpaulo} __packed; 803198429Srpaulo 804198429Srpaulo/* Structure for command IWN_CMD_BLUETOOTH. */ 805178676Ssamstruct iwn_bluetooth { 806178676Ssam uint8_t flags; 807178676Ssam uint8_t lead; 808178676Ssam uint8_t kill; 809178676Ssam uint8_t reserved; 810178676Ssam uint32_t ack; 811178676Ssam uint32_t cts; 812178676Ssam} __packed; 813178676Ssam 814198429Srpaulo/* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 815178676Ssamstruct iwn_critical_temp { 816178676Ssam uint32_t reserved; 817178676Ssam uint32_t tempM; 818178676Ssam uint32_t tempR; 819198429Srpaulo/* degK <-> degC conversion macros. */ 820178676Ssam#define IWN_CTOK(c) ((c) + 273) 821178676Ssam#define IWN_KTOC(k) ((k) - 273) 822178676Ssam#define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 823178676Ssam} __packed; 824178676Ssam 825198429Srpaulo/* Structure for command IWN_CMD_SET_SENSITIVITY. */ 826178676Ssamstruct iwn_sensitivity_cmd { 827178676Ssam uint16_t which; 828178676Ssam#define IWN_SENSITIVITY_DEFAULTTBL 0 829178676Ssam#define IWN_SENSITIVITY_WORKTBL 1 830178676Ssam 831178676Ssam uint16_t energy_cck; 832178676Ssam uint16_t energy_ofdm; 833178676Ssam uint16_t corr_ofdm_x1; 834178676Ssam uint16_t corr_ofdm_mrc_x1; 835178676Ssam uint16_t corr_cck_mrc_x4; 836178676Ssam uint16_t corr_ofdm_x4; 837178676Ssam uint16_t corr_ofdm_mrc_x4; 838178676Ssam uint16_t corr_barker; 839178676Ssam uint16_t corr_barker_mrc; 840178676Ssam uint16_t corr_cck_x4; 841178676Ssam uint16_t energy_ofdm_th; 842178676Ssam} __packed; 843178676Ssam 844198429Srpaulo/* Structures for command IWN_CMD_PHY_CALIB. */ 845198429Srpaulostruct iwn_phy_calib { 846198429Srpaulo uint8_t code; 847198429Srpaulo#define IWN4965_PHY_CALIB_DIFF_GAIN 7 848198429Srpaulo#define IWN5000_PHY_CALIB_DC 8 849198429Srpaulo#define IWN5000_PHY_CALIB_LO 9 850198429Srpaulo#define IWN5000_PHY_CALIB_TX_IQ 11 851198429Srpaulo#define IWN5000_PHY_CALIB_CRYSTAL 15 852198429Srpaulo#define IWN5000_PHY_CALIB_BASE_BAND 16 853198429Srpaulo#define IWN5000_PHY_CALIB_TX_IQ_PERD 17 854198429Srpaulo#define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 855198429Srpaulo#define IWN5000_PHY_CALIB_NOISE_GAIN 19 856178676Ssam 857198429Srpaulo uint8_t group; 858198429Srpaulo uint8_t ngroups; 859198429Srpaulo uint8_t isvalid; 860198429Srpaulo} __packed; 861178676Ssam 862198429Srpaulostruct iwn5000_phy_calib_crystal { 863198429Srpaulo uint8_t code; 864198429Srpaulo uint8_t group; 865198429Srpaulo uint8_t ngroups; 866198429Srpaulo uint8_t isvalid; 867198429Srpaulo 868198429Srpaulo uint8_t cap_pin[2]; 869198429Srpaulo uint8_t reserved[2]; 870178676Ssam} __packed; 871178676Ssam 872198429Srpaulostruct iwn_phy_calib_gain { 873198429Srpaulo uint8_t code; 874198429Srpaulo uint8_t group; 875198429Srpaulo uint8_t ngroups; 876198429Srpaulo uint8_t isvalid; 877178676Ssam 878198429Srpaulo int8_t gain[3]; 879198429Srpaulo uint8_t reserved; 880198429Srpaulo} __packed; 881198429Srpaulo 882198429Srpaulo/* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 883198429Srpaulostruct iwn_spectrum_cmd { 884198429Srpaulo uint16_t len; 885198429Srpaulo uint8_t token; 886198429Srpaulo uint8_t id; 887198429Srpaulo uint8_t origin; 888198429Srpaulo uint8_t periodic; 889198429Srpaulo uint16_t timeout; 890198429Srpaulo uint32_t start; 891198429Srpaulo uint32_t reserved1; 892198429Srpaulo uint32_t flags; 893198429Srpaulo uint32_t filter; 894198429Srpaulo uint16_t nchan; 895198429Srpaulo uint16_t reserved2; 896198429Srpaulo struct { 897198429Srpaulo uint32_t duration; 898198429Srpaulo uint8_t chan; 899198429Srpaulo uint8_t type; 900198429Srpaulo#define IWN_MEASUREMENT_BASIC (1 << 0) 901198429Srpaulo#define IWN_MEASUREMENT_CCA (1 << 1) 902198429Srpaulo#define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 903198429Srpaulo#define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 904198429Srpaulo#define IWN_MEASUREMENT_FRAME (1 << 4) 905198429Srpaulo#define IWN_MEASUREMENT_IDLE (1 << 7) 906198429Srpaulo 907198429Srpaulo uint16_t reserved; 908198429Srpaulo } __packed chan[10]; 909198429Srpaulo} __packed; 910198429Srpaulo 911198429Srpaulo/* Structure for IWN_UC_READY notification. */ 912178676Ssam#define IWN_NATTEN_GROUPS 5 913178676Ssamstruct iwn_ucode_info { 914178676Ssam uint8_t minor; 915178676Ssam uint8_t major; 916178676Ssam uint16_t reserved1; 917178676Ssam uint8_t revision[8]; 918178676Ssam uint8_t type; 919178676Ssam uint8_t subtype; 920178676Ssam#define IWN_UCODE_RUNTIME 0 921178676Ssam#define IWN_UCODE_INIT 9 922178676Ssam 923178676Ssam uint16_t reserved2; 924178676Ssam uint32_t logptr; 925198429Srpaulo uint32_t errptr; 926178676Ssam uint32_t tstamp; 927178676Ssam uint32_t valid; 928178676Ssam 929198429Srpaulo /* The following fields are for UCODE_INIT only. */ 930178676Ssam int32_t volt; 931178676Ssam struct { 932178676Ssam int32_t chan20MHz; 933178676Ssam int32_t chan40MHz; 934178676Ssam } __packed temp[4]; 935198429Srpaulo int32_t atten[IWN_NATTEN_GROUPS][2]; 936178676Ssam} __packed; 937178676Ssam 938198429Srpaulo/* Structures for IWN_TX_DONE notification. */ 939198429Srpaulo#define IWN_TX_SUCCESS 0x00 940198429Srpaulo#define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */ 941198429Srpaulo#define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */ 942198429Srpaulo#define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */ 943198429Srpaulo#define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */ 944198429Srpaulo#define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */ 945198429Srpaulo#define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */ 946198429Srpaulo 947198429Srpaulostruct iwn4965_tx_stat { 948178676Ssam uint8_t nframes; 949198429Srpaulo uint8_t killcnt; 950198429Srpaulo uint8_t rtscnt; 951198429Srpaulo uint8_t retrycnt; 952178676Ssam uint8_t rate; 953178676Ssam uint8_t rflags; 954178676Ssam uint16_t xrflags; 955178676Ssam uint16_t duration; 956178676Ssam uint16_t reserved; 957178676Ssam uint32_t power[2]; 958178676Ssam uint32_t status; 959178676Ssam} __packed; 960178676Ssam 961198429Srpaulostruct iwn5000_tx_stat { 962198429Srpaulo uint8_t nframes; 963198429Srpaulo uint8_t killcnt; 964198429Srpaulo uint8_t rtscnt; 965198429Srpaulo uint8_t retrycnt; 966198429Srpaulo uint8_t rate; 967198429Srpaulo uint8_t rflags; 968198429Srpaulo uint16_t xrflags; 969198429Srpaulo uint16_t duration; 970198429Srpaulo uint16_t reserved; 971198429Srpaulo uint32_t power[2]; 972198429Srpaulo uint32_t info; 973198429Srpaulo uint16_t seq; 974198429Srpaulo uint16_t len; 975198429Srpaulo uint32_t tlc; 976198429Srpaulo uint16_t status; 977198429Srpaulo uint16_t sequence; 978198429Srpaulo} __packed; 979198429Srpaulo 980198429Srpaulo/* Structure for IWN_BEACON_MISSED notification. */ 981178676Ssamstruct iwn_beacon_missed { 982178676Ssam uint32_t consecutive; 983178676Ssam uint32_t total; 984178676Ssam uint32_t expected; 985178676Ssam uint32_t received; 986178676Ssam} __packed; 987178676Ssam 988198429Srpaulo/* Structure for IWN_MPDU_RX_DONE notification. */ 989198429Srpaulostruct iwn_rx_mpdu { 990178676Ssam uint16_t len; 991178676Ssam uint16_t reserved; 992178676Ssam} __packed; 993178676Ssam 994198429Srpaulo/* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 995198429Srpaulostruct iwn4965_rx_phystat { 996198429Srpaulo uint16_t antenna; 997198429Srpaulo uint16_t agc; 998198429Srpaulo uint8_t rssi[6]; 999198429Srpaulo} __packed; 1000198429Srpaulo 1001198429Srpaulostruct iwn5000_rx_phystat { 1002198429Srpaulo uint32_t reserved1; 1003198429Srpaulo uint32_t agc; 1004198429Srpaulo uint16_t rssi[3]; 1005198429Srpaulo} __packed; 1006198429Srpaulo 1007178676Ssamstruct iwn_rx_stat { 1008178676Ssam uint8_t phy_len; 1009178676Ssam uint8_t cfg_phy_len; 1010178676Ssam#define IWN_STAT_MAXLEN 20 1011178676Ssam 1012178676Ssam uint8_t id; 1013178676Ssam uint8_t reserved1; 1014178676Ssam uint64_t tstamp; 1015178676Ssam uint32_t beacon; 1016178676Ssam uint16_t flags; 1017198429Srpaulo#define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1018198429Srpaulo 1019178676Ssam uint16_t chan; 1020198429Srpaulo uint8_t phybuf[32]; 1021178676Ssam uint8_t rate; 1022178676Ssam uint8_t rflags; 1023178676Ssam uint16_t xrflags; 1024178676Ssam uint16_t len; 1025178676Ssam uint16_t reserve3; 1026178676Ssam} __packed; 1027178676Ssam 1028198429Srpaulo#define IWN_RSSI_TO_DBM 44 1029198429Srpaulo 1030198429Srpaulo/* Structure for IWN_START_SCAN notification. */ 1031178676Ssamstruct iwn_start_scan { 1032178676Ssam uint64_t tstamp; 1033178676Ssam uint32_t tbeacon; 1034178676Ssam uint8_t chan; 1035178676Ssam uint8_t band; 1036178676Ssam uint16_t reserved; 1037178676Ssam uint32_t status; 1038178676Ssam} __packed; 1039178676Ssam 1040198429Srpaulo/* Structure for IWN_STOP_SCAN notification. */ 1041178676Ssamstruct iwn_stop_scan { 1042178676Ssam uint8_t nchan; 1043178676Ssam uint8_t status; 1044178676Ssam uint8_t reserved; 1045178676Ssam uint8_t chan; 1046178676Ssam uint64_t tsf; 1047178676Ssam} __packed; 1048178676Ssam 1049198429Srpaulo/* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1050198429Srpaulostruct iwn_spectrum_notif { 1051198429Srpaulo uint8_t id; 1052198429Srpaulo uint8_t token; 1053198429Srpaulo uint8_t idx; 1054198429Srpaulo uint8_t state; 1055198429Srpaulo#define IWN_MEASUREMENT_START 0 1056198429Srpaulo#define IWN_MEASUREMENT_STOP 1 1057198429Srpaulo 1058198429Srpaulo uint32_t start; 1059198429Srpaulo uint8_t band; 1060198429Srpaulo uint8_t chan; 1061198429Srpaulo uint8_t type; 1062198429Srpaulo uint8_t reserved1; 1063198429Srpaulo uint32_t cca_ofdm; 1064198429Srpaulo uint32_t cca_cck; 1065198429Srpaulo uint32_t cca_time; 1066198429Srpaulo uint8_t basic; 1067198429Srpaulo uint8_t reserved2[3]; 1068198429Srpaulo uint32_t ofdm[8]; 1069198429Srpaulo uint32_t cck[8]; 1070198429Srpaulo uint32_t stop; 1071198429Srpaulo uint32_t status; 1072198429Srpaulo#define IWN_MEASUREMENT_OK 0 1073198429Srpaulo#define IWN_MEASUREMENT_CONCURRENT 1 1074198429Srpaulo#define IWN_MEASUREMENT_CSA_CONFLICT 2 1075198429Srpaulo#define IWN_MEASUREMENT_TGH_CONFLICT 3 1076198429Srpaulo#define IWN_MEASUREMENT_STOPPED 6 1077198429Srpaulo#define IWN_MEASUREMENT_TIMEOUT 7 1078198429Srpaulo#define IWN_MEASUREMENT_FAILED 8 1079198429Srpaulo} __packed; 1080198429Srpaulo 1081198429Srpaulo/* Structure for IWN_{RX,BEACON}_STATISTICS notification. */ 1082178676Ssamstruct iwn_rx_phy_stats { 1083178676Ssam uint32_t ina; 1084178676Ssam uint32_t fina; 1085178676Ssam uint32_t bad_plcp; 1086178676Ssam uint32_t bad_crc32; 1087178676Ssam uint32_t overrun; 1088178676Ssam uint32_t eoverrun; 1089178676Ssam uint32_t good_crc32; 1090178676Ssam uint32_t fa; 1091178676Ssam uint32_t bad_fina_sync; 1092178676Ssam uint32_t sfd_timeout; 1093178676Ssam uint32_t fina_timeout; 1094178676Ssam uint32_t no_rts_ack; 1095178676Ssam uint32_t rxe_limit; 1096178676Ssam uint32_t ack; 1097178676Ssam uint32_t cts; 1098178676Ssam uint32_t ba_resp; 1099178676Ssam uint32_t dsp_kill; 1100178676Ssam uint32_t bad_mh; 1101178676Ssam uint32_t rssi_sum; 1102178676Ssam uint32_t reserved; 1103178676Ssam} __packed; 1104178676Ssam 1105178676Ssamstruct iwn_rx_general_stats { 1106178676Ssam uint32_t bad_cts; 1107178676Ssam uint32_t bad_ack; 1108178676Ssam uint32_t not_bss; 1109178676Ssam uint32_t filtered; 1110178676Ssam uint32_t bad_chan; 1111178676Ssam uint32_t beacons; 1112178676Ssam uint32_t missed_beacons; 1113178676Ssam uint32_t adc_saturated; /* time in 0.8us */ 1114178676Ssam uint32_t ina_searched; /* time in 0.8us */ 1115178676Ssam uint32_t noise[3]; 1116178676Ssam uint32_t flags; 1117178676Ssam uint32_t load; 1118178676Ssam uint32_t fa; 1119178676Ssam uint32_t rssi[3]; 1120178676Ssam uint32_t energy[3]; 1121178676Ssam} __packed; 1122178676Ssam 1123178676Ssamstruct iwn_rx_ht_phy_stats { 1124178676Ssam uint32_t bad_plcp; 1125178676Ssam uint32_t overrun; 1126178676Ssam uint32_t eoverrun; 1127178676Ssam uint32_t good_crc32; 1128178676Ssam uint32_t bad_crc32; 1129178676Ssam uint32_t bad_mh; 1130178676Ssam uint32_t good_ampdu_crc32; 1131178676Ssam uint32_t ampdu; 1132178676Ssam uint32_t fragment; 1133178676Ssam uint32_t reserved; 1134178676Ssam} __packed; 1135178676Ssam 1136178676Ssamstruct iwn_rx_stats { 1137178676Ssam struct iwn_rx_phy_stats ofdm; 1138178676Ssam struct iwn_rx_phy_stats cck; 1139178676Ssam struct iwn_rx_general_stats general; 1140178676Ssam struct iwn_rx_ht_phy_stats ht; 1141178676Ssam} __packed; 1142178676Ssam 1143178676Ssamstruct iwn_tx_stats { 1144178676Ssam uint32_t preamble; 1145178676Ssam uint32_t rx_detected; 1146178676Ssam uint32_t bt_defer; 1147178676Ssam uint32_t bt_kill; 1148178676Ssam uint32_t short_len; 1149178676Ssam uint32_t cts_timeout; 1150178676Ssam uint32_t ack_timeout; 1151178676Ssam uint32_t exp_ack; 1152178676Ssam uint32_t ack; 1153178676Ssam uint32_t msdu; 1154178676Ssam uint32_t busrt_err1; 1155178676Ssam uint32_t burst_err2; 1156178676Ssam uint32_t cts_collision; 1157178676Ssam uint32_t ack_collision; 1158178676Ssam uint32_t ba_timeout; 1159178676Ssam uint32_t ba_resched; 1160178676Ssam uint32_t query_ampdu; 1161178676Ssam uint32_t query; 1162178676Ssam uint32_t query_ampdu_frag; 1163178676Ssam uint32_t query_mismatch; 1164178676Ssam uint32_t not_ready; 1165178676Ssam uint32_t underrun; 1166178676Ssam uint32_t bt_ht_kill; 1167178676Ssam uint32_t rx_ba_resp; 1168178676Ssam uint32_t reserved[2]; 1169178676Ssam} __packed; 1170178676Ssam 1171178676Ssamstruct iwn_general_stats { 1172178676Ssam uint32_t temp; 1173178676Ssam uint32_t temp_m; 1174178676Ssam uint32_t burst_check; 1175178676Ssam uint32_t burst; 1176178676Ssam uint32_t reserved1[4]; 1177178676Ssam uint32_t sleep; 1178178676Ssam uint32_t slot_out; 1179178676Ssam uint32_t slot_idle; 1180178676Ssam uint32_t ttl_tstamp; 1181178676Ssam uint32_t tx_ant_a; 1182178676Ssam uint32_t tx_ant_b; 1183178676Ssam uint32_t exec; 1184178676Ssam uint32_t probe; 1185178676Ssam uint32_t reserved2[2]; 1186178676Ssam uint32_t rx_enabled; 1187178676Ssam uint32_t reserved3[3]; 1188178676Ssam} __packed; 1189178676Ssam 1190178676Ssamstruct iwn_stats { 1191178676Ssam uint32_t flags; 1192178676Ssam struct iwn_rx_stats rx; 1193178676Ssam struct iwn_tx_stats tx; 1194178676Ssam struct iwn_general_stats general; 1195178676Ssam} __packed; 1196178676Ssam 1197178676Ssam 1198198429Srpaulo/* Firmware error dump. */ 1199198429Srpaulostruct iwn_fw_dump { 1200198429Srpaulo uint32_t valid; 1201198429Srpaulo uint32_t id; 1202198429Srpaulo uint32_t pc; 1203198429Srpaulo uint32_t branch_link[2]; 1204198429Srpaulo uint32_t interrupt_link[2]; 1205198429Srpaulo uint32_t error_data[2]; 1206198429Srpaulo uint32_t src_line; 1207198429Srpaulo uint32_t tsf; 1208198429Srpaulo uint32_t time[2]; 1209198429Srpaulo} __packed; 1210198429Srpaulo 1211198429Srpaulo/* Firmware image file header. */ 1212178676Ssamstruct iwn_firmware_hdr { 1213178676Ssam uint32_t version; 1214178676Ssam uint32_t main_textsz; 1215178676Ssam uint32_t main_datasz; 1216178676Ssam uint32_t init_textsz; 1217178676Ssam uint32_t init_datasz; 1218178676Ssam uint32_t boot_textsz; 1219178676Ssam} __packed; 1220178676Ssam 1221198429Srpaulo#define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1222198429Srpaulo#define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1223198429Srpaulo#define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1224198429Srpaulo#define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1225178676Ssam#define IWN_FW_BOOT_TEXT_MAXSZ 1024 1226198429Srpaulo#define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1227198429Srpaulo#define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1228178676Ssam 1229178676Ssam/* 1230178676Ssam * Offsets into EEPROM. 1231178676Ssam */ 1232178676Ssam#define IWN_EEPROM_MAC 0x015 1233198429Srpaulo#define IWN_EEPROM_RFCFG 0x048 1234198429Srpaulo#define IWN4965_EEPROM_DOMAIN 0x060 1235198429Srpaulo#define IWN4965_EEPROM_BAND1 0x063 1236198429Srpaulo#define IWN5000_EEPROM_REG 0x066 1237198429Srpaulo#define IWN5000_EEPROM_CAL 0x067 1238198429Srpaulo#define IWN4965_EEPROM_BAND2 0x072 1239198429Srpaulo#define IWN4965_EEPROM_BAND3 0x080 1240198429Srpaulo#define IWN4965_EEPROM_BAND4 0x08d 1241198429Srpaulo#define IWN4965_EEPROM_BAND5 0x099 1242198429Srpaulo#define IWN4965_EEPROM_BAND6 0x0a0 1243198429Srpaulo#define IWN4965_EEPROM_BAND7 0x0a8 1244198429Srpaulo#define IWN4965_EEPROM_MAXPOW 0x0e8 1245198429Srpaulo#define IWN4965_EEPROM_VOLTAGE 0x0e9 1246198429Srpaulo#define IWN4965_EEPROM_BANDS 0x0ea 1247198429Srpaulo/* Indirect offsets. */ 1248198429Srpaulo#define IWN5000_EEPROM_DOMAIN 0x001 1249198429Srpaulo#define IWN5000_EEPROM_BAND1 0x004 1250198429Srpaulo#define IWN5000_EEPROM_BAND2 0x013 1251198429Srpaulo#define IWN5000_EEPROM_BAND3 0x021 1252198429Srpaulo#define IWN5000_EEPROM_BAND4 0x02e 1253198429Srpaulo#define IWN5000_EEPROM_BAND5 0x03a 1254198429Srpaulo#define IWN5000_EEPROM_BAND6 0x041 1255198429Srpaulo#define IWN5000_EEPROM_BAND7 0x049 1256198429Srpaulo#define IWN5000_EEPROM_CRYSTAL 0x128 1257198429Srpaulo#define IWN5000_EEPROM_TEMP 0x12a 1258198429Srpaulo#define IWN5000_EEPROM_VOLT 0x12b 1259178676Ssam 1260198429Srpaulo/* Possible flags for IWN_EEPROM_RFCFG. */ 1261198429Srpaulo#define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1262198429Srpaulo#define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1263198429Srpaulo#define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1264198429Srpaulo#define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1265198429Srpaulo#define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1266198429Srpaulo 1267178676Ssamstruct iwn_eeprom_chan { 1268178676Ssam uint8_t flags; 1269178676Ssam#define IWN_EEPROM_CHAN_VALID (1 << 0) 1270198429Srpaulo#define IWN_EEPROM_CHAN_IBSS (1 << 1) 1271198429Srpaulo#define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1272198429Srpaulo#define IWN_EEPROM_CHAN_RADAR (1 << 4) 1273178676Ssam#define IWN_EEPROM_CHAN_WIDE (1 << 5) /* HT40 */ 1274178676Ssam#define IWN_EEPROM_CHAN_NARROW (1 << 6) /* HT20 */ 1275178676Ssam 1276178676Ssam int8_t maxpwr; 1277178676Ssam} __packed; 1278178676Ssam 1279178676Ssam#define IWN_NSAMPLES 3 1280198429Srpaulostruct iwn4965_eeprom_chan_samples { 1281178676Ssam uint8_t num; 1282178676Ssam struct { 1283178676Ssam uint8_t temp; 1284178676Ssam uint8_t gain; 1285178676Ssam uint8_t power; 1286178676Ssam int8_t pa_det; 1287198429Srpaulo } samples[2][IWN_NSAMPLES]; 1288178676Ssam} __packed; 1289178676Ssam 1290178676Ssam#define IWN_NBANDS 8 1291198429Srpaulostruct iwn4965_eeprom_band { 1292178676Ssam uint8_t lo; /* low channel number */ 1293178676Ssam uint8_t hi; /* high channel number */ 1294198429Srpaulo struct iwn4965_eeprom_chan_samples chans[2]; 1295178676Ssam} __packed; 1296178676Ssam 1297198429Srpaulo/* 1298198429Srpaulo * Offsets of channels descriptions in EEPROM. 1299198429Srpaulo */ 1300198429Srpaulostatic const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1301198429Srpaulo IWN4965_EEPROM_BAND1, 1302198429Srpaulo IWN4965_EEPROM_BAND2, 1303198429Srpaulo IWN4965_EEPROM_BAND3, 1304198429Srpaulo IWN4965_EEPROM_BAND4, 1305198429Srpaulo IWN4965_EEPROM_BAND5, 1306198429Srpaulo IWN4965_EEPROM_BAND6, 1307198429Srpaulo IWN4965_EEPROM_BAND7 1308198429Srpaulo}; 1309178676Ssam 1310198429Srpaulostatic const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1311198429Srpaulo IWN5000_EEPROM_BAND1, 1312198429Srpaulo IWN5000_EEPROM_BAND2, 1313198429Srpaulo IWN5000_EEPROM_BAND3, 1314198429Srpaulo IWN5000_EEPROM_BAND4, 1315198429Srpaulo IWN5000_EEPROM_BAND5, 1316198429Srpaulo IWN5000_EEPROM_BAND6, 1317198429Srpaulo IWN5000_EEPROM_BAND7 1318198429Srpaulo}; 1319198429Srpaulo 1320198429Srpaulo#define IWN_CHAN_BANDS_COUNT 7 1321198429Srpaulo#define IWN_MAX_CHAN_PER_BAND 14 1322198429Srpaulostatic const struct iwn_chan_band { 1323198429Srpaulo uint8_t nchan; 1324198429Srpaulo uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1325198429Srpaulo} iwn_bands[] = { 1326198429Srpaulo /* 20MHz channels, 2GHz band. */ 1327198429Srpaulo { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1328198429Srpaulo /* 20MHz channels, 5GHz band. */ 1329198429Srpaulo { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1330198429Srpaulo { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1331198429Srpaulo { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1332198429Srpaulo { 6, { 145, 149, 153, 157, 161, 165 } }, 1333198429Srpaulo /* 40MHz channels (primary channels), 2GHz band. */ 1334198429Srpaulo { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1335198429Srpaulo /* 40MHz channels (primary channels), 5GHz band. */ 1336198429Srpaulo { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1337198429Srpaulo}; 1338198429Srpaulo 1339198429Srpaulo#define IWN_RIDX_MCS 0x08 /* or'd to indicate MCS */ 1340198429Srpaulo 1341198429Srpaulo/* HW rate indices. */ 1342198429Srpaulo#define IWN_RIDX_CCK1 0 1343198429Srpaulo#define IWN_RIDX_CCK11 3 1344198429Srpaulo#define IWN_RIDX_OFDM6 4 1345198429Srpaulo#define IWN_RIDX_OFDM54 11 1346198429Srpaulo 1347198429Srpaulostatic const struct iwn_rate { 1348198429Srpaulo uint8_t rate; 1349198429Srpaulo uint8_t plcp; 1350198429Srpaulo uint8_t flags; 1351198429Srpaulo} iwn_rates[IWN_RIDX_MAX + 1] = { 1352198429Srpaulo { 2, 10, IWN_RFLAG_CCK }, 1353198429Srpaulo { 4, 20, IWN_RFLAG_CCK }, 1354198429Srpaulo { 11, 55, IWN_RFLAG_CCK }, 1355198429Srpaulo { 22, 110, IWN_RFLAG_CCK }, 1356198429Srpaulo { 12, 0xd, 0 }, 1357198429Srpaulo { 18, 0xf, 0 }, 1358198429Srpaulo { 24, 0x5, 0 }, 1359198429Srpaulo { 36, 0x7, 0 }, 1360198429Srpaulo { 48, 0x9, 0 }, 1361198429Srpaulo { 72, 0xb, 0 }, 1362198429Srpaulo { 96, 0x1, 0 }, 1363198429Srpaulo { 108, 0x3, 0 }, 1364198429Srpaulo { 120, 0x3, 0 } 1365198429Srpaulo}; 1366198429Srpaulo 1367198429Srpaulo#define IWN4965_MAX_PWR_INDEX 107 1368198429Srpaulo 1369178676Ssam/* 1370178676Ssam * RF Tx gain values from highest to lowest power (values obtained from 1371178676Ssam * the reference driver.) 1372178676Ssam */ 1373198429Srpaulostatic const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1374178676Ssam 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 1375178676Ssam 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 1376178676Ssam 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 1377178676Ssam 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 1378178676Ssam 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 1379178676Ssam 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 1380178676Ssam 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1381178676Ssam 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1382178676Ssam 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1383178676Ssam 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1384178676Ssam}; 1385178676Ssam 1386198429Srpaulostatic const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1387178676Ssam 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 1388178676Ssam 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 1389178676Ssam 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 1390178676Ssam 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 1391178676Ssam 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 1392178676Ssam 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 1393178676Ssam 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 1394178676Ssam 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 1395178676Ssam 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 1396178676Ssam 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1397178676Ssam}; 1398178676Ssam 1399178676Ssam/* 1400178676Ssam * DSP pre-DAC gain values from highest to lowest power (values obtained 1401178676Ssam * from the reference driver.) 1402178676Ssam */ 1403198429Srpaulostatic const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1404178676Ssam 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1405178676Ssam 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1406178676Ssam 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1407178676Ssam 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1408178676Ssam 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1409178676Ssam 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1410178676Ssam 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 1411178676Ssam 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 1412178676Ssam 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 1413178676Ssam 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 1414178676Ssam}; 1415178676Ssam 1416198429Srpaulostatic const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1417178676Ssam 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1418178676Ssam 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1419178676Ssam 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1420178676Ssam 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1421178676Ssam 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1422178676Ssam 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1423178676Ssam 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1424178676Ssam 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1425178676Ssam 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1426178676Ssam 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 1427178676Ssam}; 1428178676Ssam 1429198429Srpaulo/* 1430198429Srpaulo * Power saving settings (values obtained from the reference driver.) 1431198429Srpaulo */ 1432198429Srpaulo#define IWN_NDTIMRANGES 3 1433198429Srpaulo#define IWN_NPOWERLEVELS 6 1434198429Srpaulostatic const struct iwn_pmgt { 1435198429Srpaulo uint32_t rxtimeout; 1436198429Srpaulo uint32_t txtimeout; 1437198429Srpaulo uint32_t intval[5]; 1438198429Srpaulo int skip_dtim; 1439198429Srpaulo} iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 1440198429Srpaulo /* DTIM <= 2 */ 1441198429Srpaulo { 1442198429Srpaulo { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1443198429Srpaulo { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 1444198429Srpaulo { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 1445198429Srpaulo { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 1446198429Srpaulo { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 1447198429Srpaulo { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 1448198429Srpaulo }, 1449198429Srpaulo /* 3 <= DTIM <= 10 */ 1450198429Srpaulo { 1451198429Srpaulo { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1452198429Srpaulo { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 1453198429Srpaulo { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 1454198429Srpaulo { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 1455198429Srpaulo { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 1456198429Srpaulo { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 1457198429Srpaulo }, 1458198429Srpaulo /* DTIM >= 11 */ 1459198429Srpaulo { 1460198429Srpaulo { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1461198429Srpaulo { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 1462198429Srpaulo { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 1463198429Srpaulo { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 1464198429Srpaulo { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 1465198429Srpaulo { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1466198429Srpaulo } 1467198429Srpaulo}; 1468198429Srpaulo 1469198429Srpaulostruct iwn_sensitivity_limits { 1470198429Srpaulo uint32_t min_ofdm_x1; 1471198429Srpaulo uint32_t max_ofdm_x1; 1472198429Srpaulo uint32_t min_ofdm_mrc_x1; 1473198429Srpaulo uint32_t max_ofdm_mrc_x1; 1474198429Srpaulo uint32_t min_ofdm_x4; 1475198429Srpaulo uint32_t max_ofdm_x4; 1476198429Srpaulo uint32_t min_ofdm_mrc_x4; 1477198429Srpaulo uint32_t max_ofdm_mrc_x4; 1478198429Srpaulo uint32_t min_cck_x4; 1479198429Srpaulo uint32_t max_cck_x4; 1480198429Srpaulo uint32_t min_cck_mrc_x4; 1481198429Srpaulo uint32_t max_cck_mrc_x4; 1482198429Srpaulo uint32_t min_energy_cck; 1483198429Srpaulo uint32_t energy_cck; 1484198429Srpaulo uint32_t energy_ofdm; 1485198429Srpaulo}; 1486198429Srpaulo 1487198429Srpaulo/* 1488198429Srpaulo * RX sensitivity limits (values obtained from the reference driver.) 1489198429Srpaulo */ 1490198429Srpaulostatic const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 1491198429Srpaulo 105, 140, 1492198429Srpaulo 170, 210, 1493198429Srpaulo 85, 120, 1494198429Srpaulo 170, 210, 1495198429Srpaulo 125, 200, 1496198429Srpaulo 200, 400, 1497198429Srpaulo 97, 1498198429Srpaulo 100, 1499198429Srpaulo 100 1500198429Srpaulo}; 1501198429Srpaulo 1502198429Srpaulostatic const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 1503198429Srpaulo 120, 155, 1504198429Srpaulo 240, 290, 1505198429Srpaulo 90, 120, 1506198429Srpaulo 170, 210, 1507198429Srpaulo 125, 200, 1508198429Srpaulo 170, 400, 1509198429Srpaulo 95, 1510198429Srpaulo 95, 1511198429Srpaulo 95 1512198429Srpaulo}; 1513198429Srpaulo 1514198429Srpaulo/* Map TID to TX scheduler's FIFO. */ 1515198429Srpaulostatic const uint8_t iwn_tid2fifo[] = { 1516198429Srpaulo 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 1517198429Srpaulo}; 1518198429Srpaulo 1519198429Srpaulo/* Firmware errors. */ 1520198429Srpaulostatic const char * const iwn_fw_errmsg[] = { 1521198429Srpaulo "OK", 1522198429Srpaulo "FAIL", 1523198429Srpaulo "BAD_PARAM", 1524198429Srpaulo "BAD_CHECKSUM", 1525198429Srpaulo "NMI_INTERRUPT_WDG", 1526198429Srpaulo "SYSASSERT", 1527198429Srpaulo "FATAL_ERROR", 1528198429Srpaulo "BAD_COMMAND", 1529198429Srpaulo "HW_ERROR_TUNE_LOCK", 1530198429Srpaulo "HW_ERROR_TEMPERATURE", 1531198429Srpaulo "ILLEGAL_CHAN_FREQ", 1532198429Srpaulo "VCC_NOT_STABLE", 1533198429Srpaulo "FH_ERROR", 1534198429Srpaulo "NMI_INTERRUPT_HOST", 1535198429Srpaulo "NMI_INTERRUPT_ACTION_PT", 1536198429Srpaulo "NMI_INTERRUPT_UNKNOWN", 1537198429Srpaulo "UCODE_VERSION_MISMATCH", 1538198429Srpaulo "HW_ERROR_ABS_LOCK", 1539198429Srpaulo "HW_ERROR_CAL_LOCK_FAIL", 1540198429Srpaulo "NMI_INTERRUPT_INST_ACTION_PT", 1541198429Srpaulo "NMI_INTERRUPT_DATA_ACTION_PT", 1542198429Srpaulo "NMI_TRM_HW_ER", 1543198429Srpaulo "NMI_INTERRUPT_TRM", 1544198429Srpaulo "NMI_INTERRUPT_BREAKPOINT" 1545198429Srpaulo "DEBUG_0", 1546198429Srpaulo "DEBUG_1", 1547198429Srpaulo "DEBUG_2", 1548198429Srpaulo "DEBUG_3", 1549198429Srpaulo "UNKNOWN" 1550198429Srpaulo}; 1551198429Srpaulo 1552198429Srpaulo/* Find least significant bit that is set. */ 1553198429Srpaulo#define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 1554198429Srpaulo 1555178676Ssam#define IWN_READ(sc, reg) \ 1556178676Ssam bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1557178676Ssam 1558178676Ssam#define IWN_WRITE(sc, reg, val) \ 1559178676Ssam bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1560178676Ssam 1561198429Srpaulo#define IWN_SETBITS(sc, reg, mask) \ 1562198429Srpaulo IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 1563198429Srpaulo 1564198429Srpaulo#define IWN_CLRBITS(sc, reg, mask) \ 1565198429Srpaulo IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 1566