1178676Ssam/* $FreeBSD$ */ 2210111Sbschmidt/* $OpenBSD: if_iwnreg.h,v 1.40 2010/05/05 19:41:57 damien Exp $ */ 3178676Ssam 4178676Ssam/*- 5198429Srpaulo * Copyright (c) 2007, 2008 6178676Ssam * Damien Bergamini <damien.bergamini@free.fr> 7178676Ssam * 8178676Ssam * Permission to use, copy, modify, and distribute this software for any 9178676Ssam * purpose with or without fee is hereby granted, provided that the above 10178676Ssam * copyright notice and this permission notice appear in all copies. 11178676Ssam * 12178676Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13178676Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14178676Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15178676Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16178676Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17178676Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18178676Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19178676Ssam */ 20257034Sadrian#ifndef __IF_IWNREG_H__ 21257034Sadrian#define __IF_IWNREG_H__ 22178676Ssam 23253898Sadrian#define IWN_CT_KILL_THRESHOLD 114 /* in Celsius */ 24253898Sadrian#define IWN_CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */ 25253898Sadrian 26178676Ssam#define IWN_TX_RING_COUNT 256 27198429Srpaulo#define IWN_TX_RING_LOMARK 192 28198429Srpaulo#define IWN_TX_RING_HIMARK 224 29198429Srpaulo#define IWN_RX_RING_COUNT_LOG 6 30198429Srpaulo#define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 31178676Ssam 32198429Srpaulo#define IWN4965_NTXQUEUES 16 33198429Srpaulo#define IWN5000_NTXQUEUES 20 34178676Ssam 35221651Sbschmidt#define IWN4965_FIRSTAGGQUEUE 7 36221651Sbschmidt#define IWN5000_FIRSTAGGQUEUE 10 37221651Sbschmidt 38198429Srpaulo#define IWN4965_NDMACHNLS 7 39198429Srpaulo#define IWN5000_NDMACHNLS 8 40178676Ssam 41198429Srpaulo#define IWN_SRVC_DMACHNL 9 42198429Srpaulo 43201209Srpaulo#define IWN_ICT_SIZE 4096 44201209Srpaulo#define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 45201209Srpaulo 46253898Sadrian/* For cards with PAN command, default is IWN_CMD_QUEUE_NUM */ 47253898Sadrian#define IWN_CMD_QUEUE_NUM 4 48253898Sadrian#define IWN_PAN_CMD_QUEUE 9 49253898Sadrian 50198429Srpaulo/* Maximum number of DMA segments for TX. */ 51178676Ssam#define IWN_MAX_SCATTER 20 52178676Ssam 53198429Srpaulo/* RX buffers must be large enough to hold a full 4K A-MPDU. */ 54178676Ssam#define IWN_RBUF_SIZE (4 * 1024) 55178676Ssam 56198429Srpaulo#if defined(__LP64__) 57198429Srpaulo/* HW supports 36-bit DMA addresses. */ 58198429Srpaulo#define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 59198429Srpaulo#define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 60198429Srpaulo#else 61198429Srpaulo#define IWN_LOADDR(paddr) (paddr) 62198429Srpaulo#define IWN_HIADDR(paddr) (0) 63198429Srpaulo#endif 64198429Srpaulo 65178676Ssam/* 66178676Ssam * Control and status registers. 67178676Ssam */ 68198429Srpaulo#define IWN_HW_IF_CONFIG 0x000 69198429Srpaulo#define IWN_INT_COALESCING 0x004 70201209Srpaulo#define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 71198429Srpaulo#define IWN_INT 0x008 72201209Srpaulo#define IWN_INT_MASK 0x00c 73198429Srpaulo#define IWN_FH_INT 0x010 74253866Sadrian#define IWN_GPIO_IN 0x018 /* read external chip pins */ 75178676Ssam#define IWN_RESET 0x020 76198429Srpaulo#define IWN_GP_CNTRL 0x024 77198429Srpaulo#define IWN_HW_REV 0x028 78198429Srpaulo#define IWN_EEPROM 0x02c 79198429Srpaulo#define IWN_EEPROM_GP 0x030 80198429Srpaulo#define IWN_OTP_GP 0x034 81198429Srpaulo#define IWN_GIO 0x03c 82253866Sadrian#define IWN_GP_UCODE 0x048 83201209Srpaulo#define IWN_GP_DRIVER 0x050 84253866Sadrian#define IWN_UCODE_GP1 0x054 85253866Sadrian#define IWN_UCODE_GP1_SET 0x058 86198429Srpaulo#define IWN_UCODE_GP1_CLR 0x05c 87253866Sadrian#define IWN_UCODE_GP2 0x060 88198429Srpaulo#define IWN_LED 0x094 89201209Srpaulo#define IWN_DRAM_INT_TBL 0x0a0 90220729Sbschmidt#define IWN_SHADOW_REG_CTRL 0x0a8 91198429Srpaulo#define IWN_GIO_CHICKEN 0x100 92198429Srpaulo#define IWN_ANA_PLL 0x20c 93201209Srpaulo#define IWN_HW_REV_WA 0x22c 94198429Srpaulo#define IWN_DBG_HPET_MEM 0x240 95201209Srpaulo#define IWN_DBG_LINK_PWR_MGMT 0x250 96253866Sadrian/* Need nic_lock for use above */ 97198429Srpaulo#define IWN_MEM_RADDR 0x40c 98178676Ssam#define IWN_MEM_WADDR 0x410 99178676Ssam#define IWN_MEM_WDATA 0x418 100198429Srpaulo#define IWN_MEM_RDATA 0x41c 101253898Sadrian#define IWN_TARG_MBX_C 0x430 102220726Sbschmidt#define IWN_PRPH_WADDR 0x444 103220726Sbschmidt#define IWN_PRPH_RADDR 0x448 104220726Sbschmidt#define IWN_PRPH_WDATA 0x44c 105220726Sbschmidt#define IWN_PRPH_RDATA 0x450 106198429Srpaulo#define IWN_HBUS_TARG_WRPTR 0x460 107178676Ssam 108198429Srpaulo/* 109198429Srpaulo * Flow-Handler registers. 110198429Srpaulo */ 111198429Srpaulo#define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 112198429Srpaulo#define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 113198429Srpaulo#define IWN_FH_KW_ADDR 0x197c 114198429Srpaulo#define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 115198429Srpaulo#define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 116198429Srpaulo#define IWN_FH_STATUS_WPTR 0x1bc0 117198429Srpaulo#define IWN_FH_RX_BASE 0x1bc4 118198429Srpaulo#define IWN_FH_RX_WPTR 0x1bc8 119198429Srpaulo#define IWN_FH_RX_CONFIG 0x1c00 120198429Srpaulo#define IWN_FH_RX_STATUS 0x1c44 121198429Srpaulo#define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 122198429Srpaulo#define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 123198429Srpaulo#define IWN_FH_TX_CHICKEN 0x1e98 124198429Srpaulo#define IWN_FH_TX_STATUS 0x1eb0 125178676Ssam 126198429Srpaulo/* 127198429Srpaulo * TX scheduler registers. 128198429Srpaulo */ 129198429Srpaulo#define IWN_SCHED_BASE 0xa02c00 130198429Srpaulo#define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 131198429Srpaulo#define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 132198429Srpaulo#define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 133198429Srpaulo#define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 134198429Srpaulo#define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 135198429Srpaulo#define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 136198429Srpaulo#define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 137198429Srpaulo#define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 138198429Srpaulo#define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 139198429Srpaulo#define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 140198429Srpaulo#define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 141198429Srpaulo#define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 142198429Srpaulo#define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 143198429Srpaulo#define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 144178676Ssam 145178676Ssam/* 146198429Srpaulo * Offsets in TX scheduler's SRAM. 147198429Srpaulo */ 148198429Srpaulo#define IWN4965_SCHED_CTX_OFF 0x380 149198429Srpaulo#define IWN4965_SCHED_CTX_LEN 416 150198429Srpaulo#define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 151198429Srpaulo#define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 152198429Srpaulo#define IWN5000_SCHED_CTX_OFF 0x600 153198429Srpaulo#define IWN5000_SCHED_CTX_LEN 520 154198429Srpaulo#define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 155198429Srpaulo#define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 156198429Srpaulo 157198429Srpaulo/* 158178676Ssam * NIC internal memory offsets. 159178676Ssam */ 160201209Srpaulo#define IWN_APMG_CLK_CTRL 0x3000 161201209Srpaulo#define IWN_APMG_CLK_EN 0x3004 162198429Srpaulo#define IWN_APMG_CLK_DIS 0x3008 163198429Srpaulo#define IWN_APMG_PS 0x300c 164201209Srpaulo#define IWN_APMG_DIGITAL_SVR 0x3058 165201209Srpaulo#define IWN_APMG_ANALOG_SVR 0x306c 166198429Srpaulo#define IWN_APMG_PCI_STT 0x3010 167198429Srpaulo#define IWN_BSM_WR_CTRL 0x3400 168198429Srpaulo#define IWN_BSM_WR_MEM_SRC 0x3404 169198429Srpaulo#define IWN_BSM_WR_MEM_DST 0x3408 170198429Srpaulo#define IWN_BSM_WR_DWCOUNT 0x340c 171198429Srpaulo#define IWN_BSM_DRAM_TEXT_ADDR 0x3490 172198429Srpaulo#define IWN_BSM_DRAM_TEXT_SIZE 0x3494 173198429Srpaulo#define IWN_BSM_DRAM_DATA_ADDR 0x3498 174198429Srpaulo#define IWN_BSM_DRAM_DATA_SIZE 0x349c 175198429Srpaulo#define IWN_BSM_SRAM_BASE 0x3800 176178676Ssam 177198429Srpaulo/* Possible flags for register IWN_HW_IF_CONFIG. */ 178198429Srpaulo#define IWN_HW_IF_CONFIG_4965_R (1 << 4) 179198429Srpaulo#define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 180198429Srpaulo#define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 181198429Srpaulo#define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 182198429Srpaulo#define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 183198429Srpaulo#define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 184198429Srpaulo#define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 185198429Srpaulo#define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 186178676Ssam 187201209Srpaulo/* Possible values for register IWN_INT_PERIODIC. */ 188201209Srpaulo#define IWN_INT_PERIODIC_DIS 0x00 189201209Srpaulo#define IWN_INT_PERIODIC_ENA 0xff 190201209Srpaulo 191198429Srpaulo/* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 192198429Srpaulo#define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 193178676Ssam 194198429Srpaulo/* Possible values for IWN_BSM_WR_MEM_DST. */ 195198429Srpaulo#define IWN_FW_TEXT_BASE 0x00000000 196198429Srpaulo#define IWN_FW_DATA_BASE 0x00800000 197178676Ssam 198198429Srpaulo/* Possible flags for register IWN_RESET. */ 199198429Srpaulo#define IWN_RESET_NEVO (1 << 0) 200198429Srpaulo#define IWN_RESET_SW (1 << 7) 201198429Srpaulo#define IWN_RESET_MASTER_DISABLED (1 << 8) 202198429Srpaulo#define IWN_RESET_STOP_MASTER (1 << 9) 203258780Seadler#define IWN_RESET_LINK_PWR_MGMT_DIS (1U << 31) 204178676Ssam 205198429Srpaulo/* Possible flags for register IWN_GP_CNTRL. */ 206198429Srpaulo#define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 207198429Srpaulo#define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 208198429Srpaulo#define IWN_GP_CNTRL_INIT_DONE (1 << 2) 209198429Srpaulo#define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 210198429Srpaulo#define IWN_GP_CNTRL_SLEEP (1 << 4) 211198429Srpaulo#define IWN_GP_CNTRL_RFKILL (1 << 27) 212178676Ssam 213198429Srpaulo/* Possible flags for register IWN_GIO_CHICKEN. */ 214198429Srpaulo#define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 215198429Srpaulo#define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 216178676Ssam 217198429Srpaulo/* Possible flags for register IWN_GIO. */ 218198429Srpaulo#define IWN_GIO_L0S_ENA (1 << 1) 219178676Ssam 220201209Srpaulo/* Possible flags for register IWN_GP_DRIVER. */ 221201209Srpaulo#define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 222201209Srpaulo#define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 223201209Srpaulo#define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 224206444Sbschmidt#define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 225220729Sbschmidt#define IWN_GP_DRIVER_6050_1X2 (1 << 3) 226253898Sadrian#define IWN_GP_DRIVER_REG_BIT_RADIO_IQ_INVERT (1 << 7) 227257880Sadrian#define IWN_GP_DRIVER_NONE 0 228201209Srpaulo 229198429Srpaulo/* Possible flags for register IWN_UCODE_GP1_CLR. */ 230198429Srpaulo#define IWN_UCODE_GP1_RFKILL (1 << 1) 231198429Srpaulo#define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 232198429Srpaulo#define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 233253898Sadrian#define IWN_UCODE_GP1_CFG_COMPLETE (1 << 5) 234178676Ssam 235198429Srpaulo/* Possible flags/values for register IWN_LED. */ 236198429Srpaulo#define IWN_LED_BSM_CTRL (1 << 5) 237198429Srpaulo#define IWN_LED_OFF 0x00000038 238198429Srpaulo#define IWN_LED_ON 0x00000078 239178676Ssam 240253898Sadrian#define IWN_MAX_BLINK_TBL 10 241253898Sadrian#define IWN_LED_STATIC_ON 0 242253898Sadrian#define IWN_LED_STATIC_OFF 1 243253898Sadrian#define IWN_LED_SLOW_BLINK 2 244253898Sadrian#define IWN_LED_INT_BLINK 3 245253898Sadrian#define IWN_LED_UNIT 0x1388 /* 5 ms */ 246253898Sadrian 247253898Sadrianstatic const struct { 248253898Sadrian uint16_t tpt; /* Mb/s */ 249253898Sadrian uint8_t on_time; 250253898Sadrian uint8_t off_time; 251253898Sadrian} blink_tbl[] = 252253898Sadrian{ 253253898Sadrian {300, 5, 5}, 254253898Sadrian {200, 8, 8}, 255253898Sadrian {100, 11, 11}, 256253898Sadrian {70, 13, 13}, 257253898Sadrian {50, 15, 15}, 258253898Sadrian {20, 17, 17}, 259253898Sadrian {10, 19, 19}, 260253898Sadrian {5, 22, 22}, 261253898Sadrian {1, 26, 26}, 262253898Sadrian {0, 33, 33}, 263253898Sadrian /* SOLID_ON */ 264253898Sadrian}; 265253898Sadrian 266201209Srpaulo/* Possible flags for register IWN_DRAM_INT_TBL. */ 267201209Srpaulo#define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) 268258780Seadler#define IWN_DRAM_INT_TBL_ENABLE (1U << 31) 269201209Srpaulo 270198429Srpaulo/* Possible values for register IWN_ANA_PLL. */ 271198429Srpaulo#define IWN_ANA_PLL_INIT 0x00880300 272178676Ssam 273198429Srpaulo/* Possible flags for register IWN_FH_RX_STATUS. */ 274198429Srpaulo#define IWN_FH_RX_STATUS_IDLE (1 << 24) 275178676Ssam 276198429Srpaulo/* Possible flags for register IWN_BSM_WR_CTRL. */ 277198429Srpaulo#define IWN_BSM_WR_CTRL_START_EN (1 << 30) 278258780Seadler#define IWN_BSM_WR_CTRL_START (1U << 31) 279178676Ssam 280198429Srpaulo/* Possible flags for register IWN_INT. */ 281198429Srpaulo#define IWN_INT_ALIVE (1 << 0) 282198429Srpaulo#define IWN_INT_WAKEUP (1 << 1) 283198429Srpaulo#define IWN_INT_SW_RX (1 << 3) 284198429Srpaulo#define IWN_INT_CT_REACHED (1 << 6) 285198429Srpaulo#define IWN_INT_RF_TOGGLED (1 << 7) 286198429Srpaulo#define IWN_INT_SW_ERR (1 << 25) 287201209Srpaulo#define IWN_INT_SCHED (1 << 26) 288198429Srpaulo#define IWN_INT_FH_TX (1 << 27) 289201209Srpaulo#define IWN_INT_RX_PERIODIC (1 << 28) 290198429Srpaulo#define IWN_INT_HW_ERR (1 << 29) 291258780Seadler#define IWN_INT_FH_RX (1U << 31) 292178676Ssam 293198429Srpaulo/* Shortcut. */ 294201209Srpaulo#define IWN_INT_MASK_DEF \ 295198429Srpaulo (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 296198429Srpaulo IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 297198429Srpaulo IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 298178676Ssam 299198429Srpaulo/* Possible flags for register IWN_FH_INT. */ 300198429Srpaulo#define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 301198429Srpaulo#define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 302198429Srpaulo#define IWN_FH_INT_HI_PRIOR (1 << 30) 303198429Srpaulo/* Shortcuts for the above. */ 304198429Srpaulo#define IWN_FH_INT_TX \ 305198429Srpaulo (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 306198429Srpaulo#define IWN_FH_INT_RX \ 307198429Srpaulo (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 308178676Ssam 309198429Srpaulo/* Possible flags/values for register IWN_FH_TX_CONFIG. */ 310198429Srpaulo#define IWN_FH_TX_CONFIG_DMA_PAUSE 0 311258780Seadler#define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 312198429Srpaulo#define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20) 313178676Ssam 314198429Srpaulo/* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 315198429Srpaulo#define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 316198429Srpaulo#define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 317198429Srpaulo#define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 318198429Srpaulo 319198429Srpaulo/* Possible flags for register IWN_FH_TX_CHICKEN. */ 320198429Srpaulo#define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 321198429Srpaulo 322198429Srpaulo/* Possible flags for register IWN_FH_TX_STATUS. */ 323220659Sbschmidt#define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16)) 324198429Srpaulo 325198429Srpaulo/* Possible flags for register IWN_FH_RX_CONFIG. */ 326258780Seadler#define IWN_FH_RX_CONFIG_ENA (1U << 31) 327198429Srpaulo#define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 328198429Srpaulo#define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16) 329198429Srpaulo#define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15) 330198429Srpaulo#define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 331198429Srpaulo#define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 332198429Srpaulo#define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2) 333198429Srpaulo 334198429Srpaulo/* Possible flags for register IWN_FH_TX_CONFIG. */ 335258780Seadler#define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 336198429Srpaulo#define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3) 337198429Srpaulo 338198429Srpaulo/* Possible flags for register IWN_EEPROM. */ 339198429Srpaulo#define IWN_EEPROM_READ_VALID (1 << 0) 340198429Srpaulo#define IWN_EEPROM_CMD (1 << 1) 341198429Srpaulo 342198429Srpaulo/* Possible flags for register IWN_EEPROM_GP. */ 343198429Srpaulo#define IWN_EEPROM_GP_IF_OWNER 0x00000180 344198429Srpaulo 345198429Srpaulo/* Possible flags for register IWN_OTP_GP. */ 346198429Srpaulo#define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 347198429Srpaulo#define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 348198429Srpaulo#define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 349198429Srpaulo#define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 350198429Srpaulo 351198429Srpaulo/* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 352198429Srpaulo#define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 353198429Srpaulo#define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 354198429Srpaulo#define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 355198429Srpaulo#define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 356198429Srpaulo#define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 357198429Srpaulo#define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 358198429Srpaulo#define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 359198429Srpaulo 360201209Srpaulo/* Possible flags for registers IWN_APMG_CLK_*. */ 361198429Srpaulo#define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 362198429Srpaulo#define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 363198429Srpaulo 364198429Srpaulo/* Possible flags for register IWN_APMG_PS. */ 365198429Srpaulo#define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 366198429Srpaulo#define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 367198429Srpaulo#define IWN_APMG_PS_PWR_SRC_VMAIN 0 368198429Srpaulo#define IWN_APMG_PS_PWR_SRC_VAUX 2 369198429Srpaulo#define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 370198429Srpaulo#define IWN_APMG_PS_RESET_REQ (1 << 26) 371198429Srpaulo 372201209Srpaulo/* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 373201209Srpaulo#define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 374201209Srpaulo#define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 375201209Srpaulo IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 376201209Srpaulo#define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 377201209Srpaulo IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 378201209Srpaulo 379198429Srpaulo/* Possible flags for IWN_APMG_PCI_STT. */ 380198429Srpaulo#define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 381198429Srpaulo 382198429Srpaulo/* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 383258780Seadler#define IWN_FW_UPDATED (1U << 31) 384178676Ssam 385198429Srpaulo#define IWN_SCHED_WINSZ 64 386198429Srpaulo#define IWN_SCHED_LIMIT 64 387198429Srpaulo#define IWN4965_SCHED_COUNT 512 388198429Srpaulo#define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 389198429Srpaulo#define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 390198429Srpaulo#define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 391178676Ssam 392198429Srpaulostruct iwn_tx_desc { 393198429Srpaulo uint8_t reserved1[3]; 394198429Srpaulo uint8_t nsegs; 395198429Srpaulo struct { 396198429Srpaulo uint32_t addr; 397198429Srpaulo uint16_t len; 398198429Srpaulo } __packed segs[IWN_MAX_SCATTER]; 399198429Srpaulo /* Pad to 128 bytes. */ 400198429Srpaulo uint32_t reserved2; 401198429Srpaulo} __packed; 402178676Ssam 403198429Srpaulostruct iwn_rx_status { 404178676Ssam uint16_t closed_count; 405178676Ssam uint16_t closed_rx_count; 406178676Ssam uint16_t finished_count; 407178676Ssam uint16_t finished_rx_count; 408178676Ssam uint32_t reserved[2]; 409178676Ssam} __packed; 410178676Ssam 411178676Ssamstruct iwn_rx_desc { 412253898Sadrian /* 413253898Sadrian * The first 4 bytes of the RX frame header contain both the RX frame 414253898Sadrian * size and some flags. 415253898Sadrian * Bit fields: 416253898Sadrian * 31: flag flush RB request 417253898Sadrian * 30: flag ignore TC (terminal counter) request 418253898Sadrian * 29: flag fast IRQ request 419253898Sadrian * 28-14: Reserved 420253898Sadrian * 13-00: RX frame size 421253898Sadrian */ 422178676Ssam uint32_t len; 423178676Ssam uint8_t type; 424198429Srpaulo#define IWN_UC_READY 1 425198429Srpaulo#define IWN_ADD_NODE_DONE 24 426198429Srpaulo#define IWN_TX_DONE 28 427253898Sadrian#define IWN_REPLY_LED_CMD 72 428198429Srpaulo#define IWN5000_CALIBRATION_RESULT 102 429198429Srpaulo#define IWN5000_CALIBRATION_DONE 103 430198429Srpaulo#define IWN_START_SCAN 130 431253898Sadrian#define IWN_NOTIF_SCAN_RESULT 131 432198429Srpaulo#define IWN_STOP_SCAN 132 433198429Srpaulo#define IWN_RX_STATISTICS 156 434198429Srpaulo#define IWN_BEACON_STATISTICS 157 435198429Srpaulo#define IWN_STATE_CHANGED 161 436198429Srpaulo#define IWN_BEACON_MISSED 162 437198429Srpaulo#define IWN_RX_PHY 192 438198429Srpaulo#define IWN_MPDU_RX_DONE 193 439198429Srpaulo#define IWN_RX_DONE 195 440201209Srpaulo#define IWN_RX_COMPRESSED_BA 197 441178676Ssam 442253898Sadrian uint8_t flags; /* 0:5 reserved, 6 abort, 7 internal */ 443253898Sadrian uint8_t idx; /* position within TX queue */ 444178676Ssam uint8_t qid; 445253898Sadrian /* 0:4 TX queue id - 5:6 reserved - 7 unsolicited RX 446253898Sadrian * or uCode-originated notification 447253898Sadrian */ 448178676Ssam} __packed; 449178676Ssam 450253898Sadrian#define IWN_RX_DESC_QID_MSK 0x1F 451253898Sadrian#define IWN_UNSOLICITED_RX_NOTIF 0x80 452253898Sadrian 453253898Sadrian/* CARD_STATE_NOTIFICATION */ 454253898Sadrian#define IWN_STATE_CHANGE_HW_CARD_DISABLED 0x01 455253898Sadrian#define IWN_STATE_CHANGE_SW_CARD_DISABLED 0x02 456253898Sadrian#define IWN_STATE_CHANGE_CT_CARD_DISABLED 0x04 457253898Sadrian#define IWN_STATE_CHANGE_RXON_CARD_DISABLED 0x10 458253898Sadrian 459198429Srpaulo/* Possible RX status flags. */ 460198429Srpaulo#define IWN_RX_NO_CRC_ERR (1 << 0) 461198429Srpaulo#define IWN_RX_NO_OVFL_ERR (1 << 1) 462198429Srpaulo/* Shortcut for the above. */ 463178676Ssam#define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 464198429Srpaulo#define IWN_RX_MPDU_MIC_OK (1 << 6) 465198429Srpaulo#define IWN_RX_CIPHER_MASK (7 << 8) 466198429Srpaulo#define IWN_RX_CIPHER_CCMP (2 << 8) 467198429Srpaulo#define IWN_RX_MPDU_DEC (1 << 11) 468198429Srpaulo#define IWN_RX_DECRYPT_MASK (3 << 11) 469198429Srpaulo#define IWN_RX_DECRYPT_OK (3 << 11) 470178676Ssam 471178676Ssamstruct iwn_tx_cmd { 472178676Ssam uint8_t code; 473201209Srpaulo#define IWN_CMD_RXON 16 474201209Srpaulo#define IWN_CMD_RXON_ASSOC 17 475198429Srpaulo#define IWN_CMD_EDCA_PARAMS 19 476198429Srpaulo#define IWN_CMD_TIMING 20 477198429Srpaulo#define IWN_CMD_ADD_NODE 24 478198429Srpaulo#define IWN_CMD_TX_DATA 28 479198429Srpaulo#define IWN_CMD_LINK_QUALITY 78 480198429Srpaulo#define IWN_CMD_SET_LED 72 481198429Srpaulo#define IWN5000_CMD_WIMAX_COEX 90 482253898Sadrian#define IWN_TEMP_NOTIFICATION 98 483198429Srpaulo#define IWN5000_CMD_CALIB_CONFIG 101 484202986Srpaulo#define IWN5000_CMD_CALIB_RESULT 102 485202986Srpaulo#define IWN5000_CMD_CALIB_COMPLETE 103 486198429Srpaulo#define IWN_CMD_SET_POWER_MODE 119 487198429Srpaulo#define IWN_CMD_SCAN 128 488202986Srpaulo#define IWN_CMD_SCAN_RESULTS 131 489201209Srpaulo#define IWN_CMD_TXPOWER_DBM 149 490198429Srpaulo#define IWN_CMD_TXPOWER 151 491201209Srpaulo#define IWN5000_CMD_TX_ANT_CONFIG 152 492270738Sadrian#define IWN_CMD_TXPOWER_DBM_V1 152 493198429Srpaulo#define IWN_CMD_BT_COEX 155 494198429Srpaulo#define IWN_CMD_GET_STATISTICS 156 495198429Srpaulo#define IWN_CMD_SET_CRITICAL_TEMP 164 496198429Srpaulo#define IWN_CMD_SET_SENSITIVITY 168 497198429Srpaulo#define IWN_CMD_PHY_CALIB 176 498220891Sbschmidt#define IWN_CMD_BT_COEX_PRIOTABLE 204 499220891Sbschmidt#define IWN_CMD_BT_COEX_PROT 205 500253898Sadrian#define IWN_CMD_BT_COEX_NOTIF 206 501253898Sadrian/* PAN commands */ 502253898Sadrian#define IWN_CMD_WIPAN_PARAMS 0xb2 503253898Sadrian#define IWN_CMD_WIPAN_RXON 0xb3 504253898Sadrian#define IWN_CMD_WIPAN_RXON_TIMING 0xb4 505253898Sadrian#define IWN_CMD_WIPAN_RXON_ASSOC 0xb6 506253898Sadrian#define IWN_CMD_WIPAN_QOS_PARAM 0xb7 507253898Sadrian#define IWN_CMD_WIPAN_WEPKEY 0xb8 508253898Sadrian#define IWN_CMD_WIPAN_P2P_CHANNEL_SWITCH 0xb9 509253898Sadrian#define IWN_CMD_WIPAN_NOA_NOTIFICATION 0xbc 510253898Sadrian#define IWN_CMD_WIPAN_DEACTIVATION_COMPLETE 0xbd 511198429Srpaulo 512178676Ssam uint8_t flags; 513178676Ssam uint8_t idx; 514178676Ssam uint8_t qid; 515178676Ssam uint8_t data[136]; 516178676Ssam} __packed; 517178676Ssam 518253898Sadrian/* 519253898Sadrian * Structure for IWN_CMD_GET_STATISTICS = (0x9c) 156 520253898Sadrian * all devices identical. 521253898Sadrian * 522253898Sadrian * This command triggers an immediate response containing uCode statistics. 523253898Sadrian * The response is in the same format as IWN_BEACON_STATISTICS (0x9d) 157. 524253898Sadrian * 525253898Sadrian * If the CLEAR_STATS configuration flag is set, uCode will clear its 526253898Sadrian * internal copy of the statistics (counters) after issuing the response. 527253898Sadrian * This flag does not affect IWN_BEACON_STATISTICS after beacons (see below). 528253898Sadrian * 529253898Sadrian * If the DISABLE_NOTIF configuration flag is set, uCode will not issue 530253898Sadrian * IWN_BEACON_STATISTICS after received beacons. This flag 531253898Sadrian * does not affect the response to the IWN_CMD_GET_STATISTICS 0x9c itself. 532253898Sadrian */ 533253898Sadrianstruct iwn_statistics_cmd { 534253898Sadrian uint32_t configuration_flags; 535253898Sadrian#define IWN_STATS_CONF_CLEAR_STATS htole32(0x1) 536253898Sadrian#define IWN_STATS_CONF_DISABLE_NOTIF htole32(0x2) 537253898Sadrian} __packed; 538253898Sadrian 539198429Srpaulo/* Antenna flags, used in various commands. */ 540198429Srpaulo#define IWN_ANT_A (1 << 0) 541198429Srpaulo#define IWN_ANT_B (1 << 1) 542198429Srpaulo#define IWN_ANT_C (1 << 2) 543201209Srpaulo/* Shortcuts. */ 544201209Srpaulo#define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 545201209Srpaulo#define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 546253898Sadrian#define IWN_ANT_AC (IWN_ANT_A | IWN_ANT_C) 547198429Srpaulo#define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 548198429Srpaulo 549201209Srpaulo/* Structure for command IWN_CMD_RXON. */ 550198429Srpaulostruct iwn_rxon { 551178676Ssam uint8_t myaddr[IEEE80211_ADDR_LEN]; 552178676Ssam uint16_t reserved1; 553178676Ssam uint8_t bssid[IEEE80211_ADDR_LEN]; 554178676Ssam uint16_t reserved2; 555178676Ssam uint8_t wlap[IEEE80211_ADDR_LEN]; 556178676Ssam uint16_t reserved3; 557178676Ssam uint8_t mode; 558178676Ssam#define IWN_MODE_HOSTAP 1 559178676Ssam#define IWN_MODE_STA 3 560178676Ssam#define IWN_MODE_IBSS 4 561178676Ssam#define IWN_MODE_MONITOR 6 562253898Sadrian#define IWN_MODE_2STA 8 563253898Sadrian#define IWN_MODE_P2P 9 564198429Srpaulo 565198429Srpaulo uint8_t air; 566178676Ssam uint16_t rxchain; 567201209Srpaulo#define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 568201209Srpaulo#define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 569201209Srpaulo#define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 570201209Srpaulo#define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 571198429Srpaulo#define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 572198429Srpaulo#define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 573198429Srpaulo#define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 574198429Srpaulo 575198429Srpaulo uint8_t ofdm_mask; 576198429Srpaulo uint8_t cck_mask; 577178676Ssam uint16_t associd; 578178676Ssam uint32_t flags; 579201209Srpaulo#define IWN_RXON_24GHZ (1 << 0) 580201209Srpaulo#define IWN_RXON_CCK (1 << 1) 581201209Srpaulo#define IWN_RXON_AUTO (1 << 2) 582201209Srpaulo#define IWN_RXON_SHSLOT (1 << 4) 583201209Srpaulo#define IWN_RXON_SHPREAMBLE (1 << 5) 584201209Srpaulo#define IWN_RXON_NODIVERSITY (1 << 7) 585201209Srpaulo#define IWN_RXON_ANTENNA_A (1 << 8) 586201209Srpaulo#define IWN_RXON_ANTENNA_B (1 << 9) 587201209Srpaulo#define IWN_RXON_TSF (1 << 15) 588221653Sbschmidt#define IWN_RXON_HT_HT40MINUS (1 << 22) 589285234Sadrian 590221653Sbschmidt#define IWN_RXON_HT_PROTMODE(x) (x << 23) 591285234Sadrian 592285234Sadrian/* 0=legacy, 1=pure40, 2=mixed */ 593221653Sbschmidt#define IWN_RXON_HT_MODEPURE40 (1 << 25) 594221653Sbschmidt#define IWN_RXON_HT_MODEMIXED (2 << 25) 595285234Sadrian 596201209Srpaulo#define IWN_RXON_CTS_TO_SELF (1 << 30) 597198429Srpaulo 598178676Ssam uint32_t filter; 599198429Srpaulo#define IWN_FILTER_PROMISC (1 << 0) 600198429Srpaulo#define IWN_FILTER_CTL (1 << 1) 601198429Srpaulo#define IWN_FILTER_MULTICAST (1 << 2) 602198429Srpaulo#define IWN_FILTER_NODECRYPT (1 << 3) 603198429Srpaulo#define IWN_FILTER_BSS (1 << 5) 604198429Srpaulo#define IWN_FILTER_BEACON (1 << 6) 605198429Srpaulo 606198429Srpaulo uint8_t chan; 607198429Srpaulo uint8_t reserved4; 608198429Srpaulo uint8_t ht_single_mask; 609198429Srpaulo uint8_t ht_dual_mask; 610201209Srpaulo /* The following fields are for >=5000 Series only. */ 611198429Srpaulo uint8_t ht_triple_mask; 612198429Srpaulo uint8_t reserved5; 613198429Srpaulo uint16_t acquisition; 614198429Srpaulo uint16_t reserved6; 615178676Ssam} __packed; 616178676Ssam 617198429Srpaulo#define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 618198429Srpaulo#define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 619198429Srpaulo 620198429Srpaulo/* Structure for command IWN_CMD_ASSOCIATE. */ 621178676Ssamstruct iwn_assoc { 622178676Ssam uint32_t flags; 623178676Ssam uint32_t filter; 624178676Ssam uint8_t ofdm_mask; 625178676Ssam uint8_t cck_mask; 626178676Ssam uint16_t reserved; 627178676Ssam} __packed; 628178676Ssam 629198429Srpaulo/* Structure for command IWN_CMD_EDCA_PARAMS. */ 630178676Ssamstruct iwn_edca_params { 631178676Ssam uint32_t flags; 632178676Ssam#define IWN_EDCA_UPDATE (1 << 0) 633178676Ssam#define IWN_EDCA_TXOP (1 << 4) 634178676Ssam 635178676Ssam struct { 636178676Ssam uint16_t cwmin; 637178676Ssam uint16_t cwmax; 638178676Ssam uint8_t aifsn; 639178676Ssam uint8_t reserved; 640178676Ssam uint16_t txoplimit; 641201209Srpaulo } __packed ac[WME_NUM_AC]; 642178676Ssam} __packed; 643178676Ssam 644198429Srpaulo/* Structure for command IWN_CMD_TIMING. */ 645198429Srpaulostruct iwn_cmd_timing { 646178676Ssam uint64_t tstamp; 647178676Ssam uint16_t bintval; 648178676Ssam uint16_t atim; 649178676Ssam uint32_t binitval; 650178676Ssam uint16_t lintval; 651253898Sadrian uint8_t dtim_period; 652253898Sadrian uint8_t delta_cp_bss_tbtts; 653178676Ssam} __packed; 654178676Ssam 655198429Srpaulo/* Structure for command IWN_CMD_ADD_NODE. */ 656178676Ssamstruct iwn_node_info { 657178676Ssam uint8_t control; 658178676Ssam#define IWN_NODE_UPDATE (1 << 0) 659198429Srpaulo 660178676Ssam uint8_t reserved1[3]; 661198429Srpaulo 662178676Ssam uint8_t macaddr[IEEE80211_ADDR_LEN]; 663178676Ssam uint16_t reserved2; 664178676Ssam uint8_t id; 665178676Ssam#define IWN_ID_BSS 0 666253898Sadrian#define IWN_STA_ID 1 667253898Sadrian 668253898Sadrian#define IWN_PAN_ID_BCAST 14 669198429Srpaulo#define IWN5000_ID_BROADCAST 15 670198429Srpaulo#define IWN4965_ID_BROADCAST 31 671198429Srpaulo 672178676Ssam uint8_t flags; 673198429Srpaulo#define IWN_FLAG_SET_KEY (1 << 0) 674198429Srpaulo#define IWN_FLAG_SET_DISABLE_TID (1 << 1) 675198429Srpaulo#define IWN_FLAG_SET_TXRATE (1 << 2) 676198429Srpaulo#define IWN_FLAG_SET_ADDBA (1 << 3) 677198429Srpaulo#define IWN_FLAG_SET_DELBA (1 << 4) 678198429Srpaulo 679178676Ssam uint16_t reserved3; 680198429Srpaulo uint16_t kflags; 681198429Srpaulo#define IWN_KFLAG_CCMP (1 << 1) 682198429Srpaulo#define IWN_KFLAG_MAP (1 << 3) 683198429Srpaulo#define IWN_KFLAG_KID(kid) ((kid) << 8) 684198429Srpaulo#define IWN_KFLAG_INVALID (1 << 11) 685198429Srpaulo#define IWN_KFLAG_GROUP (1 << 14) 686198429Srpaulo 687178676Ssam uint8_t tsc2; /* TKIP TSC2 */ 688178676Ssam uint8_t reserved4; 689178676Ssam uint16_t ttak[5]; 690198429Srpaulo uint8_t kid; 691198429Srpaulo uint8_t reserved5; 692198429Srpaulo uint8_t key[16]; 693198429Srpaulo /* The following 3 fields are for 5000 Series only. */ 694198429Srpaulo uint64_t tsc; 695198429Srpaulo uint8_t rxmic[8]; 696198429Srpaulo uint8_t txmic[8]; 697198429Srpaulo 698178676Ssam uint32_t htflags; 699221653Sbschmidt#define IWN_SMPS_MIMO_PROT (1 << 17) 700198429Srpaulo#define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 701221653Sbschmidt#define IWN_NODE_HT40 (1 << 21) 702221653Sbschmidt#define IWN_SMPS_MIMO_DIS (1 << 22) 703198429Srpaulo#define IWN_AMDPU_DENSITY(x) ((x) << 23) 704198429Srpaulo 705178676Ssam uint32_t mask; 706198429Srpaulo uint16_t disable_tid; 707198429Srpaulo uint16_t reserved6; 708198429Srpaulo uint8_t addba_tid; 709198429Srpaulo uint8_t delba_tid; 710198429Srpaulo uint16_t addba_ssn; 711198429Srpaulo uint32_t reserved7; 712198429Srpaulo} __packed; 713198429Srpaulo 714198429Srpaulostruct iwn4965_node_info { 715198429Srpaulo uint8_t control; 716198429Srpaulo uint8_t reserved1[3]; 717198429Srpaulo uint8_t macaddr[IEEE80211_ADDR_LEN]; 718198429Srpaulo uint16_t reserved2; 719198429Srpaulo uint8_t id; 720198429Srpaulo uint8_t flags; 721198429Srpaulo uint16_t reserved3; 722198429Srpaulo uint16_t kflags; 723198429Srpaulo uint8_t tsc2; /* TKIP TSC2 */ 724198429Srpaulo uint8_t reserved4; 725198429Srpaulo uint16_t ttak[5]; 726198429Srpaulo uint8_t kid; 727198429Srpaulo uint8_t reserved5; 728198429Srpaulo uint8_t key[16]; 729198429Srpaulo uint32_t htflags; 730198429Srpaulo uint32_t mask; 731198429Srpaulo uint16_t disable_tid; 732198429Srpaulo uint16_t reserved6; 733198429Srpaulo uint8_t addba_tid; 734198429Srpaulo uint8_t delba_tid; 735198429Srpaulo uint16_t addba_ssn; 736198429Srpaulo uint32_t reserved7; 737198429Srpaulo} __packed; 738198429Srpaulo 739221649Sbschmidt#define IWN_RFLAG_MCS (1 << 8) 740221648Sbschmidt#define IWN_RFLAG_CCK (1 << 9) 741221649Sbschmidt#define IWN_RFLAG_GREENFIELD (1 << 10) 742221649Sbschmidt#define IWN_RFLAG_HT40 (1 << 11) 743221649Sbschmidt#define IWN_RFLAG_DUPLICATE (1 << 12) 744221649Sbschmidt#define IWN_RFLAG_SGI (1 << 13) 745221648Sbschmidt#define IWN_RFLAG_ANT(x) ((x) << 14) 746178676Ssam 747198429Srpaulo/* Structure for command IWN_CMD_TX_DATA. */ 748178676Ssamstruct iwn_cmd_data { 749178676Ssam uint16_t len; 750178676Ssam uint16_t lnext; 751178676Ssam uint32_t flags; 752198429Srpaulo#define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 753178676Ssam#define IWN_TX_NEED_RTS (1 << 1) 754178676Ssam#define IWN_TX_NEED_CTS (1 << 2) 755178676Ssam#define IWN_TX_NEED_ACK (1 << 3) 756198429Srpaulo#define IWN_TX_LINKQ (1 << 4) 757198429Srpaulo#define IWN_TX_IMM_BA (1 << 6) 758178676Ssam#define IWN_TX_FULL_TXOP (1 << 7) 759178676Ssam#define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 760178676Ssam#define IWN_TX_AUTO_SEQ (1 << 13) 761198429Srpaulo#define IWN_TX_MORE_FRAG (1 << 14) 762178676Ssam#define IWN_TX_INSERT_TSTAMP (1 << 16) 763178676Ssam#define IWN_TX_NEED_PADDING (1 << 20) 764178676Ssam 765198429Srpaulo uint32_t scratch; 766221648Sbschmidt uint32_t rate; 767198429Srpaulo 768178676Ssam uint8_t id; 769178676Ssam uint8_t security; 770178676Ssam#define IWN_CIPHER_WEP40 1 771178676Ssam#define IWN_CIPHER_CCMP 2 772178676Ssam#define IWN_CIPHER_TKIP 3 773178676Ssam#define IWN_CIPHER_WEP104 9 774178676Ssam 775198429Srpaulo uint8_t linkq; 776178676Ssam uint8_t reserved2; 777198429Srpaulo uint8_t key[16]; 778178676Ssam uint16_t fnext; 779178676Ssam uint16_t reserved3; 780178676Ssam uint32_t lifetime; 781178676Ssam#define IWN_LIFETIME_INFINITE 0xffffffff 782178676Ssam 783178676Ssam uint32_t loaddr; 784178676Ssam uint8_t hiaddr; 785178676Ssam uint8_t rts_ntries; 786178676Ssam uint8_t data_ntries; 787178676Ssam uint8_t tid; 788178676Ssam uint16_t timeout; 789178676Ssam uint16_t txop; 790178676Ssam} __packed; 791178676Ssam 792198429Srpaulo/* Structure for command IWN_CMD_LINK_QUALITY. */ 793178676Ssam#define IWN_MAX_TX_RETRIES 16 794178676Ssamstruct iwn_cmd_link_quality { 795178676Ssam uint8_t id; 796178676Ssam uint8_t reserved1; 797178676Ssam uint16_t ctl; 798178676Ssam uint8_t flags; 799198429Srpaulo uint8_t mimo; 800198429Srpaulo uint8_t antmsk_1stream; 801198429Srpaulo uint8_t antmsk_2stream; 802201209Srpaulo uint8_t ridx[WME_NUM_AC]; 803198429Srpaulo uint16_t ampdu_limit; 804198429Srpaulo uint8_t ampdu_threshold; 805198429Srpaulo uint8_t ampdu_max; 806178676Ssam uint32_t reserved2; 807221648Sbschmidt uint32_t retry[IWN_MAX_TX_RETRIES]; 808178676Ssam uint32_t reserved3; 809178676Ssam} __packed; 810178676Ssam 811198429Srpaulo/* Structure for command IWN_CMD_SET_LED. */ 812178676Ssamstruct iwn_cmd_led { 813178676Ssam uint32_t unit; /* multiplier (in usecs) */ 814178676Ssam uint8_t which; 815178676Ssam#define IWN_LED_ACTIVITY 1 816178676Ssam#define IWN_LED_LINK 2 817178676Ssam 818178676Ssam uint8_t off; 819178676Ssam uint8_t on; 820178676Ssam uint8_t reserved; 821178676Ssam} __packed; 822178676Ssam 823198429Srpaulo/* Structure for command IWN5000_CMD_WIMAX_COEX. */ 824198429Srpaulostruct iwn5000_wimax_coex { 825198429Srpaulo uint32_t flags; 826201209Srpaulo#define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 827201209Srpaulo#define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 828201209Srpaulo#define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 829201209Srpaulo#define IWN_WIMAX_COEX_ENABLE (1 << 7) 830201209Srpaulo 831201209Srpaulo struct iwn5000_wimax_event { 832198429Srpaulo uint8_t request; 833198429Srpaulo uint8_t window; 834198429Srpaulo uint8_t reserved; 835198429Srpaulo uint8_t flags; 836198429Srpaulo } __packed events[16]; 837198429Srpaulo} __packed; 838198429Srpaulo 839198429Srpaulo/* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 840198429Srpaulostruct iwn5000_calib_elem { 841198429Srpaulo uint32_t enable; 842198429Srpaulo uint32_t start; 843227805Sbschmidt#define IWN5000_CALIB_DC (1 << 1) 844227805Sbschmidt 845198429Srpaulo uint32_t send; 846198429Srpaulo uint32_t apply; 847198429Srpaulo uint32_t reserved; 848198429Srpaulo} __packed; 849198429Srpaulo 850198429Srpaulostruct iwn5000_calib_status { 851198429Srpaulo struct iwn5000_calib_elem once; 852198429Srpaulo struct iwn5000_calib_elem perd; 853198429Srpaulo uint32_t flags; 854198429Srpaulo} __packed; 855198429Srpaulo 856198429Srpaulostruct iwn5000_calib_config { 857198429Srpaulo struct iwn5000_calib_status ucode; 858198429Srpaulo struct iwn5000_calib_status driver; 859198429Srpaulo uint32_t reserved; 860198429Srpaulo} __packed; 861198429Srpaulo 862198429Srpaulo/* Structure for command IWN_CMD_SET_POWER_MODE. */ 863198429Srpaulostruct iwn_pmgt_cmd { 864178676Ssam uint16_t flags; 865198429Srpaulo#define IWN_PS_ALLOW_SLEEP (1 << 0) 866198429Srpaulo#define IWN_PS_NOTIFY (1 << 1) 867198429Srpaulo#define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 868198429Srpaulo#define IWN_PS_PCI_PMGT (1 << 3) 869198429Srpaulo#define IWN_PS_FAST_PD (1 << 4) 870253898Sadrian#define IWN_PS_BEACON_FILTERING (1 << 5) 871253898Sadrian#define IWN_PS_SHADOW_REG (1 << 6) 872253898Sadrian#define IWN_PS_CT_KILL (1 << 7) 873253898Sadrian#define IWN_PS_BT_SCD (1 << 8) 874253898Sadrian#define IWN_PS_ADVANCED_PM (1 << 9) 875178676Ssam 876198429Srpaulo uint8_t keepalive; 877178676Ssam uint8_t debug; 878198429Srpaulo uint32_t rxtimeout; 879198429Srpaulo uint32_t txtimeout; 880198429Srpaulo uint32_t intval[5]; 881178676Ssam uint32_t beacons; 882178676Ssam} __packed; 883178676Ssam 884198429Srpaulo/* Structures for command IWN_CMD_SCAN. */ 885178676Ssamstruct iwn_scan_essid { 886178676Ssam uint8_t id; 887178676Ssam uint8_t len; 888178676Ssam uint8_t data[IEEE80211_NWID_LEN]; 889178676Ssam} __packed; 890178676Ssam 891178676Ssamstruct iwn_scan_hdr { 892178676Ssam uint16_t len; 893258117Sadrian uint8_t scan_flags; 894178676Ssam uint8_t nchan; 895198429Srpaulo uint16_t quiet_time; 896198429Srpaulo uint16_t quiet_threshold; 897178676Ssam uint16_t crc_threshold; 898178676Ssam uint16_t rxchain; 899178676Ssam uint32_t max_svc; /* background scans */ 900178676Ssam uint32_t pause_svc; /* background scans */ 901178676Ssam uint32_t flags; 902178676Ssam uint32_t filter; 903178676Ssam 904198429Srpaulo /* Followed by a struct iwn_cmd_data. */ 905198429Srpaulo /* Followed by an array of 20 structs iwn_scan_essid. */ 906198429Srpaulo /* Followed by probe request body. */ 907198429Srpaulo /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 908178676Ssam} __packed; 909178676Ssam 910178676Ssamstruct iwn_scan_chan { 911198429Srpaulo uint32_t flags; 912253898Sadrian#define IWN_CHAN_PASSIVE (0 << 0) 913198429Srpaulo#define IWN_CHAN_ACTIVE (1 << 0) 914198429Srpaulo#define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 915178676Ssam 916198429Srpaulo uint16_t chan; 917178676Ssam uint8_t rf_gain; 918178676Ssam uint8_t dsp_gain; 919178676Ssam uint16_t active; /* msecs */ 920178676Ssam uint16_t passive; /* msecs */ 921178676Ssam} __packed; 922178676Ssam 923253898Sadrian#define IWN_SCAN_CRC_TH_DISABLED 0 924253898Sadrian#define IWN_SCAN_CRC_TH_DEFAULT htole16(1) 925253898Sadrian#define IWN_SCAN_CRC_TH_NEVER htole16(0xffff) 926253898Sadrian 927198429Srpaulo/* Maximum size of a scan command. */ 928198429Srpaulo#define IWN_SCAN_MAXSZ (MCLBYTES - 4) 929198429Srpaulo 930258829Sadrian/* 931258829Sadrian * For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after 932258829Sadrian * sending probe req. This should be set long enough to hear probe responses 933258829Sadrian * from more than one AP. 934258829Sadrian */ 935258829Sadrian#define IWN_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */ 936258829Sadrian#define IWN_ACTIVE_DWELL_TIME_5GHZ (20) 937258829Sadrian#define IWN_ACTIVE_DWELL_FACTOR_2GHZ (3) 938258829Sadrian#define IWN_ACTIVE_DWELL_FACTOR_5GHZ (2) 939253898Sadrian 940258829Sadrian/* 941258829Sadrian * For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel. 942258829Sadrian * Must be set longer than active dwell time. 943258829Sadrian * For the most reliable scan, set > AP beacon interval (typically 100msec). 944258829Sadrian */ 945258829Sadrian#define IWN_PASSIVE_DWELL_TIME_2GHZ (20) /* all times in msec */ 946258829Sadrian#define IWN_PASSIVE_DWELL_TIME_5GHZ (10) 947253898Sadrian#define IWN_PASSIVE_DWELL_BASE (100) 948253898Sadrian#define IWN_CHANNEL_TUNE_TIME (5) 949253898Sadrian 950253898Sadrian#define IWN_SCAN_CHAN_TIMEOUT 2 951258829Sadrian#define IWN_MAX_SCAN_CHANNEL 50 952253898Sadrian 953258829Sadrian/* 954258829Sadrian * If active scanning is requested but a certain channel is 955258829Sadrian * marked passive, we can do active scanning if we detect 956258829Sadrian * transmissions. 957258829Sadrian * 958258829Sadrian * There is an issue with some firmware versions that triggers 959258829Sadrian * a sysassert on a "good CRC threshold" of zero (== disabled), 960258829Sadrian * on a radar channel even though this means that we should NOT 961258829Sadrian * send probes. 962258829Sadrian * 963258829Sadrian * The "good CRC threshold" is the number of frames that we 964258829Sadrian * need to receive during our dwell time on a channel before 965258829Sadrian * sending out probes -- setting this to a huge value will 966258829Sadrian * mean we never reach it, but at the same time work around 967258829Sadrian * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER 968258829Sadrian * here instead of IWL_GOOD_CRC_TH_DISABLED. 969258829Sadrian * 970258829Sadrian * This was fixed in later versions along with some other 971258829Sadrian * scan changes, and the threshold behaves as a flag in those 972258829Sadrian * versions. 973258829Sadrian */ 974258829Sadrian#define IWN_GOOD_CRC_TH_DISABLED 0 975258829Sadrian#define IWN_GOOD_CRC_TH_DEFAULT htole16(1) 976258829Sadrian#define IWN_GOOD_CRC_TH_NEVER htole16(0xffff) 977258829Sadrian 978198429Srpaulo/* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 979178676Ssam#define IWN_RIDX_MAX 32 980198429Srpaulostruct iwn4965_cmd_txpower { 981198429Srpaulo uint8_t band; 982198429Srpaulo uint8_t reserved1; 983198429Srpaulo uint8_t chan; 984198429Srpaulo uint8_t reserved2; 985178676Ssam struct { 986198429Srpaulo uint8_t rf_gain[2]; 987198429Srpaulo uint8_t dsp_gain[2]; 988198429Srpaulo } __packed power[IWN_RIDX_MAX + 1]; 989178676Ssam} __packed; 990178676Ssam 991198429Srpaulo/* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 992198429Srpaulostruct iwn5000_cmd_txpower { 993198429Srpaulo int8_t global_limit; /* in half-dBm */ 994198429Srpaulo#define IWN5000_TXPOWER_AUTO 0x7f 995198429Srpaulo#define IWN5000_TXPOWER_MAX_DBM 16 996198429Srpaulo 997198429Srpaulo uint8_t flags; 998198429Srpaulo#define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 999198429Srpaulo 1000198429Srpaulo int8_t srv_limit; /* in half-dBm */ 1001198429Srpaulo uint8_t reserved; 1002198429Srpaulo} __packed; 1003198429Srpaulo 1004220891Sbschmidt/* Structures for command IWN_CMD_BLUETOOTH. */ 1005178676Ssamstruct iwn_bluetooth { 1006178676Ssam uint8_t flags; 1007206444Sbschmidt#define IWN_BT_COEX_CHAN_ANN (1 << 0) 1008206444Sbschmidt#define IWN_BT_COEX_BT_PRIO (1 << 1) 1009206444Sbschmidt#define IWN_BT_COEX_2_WIRE (1 << 2) 1010201209Srpaulo 1011201209Srpaulo uint8_t lead_time; 1012201209Srpaulo#define IWN_BT_LEAD_TIME_DEF 30 1013201209Srpaulo 1014201209Srpaulo uint8_t max_kill; 1015201209Srpaulo#define IWN_BT_MAX_KILL_DEF 5 1016201209Srpaulo 1017178676Ssam uint8_t reserved; 1018201209Srpaulo uint32_t kill_ack; 1019201209Srpaulo uint32_t kill_cts; 1020178676Ssam} __packed; 1021178676Ssam 1022220891Sbschmidtstruct iwn6000_btcoex_config { 1023220891Sbschmidt uint8_t flags; 1024253898Sadrian#define IWN_BT_FLAG_COEX6000_CHAN_INHIBITION 1 1025253898Sadrian#define IWN_BT_FLAG_COEX6000_MODE_MASK ((1 << 3) | (1 << 4) | (1 << 5 )) 1026253898Sadrian#define IWN_BT_FLAG_COEX6000_MODE_SHIFT 3 1027253898Sadrian#define IWN_BT_FLAG_COEX6000_MODE_DISABLED 0 1028253898Sadrian#define IWN_BT_FLAG_COEX6000_MODE_LEGACY_2W 1 1029253898Sadrian#define IWN_BT_FLAG_COEX6000_MODE_3W 2 1030253898Sadrian#define IWN_BT_FLAG_COEX6000_MODE_4W 3 1031253898Sadrian 1032253898Sadrian#define IWN_BT_FLAG_UCODE_DEFAULT (1 << 6) 1033253898Sadrian#define IWN_BT_FLAG_SYNC_2_BT_DISABLE (1 << 7) 1034220891Sbschmidt uint8_t lead_time; 1035220891Sbschmidt uint8_t max_kill; 1036220891Sbschmidt uint8_t bt3_t7_timer; 1037220891Sbschmidt uint32_t kill_ack; 1038220891Sbschmidt uint32_t kill_cts; 1039220891Sbschmidt uint8_t sample_time; 1040220891Sbschmidt uint8_t bt3_t2_timer; 1041220891Sbschmidt uint16_t bt4_reaction; 1042220891Sbschmidt uint32_t lookup_table[12]; 1043220891Sbschmidt uint16_t bt4_decision; 1044220891Sbschmidt uint16_t valid; 1045220891Sbschmidt uint8_t prio_boost; 1046220891Sbschmidt uint8_t tx_prio_boost; 1047220891Sbschmidt uint16_t rx_prio_boost; 1048220891Sbschmidt} __packed; 1049220891Sbschmidt 1050253898Sadrian/* Structure for enhanced command IWN_CMD_BLUETOOTH for 2000 Series. */ 1051253898Sadrianstruct iwn2000_btcoex_config { 1052253898Sadrian uint8_t flags; /* Cf Flags in iwn6000_btcoex_config */ 1053253898Sadrian uint8_t lead_time; 1054253898Sadrian uint8_t max_kill; 1055253898Sadrian uint8_t bt3_t7_timer; 1056253898Sadrian uint32_t kill_ack; 1057253898Sadrian uint32_t kill_cts; 1058253898Sadrian uint8_t sample_time; 1059253898Sadrian uint8_t bt3_t2_timer; 1060253898Sadrian uint16_t bt4_reaction; 1061253898Sadrian uint32_t lookup_table[12]; 1062253898Sadrian uint16_t bt4_decision; 1063253898Sadrian uint16_t valid; 1064253898Sadrian 1065253898Sadrian uint32_t prio_boost; /* size change prior to iwn6000_btcoex_config */ 1066253898Sadrian uint8_t reserved; /* added prior to iwn6000_btcoex_config */ 1067253898Sadrian 1068253898Sadrian uint8_t tx_prio_boost; 1069253898Sadrian uint16_t rx_prio_boost; 1070253898Sadrian} __packed; 1071253898Sadrian 1072220891Sbschmidtstruct iwn_btcoex_priotable { 1073220891Sbschmidt uint8_t calib_init1; 1074220891Sbschmidt uint8_t calib_init2; 1075220891Sbschmidt uint8_t calib_periodic_low1; 1076220891Sbschmidt uint8_t calib_periodic_low2; 1077220891Sbschmidt uint8_t calib_periodic_high1; 1078220891Sbschmidt uint8_t calib_periodic_high2; 1079220891Sbschmidt uint8_t dtim; 1080220891Sbschmidt uint8_t scan52; 1081220891Sbschmidt uint8_t scan24; 1082220891Sbschmidt uint8_t reserved[7]; 1083220891Sbschmidt} __packed; 1084220891Sbschmidt 1085220891Sbschmidtstruct iwn_btcoex_prot { 1086220891Sbschmidt uint8_t open; 1087220891Sbschmidt uint8_t type; 1088220891Sbschmidt uint8_t reserved[2]; 1089220891Sbschmidt} __packed; 1090220891Sbschmidt 1091198429Srpaulo/* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 1092178676Ssamstruct iwn_critical_temp { 1093178676Ssam uint32_t reserved; 1094178676Ssam uint32_t tempM; 1095178676Ssam uint32_t tempR; 1096198429Srpaulo/* degK <-> degC conversion macros. */ 1097178676Ssam#define IWN_CTOK(c) ((c) + 273) 1098178676Ssam#define IWN_KTOC(k) ((k) - 273) 1099178676Ssam#define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 1100178676Ssam} __packed; 1101178676Ssam 1102220729Sbschmidt/* Structures for command IWN_CMD_SET_SENSITIVITY. */ 1103178676Ssamstruct iwn_sensitivity_cmd { 1104178676Ssam uint16_t which; 1105178676Ssam#define IWN_SENSITIVITY_DEFAULTTBL 0 1106178676Ssam#define IWN_SENSITIVITY_WORKTBL 1 1107178676Ssam 1108178676Ssam uint16_t energy_cck; 1109178676Ssam uint16_t energy_ofdm; 1110178676Ssam uint16_t corr_ofdm_x1; 1111178676Ssam uint16_t corr_ofdm_mrc_x1; 1112178676Ssam uint16_t corr_cck_mrc_x4; 1113178676Ssam uint16_t corr_ofdm_x4; 1114178676Ssam uint16_t corr_ofdm_mrc_x4; 1115178676Ssam uint16_t corr_barker; 1116178676Ssam uint16_t corr_barker_mrc; 1117178676Ssam uint16_t corr_cck_x4; 1118178676Ssam uint16_t energy_ofdm_th; 1119178676Ssam} __packed; 1120178676Ssam 1121220729Sbschmidtstruct iwn_enhanced_sensitivity_cmd { 1122220729Sbschmidt uint16_t which; 1123220729Sbschmidt uint16_t energy_cck; 1124220729Sbschmidt uint16_t energy_ofdm; 1125220729Sbschmidt uint16_t corr_ofdm_x1; 1126220729Sbschmidt uint16_t corr_ofdm_mrc_x1; 1127220729Sbschmidt uint16_t corr_cck_mrc_x4; 1128220729Sbschmidt uint16_t corr_ofdm_x4; 1129220729Sbschmidt uint16_t corr_ofdm_mrc_x4; 1130220729Sbschmidt uint16_t corr_barker; 1131220729Sbschmidt uint16_t corr_barker_mrc; 1132220729Sbschmidt uint16_t corr_cck_x4; 1133220729Sbschmidt uint16_t energy_ofdm_th; 1134220729Sbschmidt /* "Enhanced" part. */ 1135220729Sbschmidt uint16_t ina_det_ofdm; 1136220729Sbschmidt uint16_t ina_det_cck; 1137220729Sbschmidt uint16_t corr_11_9_en; 1138220729Sbschmidt uint16_t ofdm_det_slope_mrc; 1139220729Sbschmidt uint16_t ofdm_det_icept_mrc; 1140220729Sbschmidt uint16_t ofdm_det_slope; 1141220729Sbschmidt uint16_t ofdm_det_icept; 1142220729Sbschmidt uint16_t cck_det_slope_mrc; 1143220729Sbschmidt uint16_t cck_det_icept_mrc; 1144220729Sbschmidt uint16_t cck_det_slope; 1145220729Sbschmidt uint16_t cck_det_icept; 1146220729Sbschmidt uint16_t reserved; 1147220729Sbschmidt} __packed; 1148220729Sbschmidt 1149257880Sadrian/* 1150257880Sadrian * Define maximal number of calib result send to runtime firmware 1151257880Sadrian * PS: TEMP_OFFSET count for 2 (std and v2) 1152257880Sadrian */ 1153257880Sadrian#define IWN5000_PHY_CALIB_MAX_RESULT 8 1154257880Sadrian 1155198429Srpaulo/* Structures for command IWN_CMD_PHY_CALIB. */ 1156198429Srpaulostruct iwn_phy_calib { 1157198429Srpaulo uint8_t code; 1158198429Srpaulo#define IWN4965_PHY_CALIB_DIFF_GAIN 7 1159198429Srpaulo#define IWN5000_PHY_CALIB_DC 8 1160198429Srpaulo#define IWN5000_PHY_CALIB_LO 9 1161198429Srpaulo#define IWN5000_PHY_CALIB_TX_IQ 11 1162198429Srpaulo#define IWN5000_PHY_CALIB_CRYSTAL 15 1163198429Srpaulo#define IWN5000_PHY_CALIB_BASE_BAND 16 1164201209Srpaulo#define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 1165220676Sbschmidt#define IWN5000_PHY_CALIB_TEMP_OFFSET 18 1166220676Sbschmidt 1167198429Srpaulo#define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 1168198429Srpaulo#define IWN5000_PHY_CALIB_NOISE_GAIN 19 1169178676Ssam 1170198429Srpaulo uint8_t group; 1171198429Srpaulo uint8_t ngroups; 1172198429Srpaulo uint8_t isvalid; 1173198429Srpaulo} __packed; 1174178676Ssam 1175198429Srpaulostruct iwn5000_phy_calib_crystal { 1176198429Srpaulo uint8_t code; 1177198429Srpaulo uint8_t group; 1178198429Srpaulo uint8_t ngroups; 1179198429Srpaulo uint8_t isvalid; 1180198429Srpaulo 1181198429Srpaulo uint8_t cap_pin[2]; 1182198429Srpaulo uint8_t reserved[2]; 1183178676Ssam} __packed; 1184178676Ssam 1185220676Sbschmidtstruct iwn5000_phy_calib_temp_offset { 1186220676Sbschmidt uint8_t code; 1187220676Sbschmidt uint8_t group; 1188220676Sbschmidt uint8_t ngroups; 1189220676Sbschmidt uint8_t isvalid; 1190220676Sbschmidt int16_t offset; 1191220676Sbschmidt#define IWN_DEFAULT_TEMP_OFFSET 2700 1192220676Sbschmidt 1193220676Sbschmidt uint16_t reserved; 1194220676Sbschmidt} __packed; 1195220676Sbschmidt 1196253898Sadrianstruct iwn5000_phy_calib_temp_offsetv2 { 1197253898Sadrian uint8_t code; 1198253898Sadrian uint8_t group; 1199253898Sadrian uint8_t ngroups; 1200253898Sadrian uint8_t isvalid; 1201253898Sadrian int16_t offset_high; 1202253898Sadrian int16_t offset_low; 1203253898Sadrian int16_t burnt_voltage_ref; 1204253898Sadrian int16_t reserved; 1205253898Sadrian} __packed; 1206253898Sadrian 1207198429Srpaulostruct iwn_phy_calib_gain { 1208198429Srpaulo uint8_t code; 1209198429Srpaulo uint8_t group; 1210198429Srpaulo uint8_t ngroups; 1211198429Srpaulo uint8_t isvalid; 1212178676Ssam 1213198429Srpaulo int8_t gain[3]; 1214198429Srpaulo uint8_t reserved; 1215198429Srpaulo} __packed; 1216198429Srpaulo 1217198429Srpaulo/* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 1218198429Srpaulostruct iwn_spectrum_cmd { 1219198429Srpaulo uint16_t len; 1220198429Srpaulo uint8_t token; 1221198429Srpaulo uint8_t id; 1222198429Srpaulo uint8_t origin; 1223198429Srpaulo uint8_t periodic; 1224198429Srpaulo uint16_t timeout; 1225198429Srpaulo uint32_t start; 1226198429Srpaulo uint32_t reserved1; 1227198429Srpaulo uint32_t flags; 1228198429Srpaulo uint32_t filter; 1229198429Srpaulo uint16_t nchan; 1230198429Srpaulo uint16_t reserved2; 1231198429Srpaulo struct { 1232198429Srpaulo uint32_t duration; 1233198429Srpaulo uint8_t chan; 1234198429Srpaulo uint8_t type; 1235198429Srpaulo#define IWN_MEASUREMENT_BASIC (1 << 0) 1236198429Srpaulo#define IWN_MEASUREMENT_CCA (1 << 1) 1237198429Srpaulo#define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 1238198429Srpaulo#define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 1239198429Srpaulo#define IWN_MEASUREMENT_FRAME (1 << 4) 1240198429Srpaulo#define IWN_MEASUREMENT_IDLE (1 << 7) 1241198429Srpaulo 1242198429Srpaulo uint16_t reserved; 1243198429Srpaulo } __packed chan[10]; 1244198429Srpaulo} __packed; 1245198429Srpaulo 1246198429Srpaulo/* Structure for IWN_UC_READY notification. */ 1247178676Ssam#define IWN_NATTEN_GROUPS 5 1248178676Ssamstruct iwn_ucode_info { 1249178676Ssam uint8_t minor; 1250178676Ssam uint8_t major; 1251178676Ssam uint16_t reserved1; 1252178676Ssam uint8_t revision[8]; 1253178676Ssam uint8_t type; 1254178676Ssam uint8_t subtype; 1255178676Ssam#define IWN_UCODE_RUNTIME 0 1256178676Ssam#define IWN_UCODE_INIT 9 1257178676Ssam 1258178676Ssam uint16_t reserved2; 1259178676Ssam uint32_t logptr; 1260198429Srpaulo uint32_t errptr; 1261178676Ssam uint32_t tstamp; 1262178676Ssam uint32_t valid; 1263178676Ssam 1264198429Srpaulo /* The following fields are for UCODE_INIT only. */ 1265178676Ssam int32_t volt; 1266178676Ssam struct { 1267178676Ssam int32_t chan20MHz; 1268178676Ssam int32_t chan40MHz; 1269178676Ssam } __packed temp[4]; 1270198429Srpaulo int32_t atten[IWN_NATTEN_GROUPS][2]; 1271178676Ssam} __packed; 1272178676Ssam 1273198429Srpaulo/* Structures for IWN_TX_DONE notification. */ 1274253898Sadrian 1275271246Sadrian/* 1276271246Sadrian * TX command response is sent after *agn* transmission attempts. 1277271246Sadrian * 1278271246Sadrian * both postpone and abort status are expected behavior from uCode. there is 1279271246Sadrian * no special operation required from driver; except for RFKILL_FLUSH, 1280271246Sadrian * which required tx flush host command to flush all the tx frames in queues 1281271246Sadrian */ 1282271246Sadrian#define IWN_TX_STATUS_MSK 0x000000ff 1283271246Sadrian#define IWN_TX_STATUS_DELAY_MSK 0x00000040 1284271246Sadrian#define IWN_TX_STATUS_ABORT_MSK 0x00000080 1285271246Sadrian#define IWN_TX_PACKET_MODE_MSK 0x0000ff00 1286271246Sadrian#define IWN_TX_FIFO_NUMBER_MSK 0x00070000 1287271246Sadrian#define IWN_TX_RESERVED 0x00780000 1288271246Sadrian#define IWN_TX_POWER_PA_DETECT_MSK 0x7f800000 1289271246Sadrian#define IWN_TX_ABORT_REQUIRED_MSK 0x80000000 1290198429Srpaulo 1291271246Sadrian/* Success status */ 1292271246Sadrian#define IWN_TX_STATUS_SUCCESS 0x01 1293271246Sadrian#define IWN_TX_STATUS_DIRECT_DONE 0x02 1294271246Sadrian 1295271246Sadrian/* postpone TX */ 1296271246Sadrian#define IWN_TX_STATUS_POSTPONE_DELAY 0x40 1297271246Sadrian#define IWN_TX_STATUS_POSTPONE_FEW_BYTES 0x41 1298271246Sadrian#define IWN_TX_STATUS_POSTPONE_BT_PRIO 0x42 1299271246Sadrian#define IWN_TX_STATUS_POSTPONE_QUIET_PERIOD 0x43 1300271246Sadrian#define IWN_TX_STATUS_POSTPONE_CALC_TTAK 0x44 1301271246Sadrian 1302271246Sadrian/* Failures */ 1303271246Sadrian#define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */ 1304271246Sadrian#define IWN_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY 0x81 1305271246Sadrian#define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */ 1306271246Sadrian#define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */ 1307271246Sadrian#define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */ 1308271246Sadrian#define IWN_TX_STATUS_FAIL_DRAIN_FLOW 0x85 1309271246Sadrian#define IWN_TX_STATUS_FAIL_RFKILL_FLUSH 0x86 1310271246Sadrian#define IWN_TX_STATUS_FAIL_LIFE_EXPIRE 0x87 1311271246Sadrian#define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */ 1312271246Sadrian#define IWN_TX_STATUS_FAIL_HOST_ABORTED 0x89 1313271246Sadrian#define IWN_TX_STATUS_FAIL_BT_RETRY 0x8a 1314271246Sadrian#define IWN_TX_FAIL_STA_INVALID 0x8b /* XXX STA invalid (???) */ 1315271246Sadrian#define IWN_TX_STATUS_FAIL_FRAG_DROPPED 0x8c 1316271246Sadrian#define IWN_TX_STATUS_FAIL_TID_DISABLE 0x8d 1317271246Sadrian#define IWN_TX_STATUS_FAIL_FIFO_FLUSHED 0x8e 1318271246Sadrian#define IWN_TX_STATUS_FAIL_INSUFFICIENT_CF_POLL 0x8f 1319271246Sadrian#define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */ 1320271246Sadrian#define IWN_TX_STATUS_FAIL_NO_BEACON_ON_RADAR 0x91 1321271246Sadrian 1322271246Sadrian/* 1323271246Sadrian * TX command response for A-MPDU packet responses. 1324271246Sadrian * 1325271246Sadrian * The status response is different to the non A-MPDU responses. 1326271246Sadrian * In addition, the sequence number is treated as the sequence 1327271246Sadrian * number of the TX command, NOT the 802.11 sequence number! 1328271246Sadrian */ 1329271246Sadrian#define IWN_AGG_TX_STATE_TRANSMITTED 0x00 1330271246Sadrian#define IWN_AGG_TX_STATE_UNDERRUN_MSK 0x01 1331271246Sadrian#define IWN_AGG_TX_STATE_FEW_BYTES_MSK 0x04 1332271246Sadrian#define IWN_AGG_TX_STATE_ABORT_MSK 0x08 1333271246Sadrian 1334271246Sadrian#define IWN_AGG_TX_STATE_LAST_SENT_TTL_MSK 0x10 1335271246Sadrian#define IWN_AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK 0x20 1336271246Sadrian 1337271246Sadrian#define IWN_AGG_TX_STATE_SCD_QUERY_MSK 0x80 1338271246Sadrian 1339271246Sadrian#define IWN_AGG_TX_STATE_TEST_BAD_CRC32_MSK 0x100 1340271246Sadrian 1341271246Sadrian#define IWN_AGG_TX_STATE_RESPONSE_MSK 0x1ff 1342271246Sadrian#define IWN_AGG_TX_STATE_DUMP_TX_MSK 0x200 1343271246Sadrian#define IWN_AGG_TX_STATE_DELAY_TX_MSK 0x400 1344271246Sadrian 1345271246Sadrian#define IWN_AGG_TX_STATUS_MSK 0x00000fff 1346271246Sadrian#define IWN_AGG_TX_TRY_MSK 0x0000f000 1347271246Sadrian 1348271246Sadrian#define IWN_AGG_TX_STATE_LAST_SENT_MSK \ 1349271246Sadrian (IWN_AGG_TX_STATE_LAST_SENT_TTL_MSK | \ 1350271246Sadrian IWN_AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK) 1351271246Sadrian 1352271246Sadrian/* # tx attempts for first frame in aggregation */ 1353271246Sadrian#define IWN_AGG_TX_STATE_TRY_CNT_POS 12 1354271246Sadrian#define IWN_AGG_TX_STATE_TRY_CNT_MSK 0xf000 1355271246Sadrian 1356271246Sadrian/* Command ID and sequence number of Tx command for this frame */ 1357271246Sadrian#define IWN_AGG_TX_STATE_SEQ_NUM_POS 16 1358271246Sadrian#define IWN_AGG_TX_STATE_SEQ_NUM_MSK 0xffff0000 1359271246Sadrian 1360198429Srpaulostruct iwn4965_tx_stat { 1361178676Ssam uint8_t nframes; 1362201209Srpaulo uint8_t btkillcnt; 1363201209Srpaulo uint8_t rtsfailcnt; 1364201209Srpaulo uint8_t ackfailcnt; 1365221648Sbschmidt uint32_t rate; 1366178676Ssam uint16_t duration; 1367178676Ssam uint16_t reserved; 1368178676Ssam uint32_t power[2]; 1369178676Ssam uint32_t status; 1370178676Ssam} __packed; 1371178676Ssam 1372198429Srpaulostruct iwn5000_tx_stat { 1373253898Sadrian uint8_t nframes; /* 1 no aggregation, >1 aggregation */ 1374201209Srpaulo uint8_t btkillcnt; 1375201209Srpaulo uint8_t rtsfailcnt; 1376201209Srpaulo uint8_t ackfailcnt; 1377221648Sbschmidt uint32_t rate; 1378198429Srpaulo uint16_t duration; 1379198429Srpaulo uint16_t reserved; 1380198429Srpaulo uint32_t power[2]; 1381198429Srpaulo uint32_t info; 1382198429Srpaulo uint16_t seq; 1383198429Srpaulo uint16_t len; 1384201209Srpaulo uint8_t tlc; 1385253898Sadrian uint8_t ratid; /* tid (0:3), sta_id (4:7) */ 1386201209Srpaulo uint8_t fc[2]; 1387198429Srpaulo uint16_t status; 1388198429Srpaulo uint16_t sequence; 1389198429Srpaulo} __packed; 1390198429Srpaulo 1391198429Srpaulo/* Structure for IWN_BEACON_MISSED notification. */ 1392178676Ssamstruct iwn_beacon_missed { 1393178676Ssam uint32_t consecutive; 1394178676Ssam uint32_t total; 1395178676Ssam uint32_t expected; 1396178676Ssam uint32_t received; 1397178676Ssam} __packed; 1398178676Ssam 1399198429Srpaulo/* Structure for IWN_MPDU_RX_DONE notification. */ 1400198429Srpaulostruct iwn_rx_mpdu { 1401178676Ssam uint16_t len; 1402178676Ssam uint16_t reserved; 1403178676Ssam} __packed; 1404178676Ssam 1405198429Srpaulo/* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1406198429Srpaulostruct iwn4965_rx_phystat { 1407198429Srpaulo uint16_t antenna; 1408198429Srpaulo uint16_t agc; 1409198429Srpaulo uint8_t rssi[6]; 1410198429Srpaulo} __packed; 1411198429Srpaulo 1412198429Srpaulostruct iwn5000_rx_phystat { 1413198429Srpaulo uint32_t reserved1; 1414198429Srpaulo uint32_t agc; 1415198429Srpaulo uint16_t rssi[3]; 1416198429Srpaulo} __packed; 1417198429Srpaulo 1418178676Ssamstruct iwn_rx_stat { 1419178676Ssam uint8_t phy_len; 1420178676Ssam uint8_t cfg_phy_len; 1421178676Ssam#define IWN_STAT_MAXLEN 20 1422178676Ssam 1423178676Ssam uint8_t id; 1424178676Ssam uint8_t reserved1; 1425178676Ssam uint64_t tstamp; 1426178676Ssam uint32_t beacon; 1427178676Ssam uint16_t flags; 1428198429Srpaulo#define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1429198429Srpaulo 1430178676Ssam uint16_t chan; 1431198429Srpaulo uint8_t phybuf[32]; 1432221648Sbschmidt uint32_t rate; 1433253898Sadrian/* 1434253898Sadrian * rate bit fields 1435253898Sadrian * 1436253898Sadrian * High-throughput (HT) rate format for bits 7:0 (bit 8 must be "1"): 1437253898Sadrian * 2-0: 0) 6 Mbps 1438253898Sadrian * 1) 12 Mbps 1439253898Sadrian * 2) 18 Mbps 1440253898Sadrian * 3) 24 Mbps 1441253898Sadrian * 4) 36 Mbps 1442253898Sadrian * 5) 48 Mbps 1443253898Sadrian * 6) 54 Mbps 1444253898Sadrian * 7) 60 Mbps 1445253898Sadrian * 1446253898Sadrian * 4-3: 0) Single stream (SISO) 1447253898Sadrian * 1) Dual stream (MIMO) 1448253898Sadrian * 2) Triple stream (MIMO) 1449253898Sadrian * 1450253898Sadrian * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 1451253898Sadrian * 1452253898Sadrian * Legacy OFDM rate format for bits 7:0 (bit 8 must be "0", bit 9 "0"): 1453253898Sadrian * 3-0: 0xD) 6 Mbps 1454253898Sadrian * 0xF) 9 Mbps 1455253898Sadrian * 0x5) 12 Mbps 1456253898Sadrian * 0x7) 18 Mbps 1457253898Sadrian * 0x9) 24 Mbps 1458253898Sadrian * 0xB) 36 Mbps 1459253898Sadrian * 0x1) 48 Mbps 1460253898Sadrian * 0x3) 54 Mbps 1461253898Sadrian * 1462253898Sadrian * Legacy CCK rate format for bits 7:0 (bit 8 must be "0", bit 9 "1"): 1463253898Sadrian * 6-0: 10) 1 Mbps 1464253898Sadrian * 20) 2 Mbps 1465253898Sadrian * 55) 5.5 Mbps 1466253898Sadrian * 110) 11 Mbps 1467253898Sadrian * 1468253898Sadrian */ 1469178676Ssam uint16_t len; 1470178676Ssam uint16_t reserve3; 1471178676Ssam} __packed; 1472178676Ssam 1473198429Srpaulo#define IWN_RSSI_TO_DBM 44 1474198429Srpaulo 1475201209Srpaulo/* Structure for IWN_RX_COMPRESSED_BA notification. */ 1476201209Srpaulostruct iwn_compressed_ba { 1477201209Srpaulo uint8_t macaddr[IEEE80211_ADDR_LEN]; 1478201209Srpaulo uint16_t reserved; 1479201209Srpaulo uint8_t id; 1480201209Srpaulo uint8_t tid; 1481201209Srpaulo uint16_t seq; 1482201209Srpaulo uint64_t bitmap; 1483201209Srpaulo uint16_t qid; 1484201209Srpaulo uint16_t ssn; 1485271246Sadrian /* extra fields starting with iwn5000 */ 1486271246Sadrian#if 0 1487271246Sadrian uint8_t txed; /* number of frames sent */ 1488271246Sadrian uint8_t txed_2_done; /* number of frames acked */ 1489271246Sadrian uint16_t reserved1; 1490271246Sadrian#endif 1491201209Srpaulo} __packed; 1492201209Srpaulo 1493198429Srpaulo/* Structure for IWN_START_SCAN notification. */ 1494178676Ssamstruct iwn_start_scan { 1495178676Ssam uint64_t tstamp; 1496178676Ssam uint32_t tbeacon; 1497178676Ssam uint8_t chan; 1498178676Ssam uint8_t band; 1499178676Ssam uint16_t reserved; 1500178676Ssam uint32_t status; 1501178676Ssam} __packed; 1502178676Ssam 1503198429Srpaulo/* Structure for IWN_STOP_SCAN notification. */ 1504178676Ssamstruct iwn_stop_scan { 1505178676Ssam uint8_t nchan; 1506178676Ssam uint8_t status; 1507178676Ssam uint8_t reserved; 1508178676Ssam uint8_t chan; 1509178676Ssam uint64_t tsf; 1510178676Ssam} __packed; 1511178676Ssam 1512198429Srpaulo/* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1513198429Srpaulostruct iwn_spectrum_notif { 1514198429Srpaulo uint8_t id; 1515198429Srpaulo uint8_t token; 1516198429Srpaulo uint8_t idx; 1517198429Srpaulo uint8_t state; 1518198429Srpaulo#define IWN_MEASUREMENT_START 0 1519198429Srpaulo#define IWN_MEASUREMENT_STOP 1 1520198429Srpaulo 1521198429Srpaulo uint32_t start; 1522198429Srpaulo uint8_t band; 1523198429Srpaulo uint8_t chan; 1524198429Srpaulo uint8_t type; 1525198429Srpaulo uint8_t reserved1; 1526198429Srpaulo uint32_t cca_ofdm; 1527198429Srpaulo uint32_t cca_cck; 1528198429Srpaulo uint32_t cca_time; 1529198429Srpaulo uint8_t basic; 1530198429Srpaulo uint8_t reserved2[3]; 1531198429Srpaulo uint32_t ofdm[8]; 1532198429Srpaulo uint32_t cck[8]; 1533198429Srpaulo uint32_t stop; 1534198429Srpaulo uint32_t status; 1535198429Srpaulo#define IWN_MEASUREMENT_OK 0 1536198429Srpaulo#define IWN_MEASUREMENT_CONCURRENT 1 1537198429Srpaulo#define IWN_MEASUREMENT_CSA_CONFLICT 2 1538198429Srpaulo#define IWN_MEASUREMENT_TGH_CONFLICT 3 1539198429Srpaulo#define IWN_MEASUREMENT_STOPPED 6 1540198429Srpaulo#define IWN_MEASUREMENT_TIMEOUT 7 1541198429Srpaulo#define IWN_MEASUREMENT_FAILED 8 1542198429Srpaulo} __packed; 1543198429Srpaulo 1544201209Srpaulo/* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1545178676Ssamstruct iwn_rx_phy_stats { 1546178676Ssam uint32_t ina; 1547178676Ssam uint32_t fina; 1548178676Ssam uint32_t bad_plcp; 1549178676Ssam uint32_t bad_crc32; 1550178676Ssam uint32_t overrun; 1551178676Ssam uint32_t eoverrun; 1552178676Ssam uint32_t good_crc32; 1553178676Ssam uint32_t fa; 1554178676Ssam uint32_t bad_fina_sync; 1555178676Ssam uint32_t sfd_timeout; 1556178676Ssam uint32_t fina_timeout; 1557178676Ssam uint32_t no_rts_ack; 1558178676Ssam uint32_t rxe_limit; 1559178676Ssam uint32_t ack; 1560178676Ssam uint32_t cts; 1561178676Ssam uint32_t ba_resp; 1562178676Ssam uint32_t dsp_kill; 1563178676Ssam uint32_t bad_mh; 1564178676Ssam uint32_t rssi_sum; 1565178676Ssam uint32_t reserved; 1566178676Ssam} __packed; 1567178676Ssam 1568178676Ssamstruct iwn_rx_general_stats { 1569178676Ssam uint32_t bad_cts; 1570178676Ssam uint32_t bad_ack; 1571178676Ssam uint32_t not_bss; 1572178676Ssam uint32_t filtered; 1573178676Ssam uint32_t bad_chan; 1574178676Ssam uint32_t beacons; 1575178676Ssam uint32_t missed_beacons; 1576178676Ssam uint32_t adc_saturated; /* time in 0.8us */ 1577178676Ssam uint32_t ina_searched; /* time in 0.8us */ 1578178676Ssam uint32_t noise[3]; 1579178676Ssam uint32_t flags; 1580178676Ssam uint32_t load; 1581178676Ssam uint32_t fa; 1582178676Ssam uint32_t rssi[3]; 1583178676Ssam uint32_t energy[3]; 1584178676Ssam} __packed; 1585178676Ssam 1586178676Ssamstruct iwn_rx_ht_phy_stats { 1587178676Ssam uint32_t bad_plcp; 1588178676Ssam uint32_t overrun; 1589178676Ssam uint32_t eoverrun; 1590178676Ssam uint32_t good_crc32; 1591178676Ssam uint32_t bad_crc32; 1592178676Ssam uint32_t bad_mh; 1593178676Ssam uint32_t good_ampdu_crc32; 1594178676Ssam uint32_t ampdu; 1595178676Ssam uint32_t fragment; 1596262642Sadrian uint32_t unsupport_mcs; 1597178676Ssam} __packed; 1598178676Ssam 1599178676Ssamstruct iwn_rx_stats { 1600178676Ssam struct iwn_rx_phy_stats ofdm; 1601178676Ssam struct iwn_rx_phy_stats cck; 1602178676Ssam struct iwn_rx_general_stats general; 1603178676Ssam struct iwn_rx_ht_phy_stats ht; 1604178676Ssam} __packed; 1605178676Ssam 1606262642Sadrianstruct iwn_rx_general_stats_bt { 1607262642Sadrian struct iwn_rx_general_stats common; 1608262642Sadrian /* additional stats for bt */ 1609262642Sadrian uint32_t num_bt_kills; 1610262642Sadrian uint32_t reserved[2]; 1611262642Sadrian} __packed; 1612262642Sadrian 1613262642Sadrianstruct iwn_rx_stats_bt { 1614262642Sadrian struct iwn_rx_phy_stats ofdm; 1615262642Sadrian struct iwn_rx_phy_stats cck; 1616262642Sadrian struct iwn_rx_general_stats_bt general_bt; 1617262642Sadrian struct iwn_rx_ht_phy_stats ht; 1618262642Sadrian} __packed; 1619262642Sadrian 1620178676Ssamstruct iwn_tx_stats { 1621178676Ssam uint32_t preamble; 1622178676Ssam uint32_t rx_detected; 1623178676Ssam uint32_t bt_defer; 1624178676Ssam uint32_t bt_kill; 1625178676Ssam uint32_t short_len; 1626178676Ssam uint32_t cts_timeout; 1627178676Ssam uint32_t ack_timeout; 1628178676Ssam uint32_t exp_ack; 1629178676Ssam uint32_t ack; 1630178676Ssam uint32_t msdu; 1631262414Sadrian uint32_t burst_err1; 1632178676Ssam uint32_t burst_err2; 1633178676Ssam uint32_t cts_collision; 1634178676Ssam uint32_t ack_collision; 1635178676Ssam uint32_t ba_timeout; 1636178676Ssam uint32_t ba_resched; 1637178676Ssam uint32_t query_ampdu; 1638178676Ssam uint32_t query; 1639178676Ssam uint32_t query_ampdu_frag; 1640178676Ssam uint32_t query_mismatch; 1641178676Ssam uint32_t not_ready; 1642178676Ssam uint32_t underrun; 1643178676Ssam uint32_t bt_ht_kill; 1644178676Ssam uint32_t rx_ba_resp; 1645262642Sadrian /* 1646262642Sadrian * 6000 series only - LSB=ant A, ant B, ant C, MSB=reserved 1647262642Sadrian * TX power on chain in 1/2 dBm. 1648262642Sadrian */ 1649262642Sadrian uint32_t tx_power; 1650262642Sadrian uint32_t reserved[1]; 1651178676Ssam} __packed; 1652178676Ssam 1653178676Ssamstruct iwn_general_stats { 1654262642Sadrian uint32_t temp; /* radio temperature */ 1655262642Sadrian uint32_t temp_m; /* radio voltage */ 1656178676Ssam uint32_t burst_check; 1657178676Ssam uint32_t burst; 1658262642Sadrian uint32_t wait_for_silence_timeout_cnt; 1659262642Sadrian uint32_t reserved1[3]; 1660178676Ssam uint32_t sleep; 1661178676Ssam uint32_t slot_out; 1662178676Ssam uint32_t slot_idle; 1663178676Ssam uint32_t ttl_tstamp; 1664178676Ssam uint32_t tx_ant_a; 1665178676Ssam uint32_t tx_ant_b; 1666178676Ssam uint32_t exec; 1667178676Ssam uint32_t probe; 1668178676Ssam uint32_t reserved2[2]; 1669178676Ssam uint32_t rx_enabled; 1670262642Sadrian /* 1671262642Sadrian * This is the number of times we have to re-tune 1672262642Sadrian * in order to get out of bad PHY status. 1673262642Sadrian */ 1674262642Sadrian uint32_t num_of_sos_states; 1675178676Ssam} __packed; 1676178676Ssam 1677178676Ssamstruct iwn_stats { 1678178676Ssam uint32_t flags; 1679178676Ssam struct iwn_rx_stats rx; 1680178676Ssam struct iwn_tx_stats tx; 1681178676Ssam struct iwn_general_stats general; 1682262642Sadrian uint32_t reserved1[2]; 1683178676Ssam} __packed; 1684178676Ssam 1685262642Sadrianstruct iwn_bt_activity_stats { 1686262642Sadrian /* Tx statistics */ 1687262642Sadrian uint32_t hi_priority_tx_req_cnt; 1688262642Sadrian uint32_t hi_priority_tx_denied_cnt; 1689262642Sadrian uint32_t lo_priority_tx_req_cnt; 1690262642Sadrian uint32_t lo_priority_tx_denied_cnt; 1691262642Sadrian /* Rx statistics */ 1692262642Sadrian uint32_t hi_priority_rx_req_cnt; 1693262642Sadrian uint32_t hi_priority_rx_denied_cnt; 1694262642Sadrian uint32_t lo_priority_rx_req_cnt; 1695262642Sadrian uint32_t lo_priority_rx_denied_cnt; 1696262642Sadrian} __packed; 1697178676Ssam 1698262642Sadrianstruct iwn_stats_bt { 1699262642Sadrian uint32_t flags; 1700262642Sadrian struct iwn_rx_stats_bt rx_bt; 1701262642Sadrian struct iwn_tx_stats tx; 1702262642Sadrian struct iwn_general_stats general; 1703262642Sadrian struct iwn_bt_activity_stats activity; 1704262642Sadrian uint32_t reserved1[2]; 1705262642Sadrian}; 1706262642Sadrian 1707198429Srpaulo/* Firmware error dump. */ 1708198429Srpaulostruct iwn_fw_dump { 1709198429Srpaulo uint32_t valid; 1710198429Srpaulo uint32_t id; 1711198429Srpaulo uint32_t pc; 1712198429Srpaulo uint32_t branch_link[2]; 1713198429Srpaulo uint32_t interrupt_link[2]; 1714198429Srpaulo uint32_t error_data[2]; 1715198429Srpaulo uint32_t src_line; 1716198429Srpaulo uint32_t tsf; 1717198429Srpaulo uint32_t time[2]; 1718198429Srpaulo} __packed; 1719198429Srpaulo 1720210111Sbschmidt/* TLV firmware header. */ 1721210111Sbschmidtstruct iwn_fw_tlv_hdr { 1722210111Sbschmidt uint32_t zero; /* Always 0, to differentiate from legacy. */ 1723210111Sbschmidt uint32_t signature; 1724210111Sbschmidt#define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */ 1725210111Sbschmidt 1726210111Sbschmidt uint8_t descr[64]; 1727210111Sbschmidt uint32_t rev; 1728210111Sbschmidt#define IWN_FW_API(x) (((x) >> 8) & 0xff) 1729210111Sbschmidt 1730210111Sbschmidt uint32_t build; 1731210111Sbschmidt uint64_t altmask; 1732210111Sbschmidt} __packed; 1733210111Sbschmidt 1734210111Sbschmidt/* TLV header. */ 1735210111Sbschmidtstruct iwn_fw_tlv { 1736210111Sbschmidt uint16_t type; 1737210111Sbschmidt#define IWN_FW_TLV_MAIN_TEXT 1 1738210111Sbschmidt#define IWN_FW_TLV_MAIN_DATA 2 1739210111Sbschmidt#define IWN_FW_TLV_INIT_TEXT 3 1740210111Sbschmidt#define IWN_FW_TLV_INIT_DATA 4 1741210111Sbschmidt#define IWN_FW_TLV_BOOT_TEXT 5 1742210111Sbschmidt#define IWN_FW_TLV_PBREQ_MAXLEN 6 1743262397Sadrian#define IWN_FW_TLV_PAN 7 1744253898Sadrian#define IWN_FW_TLV_RUNT_EVTLOG_PTR 8 1745253898Sadrian#define IWN_FW_TLV_RUNT_EVTLOG_SIZE 9 1746253898Sadrian#define IWN_FW_TLV_RUNT_ERRLOG_PTR 10 1747253898Sadrian#define IWN_FW_TLV_INIT_EVTLOG_PTR 11 1748253898Sadrian#define IWN_FW_TLV_INIT_EVTLOG_SIZE 12 1749253898Sadrian#define IWN_FW_TLV_INIT_ERRLOG_PTR 13 1750220866Sbschmidt#define IWN_FW_TLV_ENH_SENS 14 1751220866Sbschmidt#define IWN_FW_TLV_PHY_CALIB 15 1752253898Sadrian#define IWN_FW_TLV_WOWLAN_INST 16 1753253898Sadrian#define IWN_FW_TLV_WOWLAN_DATA 17 1754262397Sadrian#define IWN_FW_TLV_FLAGS 18 1755210111Sbschmidt 1756210111Sbschmidt uint16_t alt; 1757210111Sbschmidt uint32_t len; 1758210111Sbschmidt} __packed; 1759210111Sbschmidt 1760198429Srpaulo#define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1761198429Srpaulo#define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1762198429Srpaulo#define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1763198429Srpaulo#define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1764178676Ssam#define IWN_FW_BOOT_TEXT_MAXSZ 1024 1765198429Srpaulo#define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1766198429Srpaulo#define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1767178676Ssam 1768178676Ssam/* 1769258627Sadrian * Microcode flags TLV (18.) 1770258627Sadrian */ 1771258627Sadrian 1772258627Sadrian/** 1773258627Sadrian * enum iwn_ucode_tlv_flag - ucode API flags 1774258627Sadrian * @IWN_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 1775258627Sadrian * was a separate TLV but moved here to save space. 1776258627Sadrian * @IWN_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 1777258627Sadrian * treats good CRC threshold as a boolean 1778258627Sadrian * @IWN_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 1779258627Sadrian * @IWN_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 1780258627Sadrian * @IWN_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 1781258627Sadrian * @IWN_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 1782258627Sadrian * @IWN_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 1783258627Sadrian * offload profile config command. 1784258627Sadrian * @IWN_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api 1785258627Sadrian * @IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API. 1786258627Sadrian * @IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 1787258627Sadrian * (rather than two) IPv6 addresses 1788258627Sadrian * @IWN_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API 1789258627Sadrian * @IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 1790258627Sadrian * from the probe request template. 1791258627Sadrian * @IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping 1792258627Sadrian * connection when going back to D0 1793258627Sadrian * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 1794258627Sadrian * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 1795258627Sadrian * @IWN_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan. 1796258627Sadrian * @IWN_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API 1797258627Sadrian * @IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command 1798258627Sadrian * containing CAM (Continuous Active Mode) indication. 1799258627Sadrian */ 1800258627Sadrianenum iwn_ucode_tlv_flag { 1801258627Sadrian IWN_UCODE_TLV_FLAGS_PAN = (1 << 0), 1802258627Sadrian IWN_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 1803258627Sadrian IWN_UCODE_TLV_FLAGS_MFP = (1 << 2), 1804258627Sadrian IWN_UCODE_TLV_FLAGS_P2P = (1 << 3), 1805258627Sadrian IWN_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), 1806258627Sadrian IWN_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5), 1807258627Sadrian IWN_UCODE_TLV_FLAGS_UAPSD = (1 << 6), 1808258627Sadrian IWN_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 1809258627Sadrian IWN_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8), 1810258627Sadrian IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9), 1811258627Sadrian IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 1812258627Sadrian IWN_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11), 1813258627Sadrian IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 1814258627Sadrian IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14), 1815258627Sadrian IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 1816258627Sadrian IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 1817258627Sadrian IWN_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17), 1818258627Sadrian IWN_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19), 1819258627Sadrian IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20), 1820258627Sadrian}; 1821258627Sadrian 1822258627Sadrian/* 1823178676Ssam * Offsets into EEPROM. 1824178676Ssam */ 1825178676Ssam#define IWN_EEPROM_MAC 0x015 1826220729Sbschmidt#define IWN_EEPROM_SKU_CAP 0x045 1827198429Srpaulo#define IWN_EEPROM_RFCFG 0x048 1828198429Srpaulo#define IWN4965_EEPROM_DOMAIN 0x060 1829198429Srpaulo#define IWN4965_EEPROM_BAND1 0x063 1830198429Srpaulo#define IWN5000_EEPROM_REG 0x066 1831198429Srpaulo#define IWN5000_EEPROM_CAL 0x067 1832198429Srpaulo#define IWN4965_EEPROM_BAND2 0x072 1833198429Srpaulo#define IWN4965_EEPROM_BAND3 0x080 1834198429Srpaulo#define IWN4965_EEPROM_BAND4 0x08d 1835198429Srpaulo#define IWN4965_EEPROM_BAND5 0x099 1836198429Srpaulo#define IWN4965_EEPROM_BAND6 0x0a0 1837198429Srpaulo#define IWN4965_EEPROM_BAND7 0x0a8 1838198429Srpaulo#define IWN4965_EEPROM_MAXPOW 0x0e8 1839198429Srpaulo#define IWN4965_EEPROM_VOLTAGE 0x0e9 1840198429Srpaulo#define IWN4965_EEPROM_BANDS 0x0ea 1841198429Srpaulo/* Indirect offsets. */ 1842253898Sadrian#define IWN5000_EEPROM_NO_HT40 0x000 1843198429Srpaulo#define IWN5000_EEPROM_DOMAIN 0x001 1844198429Srpaulo#define IWN5000_EEPROM_BAND1 0x004 1845198429Srpaulo#define IWN5000_EEPROM_BAND2 0x013 1846198429Srpaulo#define IWN5000_EEPROM_BAND3 0x021 1847198429Srpaulo#define IWN5000_EEPROM_BAND4 0x02e 1848198429Srpaulo#define IWN5000_EEPROM_BAND5 0x03a 1849198429Srpaulo#define IWN5000_EEPROM_BAND6 0x041 1850221635Sbschmidt#define IWN6000_EEPROM_BAND6 0x040 1851198429Srpaulo#define IWN5000_EEPROM_BAND7 0x049 1852201209Srpaulo#define IWN6000_EEPROM_ENHINFO 0x054 1853198429Srpaulo#define IWN5000_EEPROM_CRYSTAL 0x128 1854198429Srpaulo#define IWN5000_EEPROM_TEMP 0x12a 1855198429Srpaulo#define IWN5000_EEPROM_VOLT 0x12b 1856178676Ssam 1857220729Sbschmidt/* Possible flags for IWN_EEPROM_SKU_CAP. */ 1858220729Sbschmidt#define IWN_EEPROM_SKU_CAP_11N (1 << 6) 1859220729Sbschmidt#define IWN_EEPROM_SKU_CAP_AMT (1 << 7) 1860220729Sbschmidt#define IWN_EEPROM_SKU_CAP_IPAN (1 << 8) 1861220729Sbschmidt 1862198429Srpaulo/* Possible flags for IWN_EEPROM_RFCFG. */ 1863198429Srpaulo#define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1864198429Srpaulo#define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1865198429Srpaulo#define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1866198429Srpaulo#define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1867198429Srpaulo#define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1868198429Srpaulo 1869178676Ssamstruct iwn_eeprom_chan { 1870178676Ssam uint8_t flags; 1871178676Ssam#define IWN_EEPROM_CHAN_VALID (1 << 0) 1872198429Srpaulo#define IWN_EEPROM_CHAN_IBSS (1 << 1) 1873198429Srpaulo#define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1874198429Srpaulo#define IWN_EEPROM_CHAN_RADAR (1 << 4) 1875178676Ssam 1876178676Ssam int8_t maxpwr; 1877178676Ssam} __packed; 1878178676Ssam 1879201209Srpaulostruct iwn_eeprom_enhinfo { 1880221637Sbschmidt uint8_t flags; 1881221637Sbschmidt#define IWN_ENHINFO_VALID 0x01 1882221637Sbschmidt#define IWN_ENHINFO_5GHZ 0x02 1883221637Sbschmidt#define IWN_ENHINFO_OFDM 0x04 1884221637Sbschmidt#define IWN_ENHINFO_HT40 0x08 1885221637Sbschmidt#define IWN_ENHINFO_HTAP 0x10 1886221637Sbschmidt#define IWN_ENHINFO_RES1 0x20 1887221637Sbschmidt#define IWN_ENHINFO_RES2 0x40 1888221637Sbschmidt#define IWN_ENHINFO_COMMON 0x80 1889221637Sbschmidt 1890221637Sbschmidt uint8_t chan; 1891201209Srpaulo int8_t chain[3]; /* max power in half-dBm */ 1892201209Srpaulo uint8_t reserved; 1893201209Srpaulo int8_t mimo2; /* max power in half-dBm */ 1894201209Srpaulo int8_t mimo3; /* max power in half-dBm */ 1895201209Srpaulo} __packed; 1896201209Srpaulo 1897206444Sbschmidtstruct iwn5000_eeprom_calib_hdr { 1898206444Sbschmidt uint8_t version; 1899206444Sbschmidt uint8_t pa_type; 1900206444Sbschmidt uint16_t volt; 1901206444Sbschmidt} __packed; 1902206444Sbschmidt 1903178676Ssam#define IWN_NSAMPLES 3 1904198429Srpaulostruct iwn4965_eeprom_chan_samples { 1905178676Ssam uint8_t num; 1906178676Ssam struct { 1907178676Ssam uint8_t temp; 1908178676Ssam uint8_t gain; 1909178676Ssam uint8_t power; 1910178676Ssam int8_t pa_det; 1911198429Srpaulo } samples[2][IWN_NSAMPLES]; 1912178676Ssam} __packed; 1913178676Ssam 1914178676Ssam#define IWN_NBANDS 8 1915198429Srpaulostruct iwn4965_eeprom_band { 1916178676Ssam uint8_t lo; /* low channel number */ 1917178676Ssam uint8_t hi; /* high channel number */ 1918198429Srpaulo struct iwn4965_eeprom_chan_samples chans[2]; 1919178676Ssam} __packed; 1920178676Ssam 1921198429Srpaulo/* 1922198429Srpaulo * Offsets of channels descriptions in EEPROM. 1923198429Srpaulo */ 1924198429Srpaulostatic const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1925198429Srpaulo IWN4965_EEPROM_BAND1, 1926198429Srpaulo IWN4965_EEPROM_BAND2, 1927198429Srpaulo IWN4965_EEPROM_BAND3, 1928198429Srpaulo IWN4965_EEPROM_BAND4, 1929198429Srpaulo IWN4965_EEPROM_BAND5, 1930198429Srpaulo IWN4965_EEPROM_BAND6, 1931198429Srpaulo IWN4965_EEPROM_BAND7 1932198429Srpaulo}; 1933178676Ssam 1934198429Srpaulostatic const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1935198429Srpaulo IWN5000_EEPROM_BAND1, 1936198429Srpaulo IWN5000_EEPROM_BAND2, 1937198429Srpaulo IWN5000_EEPROM_BAND3, 1938198429Srpaulo IWN5000_EEPROM_BAND4, 1939198429Srpaulo IWN5000_EEPROM_BAND5, 1940198429Srpaulo IWN5000_EEPROM_BAND6, 1941198429Srpaulo IWN5000_EEPROM_BAND7 1942198429Srpaulo}; 1943198429Srpaulo 1944221635Sbschmidtstatic const uint32_t iwn6000_regulatory_bands[IWN_NBANDS] = { 1945221635Sbschmidt IWN5000_EEPROM_BAND1, 1946221635Sbschmidt IWN5000_EEPROM_BAND2, 1947221635Sbschmidt IWN5000_EEPROM_BAND3, 1948221635Sbschmidt IWN5000_EEPROM_BAND4, 1949221635Sbschmidt IWN5000_EEPROM_BAND5, 1950221635Sbschmidt IWN6000_EEPROM_BAND6, 1951221635Sbschmidt IWN5000_EEPROM_BAND7 1952221635Sbschmidt}; 1953221635Sbschmidt 1954253898Sadrianstatic const uint32_t iwn1000_regulatory_bands[IWN_NBANDS] = { 1955253898Sadrian IWN5000_EEPROM_BAND1, 1956253898Sadrian IWN5000_EEPROM_BAND2, 1957253898Sadrian IWN5000_EEPROM_BAND3, 1958253898Sadrian IWN5000_EEPROM_BAND4, 1959253898Sadrian IWN5000_EEPROM_BAND5, 1960253898Sadrian IWN5000_EEPROM_BAND6, 1961253898Sadrian IWN5000_EEPROM_NO_HT40, 1962253898Sadrian}; 1963253898Sadrian 1964257880Sadrianstatic const uint32_t iwn2030_regulatory_bands[IWN_NBANDS] = { 1965257880Sadrian IWN5000_EEPROM_BAND1, 1966257880Sadrian IWN5000_EEPROM_BAND2, 1967257880Sadrian IWN5000_EEPROM_BAND3, 1968257880Sadrian IWN5000_EEPROM_BAND4, 1969257880Sadrian IWN5000_EEPROM_BAND5, 1970257880Sadrian IWN6000_EEPROM_BAND6, 1971257880Sadrian IWN5000_EEPROM_BAND7 1972257880Sadrian}; 1973257880Sadrian 1974198429Srpaulo#define IWN_CHAN_BANDS_COUNT 7 1975198429Srpaulo#define IWN_MAX_CHAN_PER_BAND 14 1976198429Srpaulostatic const struct iwn_chan_band { 1977198429Srpaulo uint8_t nchan; 1978198429Srpaulo uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1979198429Srpaulo} iwn_bands[] = { 1980198429Srpaulo /* 20MHz channels, 2GHz band. */ 1981198429Srpaulo { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1982198429Srpaulo /* 20MHz channels, 5GHz band. */ 1983198429Srpaulo { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1984198429Srpaulo { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1985198429Srpaulo { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1986198429Srpaulo { 6, { 145, 149, 153, 157, 161, 165 } }, 1987198429Srpaulo /* 40MHz channels (primary channels), 2GHz band. */ 1988198429Srpaulo { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1989198429Srpaulo /* 40MHz channels (primary channels), 5GHz band. */ 1990198429Srpaulo { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1991198429Srpaulo}; 1992198429Srpaulo 1993253898Sadrianstatic const uint8_t iwn_bss_ac_to_queue[] = { 1994253898Sadrian 2, 3, 1, 0, 1995253898Sadrian}; 1996253898Sadrian 1997253898Sadrianstatic const uint8_t iwn_pan_ac_to_queue[] = { 1998253898Sadrian 5, 4, 6, 7, 1999253898Sadrian}; 2000257605Sadrian#define IWN1000_OTP_NBLOCKS 3 2001257605Sadrian#define IWN6000_OTP_NBLOCKS 4 2002201209Srpaulo#define IWN6050_OTP_NBLOCKS 7 2003198429Srpaulo 2004198429Srpaulo/* HW rate indices. */ 2005220715Sbschmidt#define IWN_RIDX_CCK1 0 2006220715Sbschmidt#define IWN_RIDX_OFDM6 4 2007198429Srpaulo 2008198429Srpaulo#define IWN4965_MAX_PWR_INDEX 107 2009253898Sadrian#define IWN_POWERSAVE_LVL_NONE 0 2010253898Sadrian#define IWN_POWERSAVE_LVL_VOIP_COMPATIBLE 1 2011253898Sadrian#define IWN_POWERSAVE_LVL_MAX 5 2012198429Srpaulo 2013253898Sadrian#define IWN_POWERSAVE_LVL_DEFAULT IWN_POWERSAVE_LVL_NONE 2014253898Sadrian 2015253898Sadrian/* DTIM value to pass in for IWN_POWERSAVE_LVL_VOIP_COMPATIBLE */ 2016253898Sadrian#define IWN_POWERSAVE_DTIM_VOIP_COMPATIBLE 2 2017253898Sadrian 2018178676Ssam/* 2019178676Ssam * RF Tx gain values from highest to lowest power (values obtained from 2020178676Ssam * the reference driver.) 2021178676Ssam */ 2022198429Srpaulostatic const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 2023178676Ssam 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 2024178676Ssam 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 2025178676Ssam 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 2026178676Ssam 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 2027178676Ssam 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 2028178676Ssam 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 2029178676Ssam 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 2030178676Ssam 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 2031178676Ssam 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 2032178676Ssam 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 2033178676Ssam}; 2034178676Ssam 2035198429Srpaulostatic const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 2036178676Ssam 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 2037178676Ssam 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 2038178676Ssam 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 2039178676Ssam 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 2040178676Ssam 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 2041178676Ssam 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 2042178676Ssam 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 2043178676Ssam 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 2044178676Ssam 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 2045178676Ssam 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 2046178676Ssam}; 2047178676Ssam 2048178676Ssam/* 2049178676Ssam * DSP pre-DAC gain values from highest to lowest power (values obtained 2050178676Ssam * from the reference driver.) 2051178676Ssam */ 2052198429Srpaulostatic const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 2053178676Ssam 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 2054178676Ssam 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 2055178676Ssam 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 2056178676Ssam 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 2057178676Ssam 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 2058178676Ssam 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 2059178676Ssam 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 2060178676Ssam 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 2061178676Ssam 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 2062178676Ssam 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 2063178676Ssam}; 2064178676Ssam 2065198429Srpaulostatic const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 2066178676Ssam 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 2067178676Ssam 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 2068178676Ssam 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 2069178676Ssam 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 2070178676Ssam 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 2071178676Ssam 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 2072178676Ssam 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 2073178676Ssam 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 2074178676Ssam 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 2075178676Ssam 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 2076178676Ssam}; 2077178676Ssam 2078198429Srpaulo/* 2079198429Srpaulo * Power saving settings (values obtained from the reference driver.) 2080198429Srpaulo */ 2081198429Srpaulo#define IWN_NDTIMRANGES 3 2082198429Srpaulo#define IWN_NPOWERLEVELS 6 2083198429Srpaulostatic const struct iwn_pmgt { 2084198429Srpaulo uint32_t rxtimeout; 2085198429Srpaulo uint32_t txtimeout; 2086198429Srpaulo uint32_t intval[5]; 2087198429Srpaulo int skip_dtim; 2088198429Srpaulo} iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 2089198429Srpaulo /* DTIM <= 2 */ 2090198429Srpaulo { 2091198429Srpaulo { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 2092198429Srpaulo { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 2093198429Srpaulo { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 2094198429Srpaulo { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 2095198429Srpaulo { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 2096198429Srpaulo { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 2097198429Srpaulo }, 2098198429Srpaulo /* 3 <= DTIM <= 10 */ 2099198429Srpaulo { 2100198429Srpaulo { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 2101198429Srpaulo { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 2102198429Srpaulo { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 2103198429Srpaulo { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 2104198429Srpaulo { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 2105198429Srpaulo { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 2106198429Srpaulo }, 2107198429Srpaulo /* DTIM >= 11 */ 2108198429Srpaulo { 2109198429Srpaulo { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 2110198429Srpaulo { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 2111198429Srpaulo { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 2112198429Srpaulo { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 2113198429Srpaulo { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 2114198429Srpaulo { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 2115198429Srpaulo } 2116198429Srpaulo}; 2117198429Srpaulo 2118198429Srpaulostruct iwn_sensitivity_limits { 2119198429Srpaulo uint32_t min_ofdm_x1; 2120198429Srpaulo uint32_t max_ofdm_x1; 2121198429Srpaulo uint32_t min_ofdm_mrc_x1; 2122198429Srpaulo uint32_t max_ofdm_mrc_x1; 2123198429Srpaulo uint32_t min_ofdm_x4; 2124198429Srpaulo uint32_t max_ofdm_x4; 2125198429Srpaulo uint32_t min_ofdm_mrc_x4; 2126198429Srpaulo uint32_t max_ofdm_mrc_x4; 2127198429Srpaulo uint32_t min_cck_x4; 2128198429Srpaulo uint32_t max_cck_x4; 2129198429Srpaulo uint32_t min_cck_mrc_x4; 2130198429Srpaulo uint32_t max_cck_mrc_x4; 2131198429Srpaulo uint32_t min_energy_cck; 2132198429Srpaulo uint32_t energy_cck; 2133198429Srpaulo uint32_t energy_ofdm; 2134259116Sadrian uint32_t barker_mrc; 2135198429Srpaulo}; 2136198429Srpaulo 2137198429Srpaulo/* 2138198429Srpaulo * RX sensitivity limits (values obtained from the reference driver.) 2139198429Srpaulo */ 2140198429Srpaulostatic const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 2141198429Srpaulo 105, 140, 2142201209Srpaulo 220, 270, 2143198429Srpaulo 85, 120, 2144198429Srpaulo 170, 210, 2145198429Srpaulo 125, 200, 2146198429Srpaulo 200, 400, 2147198429Srpaulo 97, 2148198429Srpaulo 100, 2149259116Sadrian 100, 2150259116Sadrian 390 2151198429Srpaulo}; 2152198429Srpaulo 2153198429Srpaulostatic const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 2154206444Sbschmidt 120, 120, /* min = max for performance bug in DSP. */ 2155206444Sbschmidt 240, 240, /* min = max for performance bug in DSP. */ 2156198429Srpaulo 90, 120, 2157198429Srpaulo 170, 210, 2158198429Srpaulo 125, 200, 2159198429Srpaulo 170, 400, 2160198429Srpaulo 95, 2161198429Srpaulo 95, 2162259116Sadrian 95, 2163259116Sadrian 390 2164198429Srpaulo}; 2165198429Srpaulo 2166201209Srpaulostatic const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 2167201209Srpaulo 105, 105, /* min = max for performance bug in DSP. */ 2168201209Srpaulo 220, 220, /* min = max for performance bug in DSP. */ 2169201209Srpaulo 90, 120, 2170201209Srpaulo 170, 210, 2171201209Srpaulo 125, 200, 2172201209Srpaulo 170, 400, 2173201209Srpaulo 95, 2174201209Srpaulo 95, 2175259116Sadrian 95, 2176259116Sadrian 390, 2177201209Srpaulo}; 2178201209Srpaulo 2179206444Sbschmidtstatic const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 2180206444Sbschmidt 120, 155, 2181206444Sbschmidt 240, 290, 2182220726Sbschmidt 90, 120, 2183206444Sbschmidt 170, 210, 2184206444Sbschmidt 125, 200, 2185206444Sbschmidt 170, 400, 2186220726Sbschmidt 95, 2187220726Sbschmidt 95, 2188259116Sadrian 95, 2189259116Sadrian 390, 2190206444Sbschmidt}; 2191206444Sbschmidt 2192201209Srpaulostatic const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 2193206444Sbschmidt 105, 110, 2194201209Srpaulo 192, 232, 2195201209Srpaulo 80, 145, 2196201209Srpaulo 128, 232, 2197201209Srpaulo 125, 175, 2198201209Srpaulo 160, 310, 2199201209Srpaulo 97, 2200201209Srpaulo 97, 2201259116Sadrian 100, 2202259116Sadrian 390 2203201209Srpaulo}; 2204201209Srpaulo 2205259116Sadrianstatic const struct iwn_sensitivity_limits iwn6235_sensitivity_limits = { 2206259116Sadrian 105, 110, 2207259116Sadrian 192, 232, 2208259116Sadrian 80, 145, 2209259116Sadrian 128, 232, 2210259116Sadrian 125, 175, 2211259116Sadrian 160, 310, 2212259116Sadrian 100, 2213259116Sadrian 110, 2214259116Sadrian 110, 2215259116Sadrian 336 2216259116Sadrian}; 2217259116Sadrian 2218259116Sadrian 2219253898Sadrian/* Get value from linux kernel 3.2.+ in Drivers/net/wireless/iwlwifi/iwl-2000.c*/ 2220253898Sadrianstatic const struct iwn_sensitivity_limits iwn2030_sensitivity_limits = { 2221253898Sadrian 105,110, 2222253898Sadrian 128,232, 2223253898Sadrian 80,145, 2224253898Sadrian 128,232, 2225253898Sadrian 125,175, 2226253898Sadrian 160,310, 2227253898Sadrian 97, 2228253898Sadrian 97, 2229253898Sadrian 110 2230253898Sadrian}; 2231253898Sadrian 2232198429Srpaulo/* Map TID to TX scheduler's FIFO. */ 2233198429Srpaulostatic const uint8_t iwn_tid2fifo[] = { 2234198429Srpaulo 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 2235198429Srpaulo}; 2236198429Srpaulo 2237201209Srpaulo/* WiFi/WiMAX coexist event priority table for 6050. */ 2238201209Srpaulostatic const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 2239201209Srpaulo { 0x04, 0x03, 0x00, 0x00 }, 2240201209Srpaulo { 0x04, 0x03, 0x00, 0x03 }, 2241201209Srpaulo { 0x04, 0x03, 0x00, 0x03 }, 2242201209Srpaulo { 0x04, 0x03, 0x00, 0x03 }, 2243201209Srpaulo { 0x04, 0x03, 0x00, 0x00 }, 2244201209Srpaulo { 0x04, 0x03, 0x00, 0x07 }, 2245201209Srpaulo { 0x04, 0x03, 0x00, 0x00 }, 2246201209Srpaulo { 0x04, 0x03, 0x00, 0x03 }, 2247201209Srpaulo { 0x04, 0x03, 0x00, 0x03 }, 2248201209Srpaulo { 0x04, 0x03, 0x00, 0x00 }, 2249201209Srpaulo { 0x06, 0x03, 0x00, 0x07 }, 2250201209Srpaulo { 0x04, 0x03, 0x00, 0x00 }, 2251201209Srpaulo { 0x06, 0x06, 0x00, 0x03 }, 2252201209Srpaulo { 0x04, 0x03, 0x00, 0x07 }, 2253201209Srpaulo { 0x04, 0x03, 0x00, 0x00 }, 2254201209Srpaulo { 0x04, 0x03, 0x00, 0x00 } 2255201209Srpaulo}; 2256201209Srpaulo 2257198429Srpaulo/* Firmware errors. */ 2258198429Srpaulostatic const char * const iwn_fw_errmsg[] = { 2259198429Srpaulo "OK", 2260198429Srpaulo "FAIL", 2261198429Srpaulo "BAD_PARAM", 2262198429Srpaulo "BAD_CHECKSUM", 2263198429Srpaulo "NMI_INTERRUPT_WDG", 2264198429Srpaulo "SYSASSERT", 2265198429Srpaulo "FATAL_ERROR", 2266198429Srpaulo "BAD_COMMAND", 2267198429Srpaulo "HW_ERROR_TUNE_LOCK", 2268198429Srpaulo "HW_ERROR_TEMPERATURE", 2269198429Srpaulo "ILLEGAL_CHAN_FREQ", 2270198429Srpaulo "VCC_NOT_STABLE", 2271198429Srpaulo "FH_ERROR", 2272198429Srpaulo "NMI_INTERRUPT_HOST", 2273198429Srpaulo "NMI_INTERRUPT_ACTION_PT", 2274198429Srpaulo "NMI_INTERRUPT_UNKNOWN", 2275198429Srpaulo "UCODE_VERSION_MISMATCH", 2276198429Srpaulo "HW_ERROR_ABS_LOCK", 2277198429Srpaulo "HW_ERROR_CAL_LOCK_FAIL", 2278198429Srpaulo "NMI_INTERRUPT_INST_ACTION_PT", 2279198429Srpaulo "NMI_INTERRUPT_DATA_ACTION_PT", 2280198429Srpaulo "NMI_TRM_HW_ER", 2281198429Srpaulo "NMI_INTERRUPT_TRM", 2282264416Sbrueffer "NMI_INTERRUPT_BREAKPOINT", 2283198429Srpaulo "DEBUG_0", 2284198429Srpaulo "DEBUG_1", 2285198429Srpaulo "DEBUG_2", 2286198429Srpaulo "DEBUG_3", 2287206444Sbschmidt "ADVANCED_SYSASSERT" 2288198429Srpaulo}; 2289198429Srpaulo 2290198429Srpaulo/* Find least significant bit that is set. */ 2291198429Srpaulo#define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 2292198429Srpaulo 2293178676Ssam#define IWN_READ(sc, reg) \ 2294178676Ssam bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 2295178676Ssam 2296178676Ssam#define IWN_WRITE(sc, reg, val) \ 2297178676Ssam bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 2298178676Ssam 2299201209Srpaulo#define IWN_WRITE_1(sc, reg, val) \ 2300201209Srpaulo bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 2301201209Srpaulo 2302198429Srpaulo#define IWN_SETBITS(sc, reg, mask) \ 2303198429Srpaulo IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 2304198429Srpaulo 2305198429Srpaulo#define IWN_CLRBITS(sc, reg, mask) \ 2306198429Srpaulo IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 2307201209Srpaulo 2308201209Srpaulo#define IWN_BARRIER_WRITE(sc) \ 2309201209Srpaulo bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2310201209Srpaulo BUS_SPACE_BARRIER_WRITE) 2311201209Srpaulo 2312201209Srpaulo#define IWN_BARRIER_READ_WRITE(sc) \ 2313201209Srpaulo bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 2314201209Srpaulo BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 2315257034Sadrian 2316257034Sadrian#endif /* __IF_IWNREG_H__ */ 2317