if_iwn_chip_cfg.h revision 258208
1258035Sadrian/*- 2258035Sadrian * Copyright (c) 2013 Cedric GROSS <cg@cgross.info> 3258035Sadrian * Copyright (c) 2011 Intel Corporation 4258035Sadrian * 5258035Sadrian * Permission to use, copy, modify, and distribute this software for any 6258035Sadrian * purpose with or without fee is hereby granted, provided that the above 7258035Sadrian * copyright notice and this permission notice appear in all copies. 8258035Sadrian * 9258035Sadrian * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10258035Sadrian * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11258035Sadrian * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12258035Sadrian * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13258035Sadrian * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14258035Sadrian * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15258035Sadrian * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16258035Sadrian * 17258035Sadrian * $FreeBSD: head/sys/dev/iwn/if_iwn_chip_cfg.h 258208 2013-11-16 04:29:02Z eadler $ 18258035Sadrian */ 19258035Sadrian 20258035Sadrian#ifndef __IF_IWN_CHIP_CFG_H__ 21258035Sadrian#define __IF_IWN_CHIP_CFG_H__ 22258035Sadrian 23258035Sadrian/* ========================================================================== 24258035Sadrian * NIC PARAMETERS 25258035Sadrian * 26258035Sadrian * ========================================================================== 27258035Sadrian */ 28258035Sadrian 29258035Sadrian/* 30258035Sadrian * Flags for managing calibration result. See calib_need 31258035Sadrian * in iwn_base_params struct 32258035Sadrian * 33258035Sadrian * These are bitmasks that determine which indexes in the calibcmd 34258035Sadrian * array are pushed up. 35258035Sadrian */ 36258035Sadrian#define IWN_FLG_NEED_PHY_CALIB_DC (1<<0) 37258035Sadrian#define IWN_FLG_NEED_PHY_CALIB_LO (1<<1) 38258035Sadrian#define IWN_FLG_NEED_PHY_CALIB_TX_IQ (1<<2) 39258035Sadrian#define IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC (1<<3) 40258035Sadrian#define IWN_FLG_NEED_PHY_CALIB_BASE_BAND (1<<4) 41258035Sadrian/* 42258035Sadrian * These aren't (yet) included in the calibcmd array, but 43258035Sadrian * are used as flags for which calibrations to use. 44258035Sadrian * 45258035Sadrian * XXX I think they should be named differently and 46258035Sadrian * stuffed in a different member in the config struct! 47258035Sadrian */ 48258035Sadrian#define IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET (1<<5) 49258035Sadrian#define IWN_FLG_NEED_PHY_CALIB_CRYSTAL (1<<6) 50258035Sadrian#define IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2 (1<<7) 51258035Sadrian 52258035Sadrian/* 53258035Sadrian * Define some parameters for managing different NIC. 54258035Sadrian * Refer to linux specific file like iwl-xxxx.c to determine correct value 55258035Sadrian * for NIC. 56258035Sadrian * 57258035Sadrian * @max_ll_items: max number of OTP blocks 58258035Sadrian * @shadow_ram_support: shadow support for OTP memory 59258035Sadrian * @shadow_reg_enable: HW shadhow register bit 60258035Sadrian * @no_idle_support: do not support idle mode 61258035Sadrian * @advanced_bt_coexist : Advanced BT management 62258035Sadrian * @bt_session_2 : NIC need a new struct for configure BT coexistence. Needed 63258035Sadrian * only if advanced_bt_coexist is true 64258035Sadrian * @bt_sco_disable : 65258035Sadrian * @additional_nic_config: For 6005 series 66258035Sadrian * @iq_invert : ? But need it for N 2000 series 67258035Sadrian * @regulatory_bands : XXX 68258035Sadrian * @enhanced_TX_power : EEPROM Has advanced TX power options. Set 'True' 69258035Sadrian * if update_enhanced_txpower = iwl_eeprom_enhanced_txpower. 70258035Sadrian * See iwl-agn-devices.c file to determine that(enhanced_txpower) 71258035Sadrian * @need_temp_offset_calib : Need to compute some temp offset for calibration. 72258035Sadrian * @calib_need : Use IWN_FLG_NEED_PHY_CALIB_* flags to specify which 73258035Sadrian * calibration data ucode need. See calib_init_cfg in iwl-xxxx.c 74258035Sadrian * linux kernel file 75258035Sadrian * @support_hostap: Define IEEE80211_C_HOSTAP for ic_caps 76258035Sadrian * @no_multi_vaps: See iwn_vap_create 77258035Sadrian * @additional_gp_drv_bit : Specific bit to defined during nic_config 78258035Sadrian * @bt_mode: BT configuration mode 79258035Sadrian */ 80258035Sadrianenum bt_mode_enum { 81258035Sadrian IWN_BT_NONE, 82258035Sadrian IWN_BT_SIMPLE, 83258035Sadrian IWN_BT_ADVANCED 84258035Sadrian}; 85258035Sadrian 86258035Sadrianstruct iwn_base_params { 87258035Sadrian uint32_t pll_cfg_val; 88258035Sadrian const uint16_t max_ll_items; 89258035Sadrian#define IWN_OTP_MAX_LL_ITEMS_1000 (3) /* OTP blocks for 1000 */ 90258035Sadrian#define IWN_OTP_MAX_LL_ITEMS_6x00 (4) /* OTP blocks for 6x00 */ 91258035Sadrian#define IWN_OTP_MAX_LL_ITEMS_6x50 (7) /* OTP blocks for 6x50 */ 92258035Sadrian#define IWN_OTP_MAX_LL_ITEMS_2x00 (4) /* OTP blocks for 2x00 */ 93258035Sadrian const bool shadow_ram_support; 94258035Sadrian const bool shadow_reg_enable; 95258035Sadrian const bool bt_session_2; 96258035Sadrian const bool bt_sco_disable; 97258035Sadrian const bool additional_nic_config; 98258035Sadrian const uint32_t *regulatory_bands; 99258035Sadrian const bool enhanced_TX_power; 100258035Sadrian const uint16_t calib_need; 101258035Sadrian const bool support_hostap; 102258035Sadrian const bool no_multi_vaps; 103258035Sadrian uint8_t additional_gp_drv_bit; 104258035Sadrian enum bt_mode_enum bt_mode; 105258035Sadrian}; 106258035Sadrian 107258035Sadrianstatic const struct iwn_base_params iwn5000_base_params = { 108258035Sadrian .pll_cfg_val = IWN_ANA_PLL_INIT, /* pll_cfg_val; */ 109258035Sadrian .max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00, /* max_ll_items */ 110258035Sadrian .shadow_ram_support = true, /* shadow_ram_support */ 111258035Sadrian .shadow_reg_enable = false, /* shadow_reg_enable */ 112258035Sadrian .bt_session_2 = false, /* bt_session_2 */ 113258035Sadrian .bt_sco_disable = true, /* bt_sco_disable */ 114258035Sadrian .additional_nic_config = false, /* additional_nic_config */ 115258035Sadrian .regulatory_bands = iwn5000_regulatory_bands, /* regulatory_bands */ 116258035Sadrian .enhanced_TX_power = false, /* enhanced_TX_power */ 117258035Sadrian .calib_need = 118258035Sadrian ( IWN_FLG_NEED_PHY_CALIB_LO 119258035Sadrian | IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC 120258035Sadrian | IWN_FLG_NEED_PHY_CALIB_TX_IQ 121258035Sadrian | IWN_FLG_NEED_PHY_CALIB_BASE_BAND ), 122258035Sadrian .support_hostap = false, /* support_hostap */ 123258035Sadrian .no_multi_vaps = true, /* no_multi_vaps */ 124258035Sadrian .additional_gp_drv_bit = IWN_GP_DRIVER_NONE, /* additional_gp_drv_bit */ 125258035Sadrian .bt_mode = IWN_BT_NONE, /* bt_mode */ 126258035Sadrian}; 127258035Sadrian 128258035Sadrian/* 129258035Sadrian * 4965 support 130258035Sadrian */ 131258035Sadrianstatic const struct iwn_base_params iwn4965_base_params = { 132258035Sadrian .pll_cfg_val = 0, /* pll_cfg_val; */ 133258035Sadrian .max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00, /* max_ll_items - ignored for 4965 */ 134258035Sadrian .shadow_ram_support = true, /* shadow_ram_support */ 135258035Sadrian .shadow_reg_enable = false, /* shadow_reg_enable */ 136258035Sadrian .bt_session_2 = false, /* bt_session_2 XXX unknown? */ 137258035Sadrian .bt_sco_disable = true, /* bt_sco_disable XXX unknown? */ 138258035Sadrian .additional_nic_config = false, /* additional_nic_config - not for 4965 */ 139258035Sadrian .regulatory_bands = iwn5000_regulatory_bands, /* regulatory_bands */ 140258035Sadrian .enhanced_TX_power = false, /* enhanced_TX_power - not for 4965 */ 141258035Sadrian .calib_need = 142258035Sadrian (IWN_FLG_NEED_PHY_CALIB_DC 143258035Sadrian | IWN_FLG_NEED_PHY_CALIB_LO 144258035Sadrian | IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC 145258035Sadrian | IWN_FLG_NEED_PHY_CALIB_TX_IQ 146258035Sadrian | IWN_FLG_NEED_PHY_CALIB_BASE_BAND ), 147258035Sadrian .support_hostap = false, /* support_hostap - XXX should work on fixing! */ 148258035Sadrian .no_multi_vaps = true, /* no_multi_vaps - XXX should work on fixing! */ 149258035Sadrian .additional_gp_drv_bit = IWN_GP_DRIVER_NONE, /* additional_gp_drv_bit */ 150258035Sadrian .bt_mode = IWN_BT_SIMPLE, /* bt_mode */ 151258035Sadrian}; 152258035Sadrian 153258035Sadrian 154258035Sadrianstatic const struct iwn_base_params iwn2000_base_params = { 155258035Sadrian .pll_cfg_val = 0, 156258035Sadrian .max_ll_items = IWN_OTP_MAX_LL_ITEMS_2x00, 157258035Sadrian .shadow_ram_support = true, 158258035Sadrian .shadow_reg_enable = false, 159258035Sadrian .bt_session_2 = false, 160258035Sadrian .bt_sco_disable = true, 161258035Sadrian .additional_nic_config = false, 162258035Sadrian .regulatory_bands = iwn2030_regulatory_bands, 163258035Sadrian .enhanced_TX_power = true, 164258035Sadrian .calib_need = 165258035Sadrian (IWN_FLG_NEED_PHY_CALIB_DC 166258035Sadrian | IWN_FLG_NEED_PHY_CALIB_LO 167258035Sadrian | IWN_FLG_NEED_PHY_CALIB_TX_IQ 168258035Sadrian | IWN_FLG_NEED_PHY_CALIB_BASE_BAND 169258035Sadrian | IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2 ), 170258035Sadrian .support_hostap = true, 171258035Sadrian .no_multi_vaps = false, 172258035Sadrian .additional_gp_drv_bit = IWN_GP_DRIVER_REG_BIT_RADIO_IQ_INVERT, 173258208Seadler .bt_mode = IWN_BT_NONE, 174258035Sadrian}; 175258035Sadrian 176258035Sadrianstatic const struct iwn_base_params iwn2030_base_params = { 177258035Sadrian .pll_cfg_val = 0, 178258035Sadrian .max_ll_items = IWN_OTP_MAX_LL_ITEMS_2x00, 179258035Sadrian .shadow_ram_support = true, 180258035Sadrian .shadow_reg_enable = false, /* XXX check? */ 181258035Sadrian .bt_session_2 = true, 182258035Sadrian .bt_sco_disable = true, 183258035Sadrian .additional_nic_config = false, 184258035Sadrian .regulatory_bands = iwn2030_regulatory_bands, 185258035Sadrian .enhanced_TX_power = true, 186258035Sadrian .calib_need = 187258035Sadrian (IWN_FLG_NEED_PHY_CALIB_DC 188258035Sadrian | IWN_FLG_NEED_PHY_CALIB_LO 189258035Sadrian | IWN_FLG_NEED_PHY_CALIB_TX_IQ 190258035Sadrian | IWN_FLG_NEED_PHY_CALIB_BASE_BAND 191258035Sadrian | IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2 ), 192258035Sadrian .support_hostap = true, 193258035Sadrian .no_multi_vaps = false, 194258035Sadrian .additional_gp_drv_bit = IWN_GP_DRIVER_REG_BIT_RADIO_IQ_INVERT, 195258035Sadrian .bt_mode = IWN_BT_ADVANCED, 196258035Sadrian}; 197258035Sadrian 198258035Sadrianstatic const struct iwn_base_params iwn1000_base_params = { 199258035Sadrian .pll_cfg_val = IWN_ANA_PLL_INIT, 200258035Sadrian .max_ll_items = IWN_OTP_MAX_LL_ITEMS_1000, 201258035Sadrian .shadow_ram_support = false, 202258035Sadrian .shadow_reg_enable = false, /* XXX check? */ 203258035Sadrian .bt_session_2 = false, 204258035Sadrian .bt_sco_disable = false, 205258035Sadrian .additional_nic_config = false, 206258035Sadrian .regulatory_bands = iwn5000_regulatory_bands, 207258035Sadrian .enhanced_TX_power = false, 208258035Sadrian .calib_need = 209258035Sadrian ( IWN_FLG_NEED_PHY_CALIB_DC 210258035Sadrian | IWN_FLG_NEED_PHY_CALIB_LO 211258035Sadrian | IWN_FLG_NEED_PHY_CALIB_TX_IQ 212258035Sadrian | IWN_FLG_NEED_PHY_CALIB_BASE_BAND ), 213258035Sadrian .support_hostap = false, 214258035Sadrian .no_multi_vaps = true, 215258035Sadrian .additional_gp_drv_bit = IWN_GP_DRIVER_NONE, 216258035Sadrian .bt_mode = IWN_BT_NONE, 217258035Sadrian}; 218258035Sadrianstatic const struct iwn_base_params iwn_6000_base_params = { 219258035Sadrian .pll_cfg_val = 0, 220258035Sadrian .max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00, 221258035Sadrian .shadow_ram_support = true, 222258035Sadrian .shadow_reg_enable = true, 223258035Sadrian .bt_session_2 = false, 224258035Sadrian .bt_sco_disable = false, 225258035Sadrian .additional_nic_config = false, 226258035Sadrian .regulatory_bands = iwn6000_regulatory_bands, 227258035Sadrian .enhanced_TX_power = true, 228258035Sadrian .calib_need = 229258035Sadrian (IWN_FLG_NEED_PHY_CALIB_DC 230258035Sadrian | IWN_FLG_NEED_PHY_CALIB_LO 231258035Sadrian | IWN_FLG_NEED_PHY_CALIB_TX_IQ 232258035Sadrian | IWN_FLG_NEED_PHY_CALIB_BASE_BAND ), 233258035Sadrian .support_hostap = false, 234258035Sadrian .no_multi_vaps = true, 235258035Sadrian .additional_gp_drv_bit = IWN_GP_DRIVER_NONE, 236258035Sadrian .bt_mode = IWN_BT_SIMPLE, 237258035Sadrian}; 238258035Sadrianstatic const struct iwn_base_params iwn_6000i_base_params = { 239258035Sadrian .pll_cfg_val = 0, 240258035Sadrian .max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00, 241258035Sadrian .shadow_ram_support = true, 242258035Sadrian .shadow_reg_enable = true, 243258035Sadrian .bt_session_2 = false, 244258035Sadrian .bt_sco_disable = true, 245258035Sadrian .additional_nic_config = false, 246258035Sadrian .regulatory_bands = iwn6000_regulatory_bands, 247258035Sadrian .enhanced_TX_power = true, 248258035Sadrian .calib_need = 249258035Sadrian (IWN_FLG_NEED_PHY_CALIB_DC 250258035Sadrian | IWN_FLG_NEED_PHY_CALIB_LO 251258035Sadrian | IWN_FLG_NEED_PHY_CALIB_TX_IQ 252258035Sadrian | IWN_FLG_NEED_PHY_CALIB_BASE_BAND ), 253258035Sadrian .support_hostap = false, 254258035Sadrian .no_multi_vaps = true, 255258035Sadrian .additional_gp_drv_bit = IWN_GP_DRIVER_NONE, 256258035Sadrian .bt_mode = IWN_BT_SIMPLE, 257258035Sadrian}; 258258035Sadrianstatic const struct iwn_base_params iwn_6000g2_base_params = { 259258035Sadrian .pll_cfg_val = 0, 260258035Sadrian .max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00, 261258035Sadrian .shadow_ram_support = true, 262258035Sadrian .shadow_reg_enable = true, 263258035Sadrian .bt_session_2 = false, 264258035Sadrian .bt_sco_disable = true, 265258035Sadrian .additional_nic_config = false, 266258035Sadrian .regulatory_bands = iwn6000_regulatory_bands, 267258035Sadrian .enhanced_TX_power = true, 268258035Sadrian .calib_need = 269258035Sadrian (IWN_FLG_NEED_PHY_CALIB_DC 270258035Sadrian | IWN_FLG_NEED_PHY_CALIB_LO 271258035Sadrian | IWN_FLG_NEED_PHY_CALIB_TX_IQ 272258035Sadrian | IWN_FLG_NEED_PHY_CALIB_BASE_BAND 273258035Sadrian | IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET ), 274258035Sadrian .support_hostap = false, 275258035Sadrian .no_multi_vaps = true, 276258035Sadrian .additional_gp_drv_bit = 0, 277258035Sadrian .bt_mode = IWN_BT_SIMPLE, 278258035Sadrian}; 279258035Sadrian 280258035Sadrianstatic const struct iwn_base_params iwn_6050_base_params = { 281258035Sadrian .pll_cfg_val = 0, 282258035Sadrian .max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x50, 283258035Sadrian .shadow_ram_support = true, 284258035Sadrian .shadow_reg_enable = true, 285258035Sadrian .bt_session_2 = false, 286258035Sadrian .bt_sco_disable = true, 287258035Sadrian .additional_nic_config = true, 288258035Sadrian .regulatory_bands = iwn6000_regulatory_bands, 289258035Sadrian .enhanced_TX_power = true, 290258035Sadrian .calib_need = 291258035Sadrian (IWN_FLG_NEED_PHY_CALIB_LO 292258035Sadrian | IWN_FLG_NEED_PHY_CALIB_TX_IQ 293258035Sadrian | IWN_FLG_NEED_PHY_CALIB_BASE_BAND 294258035Sadrian | IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET ), 295258035Sadrian .support_hostap = false, 296258035Sadrian .no_multi_vaps = true, 297258035Sadrian .additional_gp_drv_bit = IWN_GP_DRIVER_NONE, 298258035Sadrian .bt_mode = IWN_BT_SIMPLE, 299258035Sadrian}; 300258035Sadrianstatic const struct iwn_base_params iwn_6150_base_params = { 301258035Sadrian .pll_cfg_val = 0, 302258035Sadrian .max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x50, 303258035Sadrian .shadow_ram_support = true, 304258035Sadrian .shadow_reg_enable = true, 305258035Sadrian .bt_session_2 = false, 306258035Sadrian .bt_sco_disable = true, 307258035Sadrian .additional_nic_config = true, 308258035Sadrian .regulatory_bands = iwn6000_regulatory_bands, 309258035Sadrian .enhanced_TX_power = true, 310258035Sadrian .calib_need = 311258035Sadrian (IWN_FLG_NEED_PHY_CALIB_LO 312258035Sadrian | IWN_FLG_NEED_PHY_CALIB_TX_IQ 313258035Sadrian | IWN_FLG_NEED_PHY_CALIB_BASE_BAND), 314258035Sadrian .support_hostap = false, 315258035Sadrian .no_multi_vaps = true, 316258035Sadrian .additional_gp_drv_bit = IWN_GP_DRIVER_6050_1X2, 317258035Sadrian .bt_mode = IWN_BT_SIMPLE, 318258035Sadrian}; 319258035Sadrian 320258035Sadrian/* IWL_DEVICE_6035 & IWL_DEVICE_6030 */ 321258035Sadrianstatic const struct iwn_base_params iwn_6000g2b_base_params = { 322258035Sadrian .pll_cfg_val = 0, 323258035Sadrian .max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00, 324258035Sadrian .shadow_ram_support = true, 325258035Sadrian .shadow_reg_enable = true, 326258035Sadrian .bt_session_2 = false, 327258035Sadrian .bt_sco_disable = true, 328258035Sadrian .additional_nic_config = false, 329258035Sadrian .regulatory_bands = iwn6000_regulatory_bands, 330258035Sadrian .enhanced_TX_power = true, 331258035Sadrian .calib_need = 332258035Sadrian (IWN_FLG_NEED_PHY_CALIB_DC 333258035Sadrian | IWN_FLG_NEED_PHY_CALIB_LO 334258035Sadrian | IWN_FLG_NEED_PHY_CALIB_TX_IQ 335258035Sadrian | IWN_FLG_NEED_PHY_CALIB_BASE_BAND 336258035Sadrian | IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET ), 337258035Sadrian .support_hostap = false, 338258035Sadrian .no_multi_vaps = true, 339258035Sadrian .additional_gp_drv_bit = IWN_GP_DRIVER_NONE, 340258035Sadrian .bt_mode = IWN_BT_ADVANCED, 341258035Sadrian}; 342258035Sadrianstatic const struct iwn_base_params iwn_5x50_base_params = { 343258035Sadrian .pll_cfg_val = IWN_ANA_PLL_INIT, 344258035Sadrian .max_ll_items = IWN_OTP_MAX_LL_ITEMS_6x00, 345258035Sadrian .shadow_ram_support = true, 346258035Sadrian .shadow_reg_enable = false, 347258035Sadrian .bt_session_2 = false, 348258035Sadrian .bt_sco_disable = true, 349258035Sadrian .additional_nic_config = false, 350258035Sadrian .regulatory_bands = iwn5000_regulatory_bands, 351258035Sadrian .enhanced_TX_power =false, 352258035Sadrian .calib_need = 353258035Sadrian (IWN_FLG_NEED_PHY_CALIB_DC 354258035Sadrian | IWN_FLG_NEED_PHY_CALIB_LO 355258035Sadrian | IWN_FLG_NEED_PHY_CALIB_TX_IQ 356258035Sadrian | IWN_FLG_NEED_PHY_CALIB_BASE_BAND ), 357258035Sadrian .support_hostap = false, 358258035Sadrian .no_multi_vaps = true, 359258035Sadrian .additional_gp_drv_bit = IWN_GP_DRIVER_NONE, 360258035Sadrian .bt_mode = IWN_BT_SIMPLE, 361258035Sadrian}; 362258035Sadrian 363258035Sadrian#endif /* __IF_IWN_CHIP_CFG_H__ */ 364