1285883Sgrembo/*- 2285883Sgrembo * Copyright (c) 2015 Michael Gmelin <freebsd@grem.de> 3285883Sgrembo * All rights reserved. 4285883Sgrembo * 5285883Sgrembo * Redistribution and use in source and binary forms, with or without 6285883Sgrembo * modification, are permitted provided that the following conditions 7285883Sgrembo * are met: 8285883Sgrembo * 1. Redistributions of source code must retain the above copyright 9285883Sgrembo * notice, this list of conditions and the following disclaimer. 10285883Sgrembo * 2. Redistributions in binary form must reproduce the above copyright 11285883Sgrembo * notice, this list of conditions and the following disclaimer in the 12285883Sgrembo * documentation and/or other materials provided with the distribution. 13285883Sgrembo * 14285883Sgrembo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15285883Sgrembo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16285883Sgrembo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17285883Sgrembo * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18285883Sgrembo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19285883Sgrembo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20285883Sgrembo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21285883Sgrembo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22285883Sgrembo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23285883Sgrembo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24285883Sgrembo * SUCH DAMAGE. 25285883Sgrembo * 26285883Sgrembo * $FreeBSD$ 27285883Sgrembo */ 28285883Sgrembo 29285883Sgrembo#ifndef _ISL_H_ 30285883Sgrembo#define _ISL_H_ 31285883Sgrembo 32285883Sgrembo/* Command register 1 (bits 7-5) */ 33285883Sgrembo#define REG_CMD1 0x00 34285883Sgrembo#define CMD1_MASK_POWER_DOWN 0x00 /* 00000000 */ 35285883Sgrembo#define CMD1_MASK_ALS_ONCE 0x01 << 5 /* 00100000 */ 36285883Sgrembo#define CMD1_MASK_IR_ONCE 0x02 << 5 /* 01000000 */ 37285883Sgrembo#define CMD1_MASK_PROX_ONCE 0x03 << 5 /* 01100000 */ 38285883Sgrembo/* RESERVED */ /* 10000000 */ 39285883Sgrembo#define CMD1_MASK_ALS_CONT 0x05 << 5 /* 10100000 */ 40285883Sgrembo#define CMD1_MASK_IR_CONT 0x06 << 5 /* 11000000 */ 41285883Sgrembo#define CMD1_MASK_PROX_CONT 0x07 << 5 /* 11100000 */ 42285883Sgrembo 43285883Sgrembo/* Command register 2 (bits) */ 44285883Sgrembo#define REG_CMD2 0x01 45285883Sgrembo 46285883Sgrembo/* data registers */ 47285883Sgrembo#define REG_DATA1 0x02 48285883Sgrembo#define REG_DATA2 0x03 49285883Sgrembo#define CMD2_SHIFT_RANGE 0x00 50285883Sgrembo#define CMD2_MASK_RANGE (0x03 << CMD2_SHIFT_RANGE) 51285883Sgrembo#define CMD2_SHIFT_RESOLUTION 0x02 52285883Sgrembo#define CMD2_MASK_RESOLUTION (0x03 << CMD2_SHIFT_RESOLUTION) 53285883Sgrembo 54285883Sgrembo/* Interrupt registers */ 55285883Sgrembo#define REG_INT_LO_LSB 0x04 56285883Sgrembo#define REG_INT_LO_MSB 0x05 57285883Sgrembo#define REG_INT_HI_LSB 0x06 58285883Sgrembo#define REG_INT_HI_MSB 0x07 59285883Sgrembo 60285883Sgrembo/* Test register (should hold 0x00 at all times */ 61285883Sgrembo#define REG_TEST 0x08 62285883Sgrembo 63285883Sgrembo#endif 64