1230557Sjimharris/*- 2230557Sjimharris * This file is provided under a dual BSD/GPLv2 license. When using or 3230557Sjimharris * redistributing this file, you may do so under either license. 4230557Sjimharris * 5230557Sjimharris * GPL LICENSE SUMMARY 6230557Sjimharris * 7230557Sjimharris * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 8230557Sjimharris * 9230557Sjimharris * This program is free software; you can redistribute it and/or modify 10230557Sjimharris * it under the terms of version 2 of the GNU General Public License as 11230557Sjimharris * published by the Free Software Foundation. 12230557Sjimharris * 13230557Sjimharris * This program is distributed in the hope that it will be useful, but 14230557Sjimharris * WITHOUT ANY WARRANTY; without even the implied warranty of 15230557Sjimharris * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16230557Sjimharris * General Public License for more details. 17230557Sjimharris * 18230557Sjimharris * You should have received a copy of the GNU General Public License 19230557Sjimharris * along with this program; if not, write to the Free Software 20230557Sjimharris * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 21230557Sjimharris * The full GNU General Public License is included in this distribution 22230557Sjimharris * in the file called LICENSE.GPL. 23230557Sjimharris * 24230557Sjimharris * BSD LICENSE 25230557Sjimharris * 26230557Sjimharris * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 27230557Sjimharris * All rights reserved. 28230557Sjimharris * 29230557Sjimharris * Redistribution and use in source and binary forms, with or without 30230557Sjimharris * modification, are permitted provided that the following conditions 31230557Sjimharris * are met: 32230557Sjimharris * 33230557Sjimharris * * Redistributions of source code must retain the above copyright 34230557Sjimharris * notice, this list of conditions and the following disclaimer. 35230557Sjimharris * * Redistributions in binary form must reproduce the above copyright 36230557Sjimharris * notice, this list of conditions and the following disclaimer in 37230557Sjimharris * the documentation and/or other materials provided with the 38230557Sjimharris * distribution. 39230557Sjimharris * 40230557Sjimharris * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 41230557Sjimharris * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 42230557Sjimharris * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 43230557Sjimharris * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 44230557Sjimharris * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 45230557Sjimharris * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 46230557Sjimharris * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47230557Sjimharris * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48230557Sjimharris * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49230557Sjimharris * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 50230557Sjimharris * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51230557Sjimharris * 52230557Sjimharris * $FreeBSD$ 53230557Sjimharris */ 54230557Sjimharris#ifndef _SCU_BIOS_DEFINITIONS_H_ 55230557Sjimharris#define _SCU_BIOS_DEFINITIONS_H_ 56230557Sjimharris 57230557Sjimharris#ifdef __cplusplus 58230557Sjimharrisextern "C" { 59230557Sjimharris#endif // __cplusplus 60230557Sjimharris 61230557Sjimharris/** 62230557Sjimharris * IMPORTANT NOTE: 63230557Sjimharris * This file can be used by an SCI Library based driver or 64230557Sjimharris * stand-alone where the library is excluded. By excluding 65230557Sjimharris * the SCI Library, inclusion of OS specific header files can 66230557Sjimharris * be avoided. For example, a BIOS utility probably does not 67230557Sjimharris * want to be bothered with inclusion of nested OS DDK include 68230557Sjimharris * files that are not necessary for its function. 69230557Sjimharris * 70230557Sjimharris * To exclude the SCI Library, either uncomment the EXCLUDE_SCI_LIBRARY 71230557Sjimharris * #define statement in environment.h or define the statement as an input 72230557Sjimharris * to your compiler. 73230557Sjimharris */ 74230557Sjimharris 75230557Sjimharris#include <dev/isci/environment.h> 76230557Sjimharris 77230557Sjimharris#ifndef EXCLUDE_SCI_LIBRARY 78230557Sjimharris#include <dev/isci/scil/sci_types.h> 79230557Sjimharris#include <dev/isci/scil/intel_sas.h> 80230557Sjimharris#include <dev/isci/scil/sci_controller_constants.h> 81230557Sjimharris#endif /* EXCLUDE_SCI_LIBRARY */ 82230557Sjimharris 83230557Sjimharris 84230557Sjimharris 85230557Sjimharris// For Intel Storage Controller Unit OEM Block 86230557Sjimharris#define SCI_OEM_PARAM_SIGNATURE "ISCUOEMB" 87230557Sjimharris 88230557Sjimharris#define SCI_PREBOOT_SOURCE_INIT (0x00) 89230557Sjimharris#define SCI_PREBOOT_SOURCE_OROM (0x80) 90230557Sjimharris#define SCI_PREBOOT_SOURCE_EFI (0x81) 91230557Sjimharris 92230557Sjimharris#define SCI_OEM_PARAM_VER_1_0 (0x10) 93230557Sjimharris#define SCI_OEM_PARAM_VER_1_1 (0x11) 94230557Sjimharris#define SCI_OEM_PARAM_VER_1_2 (0x12) 95230557Sjimharris#define SCI_OEM_PARAM_VER_1_3 (0x13) 96230557Sjimharris 97230557Sjimharris// current version 98230557Sjimharris#define SCI_OEM_PARAM_VER_CUR SCI_OEM_PARAM_VER_1_3 99230557Sjimharris 100230557Sjimharris// port configuration mode 101230557Sjimharris#define SCI_BIOS_MODE_MPC (0x00) 102230557Sjimharris#define SCI_BIOS_MODE_APC (0x01) 103230557Sjimharris 104230557Sjimharris 105230557Sjimharris#ifndef SCI_MAX_PHYS 106230557Sjimharris#define SCI_MAX_PHYS (4) 107230557Sjimharris#endif 108230557Sjimharris 109230557Sjimharris#ifndef SCI_MAX_PORTS 110230557Sjimharris#define SCI_MAX_PORTS (4) 111230557Sjimharris#endif 112230557Sjimharris 113230557Sjimharris 114230557Sjimharris/** 115230557Sjimharris * @struct SCI_BIOS_OEM_PARAM_BLOCK_HDR 116230557Sjimharris * 117230557Sjimharris * @brief This structure defines the OEM Parameter block header. 118230557Sjimharris */ 119230557Sjimharristypedef struct SCI_BIOS_OEM_PARAM_BLOCK_HDR 120230557Sjimharris{ 121230557Sjimharris /** 122230557Sjimharris * This field contains the OEM Parameter Block Signature which is 123230557Sjimharris * used by BIOS and driver software to identify that the memory location 124230557Sjimharris * contains valid OEM Parameter data. The value must be set to 125230557Sjimharris * SCI_OEM_PARAM_SIGNATURE which is the string "ISCUOEMB" which 126230557Sjimharris * stands for Intel Storage Controller Unit OEM Block. 127230557Sjimharris */ 128230557Sjimharris U8 signature[8]; 129230557Sjimharris /** 130230557Sjimharris * This field contains the size in bytes of the complete OEM 131230557Sjimharris * Parameter Block, both header and payload hdr_length + 132230557Sjimharris * (num_elements * element_length). 133230557Sjimharris */ 134230557Sjimharris U16 total_block_length; 135230557Sjimharris /** 136230557Sjimharris * This field contains the size in bytes of the 137230557Sjimharris * SCI_BIOS_OEM_PARAM_BLOCK_HDR. It also indicates the offset from 138230557Sjimharris * the beginning of this data structure to where the actual 139230557Sjimharris * parameter data payload begins. 140230557Sjimharris */ 141230557Sjimharris U8 hdr_length; 142230557Sjimharris /** 143230557Sjimharris * This field contains the version info defining the structure 144230557Sjimharris * of the OEM Parameter block. 145230557Sjimharris */ 146230557Sjimharris U8 version; 147230557Sjimharris /** 148230557Sjimharris * This field contains a value indicating the preboot initialization 149230557Sjimharris * method (Option ROM or UEFI driver) so that after OS transition, 150230557Sjimharris * the OS driver can know the preboot method. OEMs who build a single 151230557Sjimharris * flash image where the preboot method is unknown at manufacturing 152230557Sjimharris * time should set this field to SCI_PREBOOT_SOURCE_INIT. Then 153230557Sjimharris * after the block is retrieved into host memory and under preboot 154230557Sjimharris * driver control, the OROM or UEFI driver can set this field 155230557Sjimharris * appropriately (SCI_PREBOOT_SOURCE_OROM and SCI_PREBOOT_SOURCE_EFI, 156230557Sjimharris * respectively). 157230557Sjimharris */ 158230557Sjimharris U8 preboot_source; 159230557Sjimharris /** 160230557Sjimharris * This field contains the number of parameter descriptor elements 161230557Sjimharris * (i.e. controller_elements) following this header. The number of 162230557Sjimharris * elements corresponds to the number of SCU controller units contained 163230557Sjimharris * in the platform: 164230557Sjimharris * controller_element[0] = SCU0 165230557Sjimharris * controller_element[1] = SCU1 166230557Sjimharris */ 167230557Sjimharris U8 num_elements; 168230557Sjimharris /** 169230557Sjimharris * This field contains the size in bytes of the descriptor element(s) 170230557Sjimharris * in the block. 171230557Sjimharris */ 172230557Sjimharris U16 element_length; 173230557Sjimharris /** 174230557Sjimharris * Reserve fields for future use. 175230557Sjimharris */ 176230557Sjimharris U8 reserved[8]; 177230557Sjimharris 178230557Sjimharris} SCI_BIOS_OEM_PARAM_BLOCK_HDR_T; 179230557Sjimharris 180230557Sjimharris 181230557Sjimharris/** 182230557Sjimharris * @struct SCIC_SDS_OEM_PARAMETERS VER 1.0 183230557Sjimharris * 184230557Sjimharris * @brief This structure delineates the various OEM parameters that must 185230557Sjimharris * be set for the Intel SAS Storage Controller Unit (SCU). 186230557Sjimharris */ 187230557Sjimharristypedef struct SCI_BIOS_OEM_PARAM_ELEMENT 188230557Sjimharris{ 189230557Sjimharris /** 190230557Sjimharris * Per SCU Controller Data 191230557Sjimharris */ 192230557Sjimharris struct 193230557Sjimharris { 194230557Sjimharris /** 195230557Sjimharris * This field indicates the port configuration mode for 196230557Sjimharris * this controller: 197230557Sjimharris * Automatic Port Configuration(APC) or 198230557Sjimharris * Manual Port Configuration (MPC). 199230557Sjimharris * 200230557Sjimharris * APC means the Platform OEM expects SCI to configure 201230557Sjimharris * SAS Ports automatically according to the discovered SAS 202230557Sjimharris * Address pairs of the endpoints, wide and/or narrow. 203230557Sjimharris * 204230557Sjimharris * MPC means the Platform OEM manually defines wide or narrow 205230557Sjimharris * connectors by apriori assigning PHYs to SAS Ports. 206230557Sjimharris * 207230557Sjimharris * By default, the mode type is APC 208230557Sjimharris * in APC mode, if ANY of the phy mask is non-zero, 209230557Sjimharris * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned 210230557Sjimharris * from scic_oem_parameters_set AND the default oem 211230557Sjimharris * configuration will be applied 212230557Sjimharris * in MPC mode, if ALL of the phy masks are zero, 213230557Sjimharris * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned 214230557Sjimharris * from scic_oem_parameters_set AND the default oem 215230557Sjimharris * configuration will be applied 216230557Sjimharris */ 217230557Sjimharris U8 mode_type; 218230557Sjimharris 219230557Sjimharris /** 220230557Sjimharris * This field specifies the maximum number of direct attached 221230557Sjimharris * devices the OEM will allow to have powered up simultaneously 222230557Sjimharris * on this controller. This allows the OEM to avoid exceeding 223230557Sjimharris * power supply limits for this platform. A value of zero 224230557Sjimharris * indicates there are no restrictions. 225230557Sjimharris */ 226230557Sjimharris U8 max_number_concurrent_device_spin_up; 227230557Sjimharris 228230557Sjimharris /** 229230557Sjimharris * This field indicates OEM's desired default 230230557Sjimharris * Spread Spectrum Clocking (SSC) setting for Tx: 231230557Sjimharris * enabled = 1 232230557Sjimharris * disabled = 0 233230557Sjimharris */ 234230557Sjimharris U8 do_enable_ssc; 235230557Sjimharris 236230557Sjimharris U8 reserved; 237230557Sjimharris 238230557Sjimharris } controller; 239230557Sjimharris 240230557Sjimharris /** 241230557Sjimharris * Per SAS Port data. 242230557Sjimharris */ 243230557Sjimharris struct 244230557Sjimharris { 245230557Sjimharris /** 246230557Sjimharris * This field specifies the phys to be contained inside a port. 247230557Sjimharris * The bit position in the mask specifies the index of the phy 248230557Sjimharris * to be contained in the port. Multiple bits (i.e. phys) 249230557Sjimharris * can be contained in a single port: 250230557Sjimharris * Bit 0 = This controller's PHY index 0 (0x01) 251230557Sjimharris * Bit 1 = This controller's PHY index 1 (0x02) 252230557Sjimharris * Bit 2 = This controller's PHY index 2 (0x04) 253230557Sjimharris * Bit 3 = This controller's PHY index 3 (0x08) 254230557Sjimharris * 255230557Sjimharris * Refer to the mode_type field for rules regarding APC and MPC mode. 256230557Sjimharris * General rule: For APC mode phy_mask = 0 257230557Sjimharris */ 258230557Sjimharris U8 phy_mask; 259230557Sjimharris 260230557Sjimharris } ports[SCI_MAX_PORTS]; // Up to 4 Ports per SCU controller unit 261230557Sjimharris 262230557Sjimharris /** 263230557Sjimharris * Per PHY Parameter data. 264230557Sjimharris */ 265230557Sjimharris struct 266230557Sjimharris { 267230557Sjimharris /** 268230557Sjimharris * This field indicates the SAS Address that will be transmitted on 269230557Sjimharris * this PHY index. The field is defined as a union, however, the 270230557Sjimharris * OEM should use the U8 array definition when encoding it to ensure 271230557Sjimharris * correct byte ordering. 272230557Sjimharris * 273230557Sjimharris * NOTE: If using APC MODE, along with phy_mask being set to ZERO, the 274230557Sjimharris * SAS Addresses for all PHYs within a controller group SHALL be the 275230557Sjimharris * same. 276230557Sjimharris */ 277230557Sjimharris union 278230557Sjimharris { 279230557Sjimharris /** 280230557Sjimharris * The array should be stored in little endian order. For example, 281230557Sjimharris * if the desired SAS Address is 0x50010B90_0003538D, then it 282230557Sjimharris * should be stored in the following manner: 283230557Sjimharris * array[0] = 0x90 284230557Sjimharris * array[1] = 0x0B 285230557Sjimharris * array[2] = 0x01 286230557Sjimharris * array[3] = 0x50 287230557Sjimharris * array[4] = 0x8D 288230557Sjimharris * array[5] = 0x53 289230557Sjimharris * array[6] = 0x03 290230557Sjimharris * array[7] = 0x00 291230557Sjimharris */ 292230557Sjimharris U8 array[8]; 293230557Sjimharris /** 294230557Sjimharris * This is the typedef'd version of the SAS Address used in 295230557Sjimharris * the SCI Library. 296230557Sjimharris */ 297230557Sjimharris SCI_SAS_ADDRESS_T sci_format; 298230557Sjimharris 299230557Sjimharris } sas_address; 300230557Sjimharris 301230557Sjimharris /** 302240518Seadler * These are the per PHY equalization settings associated with the 303230557Sjimharris * AFE XCVR Tx Amplitude and Equalization Control Register Set 304230557Sjimharris * (0 thru 3). 305230557Sjimharris * 306230557Sjimharris * Operational Note: The following Look-Up-Table registers are engaged 307230557Sjimharris * by the AFE block after the following: 308230557Sjimharris * - Software programs the Link Layer AFE Look Up Table Control 309230557Sjimharris * Registers (AFE_LUTCR). 310230557Sjimharris * - Software sets AFE XCVR Tx Control Register Tx Equalization 311230557Sjimharris * Enable bit. 312230557Sjimharris */ 313230557Sjimharris /** 314230557Sjimharris * AFE_TX_AMP_CTRL0. This register is associated with AFE_LUTCR 315230557Sjimharris * LUTSel=00b. It contains the Tx Equalization settings that will be 316230557Sjimharris * used if a SATA 1.5Gbs or SATA 3.0Gbs device is direct-attached. 317230557Sjimharris */ 318230557Sjimharris U32 afe_tx_amp_control0; 319230557Sjimharris 320230557Sjimharris /** 321230557Sjimharris * AFE_TX_AMP_CTRL1. This register is associated with AFE_LUTCR 322230557Sjimharris * LUTSel=01b. It contains the Tx Equalization settings that will 323230557Sjimharris * be used if a SATA 6.0Gbs device is direct-attached. 324230557Sjimharris */ 325230557Sjimharris U32 afe_tx_amp_control1; 326230557Sjimharris 327230557Sjimharris /** 328230557Sjimharris * AFE_TX_AMP_CTRL2. This register is associated with AFE_LUTCR 329230557Sjimharris * LUTSel=10b. It contains the Tx Equalization settings that will 330230557Sjimharris * be used if a SAS 1.5Gbs or SAS 3.0Gbs device is direct-attached. 331230557Sjimharris */ 332230557Sjimharris U32 afe_tx_amp_control2; 333230557Sjimharris 334230557Sjimharris /** 335230557Sjimharris * AFE_TX_AMP_CTRL3. This register is associated with AFE_LUTCR 336230557Sjimharris * LUTSel=11b. It contains the Tx Equalization settings that will 337230557Sjimharris * be used if a SAS 6.0Gbs device is direct-attached. 338230557Sjimharris */ 339230557Sjimharris U32 afe_tx_amp_control3; 340230557Sjimharris 341230557Sjimharris } phys[SCI_MAX_PHYS]; // 4 PHYs per SCU controller unit 342230557Sjimharris 343230557Sjimharris} SCI_BIOS_OEM_PARAM_ELEMENT_T; 344230557Sjimharris 345230557Sjimharris/** 346230557Sjimharris * @struct SCIC_SDS_OEM_PARAMETERS VER 1.1 347230557Sjimharris * 348230557Sjimharris * @brief This structure delineates the various OEM parameters that must 349230557Sjimharris * be set for the Intel SAS Storage Controller Unit (SCU). 350230557Sjimharris */ 351230557Sjimharristypedef struct SCI_BIOS_OEM_PARAM_ELEMENT_v_1_1 352230557Sjimharris{ 353230557Sjimharris /** 354230557Sjimharris * Per SCU Controller Data 355230557Sjimharris */ 356230557Sjimharris struct 357230557Sjimharris { 358230557Sjimharris /** 359230557Sjimharris * This field indicates the port configuration mode for 360230557Sjimharris * this controller: 361230557Sjimharris * Automatic Port Configuration(APC) or 362230557Sjimharris * Manual Port Configuration (MPC). 363230557Sjimharris * 364230557Sjimharris * APC means the Platform OEM expects SCI to configure 365230557Sjimharris * SAS Ports automatically according to the discovered SAS 366230557Sjimharris * Address pairs of the endpoints, wide and/or narrow. 367230557Sjimharris * 368230557Sjimharris * MPC means the Platform OEM manually defines wide or narrow 369230557Sjimharris * connectors by apriori assigning PHYs to SAS Ports. 370230557Sjimharris * 371230557Sjimharris * By default, the mode type is APC 372230557Sjimharris * in APC mode, if ANY of the phy mask is non-zero, 373230557Sjimharris * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned 374230557Sjimharris * from scic_oem_parameters_set AND the default oem 375230557Sjimharris * configuration will be applied 376230557Sjimharris * in MPC mode, if ALL of the phy masks are zero, 377230557Sjimharris * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned 378230557Sjimharris * from scic_oem_parameters_set AND the default oem 379230557Sjimharris * configuration will be applied 380230557Sjimharris */ 381230557Sjimharris U8 mode_type; 382230557Sjimharris 383230557Sjimharris /** 384230557Sjimharris * This field specifies the maximum number of direct attached 385230557Sjimharris * devices the OEM will allow to have powered up simultaneously 386230557Sjimharris * on this controller. This allows the OEM to avoid exceeding 387230557Sjimharris * power supply limits for this platform. A value of zero 388230557Sjimharris * indicates there are no restrictions. 389230557Sjimharris */ 390230557Sjimharris U8 max_number_concurrent_device_spin_up; 391230557Sjimharris 392230557Sjimharris /** 393230557Sjimharris * This bitfield indicates the OEM's desired default Tx 394230557Sjimharris * Spread Spectrum Clocking (SSC) settings for SATA and SAS. 395230557Sjimharris * NOTE: Default SSC Modulation Frequency is 31.5KHz. 396230557Sjimharris *--------------------------------------------------------------------*/ 397230557Sjimharris /** 398230557Sjimharris * NOTE: Max spread for SATA is +0 / -5000 PPM. 399230557Sjimharris * Down-spreading SSC (only method allowed for SATA): 400230557Sjimharris * SATA SSC Tx Disabled = 0x0 401230557Sjimharris * SATA SSC Tx at +0 / -1419 PPM Spread = 0x2 402230557Sjimharris * SATA SSC Tx at +0 / -2129 PPM Spread = 0x3 403230557Sjimharris * SATA SSC Tx at +0 / -4257 PPM Spread = 0x6 404230557Sjimharris * SATA SSC Tx at +0 / -4967 PPM Spread = 0x7 405230557Sjimharris */ 406230557Sjimharris U8 ssc_sata_tx_spread_level : 4; 407230557Sjimharris 408230557Sjimharris /** 409230557Sjimharris * SAS SSC Tx Disabled = 0x0 410230557Sjimharris * 411230557Sjimharris * NOTE: Max spread for SAS down-spreading +0 / -2300 PPM 412230557Sjimharris * Down-spreading SSC: 413230557Sjimharris * SAS SSC Tx at +0 / -1419 PPM Spread = 0x2 414230557Sjimharris * SAS SSC Tx at +0 / -2129 PPM Spread = 0x3 415230557Sjimharris * 416230557Sjimharris * NOTE: Max spread for SAS center-spreading +2300 / -2300 PPM 417230557Sjimharris * Center-spreading SSC: 418230557Sjimharris * SAS SSC Tx at +1064 / -1064 PPM Spread = 0x3 419230557Sjimharris * SAS SSC Tx at +2129 / -2129 PPM Spread = 0x6 420230557Sjimharris */ 421230557Sjimharris U8 ssc_sas_tx_spread_level : 3; 422230557Sjimharris /** 423230557Sjimharris * NOTE: Refer to the SSC section of the SAS 2.x Specification 424230557Sjimharris * for proper setting of this field. For standard SAS Initiator 425230557Sjimharris * SAS PHY operation it should be 0 for Down-spreading. 426230557Sjimharris * SAS SSC Tx spread type: 427230557Sjimharris * Down-spreading SSC = 0 428230557Sjimharris * Center-spreading SSC = 1 429230557Sjimharris */ 430230557Sjimharris U8 ssc_sas_tx_type : 1; 431230557Sjimharris /*--------------------------------------------------------------------*/ 432230557Sjimharris 433230557Sjimharris U8 reserved; 434230557Sjimharris 435230557Sjimharris } controller; 436230557Sjimharris 437230557Sjimharris /** 438230557Sjimharris * Per SAS Port data. 439230557Sjimharris */ 440230557Sjimharris struct 441230557Sjimharris { 442230557Sjimharris /** 443230557Sjimharris * This field specifies the phys to be contained inside a port. 444230557Sjimharris * The bit position in the mask specifies the index of the phy 445230557Sjimharris * to be contained in the port. Multiple bits (i.e. phys) 446230557Sjimharris * can be contained in a single port: 447230557Sjimharris * Bit 0 = This controller's PHY index 0 (0x01) 448230557Sjimharris * Bit 1 = This controller's PHY index 1 (0x02) 449230557Sjimharris * Bit 2 = This controller's PHY index 2 (0x04) 450230557Sjimharris * Bit 3 = This controller's PHY index 3 (0x08) 451230557Sjimharris * 452230557Sjimharris * Refer to the mode_type field for rules regarding APC and MPC mode. 453230557Sjimharris * General rule: For APC mode phy_mask = 0 454230557Sjimharris */ 455230557Sjimharris U8 phy_mask; 456230557Sjimharris 457230557Sjimharris } ports[SCI_MAX_PORTS]; // Up to 4 Ports per SCU controller unit 458230557Sjimharris 459230557Sjimharris /** 460230557Sjimharris * Per PHY Parameter data. 461230557Sjimharris */ 462230557Sjimharris struct 463230557Sjimharris { 464230557Sjimharris /** 465230557Sjimharris * This field indicates the SAS Address that will be transmitted on 466230557Sjimharris * this PHY index. The field is defined as a union, however, the 467230557Sjimharris * OEM should use the U8 array definition when encoding it to ensure 468230557Sjimharris * correct byte ordering. 469230557Sjimharris * 470230557Sjimharris * NOTE: If using APC MODE, along with phy_mask being set to ZERO, the 471230557Sjimharris * SAS Addresses for all PHYs within a controller group SHALL be the 472230557Sjimharris * same. 473230557Sjimharris */ 474230557Sjimharris union 475230557Sjimharris { 476230557Sjimharris /** 477230557Sjimharris * The array should be stored in little endian order. For example, 478230557Sjimharris * if the desired SAS Address is 0x50010B90_0003538D, then it 479230557Sjimharris * should be stored in the following manner: 480230557Sjimharris * array[0] = 0x90 481230557Sjimharris * array[1] = 0x0B 482230557Sjimharris * array[2] = 0x01 483230557Sjimharris * array[3] = 0x50 484230557Sjimharris * array[4] = 0x8D 485230557Sjimharris * array[5] = 0x53 486230557Sjimharris * array[6] = 0x03 487230557Sjimharris * array[7] = 0x00 488230557Sjimharris */ 489230557Sjimharris U8 array[8]; 490230557Sjimharris /** 491230557Sjimharris * This is the typedef'd version of the SAS Address used in 492230557Sjimharris * the SCI Library. 493230557Sjimharris */ 494230557Sjimharris SCI_SAS_ADDRESS_T sci_format; 495230557Sjimharris 496230557Sjimharris } sas_address; 497230557Sjimharris 498230557Sjimharris /** 499240518Seadler * These are the per PHY equalization settings associated with the 500230557Sjimharris * AFE XCVR Tx Amplitude and Equalization Control Register Set 501230557Sjimharris * (0 thru 3). 502230557Sjimharris * 503230557Sjimharris * Operational Note: The following Look-Up-Table registers are engaged 504230557Sjimharris * by the AFE block after the following: 505230557Sjimharris * - Software programs the Link Layer AFE Look Up Table Control 506230557Sjimharris * Registers (AFE_LUTCR). 507230557Sjimharris * - Software sets AFE XCVR Tx Control Register Tx Equalization 508230557Sjimharris * Enable bit. 509230557Sjimharris */ 510230557Sjimharris /** 511230557Sjimharris * AFE_TX_AMP_CTRL0. This register is associated with AFE_LUTCR 512230557Sjimharris * LUTSel=00b. It contains the Tx Equalization settings that will be 513230557Sjimharris * used if a SATA 1.5Gbs or SATA 3.0Gbs device is direct-attached. 514230557Sjimharris */ 515230557Sjimharris U32 afe_tx_amp_control0; 516230557Sjimharris 517230557Sjimharris /** 518230557Sjimharris * AFE_TX_AMP_CTRL1. This register is associated with AFE_LUTCR 519230557Sjimharris * LUTSel=01b. It contains the Tx Equalization settings that will 520230557Sjimharris * be used if a SATA 6.0Gbs device is direct-attached. 521230557Sjimharris */ 522230557Sjimharris U32 afe_tx_amp_control1; 523230557Sjimharris 524230557Sjimharris /** 525230557Sjimharris * AFE_TX_AMP_CTRL2. This register is associated with AFE_LUTCR 526230557Sjimharris * LUTSel=10b. It contains the Tx Equalization settings that will 527230557Sjimharris * be used if a SAS 1.5Gbs or SAS 3.0Gbs device is direct-attached. 528230557Sjimharris */ 529230557Sjimharris U32 afe_tx_amp_control2; 530230557Sjimharris 531230557Sjimharris /** 532230557Sjimharris * AFE_TX_AMP_CTRL3. This register is associated with AFE_LUTCR 533230557Sjimharris * LUTSel=11b. It contains the Tx Equalization settings that will 534230557Sjimharris * be used if a SAS 6.0Gbs device is direct-attached. 535230557Sjimharris */ 536230557Sjimharris U32 afe_tx_amp_control3; 537230557Sjimharris 538230557Sjimharris } phys[SCI_MAX_PHYS]; // 4 PHYs per SCU controller unit 539230557Sjimharris 540230557Sjimharris} SCI_BIOS_OEM_PARAM_ELEMENT_v_1_1_T; 541230557Sjimharris 542230557Sjimharris/** 543230557Sjimharris * @struct SCIC_SDS_OEM_PARAMETERS VER 1.2 544230557Sjimharris * 545230557Sjimharris * @brief This structure delineates the various OEM parameters that must 546230557Sjimharris * be set for the Intel SAS Storage Controller Unit (SCU). 547230557Sjimharris */ 548230557Sjimharristypedef struct SCI_BIOS_OEM_PARAM_ELEMENT_v_1_2 549230557Sjimharris{ 550230557Sjimharris /** 551230557Sjimharris * Per SCU Controller Data 552230557Sjimharris */ 553230557Sjimharris struct 554230557Sjimharris { 555230557Sjimharris /** 556230557Sjimharris * This field indicates the port configuration mode for 557230557Sjimharris * this controller: 558230557Sjimharris * Automatic Port Configuration(APC) or 559230557Sjimharris * Manual Port Configuration (MPC). 560230557Sjimharris * 561230557Sjimharris * APC means the Platform OEM expects SCI to configure 562230557Sjimharris * SAS Ports automatically according to the discovered SAS 563230557Sjimharris * Address pairs of the endpoints, wide and/or narrow. 564230557Sjimharris * 565230557Sjimharris * MPC means the Platform OEM manually defines wide or narrow 566230557Sjimharris * connectors by apriori assigning PHYs to SAS Ports. 567230557Sjimharris * 568230557Sjimharris * By default, the mode type is APC 569230557Sjimharris * in APC mode, if ANY of the phy mask is non-zero, 570230557Sjimharris * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned 571230557Sjimharris * from scic_oem_parameters_set AND the default oem 572230557Sjimharris * configuration will be applied 573230557Sjimharris * in MPC mode, if ALL of the phy masks are zero, 574230557Sjimharris * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned 575230557Sjimharris * from scic_oem_parameters_set AND the default oem 576230557Sjimharris * configuration will be applied 577230557Sjimharris */ 578230557Sjimharris U8 mode_type; 579230557Sjimharris 580230557Sjimharris /** 581230557Sjimharris * This field specifies the maximum number of direct attached 582230557Sjimharris * devices the OEM will allow to have powered up simultaneously 583230557Sjimharris * on this controller. This allows the OEM to avoid exceeding 584230557Sjimharris * power supply limits for this platform. A value of zero 585230557Sjimharris * indicates there are no restrictions. 586230557Sjimharris */ 587230557Sjimharris U8 max_number_concurrent_device_spin_up; 588230557Sjimharris 589230557Sjimharris /** 590230557Sjimharris * This bitfield indicates the OEM's desired default Tx 591230557Sjimharris * Spread Spectrum Clocking (SSC) settings for SATA and SAS. 592230557Sjimharris * NOTE: Default SSC Modulation Frequency is 31.5KHz. 593230557Sjimharris *--------------------------------------------------------------------*/ 594230557Sjimharris /** 595230557Sjimharris * NOTE: Max spread for SATA is +0 / -5000 PPM. 596230557Sjimharris * Down-spreading SSC (only method allowed for SATA): 597230557Sjimharris * SATA SSC Tx Disabled = 0x0 598230557Sjimharris * SATA SSC Tx at +0 / -1419 PPM Spread = 0x2 599230557Sjimharris * SATA SSC Tx at +0 / -2129 PPM Spread = 0x3 600230557Sjimharris * SATA SSC Tx at +0 / -4257 PPM Spread = 0x6 601230557Sjimharris * SATA SSC Tx at +0 / -4967 PPM Spread = 0x7 602230557Sjimharris */ 603230557Sjimharris U8 ssc_sata_tx_spread_level : 4; 604230557Sjimharris 605230557Sjimharris /** 606230557Sjimharris * SAS SSC Tx Disabled = 0x0 607230557Sjimharris * 608230557Sjimharris * NOTE: Max spread for SAS down-spreading +0 / -2300 PPM 609230557Sjimharris * Down-spreading SSC: 610230557Sjimharris * SAS SSC Tx at +0 / -1419 PPM Spread = 0x2 611230557Sjimharris * SAS SSC Tx at +0 / -2129 PPM Spread = 0x3 612230557Sjimharris * 613230557Sjimharris * NOTE: Max spread for SAS center-spreading +2300 / -2300 PPM 614230557Sjimharris * Center-spreading SSC: 615230557Sjimharris * SAS SSC Tx at +1064 / -1064 PPM Spread = 0x3 616230557Sjimharris * SAS SSC Tx at +2129 / -2129 PPM Spread = 0x6 617230557Sjimharris */ 618230557Sjimharris U8 ssc_sas_tx_spread_level : 3; 619230557Sjimharris /** 620230557Sjimharris * NOTE: Refer to the SSC section of the SAS 2.x Specification 621230557Sjimharris * for proper setting of this field. For standard SAS Initiator 622230557Sjimharris * SAS PHY operation it should be 0 for Down-spreading. 623230557Sjimharris * SAS SSC Tx spread type: 624230557Sjimharris * Down-spreading SSC = 0 625230557Sjimharris * Center-spreading SSC = 1 626230557Sjimharris */ 627230557Sjimharris U8 ssc_sas_tx_type : 1; 628230557Sjimharris 629230557Sjimharris /** 630230557Sjimharris * This field indicates length of the SAS/SATA cable between 631230557Sjimharris * host and device. 632230557Sjimharris * This field is used make relationship between analog parameters of 633230557Sjimharris * the phy in the silicon and length of the cable. 634230557Sjimharris * Supported length: "short"- up to 3m, "long"- more than 3m 635230557Sjimharris * This is bit mask field: 636230557Sjimharris * 637230557Sjimharris * BIT: 7 6 5 4 3 2 1 0 (LSB) 638230557Sjimharris * ASSIGNMENT: <-><-><-><-><phy3><phy2><phy1><phy0> 639230557Sjimharris * 640230557Sjimharris * For short cable corresponding bit shall be reset, 641230557Sjimharris * for long cable shall be set. 642230557Sjimharris */ 643230557Sjimharris U8 long_cable_selection_mask; 644230557Sjimharris 645230557Sjimharris } controller; 646230557Sjimharris 647230557Sjimharris /** 648230557Sjimharris * Per SAS Port data. 649230557Sjimharris */ 650230557Sjimharris struct 651230557Sjimharris { 652230557Sjimharris /** 653230557Sjimharris * This field specifies the phys to be contained inside a port. 654230557Sjimharris * The bit position in the mask specifies the index of the phy 655230557Sjimharris * to be contained in the port. Multiple bits (i.e. phys) 656230557Sjimharris * can be contained in a single port: 657230557Sjimharris * Bit 0 = This controller's PHY index 0 (0x01) 658230557Sjimharris * Bit 1 = This controller's PHY index 1 (0x02) 659230557Sjimharris * Bit 2 = This controller's PHY index 2 (0x04) 660230557Sjimharris * Bit 3 = This controller's PHY index 3 (0x08) 661230557Sjimharris * 662230557Sjimharris * Refer to the mode_type field for rules regarding APC and MPC mode. 663230557Sjimharris * General rule: For APC mode phy_mask = 0 664230557Sjimharris */ 665230557Sjimharris U8 phy_mask; 666230557Sjimharris 667230557Sjimharris } ports[SCI_MAX_PORTS]; // Up to 4 Ports per SCU controller unit 668230557Sjimharris 669230557Sjimharris /** 670230557Sjimharris * Per PHY Parameter data. 671230557Sjimharris */ 672230557Sjimharris struct 673230557Sjimharris { 674230557Sjimharris /** 675230557Sjimharris * This field indicates the SAS Address that will be transmitted on 676230557Sjimharris * this PHY index. The field is defined as a union, however, the 677230557Sjimharris * OEM should use the U8 array definition when encoding it to ensure 678230557Sjimharris * correct byte ordering. 679230557Sjimharris * 680230557Sjimharris * NOTE: If using APC MODE, along with phy_mask being set to ZERO, the 681230557Sjimharris * SAS Addresses for all PHYs within a controller group SHALL be the 682230557Sjimharris * same. 683230557Sjimharris */ 684230557Sjimharris union 685230557Sjimharris { 686230557Sjimharris /** 687230557Sjimharris * The array should be stored in little endian order. For example, 688230557Sjimharris * if the desired SAS Address is 0x50010B90_0003538D, then it 689230557Sjimharris * should be stored in the following manner: 690230557Sjimharris * array[0] = 0x90 691230557Sjimharris * array[1] = 0x0B 692230557Sjimharris * array[2] = 0x01 693230557Sjimharris * array[3] = 0x50 694230557Sjimharris * array[4] = 0x8D 695230557Sjimharris * array[5] = 0x53 696230557Sjimharris * array[6] = 0x03 697230557Sjimharris * array[7] = 0x00 698230557Sjimharris */ 699230557Sjimharris U8 array[8]; 700230557Sjimharris /** 701230557Sjimharris * This is the typedef'd version of the SAS Address used in 702230557Sjimharris * the SCI Library. 703230557Sjimharris */ 704230557Sjimharris SCI_SAS_ADDRESS_T sci_format; 705230557Sjimharris 706230557Sjimharris } sas_address; 707230557Sjimharris 708230557Sjimharris /** 709240518Seadler * These are the per PHY equalization settings associated with the 710230557Sjimharris * AFE XCVR Tx Amplitude and Equalization Control Register Set 711230557Sjimharris * (0 thru 3). 712230557Sjimharris * 713230557Sjimharris * Operational Note: The following Look-Up-Table registers are engaged 714230557Sjimharris * by the AFE block after the following: 715230557Sjimharris * - Software programs the Link Layer AFE Look Up Table Control 716230557Sjimharris * Registers (AFE_LUTCR). 717230557Sjimharris * - Software sets AFE XCVR Tx Control Register Tx Equalization 718230557Sjimharris * Enable bit. 719230557Sjimharris */ 720230557Sjimharris /** 721230557Sjimharris * AFE_TX_AMP_CTRL0. This register is associated with AFE_LUTCR 722230557Sjimharris * LUTSel=00b. It contains the Tx Equalization settings that will be 723230557Sjimharris * used if a SATA 1.5Gbs or SATA 3.0Gbs device is direct-attached. 724230557Sjimharris */ 725230557Sjimharris U32 afe_tx_amp_control0; 726230557Sjimharris 727230557Sjimharris /** 728230557Sjimharris * AFE_TX_AMP_CTRL1. This register is associated with AFE_LUTCR 729230557Sjimharris * LUTSel=01b. It contains the Tx Equalization settings that will 730230557Sjimharris * be used if a SATA 6.0Gbs device is direct-attached. 731230557Sjimharris */ 732230557Sjimharris U32 afe_tx_amp_control1; 733230557Sjimharris 734230557Sjimharris /** 735230557Sjimharris * AFE_TX_AMP_CTRL2. This register is associated with AFE_LUTCR 736230557Sjimharris * LUTSel=10b. It contains the Tx Equalization settings that will 737230557Sjimharris * be used if a SAS 1.5Gbs or SAS 3.0Gbs device is direct-attached. 738230557Sjimharris */ 739230557Sjimharris U32 afe_tx_amp_control2; 740230557Sjimharris 741230557Sjimharris /** 742230557Sjimharris * AFE_TX_AMP_CTRL3. This register is associated with AFE_LUTCR 743230557Sjimharris * LUTSel=11b. It contains the Tx Equalization settings that will 744230557Sjimharris * be used if a SAS 6.0Gbs device is direct-attached. 745230557Sjimharris */ 746230557Sjimharris U32 afe_tx_amp_control3; 747230557Sjimharris 748230557Sjimharris } phys[SCI_MAX_PHYS]; // 4 PHYs per SCU controller unit 749230557Sjimharris 750230557Sjimharris} SCI_BIOS_OEM_PARAM_ELEMENT_v_1_2_T; 751230557Sjimharris 752230557Sjimharris/** 753230557Sjimharris * @struct SCIC_SDS_OEM_PARAMETERS VER 1.3 754230557Sjimharris * 755230557Sjimharris * @brief This structure delineates the various OEM parameters that must 756230557Sjimharris * be set for the Intel SAS Storage Controller Unit (SCU). 757230557Sjimharris */ 758230557Sjimharristypedef struct SCI_BIOS_OEM_PARAM_ELEMENT_v_1_3 759230557Sjimharris{ 760230557Sjimharris /** 761230557Sjimharris * Per SCU Controller Data 762230557Sjimharris */ 763230557Sjimharris struct 764230557Sjimharris { 765230557Sjimharris /** 766230557Sjimharris * This field indicates the port configuration mode for 767230557Sjimharris * this controller: 768230557Sjimharris * Automatic Port Configuration(APC) or 769230557Sjimharris * Manual Port Configuration (MPC). 770230557Sjimharris * 771230557Sjimharris * APC means the Platform OEM expects SCI to configure 772230557Sjimharris * SAS Ports automatically according to the discovered SAS 773230557Sjimharris * Address pairs of the endpoints, wide and/or narrow. 774230557Sjimharris * 775230557Sjimharris * MPC means the Platform OEM manually defines wide or narrow 776230557Sjimharris * connectors by apriori assigning PHYs to SAS Ports. 777230557Sjimharris * 778230557Sjimharris * By default, the mode type is APC 779230557Sjimharris * in APC mode, if ANY of the phy mask is non-zero, 780230557Sjimharris * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned 781230557Sjimharris * from scic_oem_parameters_set AND the default oem 782230557Sjimharris * configuration will be applied 783230557Sjimharris * in MPC mode, if ALL of the phy masks are zero, 784230557Sjimharris * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned 785230557Sjimharris * from scic_oem_parameters_set AND the default oem 786230557Sjimharris * configuration will be applied 787230557Sjimharris */ 788230557Sjimharris U8 mode_type; 789230557Sjimharris 790230557Sjimharris /** 791230557Sjimharris * This field specifies the maximum number of direct attached 792230557Sjimharris * devices the OEM will allow to have powered up simultaneously 793230557Sjimharris * on this controller. This allows the OEM to avoid exceeding 794230557Sjimharris * power supply limits for this platform. A value of zero 795230557Sjimharris * indicates there are no restrictions. 796230557Sjimharris */ 797230557Sjimharris U8 max_number_concurrent_device_spin_up; 798230557Sjimharris 799230557Sjimharris /** 800230557Sjimharris * This bitfield indicates the OEM's desired default Tx 801230557Sjimharris * Spread Spectrum Clocking (SSC) settings for SATA and SAS. 802230557Sjimharris * NOTE: Default SSC Modulation Frequency is 31.5KHz. 803230557Sjimharris *--------------------------------------------------------------------*/ 804230557Sjimharris /** 805230557Sjimharris * NOTE: Max spread for SATA is +0 / -5000 PPM. 806230557Sjimharris * Down-spreading SSC (only method allowed for SATA): 807230557Sjimharris * SATA SSC Tx Disabled = 0x0 808230557Sjimharris * SATA SSC Tx at +0 / -1419 PPM Spread = 0x2 809230557Sjimharris * SATA SSC Tx at +0 / -2129 PPM Spread = 0x3 810230557Sjimharris * SATA SSC Tx at +0 / -4257 PPM Spread = 0x6 811230557Sjimharris * SATA SSC Tx at +0 / -4967 PPM Spread = 0x7 812230557Sjimharris */ 813230557Sjimharris U8 ssc_sata_tx_spread_level : 4; 814230557Sjimharris 815230557Sjimharris /** 816230557Sjimharris * SAS SSC Tx Disabled = 0x0 817230557Sjimharris * 818230557Sjimharris * NOTE: Max spread for SAS down-spreading +0 / -2300 PPM 819230557Sjimharris * Down-spreading SSC: 820230557Sjimharris * SAS SSC Tx at +0 / -1419 PPM Spread = 0x2 821230557Sjimharris * SAS SSC Tx at +0 / -2129 PPM Spread = 0x3 822230557Sjimharris * 823230557Sjimharris * NOTE: Max spread for SAS center-spreading +2300 / -2300 PPM 824230557Sjimharris * Center-spreading SSC: 825230557Sjimharris * SAS SSC Tx at +1064 / -1064 PPM Spread = 0x3 826230557Sjimharris * SAS SSC Tx at +2129 / -2129 PPM Spread = 0x6 827230557Sjimharris */ 828230557Sjimharris U8 ssc_sas_tx_spread_level : 3; 829230557Sjimharris /** 830230557Sjimharris * NOTE: Refer to the SSC section of the SAS 2.x Specification 831230557Sjimharris * for proper setting of this field. For standard SAS Initiator 832230557Sjimharris * SAS PHY operation it should be 0 for Down-spreading. 833230557Sjimharris * SAS SSC Tx spread type: 834230557Sjimharris * Down-spreading SSC = 0 835230557Sjimharris * Center-spreading SSC = 1 836230557Sjimharris */ 837230557Sjimharris U8 ssc_sas_tx_type : 1; 838230557Sjimharris 839230557Sjimharris /** 840230557Sjimharris * This field indicates length of the SAS/SATA cable between 841230557Sjimharris * host and device. 842230557Sjimharris * This field is used make relationship between analog parameters of 843230557Sjimharris * the phy in the silicon and length of the cable. 844230557Sjimharris * Supported cable attenuation levels: 845230557Sjimharris * "short"- up to 3m, "medium"-3m to 6m, and "long"- more than 6m 846230557Sjimharris * This is bit mask field: 847230557Sjimharris * 848230557Sjimharris * BIT: (MSB) 7 6 5 4 849230557Sjimharris * ASSIGNMENT: <phy3><phy2><phy1><phy0> - Medium cable length assignment 850230557Sjimharris * BIT: 3 2 1 0 (LSB) 851230557Sjimharris * ASSIGNMENT: <phy3><phy2><phy1><phy0> - Long cable length assignment 852230557Sjimharris * 853230557Sjimharris * BITS 7-4 are set when the cable length is assigned to medium 854230557Sjimharris * BITS 3-0 are set when the cable length is assigned to long 855230557Sjimharris * The BIT positions are clear when the cable length is assigned to short 856230557Sjimharris * Setting the bits for both long and medium cable length is undefined. 857230557Sjimharris * 858230557Sjimharris * A value of 0x84 would assign 859230557Sjimharris * phy3 - medium 860230557Sjimharris * phy2 - long 861230557Sjimharris * phy1 - short 862230557Sjimharris * phy0 - short 863230557Sjimharris */ 864230557Sjimharris U8 cable_selection_mask; 865230557Sjimharris 866230557Sjimharris } controller; 867230557Sjimharris 868230557Sjimharris /** 869230557Sjimharris * Per SAS Port data. 870230557Sjimharris */ 871230557Sjimharris struct 872230557Sjimharris { 873230557Sjimharris /** 874230557Sjimharris * This field specifies the phys to be contained inside a port. 875230557Sjimharris * The bit position in the mask specifies the index of the phy 876230557Sjimharris * to be contained in the port. Multiple bits (i.e. phys) 877230557Sjimharris * can be contained in a single port: 878230557Sjimharris * Bit 0 = This controller's PHY index 0 (0x01) 879230557Sjimharris * Bit 1 = This controller's PHY index 1 (0x02) 880230557Sjimharris * Bit 2 = This controller's PHY index 2 (0x04) 881230557Sjimharris * Bit 3 = This controller's PHY index 3 (0x08) 882230557Sjimharris * 883230557Sjimharris * Refer to the mode_type field for rules regarding APC and MPC mode. 884230557Sjimharris * General rule: For APC mode phy_mask = 0 885230557Sjimharris */ 886230557Sjimharris U8 phy_mask; 887230557Sjimharris 888230557Sjimharris } ports[SCI_MAX_PORTS]; // Up to 4 Ports per SCU controller unit 889230557Sjimharris 890230557Sjimharris /** 891230557Sjimharris * Per PHY Parameter data. 892230557Sjimharris */ 893230557Sjimharris struct 894230557Sjimharris { 895230557Sjimharris /** 896230557Sjimharris * This field indicates the SAS Address that will be transmitted on 897230557Sjimharris * this PHY index. The field is defined as a union, however, the 898230557Sjimharris * OEM should use the U8 array definition when encoding it to ensure 899230557Sjimharris * correct byte ordering. 900230557Sjimharris * 901230557Sjimharris * NOTE: If using APC MODE, along with phy_mask being set to ZERO, the 902230557Sjimharris * SAS Addresses for all PHYs within a controller group SHALL be the 903230557Sjimharris * same. 904230557Sjimharris */ 905230557Sjimharris union 906230557Sjimharris { 907230557Sjimharris /** 908230557Sjimharris * The array should be stored in little endian order. For example, 909230557Sjimharris * if the desired SAS Address is 0x50010B90_0003538D, then it 910230557Sjimharris * should be stored in the following manner: 911230557Sjimharris * array[0] = 0x90 912230557Sjimharris * array[1] = 0x0B 913230557Sjimharris * array[2] = 0x01 914230557Sjimharris * array[3] = 0x50 915230557Sjimharris * array[4] = 0x8D 916230557Sjimharris * array[5] = 0x53 917230557Sjimharris * array[6] = 0x03 918230557Sjimharris * array[7] = 0x00 919230557Sjimharris */ 920230557Sjimharris U8 array[8]; 921230557Sjimharris /** 922230557Sjimharris * This is the typedef'd version of the SAS Address used in 923230557Sjimharris * the SCI Library. 924230557Sjimharris */ 925230557Sjimharris SCI_SAS_ADDRESS_T sci_format; 926230557Sjimharris 927230557Sjimharris } sas_address; 928230557Sjimharris 929230557Sjimharris /** 930240518Seadler * These are the per PHY equalization settings associated with the 931230557Sjimharris * AFE XCVR Tx Amplitude and Equalization Control Register Set 932230557Sjimharris * (0 thru 3). 933230557Sjimharris * 934230557Sjimharris * Operational Note: The following Look-Up-Table registers are engaged 935230557Sjimharris * by the AFE block after the following: 936230557Sjimharris * - Software programs the Link Layer AFE Look Up Table Control 937230557Sjimharris * Registers (AFE_LUTCR). 938230557Sjimharris * - Software sets AFE XCVR Tx Control Register Tx Equalization 939230557Sjimharris * Enable bit. 940230557Sjimharris */ 941230557Sjimharris /** 942230557Sjimharris * AFE_TX_AMP_CTRL0. This register is associated with AFE_LUTCR 943230557Sjimharris * LUTSel=00b. It contains the Tx Equalization settings that will be 944230557Sjimharris * used if a SATA 1.5Gbs or SATA 3.0Gbs device is direct-attached. 945230557Sjimharris */ 946230557Sjimharris U32 afe_tx_amp_control0; 947230557Sjimharris 948230557Sjimharris /** 949230557Sjimharris * AFE_TX_AMP_CTRL1. This register is associated with AFE_LUTCR 950230557Sjimharris * LUTSel=01b. It contains the Tx Equalization settings that will 951230557Sjimharris * be used if a SATA 6.0Gbs device is direct-attached. 952230557Sjimharris */ 953230557Sjimharris U32 afe_tx_amp_control1; 954230557Sjimharris 955230557Sjimharris /** 956230557Sjimharris * AFE_TX_AMP_CTRL2. This register is associated with AFE_LUTCR 957230557Sjimharris * LUTSel=10b. It contains the Tx Equalization settings that will 958230557Sjimharris * be used if a SAS 1.5Gbs or SAS 3.0Gbs device is direct-attached. 959230557Sjimharris */ 960230557Sjimharris U32 afe_tx_amp_control2; 961230557Sjimharris 962230557Sjimharris /** 963230557Sjimharris * AFE_TX_AMP_CTRL3. This register is associated with AFE_LUTCR 964230557Sjimharris * LUTSel=11b. It contains the Tx Equalization settings that will 965230557Sjimharris * be used if a SAS 6.0Gbs device is direct-attached. 966230557Sjimharris */ 967230557Sjimharris U32 afe_tx_amp_control3; 968230557Sjimharris 969230557Sjimharris } phys[SCI_MAX_PHYS]; // 4 PHYs per SCU controller unit 970230557Sjimharris 971230557Sjimharris} SCI_BIOS_OEM_PARAM_ELEMENT_v_1_3_T; 972230557Sjimharris 973230557Sjimharris/** 974230557Sjimharris * @struct SCI_BIOS_OEM_PARAM_BLOCK 975230557Sjimharris * 976230557Sjimharris * @brief This structure defines the OEM Parameter block as it will be stored 977230557Sjimharris * in the last 512 bytes of the PDR region in the SPI flash. It must be 978230557Sjimharris * unpacked or pack(1). 979230557Sjimharris */ 980230557Sjimharristypedef struct SCI_BIOS_OEM_PARAM_BLOCK 981230557Sjimharris{ 982230557Sjimharris /** 983230557Sjimharris * OEM Parameter Block header. 984230557Sjimharris */ 985230557Sjimharris SCI_BIOS_OEM_PARAM_BLOCK_HDR_T header; 986230557Sjimharris 987230557Sjimharris /** 988230557Sjimharris * Per controller element descriptor containing the controller's 989230557Sjimharris * parameter data. The prototype defines just one of these descriptors, 990230557Sjimharris * however, the actual runtime number is determined by the num_elements 991230557Sjimharris * field in the header. 992230557Sjimharris */ 993230557Sjimharris SCI_BIOS_OEM_PARAM_ELEMENT_T controller_element[1]; 994230557Sjimharris 995230557Sjimharris} SCI_BIOS_OEM_PARAM_BLOCK_T; 996230557Sjimharris 997230557Sjimharris#ifdef __cplusplus 998230557Sjimharris} 999230557Sjimharris#endif // __cplusplus 1000230557Sjimharris 1001230557Sjimharris#endif // _SCU_BIOS_DEFINITIONS_H_ 1002230557Sjimharris 1003