1287117Scem/*-
2287117Scem * Copyright (C) 2012 Intel Corporation
3287117Scem * All rights reserved.
4287117Scem *
5287117Scem * Redistribution and use in source and binary forms, with or without
6287117Scem * modification, are permitted provided that the following conditions
7287117Scem * are met:
8287117Scem * 1. Redistributions of source code must retain the above copyright
9287117Scem *    notice, this list of conditions and the following disclaimer.
10287117Scem * 2. Redistributions in binary form must reproduce the above copyright
11287117Scem *    notice, this list of conditions and the following disclaimer in the
12287117Scem *    documentation and/or other materials provided with the distribution.
13287117Scem *
14287117Scem * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15287117Scem * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16287117Scem * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17287117Scem * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18287117Scem * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19287117Scem * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20287117Scem * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21287117Scem * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22287117Scem * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23287117Scem * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24287117Scem * SUCH DAMAGE.
25287117Scem */
26287117Scem
27287117Scem__FBSDID("$FreeBSD: stable/11/sys/dev/ioat/ioat_test.h 355198 2019-11-29 00:38:34Z mav $");
28287117Scem
29287117Scem#ifndef __IOAT_TEST_H__
30287117Scem#define __IOAT_TEST_H__
31287117Scem
32289733Scemenum ioat_res {
33289733Scem	IOAT_TEST_OK = 0,
34289733Scem	IOAT_TEST_NO_DMA_ENGINE,
35289733Scem	IOAT_TEST_NO_MEMORY,
36289733Scem	IOAT_TEST_MISCOMPARE,
37290021Scem	IOAT_TEST_INVALID_INPUT,
38289733Scem	IOAT_NUM_RES
39289733Scem};
40289733Scem
41290021Scemenum ioat_test_kind {
42290021Scem	IOAT_TEST_FILL = 0,
43290021Scem	IOAT_TEST_DMA,
44290129Scem	IOAT_TEST_RAW_DMA,
45292044Scem	IOAT_TEST_DMA_8K,
46292044Scem	IOAT_TEST_MEMCPY,
47355198Smav	IOAT_TEST_DMA_8K_PB,
48355198Smav	IOAT_TEST_DMA_CRC,
49355198Smav	IOAT_TEST_DMA_CRC_COPY,
50290021Scem	IOAT_NUM_TESTKINDS
51290021Scem};
52290021Scem
53289733Scemstruct test_transaction;
54289733Scem
55287117Scemstruct ioat_test {
56289733Scem	volatile uint32_t status[IOAT_NUM_RES];
57287117Scem	uint32_t channel_index;
58289733Scem
59290021Scem	enum ioat_test_kind testkind;
60290021Scem
61289733Scem	/* HW max of 1MB */
62289733Scem	uint32_t buffer_size;
63289733Scem	uint32_t chain_depth;
64289733Scem	uint32_t transactions;
65289733Scem
66289733Scem	/*
67289733Scem	 * If non-zero, duration is time in ms;
68289733Scem	 * If zero, bounded by 'transactions' above.
69289733Scem	 */
70289733Scem	uint32_t duration;
71289733Scem
72289733Scem	/* If true, check for miscompares after a copy. */
73289733Scem	bool verify;
74289733Scem
75290129Scem	/* DMA directly to/from some memory address */
76290129Scem	uint64_t raw_target;
77290129Scem	void *raw_vtarget;
78290129Scem	bool raw_write;
79290129Scem	bool raw_is_virtual;
80290129Scem
81292229Scem	bool zero_stats;
82292229Scem	/* Configure coalesce period */
83292229Scem	uint16_t coalesce_period;
84292229Scem
85289733Scem	/* Internal usage -- not test inputs */
86289733Scem	TAILQ_HEAD(, test_transaction) free_q;
87289733Scem	TAILQ_HEAD(, test_transaction) pend_q;
88289733Scem	volatile bool too_late;
89287117Scem};
90287117Scem
91287117Scem#define	IOAT_DMATEST	_IOWR('i', 0, struct ioat_test)
92287117Scem
93287117Scem#endif /* __IOAT_TEST_H__ */
94